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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id k7sm23595803wrw.64.2021.04.19.12.18.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Apr 2021 12:18:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pi4Yqp/Ga3uNxjsupGFLY1gAQ5ebMQowaCuPTS7xonw=; b=MfFAGYhNTJSwbC6t2CU94Ccq6va8Po2S2i9nydoA7azvNCnXcUq4Siz8WF9FiIgwFu h52pWk+pPNNZEfYR8qNHdEUg5hbQGVeqEnrTus8s6rgDeCoK+/o/LU6+q3G679M/QfG4 jzOyFFDAJTXxHG/BFANPiZYVZYEbHOXuXh/hvzFtAo8MBD67wqUuHwwsxQQrKWvf13q8 xEewZYdxbgd2Hc7YQ8oPivnneq4KiB02sO1ZaFk4tPftcJhjdyTJU9h848siQord2wWj PY0fc5MdSVxICbCFd/+cNZ6mb/f8tNRaIylTrHzlKwzV/ryMQhczw0LH8DhmYABD3QIW 3WRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=pi4Yqp/Ga3uNxjsupGFLY1gAQ5ebMQowaCuPTS7xonw=; b=F9iGrys6mlzUI6da5IoqoAYTf22iA7e/aKgo7BM9UjORduQxc2ZaCUgZgZcXE0wHty QzzggIsRWR/Qo0mnsBVg023uoB91gNs65Mvur3BNKbv+j+ho9fAtYQwbzxl5ieGQeQqd FoTSGLeiHoNW/umiuTFKrDwpINPinIbUzT7+/j3fzV6bAXZiNWoJL4XpFZJZ+W3Dy4nq 5Uftts1JOWwE6lEHda7ZeMstRMGL0XZSpF23M3O7Arfnq9TpMb4tLD3i/HSfJdP2mNTM mDTdWt507WKBY+uulQVZ8OmEEvQetOoTWiTss6WNaF6L6r5mHi9lQrJeJiqPvGcwcxvd c4Wg== X-Gm-Message-State: AOAM530ssuuVAhNO1C593D0LxURaTZQ7MnYg/3tdaEiNctd4kozOew+d yH8fXHqQ0ykqP7RKBGGAbUg= X-Google-Smtp-Source: ABdhPJwbH+mBtdLwl0+wvzq4Xn2JF1cKppojS+1jkY9jP02xNiPUpT4oTeNxoZrAcxBak6cHt2FzeQ== X-Received: by 2002:a05:6000:1aca:: with SMTP id i10mr16385482wry.194.1618859910013; Mon, 19 Apr 2021 12:18:30 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Aurelien Jarno , Huacai Chen Subject: [PATCH v3 01/30] target/mips: Simplify meson TCG rules Date: Mon, 19 Apr 2021 21:17:54 +0200 Message-Id: <20210419191823.1555482-2-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210419191823.1555482-1-f4bug@amsat.org> References: <20210419191823.1555482-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) We already have the mips_tcg_ss source set for TCG-specific files, use it for mxu_translate.c and tx79_translate.c to simplify a bit. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/meson.build | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/target/mips/meson.build b/target/mips/meson.build index 3b131c4a7f6..3733d1200f7 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -26,10 +26,9 @@ 'translate_addr_const.c', 'txx9_translate.c', )) -mips_ss.add(when: ['CONFIG_TCG', 'TARGET_MIPS64'], if_true: files( +mips_tcg_ss.add(when: 'TARGET_MIPS64', if_true: files( 'tx79_translate.c', -)) -mips_tcg_ss.add(when: 'TARGET_MIPS64', if_false: files( +), if_false: files( 'mxu_translate.c', )) =20 --=20 2.26.3 From nobody Sat May 4 03:43:33 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.50 as permitted sender) client-ip=209.85.221.50; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f50.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.50 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1618859916; cv=none; d=zohomail.com; s=zohoarc; b=GbRxyUIjXHDg+SYIEOI33c5W/26H6lR7B0jHDUM1eNUwKBoXxwnImW3Ty8K8si9fORQSW6OwmIUo+/Hnpr4mUUPDoyFbo4Pp+s4+xj0qbv8h9FLdWBznjBYEpHi55D9GBJjaWexjSUyEvLO2vWriGFadbQv/gAY0H4l0gGtqR24= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618859916; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=fGOvaajXfmrpLSnOyhpIroCQXe3e+OS5MF3gQarLZWU=; b=Nhro8rppQX2Y0yP5vOUZTSxK293INh4tUjsKT1Aub9OUa28gJ54Kgsc30d64VR9bcSNoekr/OUGXzEGTlwvihfoy9ikXJewApN0byVhVud4VjZOUviv3Sg33xmKeS5dWao6Zt828ag3I0ldUPgKWkhDCRclzTHMPcu62BYfj0sg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.50 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f50.google.com (mail-wr1-f50.google.com [209.85.221.50]) by mx.zohomail.com with SMTPS id 1618859916795811.3098013816987; Mon, 19 Apr 2021 12:18:36 -0700 (PDT) Received: by mail-wr1-f50.google.com with SMTP id x7so35150802wrw.10 for ; Mon, 19 Apr 2021 12:18:36 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.redhat.com (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id f23sm545631wmf.37.2021.04.19.12.18.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Apr 2021 12:18:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fGOvaajXfmrpLSnOyhpIroCQXe3e+OS5MF3gQarLZWU=; b=mOjaQ8Os+wMa5eXWTbLTFe+2E4ZBAkAODgCIhYnBE3BDDnlrR5zlUnwFzk9yaWXahU Gu0jEn3Wy0iRiPCm01xTmPLMK+9Sj9hjMEpFY9zbWPx+RPk4PJZS338Ugmdeys1g+pt2 ITDWb1jj7PvHI5nzTRypC76yZeHjLl8ltj8g6j2ZshPM4cKnfsHiaBb+5o3cCxxQmT2o 4wQ7UvjMGTXczER46qY6yAgkxFAvJJujtx42A+ACeiWVzIzQsRShbVN24LR77qoO84ze ojWg3G2B3xACMR9VXtdBSkNjP2uPc2kMiCmu4HibNPpvblRpNzcBAgzC7R7TDoxutby1 FSqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=fGOvaajXfmrpLSnOyhpIroCQXe3e+OS5MF3gQarLZWU=; b=YuhvcU4lT6MDA/taP7Pp/J+01QXIBB5uDdlHc8+4e7wQISe2gb+GLKAei+qHM5P5pL LupnHyjqNSu/t1OCJT+wi5Ssl28dPfblf0iYQ//dgj5I0LlIhSzyOQGDq99vKOh+xMSU 05+/ka43rPSXcjElMxCcMemVPiRW2s9x0k6wIBqAJurj1Zs+DjibGwi19G/esDcxXQWZ 6mTSvgSEF8W7I9dM98IY2z5NLLApklbJTqzXvw11ZL+u7jBuWMl2LDbd66oEkTF2mdxD JUvhfwRmPB0SYiQWMHcHzDuAuh6i3nmzQCPi8bZ6kk+oPqH424aal95ya6mkEXsLWRT+ dAjA== X-Gm-Message-State: AOAM5338GHKAVxgVAlLaTMRwApKKtAzHKY10y0IWZSD77CCXrhg07mpN QD69xkcGoGdRrkRxcZl5IYY= X-Google-Smtp-Source: ABdhPJxcFKG1mEOJQbvsCg2CAHPJb1YNiCdHaYAZPgOsUJi7bUQcClWyyyCNMSwt//Z3tejgG7RFrg== X-Received: by 2002:adf:8b02:: with SMTP id n2mr15720884wra.259.1618859914883; Mon, 19 Apr 2021 12:18:34 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Aurelien Jarno , Huacai Chen Subject: [PATCH v3 02/30] target/mips: Move IEEE rounding mode array to new source file Date: Mon, 19 Apr 2021 21:17:55 +0200 Message-Id: <20210419191823.1555482-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210419191823.1555482-1-f4bug@amsat.org> References: <20210419191823.1555482-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) restore_msa_fp_status() is declared inlined in fpu_helper.h, and uses the ieee_rm[] array. Therefore any code calling restore_msa_fp_status() must have access to this ieee_rm[] array. kvm_mips_get_fpu_registers(), which is in target/mips/kvm.c, calls restore_msa_fp_status. Except this tiny array, the rest of fpu_helper.c is only useful for the TCG accelerator. To be able to restrict fpu_helper.c to TCG, we need to move the ieee_rm[] array to a new source file. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/fpu.c | 18 ++++++++++++++++++ target/mips/fpu_helper.c | 8 -------- target/mips/meson.build | 1 + 3 files changed, 19 insertions(+), 8 deletions(-) create mode 100644 target/mips/fpu.c diff --git a/target/mips/fpu.c b/target/mips/fpu.c new file mode 100644 index 00000000000..39a2f7fd22e --- /dev/null +++ b/target/mips/fpu.c @@ -0,0 +1,18 @@ +/* + * Helpers for emulation of FPU-related MIPS instructions. + * + * Copyright (C) 2004-2005 Jocelyn Mayer + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ +#include "qemu/osdep.h" +#include "fpu/softfloat-helpers.h" +#include "fpu_helper.h" + +/* convert MIPS rounding mode in FCR31 to IEEE library */ +const FloatRoundMode ieee_rm[4] =3D { + float_round_nearest_even, + float_round_to_zero, + float_round_up, + float_round_down +}; diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c index 6dd853259e2..8ce56ed7c81 100644 --- a/target/mips/fpu_helper.c +++ b/target/mips/fpu_helper.c @@ -38,14 +38,6 @@ #define FP_TO_INT32_OVERFLOW 0x7fffffff #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL =20 -/* convert MIPS rounding mode in FCR31 to IEEE library */ -const FloatRoundMode ieee_rm[4] =3D { - float_round_nearest_even, - float_round_to_zero, - float_round_up, - float_round_down -}; - target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg) { target_ulong arg1 =3D 0; diff --git a/target/mips/meson.build b/target/mips/meson.build index 3733d1200f7..5fcb211ca9a 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -9,6 +9,7 @@ mips_ss =3D ss.source_set() mips_ss.add(files( 'cpu.c', + 'fpu.c', 'gdbstub.c', )) mips_tcg_ss =3D ss.source_set() --=20 2.26.3 From nobody Sat May 4 03:43:33 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.48 as permitted sender) client-ip=209.85.221.48; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f48.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.48 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1618859921; cv=none; d=zohomail.com; s=zohoarc; b=fOc/izksxGaYbC0fUB1RBjD55rnwo+AwNGrn0Gb9B01dYJAxhG0vCQBih+Wk5RlOaqL+8xSjv1zTMSgWBuoY4a9aK5j1+q876V9XUVSJ4l9+svzhPc0l9D/hgAyR8tho1VbevVzQaUiuzXQtnPZMMqyyXOOIYnllGhL6ZMeyvpQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618859921; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=yMxvZRcRgCBUS8Ws91rPcuJR47xd/yHVMPRhORw6260=; b=Bs/T97Aa828P83XeLAOE6xS26X07zdSTbcK0xFTGW/7gu5LXRKhZ8kEnhOGSUKhQElQBrtYw9W8TNgKtErYxmRnUZJ0IsXsJjZxRo9rJa6f1F/a8RV6eb9lL8JbVbvZA9q8WHSH4jyHSCerg+9rzz6UVHP9kS7pKhpWsu7CBLy4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.48 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f48.google.com (mail-wr1-f48.google.com [209.85.221.48]) by mx.zohomail.com with SMTPS id 1618859921560659.5700540351123; Mon, 19 Apr 2021 12:18:41 -0700 (PDT) Received: by mail-wr1-f48.google.com with SMTP id p6so28471615wrn.9 for ; Mon, 19 Apr 2021 12:18:40 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.redhat.com (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id g5sm23970738wrq.30.2021.04.19.12.18.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Apr 2021 12:18:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yMxvZRcRgCBUS8Ws91rPcuJR47xd/yHVMPRhORw6260=; b=nQE502sHi5eGXJbb1fVxBwVrznc3AS7pXvc8Qa/ZpuNM+OG0Yfy8boGqOR1OfgOQhM 0ydB6OKTfl4YDhx9QM+yHiZZQuNC/eV+IjW9OW232W8EZLgUOPiq0zaHtZrHgDGVylXl bGpx1k+lhD2cmpHzljRV3YGWjxD8fypndsbfs6PDUgXqtedb1kHY23VCr0hN5jo4jBke FaaQt2tEVyPhL4rVWJklWVBdHiHCp1FnkE1CN3HeJQhGNTtHseBDf2YaiKBQ4dNKsUQc fTcBG8Ksma45W0RitXPZdSPgAphx2VTonrYLJoJcEmKGlVTyh0cj+zi+SW2IfFCEO1zZ fPsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=yMxvZRcRgCBUS8Ws91rPcuJR47xd/yHVMPRhORw6260=; b=blYPdh+anZCMkJ8G8ca7GJ2tRCFQu2hn3NVLxDv4Rkq1ME8EZqMdjfIY+f8O2GK8Z3 3GNOsB96F799NFg0UjC8/QGf83KtcUaDn6PSK76BDzvux9hr+YsfAwqBJbRQApzUUwRx qXuFchJijD2Z25yPjoZDfZgAERNdXRMBPojy4xk74Jn4EbsPQpX0Bo1aQyHS+EzgzJ6H hpD2tcoMpN0iAZYx5EXI0Fak4/gOqUonbkvkv4zWtoLXTYlD8xSml/e2aGD27n/zsKGF FyfByAkaJNdJTKb7BVPR5yxtYPYQKJ5XfGrWHffB4O9VZTqDvwG7jmIcikUDMYhWS+tM OkSg== X-Gm-Message-State: AOAM532ok5MilvIUsUGuQ4xulvrDdtzYuLZkuo57IVu2GH86qbSFkB4V SOSbqJIymtRGjvm94Y9aoXk= X-Google-Smtp-Source: ABdhPJxwGLP6MlXN6ThkTGEFofWzQJz6yBu73ZjjgmqIhu+NOoRHZ8TOzzEw0x7Hnsxg8MZKRI9LmQ== X-Received: by 2002:a5d:4cc1:: with SMTP id c1mr16408730wrt.291.1618859919698; Mon, 19 Apr 2021 12:18:39 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Aurelien Jarno , Huacai Chen Subject: [PATCH v3 03/30] target/mips: Move msa_reset() to new source file Date: Mon, 19 Apr 2021 21:17:56 +0200 Message-Id: <20210419191823.1555482-4-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210419191823.1555482-1-f4bug@amsat.org> References: <20210419191823.1555482-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) mips_cpu_reset() is used by all accelerators, and calls msa_reset(), which is defined in msa_helper.c. Beside msa_reset(), the rest of msa_helper.c is only useful to the TCG accelerator. To be able to restrict this helper file to TCG, we need to move msa_reset() out of it. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/msa.c | 60 ++++++++++++++++++++++++++++++++++++++++ target/mips/msa_helper.c | 36 ------------------------ target/mips/meson.build | 1 + 3 files changed, 61 insertions(+), 36 deletions(-) create mode 100644 target/mips/msa.c diff --git a/target/mips/msa.c b/target/mips/msa.c new file mode 100644 index 00000000000..61f1a9a5936 --- /dev/null +++ b/target/mips/msa.c @@ -0,0 +1,60 @@ +/* + * MIPS SIMD Architecture Module Instruction emulation helpers for QEMU. + * + * Copyright (c) 2014 Imagination Technologies + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "internal.h" +#include "fpu/softfloat.h" +#include "fpu_helper.h" + +void msa_reset(CPUMIPSState *env) +{ + if (!ase_msa_available(env)) { + return; + } + +#ifdef CONFIG_USER_ONLY + /* MSA access enabled */ + env->CP0_Config5 |=3D 1 << CP0C5_MSAEn; + env->CP0_Status |=3D (1 << CP0St_CU1) | (1 << CP0St_FR); +#endif + + /* + * MSA CSR: + * - non-signaling floating point exception mode off (NX bit is 0) + * - Cause, Enables, and Flags are all 0 + * - round to nearest / ties to even (RM bits are 0) + */ + env->active_tc.msacsr =3D 0; + + restore_msa_fp_status(env); + + /* tininess detected after rounding.*/ + set_float_detect_tininess(float_tininess_after_rounding, + &env->active_tc.msa_fp_status); + + /* clear float_status exception flags */ + set_float_exception_flags(0, &env->active_tc.msa_fp_status); + + /* clear float_status nan mode */ + set_default_nan_mode(0, &env->active_tc.msa_fp_status); + + /* set proper signanling bit meaning ("1" means "quiet") */ + set_snan_bit_is_one(0, &env->active_tc.msa_fp_status); +} diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index 4caefe29ad7..04af54f66d1 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -8595,39 +8595,3 @@ void helper_msa_st_d(CPUMIPSState *env, uint32_t wd, cpu_stq_data(env, addr + (1 << DF_DOUBLE), pwd->d[1]); #endif } - -void msa_reset(CPUMIPSState *env) -{ - if (!ase_msa_available(env)) { - return; - } - -#ifdef CONFIG_USER_ONLY - /* MSA access enabled */ - env->CP0_Config5 |=3D 1 << CP0C5_MSAEn; - env->CP0_Status |=3D (1 << CP0St_CU1) | (1 << CP0St_FR); -#endif - - /* - * MSA CSR: - * - non-signaling floating point exception mode off (NX bit is 0) - * - Cause, Enables, and Flags are all 0 - * - round to nearest / ties to even (RM bits are 0) - */ - env->active_tc.msacsr =3D 0; - - restore_msa_fp_status(env); - - /* tininess detected after rounding.*/ - set_float_detect_tininess(float_tininess_after_rounding, - &env->active_tc.msa_fp_status); - - /* clear float_status exception flags */ - set_float_exception_flags(0, &env->active_tc.msa_fp_status); - - /* clear float_status nan mode */ - set_default_nan_mode(0, &env->active_tc.msa_fp_status); - - /* set proper signanling bit meaning ("1" means "quiet") */ - set_snan_bit_is_one(0, &env->active_tc.msa_fp_status); -} diff --git a/target/mips/meson.build b/target/mips/meson.build index 5fcb211ca9a..daf5f1d55bc 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -11,6 +11,7 @@ 'cpu.c', 'fpu.c', 'gdbstub.c', + 'msa.c', )) mips_tcg_ss =3D ss.source_set() mips_tcg_ss.add(gen) --=20 2.26.3 From nobody Sat May 4 03:43:33 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.47 as permitted sender) client-ip=209.85.221.47; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f47.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.47 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1618859926; cv=none; d=zohomail.com; s=zohoarc; b=BtjhfbfKx2FsUzAxcwohMwzR5zmx3d6DReavnpPu4f9Y5ya4+Tm51QJv6PdDlWqaOuHtCBvnJLfoeAEvF27TPGr39fza1Ye1wSBQWfw0jVYvqHAPWjDfYabCLTREU8xXFbVJTvkWWU5j2jQAaZrjZ0lEbRKXULx912giYNbHXvk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618859926; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=JdLEvydvbX477BhH/ZmKV47FrIUBwZZqHvybwivTF10=; b=cFCVpuNKssneuBdvoa7GuDsUU2BmgAMl2PQZh+z9pnXuYhjP+P/96sAlCDMWq1jFUZW3XE7nPqsUozQXv+1yHsBuTfYsXsjjlVKUnW/8zwl8ztXAR4qrcRhY/mLt1QSktl9owvR/AuMdvYkQe5NsTDo18rq/EZsL3uKjx+aNeTs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.47 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f47.google.com (mail-wr1-f47.google.com [209.85.221.47]) by mx.zohomail.com with SMTPS id 1618859926278524.2137377286023; Mon, 19 Apr 2021 12:18:46 -0700 (PDT) Received: by mail-wr1-f47.google.com with SMTP id c15so26235739wro.13 for ; Mon, 19 Apr 2021 12:18:45 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.redhat.com (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id l14sm522342wmq.4.2021.04.19.12.18.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Apr 2021 12:18:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JdLEvydvbX477BhH/ZmKV47FrIUBwZZqHvybwivTF10=; b=deltvGSS5dyc4th/Or9JYeoc8/sBGeL14V7j1CHjJmRPBMYszO9We6SAGbR/1Q7gd1 f6OitR3u0xZonZuaAZr+f2qYIMyJqj3CH9YVqHPNhv67K/KQjQvoDclc7su8WohW/39l hWcgFUvKA/YHDUOBOkIPtvc9TgJxOYgN4hozmP3KewS8ZpeKnd/dRHN3EEvi91LykHIJ +7yhZYMMAwe60PseXkCS62kTwgAtYYA0CQ0f+VDfK4zrbPNK5oQet6K5DdDFA1G0R1+a 1S3iMm7EHdnqHp3zAcEgJgNfc60ncbRTE3pYdzNGXhmrbhe6pzJ1twAK/17RAQW2oJSo LC9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=JdLEvydvbX477BhH/ZmKV47FrIUBwZZqHvybwivTF10=; b=fjVMOM9qLmRF88uMl6M7juraKMnz2YWTgiaCBiQdi+Cq4kQcaY2D0xOkGsgz5wlIQZ BMvGQXPxwn8iRgq5C3K2VJFt6AThdWH4tf1ShQxZpNWKE9Tb4MdbcVYwXgUx9msQrsaR KZmXQnFupaqfT9FywSVZJH2K7MtVlcR16LQcG/3Jyy6W8TSi0cGRPm7Cj0TqhsysWKJu Thoiqmi5tlCqMRFwk6j/7dWC82O6V/1UajE6vPb+cJD3L5SYuWAzn40Ha57Tr2lkVxsq 96HDCApZynW6Y5r4amnoCkFWbHDMyENFZVy54lCMwxX0LndzBkt02WhW+wm7ipfTwXea CPNQ== X-Gm-Message-State: AOAM530dixOuDsWka83t4drcRnr7aaimEZ3QnfPkHdt0+jWB0I+E6idF ritOXndRMIQNPSkRB6Pixoo= X-Google-Smtp-Source: ABdhPJxsQPEgEeJQ62/ux3atd5vqJj3q0umH9oqJYDF5uwzLlq0fo1W+0H1alfWC1Q4oMf+/TgFe4w== X-Received: by 2002:a5d:4405:: with SMTP id z5mr16594720wrq.313.1618859924495; Mon, 19 Apr 2021 12:18:44 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Aurelien Jarno , Huacai Chen Subject: [PATCH v3 04/30] target/mips: Make CPU/FPU regnames[] arrays global Date: Mon, 19 Apr 2021 21:17:57 +0200 Message-Id: <20210419191823.1555482-5-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210419191823.1555482-1-f4bug@amsat.org> References: <20210419191823.1555482-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) The CPU/FPU regnames[] arrays is used in mips_tcg_init() and mips_cpu_dump_state(), which while being in translate.c is not specific to TCG. To be able to move mips_cpu_dump_state() to cpu.c, which is compiled for all accelerator, we need to make the regnames[] arrays global to target/mips/ by declaring them in "internal.h". Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/internal.h | 3 +++ target/mips/cpu.c | 7 +++++++ target/mips/fpu.c | 7 +++++++ target/mips/translate.c | 14 -------------- 4 files changed, 17 insertions(+), 14 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 99264b8bf6a..a8644f754a6 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -71,6 +71,9 @@ struct mips_def_t { int32_t SAARP; }; =20 +extern const char * const regnames[32]; +extern const char * const fregnames[32]; + extern const struct mips_def_t mips_defs[]; extern const int mips_defs_number; =20 diff --git a/target/mips/cpu.c b/target/mips/cpu.c index dce1e166bde..f354d18aec4 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -35,6 +35,13 @@ #include "qapi/qapi-commands-machine-target.h" #include "fpu_helper.h" =20 +const char * const regnames[32] =3D { + "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3", + "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", + "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", + "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", +}; + #if !defined(CONFIG_USER_ONLY) =20 /* Called for updates to CP0_Status. */ diff --git a/target/mips/fpu.c b/target/mips/fpu.c index 39a2f7fd22e..1447dba3fa3 100644 --- a/target/mips/fpu.c +++ b/target/mips/fpu.c @@ -16,3 +16,10 @@ const FloatRoundMode ieee_rm[4] =3D { float_round_up, float_round_down }; + +const char * const fregnames[32] =3D { + "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", + "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", + "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", + "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", +}; diff --git a/target/mips/translate.c b/target/mips/translate.c index 71fa5ec1973..f99d4d4016d 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1267,13 +1267,6 @@ TCGv_i64 fpu_f64[32]; #define DISAS_STOP DISAS_TARGET_0 #define DISAS_EXIT DISAS_TARGET_1 =20 -static const char * const regnames[] =3D { - "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3", - "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", - "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", - "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", -}; - static const char * const regnames_HI[] =3D { "HI0", "HI1", "HI2", "HI3", }; @@ -1282,13 +1275,6 @@ static const char * const regnames_LO[] =3D { "LO0", "LO1", "LO2", "LO3", }; =20 -static const char * const fregnames[] =3D { - "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", - "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", - "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", - "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", -}; - /* General purpose registers moves. */ void gen_load_gpr(TCGv t, int reg) { --=20 2.26.3 From nobody Sat May 4 03:43:33 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.50 as permitted sender) client-ip=209.85.221.50; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f50.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.50 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1618859931; cv=none; d=zohomail.com; s=zohoarc; b=ZUIKfFxzXmHD6vbpzp1otOwPnkIoX8FUYXOqlktkUilZ8trDT3loxHRLOxLP18+zKZk8tgpWRsbx4FzoLr6VAhyce9cxlDftzoEF9JaUOd6S5KQmSoly2IVl5vOXOLzUfUCnt81+S82sZli/EG1u2JgX4dbjYwY/Y5mNk1xWKrA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618859931; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=jK+gaco4qgdVhboeMerJ/bnvg6dnQ6kpU1z6QqW9e3M=; b=jp+HWz9xtl0HHVXyX8HvjsH7rHaGvc6oGMK4FP09uy5G+Y5I/XnaIP1/eE3xcnsSXZG2EL7elCgAyDkzZazNcXuCZmvc6Lt+feT4IIlOlkxioykDiSZlpBUcpEpUmvl6AvB0Z4OtEAPqMZr9IV1j84m/DoUCqFavmVgagiIUr2g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.50 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-wr1-f50.google.com (mail-wr1-f50.google.com [209.85.221.50]) by mx.zohomail.com with SMTPS id 1618859931156399.692976819554; Mon, 19 Apr 2021 12:18:51 -0700 (PDT) Received: by mail-wr1-f50.google.com with SMTP id g9so19152010wrx.0 for ; Mon, 19 Apr 2021 12:18:50 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.redhat.com (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id c1sm23538279wrx.89.2021.04.19.12.18.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Apr 2021 12:18:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jK+gaco4qgdVhboeMerJ/bnvg6dnQ6kpU1z6QqW9e3M=; b=Nhj2vqKHQdKioneDnC2EAcLaGuo4ppKDS7DnZs0P4Y1GYs3G8/QYQ1nzi9ikCy4UqO pi68PN+GO8kKLVf+P/lJGhQF9pid9b7u4NMNEJy20PS3IUKboHLxfZIyUbDTAU7nKNWJ onVpf5KW3Y0c8GPma/s1iyIAUN657nV0LTd0sWUoYD9cEjLrdQ9CcrAxuJKbsAz6DpeE fQSOhkiskJdlLq3GkcpMHO2vNQ9Cbcheh1t85RxMGzH1BKEuwcRUmdQI6XEJxlJWppdI zRmNY7bDUqUKVisU01nHl51E8O71rErT51Iu3prLh967zKW4qavJZGNM6QqwT6IgdhUt 9X3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=jK+gaco4qgdVhboeMerJ/bnvg6dnQ6kpU1z6QqW9e3M=; b=CFTJYFXOKIuBt8bl1R4HkQI9m8DQby+DEIeynWFhh6jYI4lo95bcdfoyktiRv6FugK QSX7ESJ2aH0E4BRWyfMCtu5GBBpCkP/d0fBwmQs7Ofhl2o/i2AwIB+pG5/AkmePaetoS LQx9rsU+JatYDCgM+hkhcuIyI8OEBLlHMebRxT5VLD06Asf7gcf9CPk3bYr/mQFch8ef MgVprZSdCOEFuk/boYpk7A+kXHxwC+Td9kgyUHiYJJSVNuDxX1m7+ji8s8D8MAnMSaDa HgKBjtgE6ZnXkoBEjbHGRCwjyK7chhCThZulQLWEnITxtCe9vVXshF9mCHVmXyQSX9Y4 agvw== X-Gm-Message-State: AOAM531m0EKyNP+snsJYHjI7v2gVewfslzaCqvtgdSaYr3Ai6ci7F7ff o7HPewaaJ+PwETQpVtEoch0= X-Google-Smtp-Source: ABdhPJzLoFi4JNVy2b0YsHmsILZ3ie5xTYyHpk45C+EBbhLqTsmhAjW4A5vaEi2iUhqteEASdl3Xog== X-Received: by 2002:a5d:6b50:: with SMTP id x16mr16090532wrw.379.1618859929386; Mon, 19 Apr 2021 12:18:49 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Aurelien Jarno , Huacai Chen Subject: [PATCH v3 05/30] target/mips: Optimize CPU/FPU regnames[] arrays Date: Mon, 19 Apr 2021 21:17:58 +0200 Message-Id: <20210419191823.1555482-6-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210419191823.1555482-1-f4bug@amsat.org> References: <20210419191823.1555482-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Since all entries are no more than 4 bytes (including nul terminator), can save space and pie runtime relocations by declaring regnames[] as array of 4 const char. Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/internal.h | 4 ++-- target/mips/cpu.c | 2 +- target/mips/fpu.c | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index a8644f754a6..37f54a8b3fc 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -71,8 +71,8 @@ struct mips_def_t { int32_t SAARP; }; =20 -extern const char * const regnames[32]; -extern const char * const fregnames[32]; +extern const char regnames[32][4]; +extern const char fregnames[32][4]; =20 extern const struct mips_def_t mips_defs[]; extern const int mips_defs_number; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index f354d18aec4..ed9552ebeb7 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -35,7 +35,7 @@ #include "qapi/qapi-commands-machine-target.h" #include "fpu_helper.h" =20 -const char * const regnames[32] =3D { +const char regnames[32][4] =3D { "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3", "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", diff --git a/target/mips/fpu.c b/target/mips/fpu.c index 1447dba3fa3..c7c487c1f9f 100644 --- a/target/mips/fpu.c +++ b/target/mips/fpu.c @@ -17,7 +17,7 @@ const FloatRoundMode ieee_rm[4] =3D { float_round_down }; =20 -const char * const fregnames[32] =3D { +const char fregnames[32][4] =3D { "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", --=20 2.26.3 From nobody Sat May 4 03:43:33 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.41 as permitted sender) client-ip=209.85.128.41; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f41.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.41 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1618859937; cv=none; d=zohomail.com; s=zohoarc; b=gnIzB2MsLgf4WWxV3J7X3NfJMmYzAIPp65xMmDCG+Rb5p1XSeaFxQAS7B3FKXED58sQm8vyHbq011uq4mMBd3aSvbdW+c1OtsXaWoizYxeo7u0lD09ckYBPgy1MxY7ccqXPNBQZvnxgP9sA9PuUVnPDU1+ZSymvs8/yFrtiBGv4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618859937; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=HEDVE1BH0ASPFbPC+pm0317mb0q/DhypvkeSRH/j5kw=; b=PN2cL8VqMbqVVGV8jEcOyIuypCoGrus3yYN2b+tMgEmZGIXdhIwOpdG7HcNtIRoeaz9ofGjYu3920LyvIz0rRwEvEarRCAMpBSnFQi+ySiNjxDClAykNtD6z758UbP3Ah5NS2psMrhJpC0n2oXZuN0evqVNiwkJ/GgPc0P4Kiis= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.41 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) by mx.zohomail.com with SMTPS id 1618859937006797.6391136939634; Mon, 19 Apr 2021 12:18:57 -0700 (PDT) Received: by mail-wm1-f41.google.com with SMTP id k4-20020a7bc4040000b02901331d89fb83so6556386wmi.5 for ; Mon, 19 Apr 2021 12:18:55 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.redhat.com (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id n9sm488089wmo.27.2021.04.19.12.18.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Apr 2021 12:18:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HEDVE1BH0ASPFbPC+pm0317mb0q/DhypvkeSRH/j5kw=; b=l/rJB4kC+GQ0hplUwDmreH0u5fXwYF8uxn7F+7CvbRTo7ULAbIofpQwm2680rldK3W 6GON0K8WR+g9Cze4lR6tbgmTpjFqy7N//w5EovPDN3cUwl8qVT2oadvzQCpDkzyLhjim K5fqpfdstjXwL/tVFWfywXQOFz+srSPu+6VkfIVB4UZyJm7IhXL3xFbu3Gxrq/JUTu2w ys4orrleJmQLFfwq29VWNAriYp/1WZQAx8s55G97m6E/hhsSBcPm8CkM7e5OovI/ujrt vKYOowKsURHvfKRFXtfk5YoBzckbJznibncKrYiEnI4gayOIRqbN5CCQteyxVcbw5vVS KUKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=HEDVE1BH0ASPFbPC+pm0317mb0q/DhypvkeSRH/j5kw=; b=hg/PwbNJOpEN0Sk/I2EqK+rPSu/oYPQGcPL2de0k/rZarnJTBoRaZ5Ps56qN/8emvt 4kTYMxhXHofdCDhmllnfWyyX6N2BVDJPpDBBoE/yqjS1GS+LLaclUOk3eHlhs417EXIF uMrBqxrnOqygaOh/7W6DYzKqahbBEP0Ikz7rUuqKO/mu51PrB1A+ueETglceXaCP4daj x157xVKqdQUziQNelmwJ0c2+vFOt95xxJSqv6zcD2AY5WZSDPomcNVQJfWzRbn9v+khc rJ9UOpIzYTPzsgb7DEslZf6JPuJ47vFrfkHlI3yw02zDUp5+Ux7kHiI8Dz6O7/I8fB2O b5+Q== X-Gm-Message-State: AOAM532bwK9JNqwbQQP4PcDY+VFoFlGoO1CW+JCyMHBYsfcr4m0BLNlj m3I2jv/w2nNC4b2g42URqnE= X-Google-Smtp-Source: ABdhPJyxlBsL0bkvwa1jdZFcWjast6omKSyWlkrWrcgaYYM5x1twxsdtJzospcTs+bDozcGkbH+8Cg== X-Received: by 2002:a1c:4186:: with SMTP id o128mr546632wma.141.1618859934276; Mon, 19 Apr 2021 12:18:54 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Aurelien Jarno , Huacai Chen Subject: [PATCH v3 06/30] target/mips: Restrict mips_cpu_dump_state() to cpu.c Date: Mon, 19 Apr 2021 21:17:59 +0200 Message-Id: <20210419191823.1555482-7-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210419191823.1555482-1-f4bug@amsat.org> References: <20210419191823.1555482-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) As mips_cpu_dump_state() is only used once to initialize the CPUClass::dump_state handler, we can move it to cpu.c to keep it symbol local. Beside, this handler is used by all accelerators, while the translate.c file targets TCG. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/internal.h | 1 - target/mips/cpu.c | 77 +++++++++++++++++++++++++++++++++++++++++ target/mips/translate.c | 77 ----------------------------------------- 3 files changed, 77 insertions(+), 78 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 37f54a8b3fc..57072a941e7 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -79,7 +79,6 @@ extern const int mips_defs_number; =20 void mips_cpu_do_interrupt(CPUState *cpu); bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); -void mips_cpu_dump_state(CPUState *cpu, FILE *f, int flags); hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); diff --git a/target/mips/cpu.c b/target/mips/cpu.c index ed9552ebeb7..232f701b836 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -145,6 +145,83 @@ void cpu_mips_store_cause(CPUMIPSState *env, target_ul= ong val) =20 #endif /* !CONFIG_USER_ONLY */ =20 +static void fpu_dump_state(CPUMIPSState *env, FILE *f, int flags) +{ + int i; + int is_fpu64 =3D !!(env->hflags & MIPS_HFLAG_F64); + +#define printfpr(fp) \ + do { \ + if (is_fpu64) \ + qemu_fprintf(f, "w:%08x d:%016" PRIx64 \ + " fd:%13g fs:%13g psu: %13g\n", \ + (fp)->w[FP_ENDIAN_IDX], (fp)->d, \ + (double)(fp)->fd, \ + (double)(fp)->fs[FP_ENDIAN_IDX], \ + (double)(fp)->fs[!FP_ENDIAN_IDX]); \ + else { \ + fpr_t tmp; \ + tmp.w[FP_ENDIAN_IDX] =3D (fp)->w[FP_ENDIAN_IDX]; \ + tmp.w[!FP_ENDIAN_IDX] =3D ((fp) + 1)->w[FP_ENDIAN_IDX]; \ + qemu_fprintf(f, "w:%08x d:%016" PRIx64 \ + " fd:%13g fs:%13g psu:%13g\n", \ + tmp.w[FP_ENDIAN_IDX], tmp.d, \ + (double)tmp.fd, \ + (double)tmp.fs[FP_ENDIAN_IDX], \ + (double)tmp.fs[!FP_ENDIAN_IDX]); \ + } \ + } while (0) + + + qemu_fprintf(f, + "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%02= x\n", + env->active_fpu.fcr0, env->active_fpu.fcr31, is_fpu64, + get_float_exception_flags(&env->active_fpu.fp_status)); + for (i =3D 0; i < 32; (is_fpu64) ? i++ : (i +=3D 2)) { + qemu_fprintf(f, "%3s: ", fregnames[i]); + printfpr(&env->active_fpu.fpr[i]); + } + +#undef printfpr +} + +static void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags) +{ + MIPSCPU *cpu =3D MIPS_CPU(cs); + CPUMIPSState *env =3D &cpu->env; + int i; + + qemu_fprintf(f, "pc=3D0x" TARGET_FMT_lx " HI=3D0x" TARGET_FMT_lx + " LO=3D0x" TARGET_FMT_lx " ds %04x " + TARGET_FMT_lx " " TARGET_FMT_ld "\n", + env->active_tc.PC, env->active_tc.HI[0], env->active_tc.L= O[0], + env->hflags, env->btarget, env->bcond); + for (i =3D 0; i < 32; i++) { + if ((i & 3) =3D=3D 0) { + qemu_fprintf(f, "GPR%02d:", i); + } + qemu_fprintf(f, " %s " TARGET_FMT_lx, + regnames[i], env->active_tc.gpr[i]); + if ((i & 3) =3D=3D 3) { + qemu_fprintf(f, "\n"); + } + } + + qemu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" + TARGET_FMT_lx "\n", + env->CP0_Status, env->CP0_Cause, env->CP0_EPC); + qemu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x%016" + PRIx64 "\n", + env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr); + qemu_fprintf(f, " Config2 0x%08x Config3 0x%08x\n", + env->CP0_Config2, env->CP0_Config3); + qemu_fprintf(f, " Config4 0x%08x Config5 0x%08x\n", + env->CP0_Config4, env->CP0_Config5); + if ((flags & CPU_DUMP_FPU) && (env->hflags & MIPS_HFLAG_FPU)) { + fpu_dump_state(env, f, flags); + } +} + static const char * const excp_names[EXCP_LAST + 1] =3D { [EXCP_RESET] =3D "reset", [EXCP_SRESET] =3D "soft reset", diff --git a/target/mips/translate.c b/target/mips/translate.c index f99d4d4016d..8702f9220be 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -25579,83 +25579,6 @@ void gen_intermediate_code(CPUState *cs, Translati= onBlock *tb, int max_insns) translator_loop(&mips_tr_ops, &ctx.base, cs, tb, max_insns); } =20 -static void fpu_dump_state(CPUMIPSState *env, FILE * f, int flags) -{ - int i; - int is_fpu64 =3D !!(env->hflags & MIPS_HFLAG_F64); - -#define printfpr(fp) \ - do { \ - if (is_fpu64) \ - qemu_fprintf(f, "w:%08x d:%016" PRIx64 \ - " fd:%13g fs:%13g psu: %13g\n", \ - (fp)->w[FP_ENDIAN_IDX], (fp)->d, \ - (double)(fp)->fd, \ - (double)(fp)->fs[FP_ENDIAN_IDX], \ - (double)(fp)->fs[!FP_ENDIAN_IDX]); \ - else { \ - fpr_t tmp; \ - tmp.w[FP_ENDIAN_IDX] =3D (fp)->w[FP_ENDIAN_IDX]; \ - tmp.w[!FP_ENDIAN_IDX] =3D ((fp) + 1)->w[FP_ENDIAN_IDX]; \ - qemu_fprintf(f, "w:%08x d:%016" PRIx64 \ - " fd:%13g fs:%13g psu:%13g\n", \ - tmp.w[FP_ENDIAN_IDX], tmp.d, \ - (double)tmp.fd, \ - (double)tmp.fs[FP_ENDIAN_IDX], \ - (double)tmp.fs[!FP_ENDIAN_IDX]); \ - } \ - } while (0) - - - qemu_fprintf(f, - "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%02= x\n", - env->active_fpu.fcr0, env->active_fpu.fcr31, is_fpu64, - get_float_exception_flags(&env->active_fpu.fp_status)); - for (i =3D 0; i < 32; (is_fpu64) ? i++ : (i +=3D 2)) { - qemu_fprintf(f, "%3s: ", fregnames[i]); - printfpr(&env->active_fpu.fpr[i]); - } - -#undef printfpr -} - -void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags) -{ - MIPSCPU *cpu =3D MIPS_CPU(cs); - CPUMIPSState *env =3D &cpu->env; - int i; - - qemu_fprintf(f, "pc=3D0x" TARGET_FMT_lx " HI=3D0x" TARGET_FMT_lx - " LO=3D0x" TARGET_FMT_lx " ds %04x " - TARGET_FMT_lx " " TARGET_FMT_ld "\n", - env->active_tc.PC, env->active_tc.HI[0], env->active_tc.L= O[0], - env->hflags, env->btarget, env->bcond); - for (i =3D 0; i < 32; i++) { - if ((i & 3) =3D=3D 0) { - qemu_fprintf(f, "GPR%02d:", i); - } - qemu_fprintf(f, " %s " TARGET_FMT_lx, - regnames[i], env->active_tc.gpr[i]); - if ((i & 3) =3D=3D 3) { - qemu_fprintf(f, "\n"); - } - } - - qemu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" - TARGET_FMT_lx "\n", - env->CP0_Status, env->CP0_Cause, env->CP0_EPC); - qemu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x%016" - PRIx64 "\n", - env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr); - qemu_fprintf(f, " Config2 0x%08x Config3 0x%08x\n", - env->CP0_Config2, env->CP0_Config3); - qemu_fprintf(f, " Config4 0x%08x Config5 0x%08x\n", - env->CP0_Config4, env->CP0_Config5); - if ((flags & CPU_DUMP_FPU) && (env->hflags & MIPS_HFLAG_FPU)) { - fpu_dump_state(env, f, flags); - } -} - void mips_tcg_init(void) { int i; --=20 2.26.3 From nobody Sat May 4 03:43:33 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.54 as permitted sender) client-ip=209.85.128.54; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f54.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.54 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1618859940; cv=none; d=zohomail.com; s=zohoarc; b=kVlfbmJ66pwaOs5umSiSUZDGFY/QVWM2X1b8isir3UaYX+UgqigA2CS7xpHA2rUUF4ocKUt1YPpyEcMwHP0J/D6RG8XnIvWKxUNugZ9/0BUMc+gSeYGLVx4l+dSCDJRBS0TyOch9kgFyxCg8cXvHE9KwoVrOLGRmwMInYWVBbsc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618859940; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=fTQ5LbmfBKa+DkChI03N3lX+fZBlTslCfIb2OafYz+c=; b=FqJKiARXJ0VZ3mS94ck0X8ze6G2D8sNVU57mkXuBQ1hXFnTxy9YLc9B2KXPkSOI9ODUbO/4DNSnGwXdA6g8QFYcZJ7NGm2FPcGJze2t8sjK+/7AD/tDvbop24smetvbyNKsgzmmee+XVKnN7CbrHq+IJ2sYJ6UoLsVZPLEHMDTw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.54 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) by mx.zohomail.com with SMTPS id 1618859940918746.060234598215; Mon, 19 Apr 2021 12:19:00 -0700 (PDT) Received: by mail-wm1-f54.google.com with SMTP id n127so7034630wmb.5 for ; Mon, 19 Apr 2021 12:19:00 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.redhat.com (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id c6sm1858039wmr.0.2021.04.19.12.18.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Apr 2021 12:18:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fTQ5LbmfBKa+DkChI03N3lX+fZBlTslCfIb2OafYz+c=; b=tvgYuzTtjo05RsirAdOmxuKSV8+x6wwgBpV9Cbj3IIkCLGff0vPgZ4wK5WKhDmxaa7 kqFNuEtRfma0l71izVu5OKPF+2Bjat279FgV3wJ4gS3Zsqs6H6LDMJvA7u6L8ZUT9tCD 0ILbDIqR6/YyKFgb1oXR6E6y6FIov72P0gwmW+siy+BxwHGSa84GWHZ3C2L4bKnUY+CA AVjbv1AEi/H1rMu1uumMx25GjJ17356vuqY4UTOOmOmMfhg7CVG95jWu7KKzdWrJlDQS CMmO79n4dEDfJAfhTNwHP8ed82FgJ4RyDdx9nU199SB+8477vvcMgMsiJMAE2d2+T78D IdfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=fTQ5LbmfBKa+DkChI03N3lX+fZBlTslCfIb2OafYz+c=; b=TKArK2uGT4kMIAh56Vd/JvsJG5WWvvCVvFEtTgat2TM2TiDeHBIBM3hssUt1AeaFOT /D0sSmuDrnxP+Kbdhhc7P7VUa8QZ9D2IZstpVT2ciWfL8RIXRM4pkFVQzJ/kS3FMCLnm lX5avrRTu/URR06O8opTT3BPZ119ylRb9wIcfsoSdtyOZqvfjiq7GwlniB6qbNaw4UeW aQtfUk2ila3/tSdXSEeeVjUjife3Kkvrkk3uitOCvaqeJDGTdKlrHafFKABkUK5JebI8 Lacio5WHE2AxqhKXTZG2Bvgm6sSwix05BbYeUdATYYNLZlHpzJYpjYWzi5R13S5hkvhn OLwA== X-Gm-Message-State: AOAM531Nzv8CdebQwBpMvgSTuXtSRU/Myrx9kduIk1cgpPVmTD5LtPIQ BSL49ijAvB68mY9nUeXlo4E= X-Google-Smtp-Source: ABdhPJwAXQEzFiWtuarEgZ+SNGdpcgPjXTR/1xEAOLiTz/kdMakXyagXWC1UijTbqfvRLj8idzxX3w== X-Received: by 2002:a1c:7c08:: with SMTP id x8mr580525wmc.130.1618859939153; Mon, 19 Apr 2021 12:18:59 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Aurelien Jarno , Huacai Chen Subject: [PATCH v3 07/30] target/mips: Turn printfpr() macro into a proper function Date: Mon, 19 Apr 2021 21:18:00 +0200 Message-Id: <20210419191823.1555482-8-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210419191823.1555482-1-f4bug@amsat.org> References: <20210419191823.1555482-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Turn printfpr() macro into a proper function: fpu_dump_fpr(). Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/cpu.c | 48 ++++++++++++++++++++++------------------------- 1 file changed, 22 insertions(+), 26 deletions(-) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 232f701b836..90ae232c8b8 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -145,44 +145,40 @@ void cpu_mips_store_cause(CPUMIPSState *env, target_u= long val) =20 #endif /* !CONFIG_USER_ONLY */ =20 +static void fpu_dump_fpr(fpr_t *fpr, FILE *f, bool is_fpu64) +{ + if (is_fpu64) { + qemu_fprintf(f, "w:%08x d:%016" PRIx64 " fd:%13g fs:%13g psu: %13g= \n", + fpr->w[FP_ENDIAN_IDX], fpr->d, + (double)fpr->fd, + (double)fpr->fs[FP_ENDIAN_IDX], + (double)fpr->fs[!FP_ENDIAN_IDX]); + } else { + fpr_t tmp; + + tmp.w[FP_ENDIAN_IDX] =3D fpr->w[FP_ENDIAN_IDX]; + tmp.w[!FP_ENDIAN_IDX] =3D (fpr + 1)->w[FP_ENDIAN_IDX]; + qemu_fprintf(f, "w:%08x d:%016" PRIx64 " fd:%13g fs:%13g psu:%13g\= n", + tmp.w[FP_ENDIAN_IDX], tmp.d, + (double)tmp.fd, + (double)tmp.fs[FP_ENDIAN_IDX], + (double)tmp.fs[!FP_ENDIAN_IDX]); + } +} + static void fpu_dump_state(CPUMIPSState *env, FILE *f, int flags) { int i; int is_fpu64 =3D !!(env->hflags & MIPS_HFLAG_F64); =20 -#define printfpr(fp) \ - do { \ - if (is_fpu64) \ - qemu_fprintf(f, "w:%08x d:%016" PRIx64 \ - " fd:%13g fs:%13g psu: %13g\n", \ - (fp)->w[FP_ENDIAN_IDX], (fp)->d, \ - (double)(fp)->fd, \ - (double)(fp)->fs[FP_ENDIAN_IDX], \ - (double)(fp)->fs[!FP_ENDIAN_IDX]); \ - else { \ - fpr_t tmp; \ - tmp.w[FP_ENDIAN_IDX] =3D (fp)->w[FP_ENDIAN_IDX]; \ - tmp.w[!FP_ENDIAN_IDX] =3D ((fp) + 1)->w[FP_ENDIAN_IDX]; \ - qemu_fprintf(f, "w:%08x d:%016" PRIx64 \ - " fd:%13g fs:%13g psu:%13g\n", \ - tmp.w[FP_ENDIAN_IDX], tmp.d, \ - (double)tmp.fd, \ - (double)tmp.fs[FP_ENDIAN_IDX], \ - (double)tmp.fs[!FP_ENDIAN_IDX]); \ - } \ - } while (0) - - qemu_fprintf(f, "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%02= x\n", env->active_fpu.fcr0, env->active_fpu.fcr31, is_fpu64, get_float_exception_flags(&env->active_fpu.fp_status)); for (i =3D 0; i < 32; (is_fpu64) ? i++ : (i +=3D 2)) { qemu_fprintf(f, "%3s: ", fregnames[i]); - printfpr(&env->active_fpu.fpr[i]); + fpu_dump_fpr(&env->active_fpu.fpr[i], f, is_fpu64); } - -#undef printfpr } =20 static void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags) --=20 2.26.3 From nobody Sat May 4 03:43:33 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) client-ip=209.85.221.53; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f53.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1618859945; cv=none; d=zohomail.com; s=zohoarc; b=Z1s+/25pdmDMmwBPMQh8RB+MpPws/hjk90qhirRPgfALvJJusLgwjF5Kv7tpx6/Rm5nRbgtOvsJMIwjFVVfiZ+B33SnM98cgD/kEqh0KnOGiTzlymBj3iHEh/+rEOlykrf40zaKF0m8MH837E/mS2W+wGv2N2zNmhzQIZMcUoZU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618859945; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=eApDsHd46Y+IQH1RVKAdhqg7h/PQQ2n3i/53YZQWS2A=; b=drraBwnMPXZPvhBX20/b1fqBj8VIgOYx9Z5QFXpMMAcQDOCvi8S7zggxiP1FYfN9ZCkhYtPmwvz4Tf4q0uq4h/kfMxxC1YUMokL8ekQTcaOgG1/ROOB0nbwa38Qzb/OUw3RKxAuIEZx3QZb3OGFvsXAMsVqjg95lBtnimN0cmpU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-wr1-f53.google.com (mail-wr1-f53.google.com [209.85.221.53]) by mx.zohomail.com with SMTPS id 1618859945839587.6675239982914; Mon, 19 Apr 2021 12:19:05 -0700 (PDT) Received: by mail-wr1-f53.google.com with SMTP id h4so26140162wrt.12 for ; Mon, 19 Apr 2021 12:19:05 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.redhat.com (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id g12sm25363768wru.47.2021.04.19.12.19.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Apr 2021 12:19:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=eApDsHd46Y+IQH1RVKAdhqg7h/PQQ2n3i/53YZQWS2A=; b=edhyp5qg0Q7oudOcQoIIa2uDYJ0zoV4CQHKIgy1nJN2lqUGkH8XkCsQDdwjyzqo/I/ PeVKADO8ChahDVncMTX32gZeMwlEKz1EwRaOtdrr6wPiN0M1PFvF0hm9b2gq7rRCc4mg sY201XuuPuoy0d+tZ/V+Fq6vT26AjLzmp8tjBKV8Gm9rIF3lbC+2OWPd3Dzx5eAQltbq Kmpo5PCeD/jh+8VXMqffUiyPMSmjpi7Ma7zIX+MSLOpFM/BhxSMEnZzhPKHD18C0w8oW RUsSiRxMT+aE7a+KfpL6jCHZqBeW9XmYAOTjRcsTVuN0xOAQwwgqJeO2Pylehemu8T0W 0+hQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=eApDsHd46Y+IQH1RVKAdhqg7h/PQQ2n3i/53YZQWS2A=; b=IBH/NnHfdYrQMC/BDwxbqgN4CA3IQ/4jPPoaEC602YOeJovGyYdRYW/7BaH2ridBCw ktx6zhqC8sluGfdo6FaZ3s0xGwfHE/2N+Lca/6cCp0+mY4jawTZMDZsqNzhK6rjr9JON 2mEeteisAjCTj2RzHTwf1yIlq2zEvDZjDr4FJMGsKZ0ELdutsgBx5CjMcUOHzpqhdzgD MF7l4xqoA9BbUch/U5F8sWY+RKIq/uij8YykJl/BWt12Z8wwJHdzxHYG+gWKJwGUVV/S FpxBN3/Tyzn7CQE++vXfA9WMUA+6bl8AL+dQjJgCs9M7v7yxLLqVCd8gXSEf/V3TVRaj aCTg== X-Gm-Message-State: AOAM531l9NtEO3/fWFKAIkV/iCMD6eCYf0J1Ptu7qX2+6HaKzV1xh+x2 Cdy/81/xGOzDqrRekZuw+40= X-Google-Smtp-Source: ABdhPJxTi2NZ3EwXZS6MM7YlXgd0kM4dgGHlWbws3huczX9hs7weFKms+6SU53TZDBjMiU/MOpWJUg== X-Received: by 2002:adf:fdcd:: with SMTP id i13mr15875447wrs.185.1618859944079; Mon, 19 Apr 2021 12:19:04 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Aurelien Jarno , Huacai Chen Subject: [PATCH v3 08/30] target/mips: Declare mips_cpu_set_error_pc() inlined in "internal.h" Date: Mon, 19 Apr 2021 21:18:01 +0200 Message-Id: <20210419191823.1555482-9-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210419191823.1555482-1-f4bug@amsat.org> References: <20210419191823.1555482-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Rename set_pc() as mips_cpu_set_error_pc(), declare it inlined and use it in cpu.c and op_helper.c. Reported-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/internal.h | 11 +++++++++++ target/mips/cpu.c | 8 +------- target/mips/op_helper.c | 16 +++------------- 3 files changed, 15 insertions(+), 20 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 57072a941e7..81671d567d0 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -219,6 +219,17 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, /* op_helper.c */ void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagema= sk); =20 +static inline void mips_cpu_set_error_pc(CPUMIPSState *env, + target_ulong error_pc) +{ + env->active_tc.PC =3D error_pc & ~(target_ulong)1; + if (error_pc & 1) { + env->hflags |=3D MIPS_HFLAG_M16; + } else { + env->hflags &=3D ~(MIPS_HFLAG_M16); + } +} + static inline void restore_pamask(CPUMIPSState *env) { if (env->hflags & MIPS_HFLAG_ELPA) { diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 90ae232c8b8..fcbf95c85b9 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -327,14 +327,8 @@ void QEMU_NORETURN do_raise_exception_err(CPUMIPSState= *env, static void mips_cpu_set_pc(CPUState *cs, vaddr value) { MIPSCPU *cpu =3D MIPS_CPU(cs); - CPUMIPSState *env =3D &cpu->env; =20 - env->active_tc.PC =3D value & ~(target_ulong)1; - if (value & 1) { - env->hflags |=3D MIPS_HFLAG_M16; - } else { - env->hflags &=3D ~(MIPS_HFLAG_M16); - } + mips_cpu_set_error_pc(&cpu->env, value); } =20 #ifdef CONFIG_TCG diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index b80e8f75401..f7da8c83aee 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -993,24 +993,14 @@ static void debug_post_eret(CPUMIPSState *env) } } =20 -static void set_pc(CPUMIPSState *env, target_ulong error_pc) -{ - env->active_tc.PC =3D error_pc & ~(target_ulong)1; - if (error_pc & 1) { - env->hflags |=3D MIPS_HFLAG_M16; - } else { - env->hflags &=3D ~(MIPS_HFLAG_M16); - } -} - static inline void exception_return(CPUMIPSState *env) { debug_pre_eret(env); if (env->CP0_Status & (1 << CP0St_ERL)) { - set_pc(env, env->CP0_ErrorEPC); + mips_cpu_set_error_pc(env, env->CP0_ErrorEPC); env->CP0_Status &=3D ~(1 << CP0St_ERL); } else { - set_pc(env, env->CP0_EPC); + mips_cpu_set_error_pc(env, env->CP0_EPC); env->CP0_Status &=3D ~(1 << CP0St_EXL); } compute_hflags(env); @@ -1036,7 +1026,7 @@ void helper_deret(CPUMIPSState *env) env->hflags &=3D ~MIPS_HFLAG_DM; compute_hflags(env); =20 - set_pc(env, env->CP0_DEPC); + mips_cpu_set_error_pc(env, env->CP0_DEPC); =20 debug_post_eret(env); } --=20 2.26.3 From nobody Sat May 4 03:43:33 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.44 as permitted sender) client-ip=209.85.221.44; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f44.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.44 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1618859950; cv=none; d=zohomail.com; s=zohoarc; b=SJxR6/OgAoGXJCSqyEUfyHB+2RIyOm5htX1XwwyVw1spgLtx1LVVcG0hapuqsDAO5Iznxqqv4uH8g30Za5LIwH4eqXxBILVNP9r4eSXTKHJpS+qVkriBQT/fFqyUNcr626jV/jhY1rniz95qxpkw1QRgLV2UDjtHzbDIgB8OWuk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618859950; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=9idQeRNSVgpcYg4jC2bsnFCTDNB04ha1mM3lDtmDX/g=; b=lOHzKMM6EUdE7BIuIxxVXIawg26BsQzDdIRUbS2Meu6X0IeB77EKompFWcrHejjuBHTtb0VFGBIfki7nfYy+fqlpJKq98FaqjQircr0ob1QnvafQKp0Byxi3vVZZrzcccN5OJvVq9erF4hkWHHYiZT/BIm55R2w18NZ+EVv5qfs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.44 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-wr1-f44.google.com (mail-wr1-f44.google.com [209.85.221.44]) by mx.zohomail.com with SMTPS id 1618859950693744.5104996297501; Mon, 19 Apr 2021 12:19:10 -0700 (PDT) Received: by mail-wr1-f44.google.com with SMTP id r7so23165086wrm.1 for ; Mon, 19 Apr 2021 12:19:10 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.redhat.com (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id l20sm510160wmg.33.2021.04.19.12.19.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Apr 2021 12:19:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9idQeRNSVgpcYg4jC2bsnFCTDNB04ha1mM3lDtmDX/g=; b=P5yDUNz8mNDAqz0rIZlRpo2axmEAWEY3qKoo3bdVRneKgLv2e7rzKd/QsCBUbNH9Ta ZaFtJIqF3R+yE51h99H1284ogezoZOJFVFsDG//eI8L43OeFDkVdtC7bBG4FIZLU+FQr P/pcEz3mrJMU7SYUFNNZndBA6NiBmmzHAf4mVHwPhMOzDfEW+kI0269ADRdRhp1+Wd02 9FFtrnxAymmH4R4RmHz9NxUFH6uhk1w6m8S+wrzNBuRQgUCEEbjhG/wVSCnczZqYkZM/ Qk6qL16jjT2xmOshw045ZZZTabVOfguvKKUZgfLvfA1o0c6rHNJBAXDom7iYPyEZAtDY d1aA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=9idQeRNSVgpcYg4jC2bsnFCTDNB04ha1mM3lDtmDX/g=; b=iragL6s/yf3fPcCnMq8fp8ULaydYAwZzFQhNWFgdiewVKo0BOYVj5oTkoCpYFk8e2X /58j1kVMZwTGzJo4vdfr2vyZhx6wj/9zEMHyx1b0Bhd82OZfdgoJOE2gj/VG9jcISGBa 67HXx1ZUesUTQcHOYg2QbirpaSHoyvZUzzALQVqZZzAmFZzC7tdRp9xDx2E3hv9q9gyV NbPuxPPJfwvj4d5Y6mvhT//kzp6qwqVzw3lh0xEyNIvHRWTCxI8pt3eJ29MsWdhSwPlT zNurOAti+2Idg4d71s1bRtx4F5d49zG+2eCU0t5G5yLDhHlDo0gPwTHaIe1SxAeADNyY 0CvQ== X-Gm-Message-State: AOAM530eWWD1ioFzBrGx4Nfbp5DhhRFTsySNrSpbS326dyLaD4UKM4dR 6WGr9hU4aOmm4Auq4Txtkdg= X-Google-Smtp-Source: ABdhPJxH580qYZZS1oehqGPSKisZxVPPVdfdkSMzcmMSlYLGXGNCohYz1jpsw4Pzkr4yNftBfR70PA== X-Received: by 2002:adf:f106:: with SMTP id r6mr15982021wro.214.1618859948967; Mon, 19 Apr 2021 12:19:08 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Aurelien Jarno , Huacai Chen Subject: [PATCH v3 09/30] target/mips: Merge do_translate_address into cpu_mips_translate_address Date: Mon, 19 Apr 2021 21:18:02 +0200 Message-Id: <20210419191823.1555482-10-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210419191823.1555482-1-f4bug@amsat.org> References: <20210419191823.1555482-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Currently cpu_mips_translate_address() calls raise_mmu_exception(), and do_translate_address() calls cpu_loop_exit_restore(). This API split is dangerous, we could call cpu_mips_translate_address without returning to the main loop. As there is only one caller, it is trivial (and safer) to merge do_translate_address() back to cpu_mips_translate_address(). Reported-by: Richard Henderson Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/internal.h | 2 +- target/mips/op_helper.c | 20 ++------------------ target/mips/tlb_helper.c | 11 ++++++----- 3 files changed, 9 insertions(+), 24 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 81671d567d0..806d39fa6c3 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -148,7 +148,7 @@ void mips_cpu_do_transaction_failed(CPUState *cs, hwadd= r physaddr, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retadd= r); hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, - MMUAccessType access_type); + MMUAccessType access_type, uintptr_t ret= addr); #endif =20 #define cpu_signal_handler cpu_mips_signal_handler diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index f7da8c83aee..fdae5a3d687 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -287,23 +287,6 @@ target_ulong helper_rotx(target_ulong rs, uint32_t shi= ft, uint32_t shiftx, =20 #ifndef CONFIG_USER_ONLY =20 -static inline hwaddr do_translate_address(CPUMIPSState *env, - target_ulong address, - MMUAccessType access_type, - uintptr_t retaddr) -{ - hwaddr paddr; - CPUState *cs =3D env_cpu(env); - - paddr =3D cpu_mips_translate_address(env, address, access_type); - - if (paddr =3D=3D -1LL) { - cpu_loop_exit_restore(cs, retaddr); - } else { - return paddr; - } -} - #define HELPER_LD_ATOMIC(name, insn, almask, do_cast) = \ target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_id= x) \ { = \ @@ -313,7 +296,8 @@ target_ulong helper_##name(CPUMIPSState *env, target_ul= ong arg, int mem_idx) \ } = \ do_raise_exception(env, EXCP_AdEL, GETPC()); = \ } = \ - env->CP0_LLAddr =3D do_translate_address(env, arg, MMU_DATA_LOAD, GETP= C()); \ + env->CP0_LLAddr =3D cpu_mips_translate_address(env, arg, MMU_DATA_LOAD= , \ + GETPC()); = \ env->lladdr =3D arg; = \ env->llval =3D do_cast cpu_##insn##_mmuidx_ra(env, arg, mem_idx, GETPC= ()); \ return env->llval; = \ diff --git a/target/mips/tlb_helper.c b/target/mips/tlb_helper.c index 8d3ea497803..1ffdc1f8304 100644 --- a/target/mips/tlb_helper.c +++ b/target/mips/tlb_helper.c @@ -904,21 +904,22 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, =20 #ifndef CONFIG_USER_ONLY hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, - MMUAccessType access_type) + MMUAccessType access_type, uintptr_t ret= addr) { hwaddr physical; int prot; int ret =3D 0; + CPUState *cs =3D env_cpu(env); =20 /* data access */ ret =3D get_physical_address(env, &physical, &prot, address, access_ty= pe, cpu_mmu_index(env, false)); - if (ret !=3D TLBRET_MATCH) { - raise_mmu_exception(env, address, access_type, ret); - return -1LL; - } else { + if (ret =3D=3D TLBRET_MATCH) { return physical; } + + raise_mmu_exception(env, address, access_type, ret); + cpu_loop_exit_restore(cs, retaddr); } =20 static void set_hflags_for_handler(CPUMIPSState *env) --=20 2.26.3 From nobody Sat May 4 03:43:33 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.50 as permitted sender) client-ip=209.85.221.50; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f50.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.50 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1618859955; cv=none; d=zohomail.com; s=zohoarc; b=iUdP5H2XsLMuXX5erthZDUBMces6vDxQxyGB2u5654ZQP1IS3FLCDVxf9jX5AwC9yMgVAPjF43gbz36BmDxD23Oi4a/F0/vckZF4MxYnixau4MrLhVBgcWUGLq3NcSuQWxSK1u3VznVU/wBmFg1BbPVSlMmOGe0e2QLVqXWq28Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618859955; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=0UJDKlzgzSLuTe+b0euAM/mDik6TmWud0HLg5ODUMKE=; b=DsoX6V6un+a667CKs08D3BnOE+nk0prTwWuWamnDdm1bZ9gk4DqO6SYQY2U6W85MiVTBK8Qv3nmhj9gEwcRvQKiVPYcVckfORcaDR/wYEC2ttpnZBdUix3CKSiXyTWDH1DM7HO81SxQeEKQ6n8olWT6bldXFg+dy569M1ZbkMjQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.50 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f50.google.com (mail-wr1-f50.google.com [209.85.221.50]) by mx.zohomail.com with SMTPS id 1618859955663870.8394333523414; Mon, 19 Apr 2021 12:19:15 -0700 (PDT) Received: by mail-wr1-f50.google.com with SMTP id r7so23165272wrm.1 for ; Mon, 19 Apr 2021 12:19:15 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.redhat.com (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id q20sm1853689wmq.2.2021.04.19.12.19.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Apr 2021 12:19:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0UJDKlzgzSLuTe+b0euAM/mDik6TmWud0HLg5ODUMKE=; b=KNXRbnYZc/nOJkSTMGIn+Ib9VbvKEt4JUm78gqZDVwjVaOflpZ1Y4n9mctWqgHehs2 tlx2N8aH/1m+EbvdM5qIQR0677fev19lTl/8kJ5i2M1w1HdpqSs/47pCItIGPynLwtd2 sOG3bZGWIQ0sVFv5bQa0JF9EdC9u/32KgJIbCn8KWcjm/PbhrEUMxtLM6qcudkNdK6D8 QbHSonXnf1SPNf2Yacw3ZsW6pVbVF7D6SJsQjWxz5HPEIL6nZfqmo5rtF1RDVtH/WKN2 E/HGESRNOo8uACsz2wJVeYwfsulqm3l8sJy/IneVVWo1UnphiXNzK/Akelrgk6jZzJfk HVSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=0UJDKlzgzSLuTe+b0euAM/mDik6TmWud0HLg5ODUMKE=; b=nEev6jcrswCZIHggbWyk4sQvsWZtvi1w7JxyE7pExvw6hrDL2KnDzcBHFargECLCF4 cxSoQXj8k5DFGb8BvhRg002TWGzcs9gH7femgBoF+ReZSPn+2iWWKY+VMGmwqG3Iy0n/ W2/mi7XfMzNAXyH2LlMWBMaQhE2hRwGy3DI7giUz5UuoNQCAItYYY57LrIgLvTgxJerM FKBmP5Gd207PhsaEblfDFFQuKhxktKzOeAE51o5N+2WEnszMvQmIvjDPGl0aY0GPJ46K NCygdNOVVfcuyYVKnW0BTWOyAah6X07wHBGEmKf0piakAcTFOQGrjKgI0J13NIF6eIf7 pV/A== X-Gm-Message-State: AOAM530VUwKBPO1T8+zbnI0W2zHqnhV4IJsKZbvO6hnDqkfV+0MxBFY+ U4Q6t5HNRuNHckOhft3DZfk= X-Google-Smtp-Source: ABdhPJwwTIusEapjHA+7HEDN0cPOHkK1WfT4q6zVYO5xLv/GPy5HGihdxT+MwJRXkUfVSMoXNpLUGg== X-Received: by 2002:a5d:4488:: with SMTP id j8mr16310783wrq.83.1618859953790; Mon, 19 Apr 2021 12:19:13 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Aurelien Jarno , Huacai Chen Subject: [PATCH v3 10/30] target/mips: Extract load/store helpers to ldst_helper.c Date: Mon, 19 Apr 2021 21:18:03 +0200 Message-Id: <20210419191823.1555482-11-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210419191823.1555482-1-f4bug@amsat.org> References: <20210419191823.1555482-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/ldst_helper.c | 288 ++++++++++++++++++++++++++++++++++++++ target/mips/op_helper.c | 259 ---------------------------------- target/mips/meson.build | 1 + 3 files changed, 289 insertions(+), 259 deletions(-) create mode 100644 target/mips/ldst_helper.c diff --git a/target/mips/ldst_helper.c b/target/mips/ldst_helper.c new file mode 100644 index 00000000000..d42812b8a6a --- /dev/null +++ b/target/mips/ldst_helper.c @@ -0,0 +1,288 @@ +/* + * MIPS emulation load/store helpers for QEMU. + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * + * SPDX-License-Identifier: LGPL-2.1-or-later + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + * + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "exec/helper-proto.h" +#include "exec/exec-all.h" +#include "exec/memop.h" +#include "internal.h" + +#ifndef CONFIG_USER_ONLY + +#define HELPER_LD_ATOMIC(name, insn, almask, do_cast) = \ +target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_id= x) \ +{ = \ + if (arg & almask) { = \ + if (!(env->hflags & MIPS_HFLAG_DM)) { = \ + env->CP0_BadVAddr =3D arg; = \ + } = \ + do_raise_exception(env, EXCP_AdEL, GETPC()); = \ + } = \ + env->CP0_LLAddr =3D cpu_mips_translate_address(env, arg, MMU_DATA_LOAD= , \ + GETPC()); = \ + env->lladdr =3D arg; = \ + env->llval =3D do_cast cpu_##insn##_mmuidx_ra(env, arg, mem_idx, GETPC= ()); \ + return env->llval; = \ +} +HELPER_LD_ATOMIC(ll, ldl, 0x3, (target_long)(int32_t)) +#ifdef TARGET_MIPS64 +HELPER_LD_ATOMIC(lld, ldq, 0x7, (target_ulong)) +#endif +#undef HELPER_LD_ATOMIC + +#endif /* !CONFIG_USER_ONLY */ + +#ifdef TARGET_WORDS_BIGENDIAN +#define GET_LMASK(v) ((v) & 3) +#define GET_OFFSET(addr, offset) (addr + (offset)) +#else +#define GET_LMASK(v) (((v) & 3) ^ 3) +#define GET_OFFSET(addr, offset) (addr - (offset)) +#endif + +void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, + int mem_idx) +{ + cpu_stb_mmuidx_ra(env, arg2, (uint8_t)(arg1 >> 24), mem_idx, GETPC()); + + if (GET_LMASK(arg2) <=3D 2) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), + mem_idx, GETPC()); + } + + if (GET_LMASK(arg2) <=3D 1) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), + mem_idx, GETPC()); + } + + if (GET_LMASK(arg2) =3D=3D 0) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, + mem_idx, GETPC()); + } +} + +void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, + int mem_idx) +{ + cpu_stb_mmuidx_ra(env, arg2, (uint8_t)arg1, mem_idx, GETPC()); + + if (GET_LMASK(arg2) >=3D 1) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), + mem_idx, GETPC()); + } + + if (GET_LMASK(arg2) >=3D 2) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), + mem_idx, GETPC()); + } + + if (GET_LMASK(arg2) =3D=3D 3) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), + mem_idx, GETPC()); + } +} + +#if defined(TARGET_MIPS64) +/* + * "half" load and stores. We must do the memory access inline, + * or fault handling won't work. + */ +#ifdef TARGET_WORDS_BIGENDIAN +#define GET_LMASK64(v) ((v) & 7) +#else +#define GET_LMASK64(v) (((v) & 7) ^ 7) +#endif + +void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, + int mem_idx) +{ + cpu_stb_mmuidx_ra(env, arg2, (uint8_t)(arg1 >> 56), mem_idx, GETPC()); + + if (GET_LMASK64(arg2) <=3D 6) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), + mem_idx, GETPC()); + } + + if (GET_LMASK64(arg2) <=3D 5) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), + mem_idx, GETPC()); + } + + if (GET_LMASK64(arg2) <=3D 4) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), + mem_idx, GETPC()); + } + + if (GET_LMASK64(arg2) <=3D 3) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), + mem_idx, GETPC()); + } + + if (GET_LMASK64(arg2) <=3D 2) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), + mem_idx, GETPC()); + } + + if (GET_LMASK64(arg2) <=3D 1) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), + mem_idx, GETPC()); + } + + if (GET_LMASK64(arg2) <=3D 0) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, + mem_idx, GETPC()); + } +} + +void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, + int mem_idx) +{ + cpu_stb_mmuidx_ra(env, arg2, (uint8_t)arg1, mem_idx, GETPC()); + + if (GET_LMASK64(arg2) >=3D 1) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), + mem_idx, GETPC()); + } + + if (GET_LMASK64(arg2) >=3D 2) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), + mem_idx, GETPC()); + } + + if (GET_LMASK64(arg2) >=3D 3) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), + mem_idx, GETPC()); + } + + if (GET_LMASK64(arg2) >=3D 4) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), + mem_idx, GETPC()); + } + + if (GET_LMASK64(arg2) >=3D 5) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), + mem_idx, GETPC()); + } + + if (GET_LMASK64(arg2) >=3D 6) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), + mem_idx, GETPC()); + } + + if (GET_LMASK64(arg2) =3D=3D 7) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), + mem_idx, GETPC()); + } +} +#endif /* TARGET_MIPS64 */ + +static const int multiple_regs[] =3D { 16, 17, 18, 19, 20, 21, 22, 23, 30 = }; + +void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, + uint32_t mem_idx) +{ + target_ulong base_reglist =3D reglist & 0xf; + target_ulong do_r31 =3D reglist & 0x10; + + if (base_reglist > 0 && base_reglist <=3D ARRAY_SIZE(multiple_regs)) { + target_ulong i; + + for (i =3D 0; i < base_reglist; i++) { + env->active_tc.gpr[multiple_regs[i]] =3D + (target_long)cpu_ldl_mmuidx_ra(env, addr, mem_idx, GETPC()= ); + addr +=3D 4; + } + } + + if (do_r31) { + env->active_tc.gpr[31] =3D + (target_long)cpu_ldl_mmuidx_ra(env, addr, mem_idx, GETPC()); + } +} + +void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, + uint32_t mem_idx) +{ + target_ulong base_reglist =3D reglist & 0xf; + target_ulong do_r31 =3D reglist & 0x10; + + if (base_reglist > 0 && base_reglist <=3D ARRAY_SIZE(multiple_regs)) { + target_ulong i; + + for (i =3D 0; i < base_reglist; i++) { + cpu_stw_mmuidx_ra(env, addr, env->active_tc.gpr[multiple_regs[= i]], + mem_idx, GETPC()); + addr +=3D 4; + } + } + + if (do_r31) { + cpu_stw_mmuidx_ra(env, addr, env->active_tc.gpr[31], mem_idx, GETP= C()); + } +} + +#if defined(TARGET_MIPS64) +void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, + uint32_t mem_idx) +{ + target_ulong base_reglist =3D reglist & 0xf; + target_ulong do_r31 =3D reglist & 0x10; + + if (base_reglist > 0 && base_reglist <=3D ARRAY_SIZE(multiple_regs)) { + target_ulong i; + + for (i =3D 0; i < base_reglist; i++) { + env->active_tc.gpr[multiple_regs[i]] =3D + cpu_ldq_mmuidx_ra(env, addr, mem_idx, GETPC()); + addr +=3D 8; + } + } + + if (do_r31) { + env->active_tc.gpr[31] =3D + cpu_ldq_mmuidx_ra(env, addr, mem_idx, GETPC()); + } +} + +void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, + uint32_t mem_idx) +{ + target_ulong base_reglist =3D reglist & 0xf; + target_ulong do_r31 =3D reglist & 0x10; + + if (base_reglist > 0 && base_reglist <=3D ARRAY_SIZE(multiple_regs)) { + target_ulong i; + + for (i =3D 0; i < base_reglist; i++) { + cpu_stq_mmuidx_ra(env, addr, env->active_tc.gpr[multiple_regs[= i]], + mem_idx, GETPC()); + addr +=3D 8; + } + } + + if (do_r31) { + cpu_stq_mmuidx_ra(env, addr, env->active_tc.gpr[31], mem_idx, GETP= C()); + } +} + +#endif /* TARGET_MIPS64 */ diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index fdae5a3d687..47d67053f4b 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -285,265 +285,6 @@ target_ulong helper_rotx(target_ulong rs, uint32_t sh= ift, uint32_t shiftx, return (int64_t)(int32_t)(uint32_t)tmp5; } =20 -#ifndef CONFIG_USER_ONLY - -#define HELPER_LD_ATOMIC(name, insn, almask, do_cast) = \ -target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_id= x) \ -{ = \ - if (arg & almask) { = \ - if (!(env->hflags & MIPS_HFLAG_DM)) { = \ - env->CP0_BadVAddr =3D arg; = \ - } = \ - do_raise_exception(env, EXCP_AdEL, GETPC()); = \ - } = \ - env->CP0_LLAddr =3D cpu_mips_translate_address(env, arg, MMU_DATA_LOAD= , \ - GETPC()); = \ - env->lladdr =3D arg; = \ - env->llval =3D do_cast cpu_##insn##_mmuidx_ra(env, arg, mem_idx, GETPC= ()); \ - return env->llval; = \ -} -HELPER_LD_ATOMIC(ll, ldl, 0x3, (target_long)(int32_t)) -#ifdef TARGET_MIPS64 -HELPER_LD_ATOMIC(lld, ldq, 0x7, (target_ulong)) -#endif -#undef HELPER_LD_ATOMIC -#endif - -#ifdef TARGET_WORDS_BIGENDIAN -#define GET_LMASK(v) ((v) & 3) -#define GET_OFFSET(addr, offset) (addr + (offset)) -#else -#define GET_LMASK(v) (((v) & 3) ^ 3) -#define GET_OFFSET(addr, offset) (addr - (offset)) -#endif - -void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, - int mem_idx) -{ - cpu_stb_mmuidx_ra(env, arg2, (uint8_t)(arg1 >> 24), mem_idx, GETPC()); - - if (GET_LMASK(arg2) <=3D 2) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), - mem_idx, GETPC()); - } - - if (GET_LMASK(arg2) <=3D 1) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), - mem_idx, GETPC()); - } - - if (GET_LMASK(arg2) =3D=3D 0) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, - mem_idx, GETPC()); - } -} - -void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, - int mem_idx) -{ - cpu_stb_mmuidx_ra(env, arg2, (uint8_t)arg1, mem_idx, GETPC()); - - if (GET_LMASK(arg2) >=3D 1) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), - mem_idx, GETPC()); - } - - if (GET_LMASK(arg2) >=3D 2) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), - mem_idx, GETPC()); - } - - if (GET_LMASK(arg2) =3D=3D 3) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), - mem_idx, GETPC()); - } -} - -#if defined(TARGET_MIPS64) -/* - * "half" load and stores. We must do the memory access inline, - * or fault handling won't work. - */ -#ifdef TARGET_WORDS_BIGENDIAN -#define GET_LMASK64(v) ((v) & 7) -#else -#define GET_LMASK64(v) (((v) & 7) ^ 7) -#endif - -void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, - int mem_idx) -{ - cpu_stb_mmuidx_ra(env, arg2, (uint8_t)(arg1 >> 56), mem_idx, GETPC()); - - if (GET_LMASK64(arg2) <=3D 6) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), - mem_idx, GETPC()); - } - - if (GET_LMASK64(arg2) <=3D 5) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), - mem_idx, GETPC()); - } - - if (GET_LMASK64(arg2) <=3D 4) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), - mem_idx, GETPC()); - } - - if (GET_LMASK64(arg2) <=3D 3) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), - mem_idx, GETPC()); - } - - if (GET_LMASK64(arg2) <=3D 2) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), - mem_idx, GETPC()); - } - - if (GET_LMASK64(arg2) <=3D 1) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), - mem_idx, GETPC()); - } - - if (GET_LMASK64(arg2) <=3D 0) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, - mem_idx, GETPC()); - } -} - -void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, - int mem_idx) -{ - cpu_stb_mmuidx_ra(env, arg2, (uint8_t)arg1, mem_idx, GETPC()); - - if (GET_LMASK64(arg2) >=3D 1) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), - mem_idx, GETPC()); - } - - if (GET_LMASK64(arg2) >=3D 2) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), - mem_idx, GETPC()); - } - - if (GET_LMASK64(arg2) >=3D 3) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), - mem_idx, GETPC()); - } - - if (GET_LMASK64(arg2) >=3D 4) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), - mem_idx, GETPC()); - } - - if (GET_LMASK64(arg2) >=3D 5) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), - mem_idx, GETPC()); - } - - if (GET_LMASK64(arg2) >=3D 6) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), - mem_idx, GETPC()); - } - - if (GET_LMASK64(arg2) =3D=3D 7) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), - mem_idx, GETPC()); - } -} -#endif /* TARGET_MIPS64 */ - -static const int multiple_regs[] =3D { 16, 17, 18, 19, 20, 21, 22, 23, 30 = }; - -void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, - uint32_t mem_idx) -{ - target_ulong base_reglist =3D reglist & 0xf; - target_ulong do_r31 =3D reglist & 0x10; - - if (base_reglist > 0 && base_reglist <=3D ARRAY_SIZE(multiple_regs)) { - target_ulong i; - - for (i =3D 0; i < base_reglist; i++) { - env->active_tc.gpr[multiple_regs[i]] =3D - (target_long)cpu_ldl_mmuidx_ra(env, addr, mem_idx, GETPC()= ); - addr +=3D 4; - } - } - - if (do_r31) { - env->active_tc.gpr[31] =3D - (target_long)cpu_ldl_mmuidx_ra(env, addr, mem_idx, GETPC()); - } -} - -void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, - uint32_t mem_idx) -{ - target_ulong base_reglist =3D reglist & 0xf; - target_ulong do_r31 =3D reglist & 0x10; - - if (base_reglist > 0 && base_reglist <=3D ARRAY_SIZE(multiple_regs)) { - target_ulong i; - - for (i =3D 0; i < base_reglist; i++) { - cpu_stw_mmuidx_ra(env, addr, env->active_tc.gpr[multiple_regs[= i]], - mem_idx, GETPC()); - addr +=3D 4; - } - } - - if (do_r31) { - cpu_stw_mmuidx_ra(env, addr, env->active_tc.gpr[31], mem_idx, GETP= C()); - } -} - -#if defined(TARGET_MIPS64) -void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, - uint32_t mem_idx) -{ - target_ulong base_reglist =3D reglist & 0xf; - target_ulong do_r31 =3D reglist & 0x10; - - if (base_reglist > 0 && base_reglist <=3D ARRAY_SIZE(multiple_regs)) { - target_ulong i; - - for (i =3D 0; i < base_reglist; i++) { - env->active_tc.gpr[multiple_regs[i]] =3D - cpu_ldq_mmuidx_ra(env, addr, mem_idx, GETPC()); - addr +=3D 8; - } - } - - if (do_r31) { - env->active_tc.gpr[31] =3D - cpu_ldq_mmuidx_ra(env, addr, mem_idx, GETPC()); - } -} - -void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, - uint32_t mem_idx) -{ - target_ulong base_reglist =3D reglist & 0xf; - target_ulong do_r31 =3D reglist & 0x10; - - if (base_reglist > 0 && base_reglist <=3D ARRAY_SIZE(multiple_regs)) { - target_ulong i; - - for (i =3D 0; i < base_reglist; i++) { - cpu_stq_mmuidx_ra(env, addr, env->active_tc.gpr[multiple_regs[= i]], - mem_idx, GETPC()); - addr +=3D 8; - } - } - - if (do_r31) { - cpu_stq_mmuidx_ra(env, addr, env->active_tc.gpr[31], mem_idx, GETP= C()); - } -} -#endif - - void helper_fork(target_ulong arg1, target_ulong arg2) { /* diff --git a/target/mips/meson.build b/target/mips/meson.build index daf5f1d55bc..15c2f835c68 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -18,6 +18,7 @@ mips_tcg_ss.add(files( 'dsp_helper.c', 'fpu_helper.c', + 'ldst_helper.c', 'lmmi_helper.c', 'msa_helper.c', 'msa_translate.c', --=20 2.26.3 From nobody Sat May 4 03:43:33 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.41 as permitted sender) client-ip=209.85.221.41; envelope-from=philippe.mathieu.daude@gmail.com; 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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id a15sm23526464wrr.53.2021.04.19.12.19.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Apr 2021 12:19:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cJdBKLIJjo1FmzN1QJg7i4Ge0av2J5mMxKO6UU2xPVo=; b=mJHteTGRM38Lmzt3jI75uB38PZtPz2CrR9LM8L3P/dktPfOE32D03D1+e3A38/2yyv Z8xfdSlnZ8EBX6mTOyV8xzmeT5t5ZPwgUxpn8FtyW3SwQSK86Seayx0n5EjMOLqjvaTT b/DY5ROx0Sff7+v94EjS0nOX5X+MeseeTQMuZZplrzvhPa/yH1FpGhJjZv3Rma1Bwa9W Wz/JQa4dBxuFYz0LXWOJGx0C7ZJRoEcaMZNXxJ+58dwtBmgKhSdA8WxrXPnhfCnU8dYo q92apr1NjXaU8g1BIVbKFI6w/9KgIZMUlHfuv6LC/Zehkb2vu33UHRMe6EEanE6ctBab sgZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=cJdBKLIJjo1FmzN1QJg7i4Ge0av2J5mMxKO6UU2xPVo=; b=PZRF+K4lSvUd6zx4INzsX03mCOgiz82DXVPxOfpnrpnFjN0vInOYuYRdP7WcrHZbMk bfkjiQIY1jl44hQ2PHk1qKM/SxWh8WDAsYsl5cm9a7czsmG+SGY8g/SnkkCXlylTIk4r OmttZMTQi/cVDCy/YZjxsSJGoTme7YFZiKRWRa5G4/VVdMcuEydunGfKngVGhT85bAGA pw74wECDEJcAoVjpO33x0WBqL2vvdeC/OpL68wQiJzvfxX4H0rka6oMRaAvu3XlyQ4cx 0Zlq+9sDc5It0sdtdd+qpeDxo4Tx9Jxu5oifsfHYrMtRQmLsc6xbkdlAb9N/FLUkoOuE W7aw== X-Gm-Message-State: AOAM533jqlvb15kieOYjsz10Vc/yDe7NB2S3KhFitwGxtFzGXvfieCx+ +sAHMSyElmUEC/clk54C7Vk= X-Google-Smtp-Source: ABdhPJwce4mlpeV6e81Yvg2irFmr+1s/seP+nqUxjLRwZaOIcOjE/4EzU7NsY7QKT7CDI/mbXMj+Vw== X-Received: by 2002:adf:e583:: with SMTP id l3mr16725135wrm.63.1618859958721; Mon, 19 Apr 2021 12:19:18 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Aurelien Jarno , Huacai Chen , Paolo Bonzini Subject: [PATCH v3 11/30] meson: Introduce meson_user_arch source set for arch-specific user-mode Date: Mon, 19 Apr 2021 21:18:04 +0200 Message-Id: <20210419191823.1555482-12-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210419191823.1555482-1-f4bug@amsat.org> References: <20210419191823.1555482-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Similarly to the 'target_softmmu_arch' source set which allows to restrict target-specific sources to system emulation, add the equivalent 'target_user_arch' set for user emulation. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- v2: meson_user_arch -> target_user_arch in description (rth) Cc: Paolo Bonzini --- meson.build | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/meson.build b/meson.build index d8bb1ec5aa9..1ffdc9e6c4e 100644 --- a/meson.build +++ b/meson.build @@ -1751,6 +1751,7 @@ hw_arch =3D {} target_arch =3D {} target_softmmu_arch =3D {} +target_user_arch =3D {} =20 ############### # Trace files # @@ -2168,6 +2169,11 @@ abi =3D config_target['TARGET_ABI_DIR'] target_type=3D'user' qemu_target_name =3D 'qemu-' + target_name + if arch in target_user_arch + t =3D target_user_arch[arch].apply(config_target, strict: false) + arch_srcs +=3D t.sources() + arch_deps +=3D t.dependencies() + endif if 'CONFIG_LINUX_USER' in config_target base_dir =3D 'linux-user' target_inc +=3D include_directories('linux-user/host/' / config_host= ['ARCH']) --=20 2.26.3 From nobody Sat May 4 03:43:33 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.49 as permitted sender) client-ip=209.85.221.49; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f49.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.49 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1618859965; cv=none; d=zohomail.com; s=zohoarc; b=WD5CdHdSI80MoeAfYd+TyAUVrrhWJ+7/LJX865ph3t1eQuS50WJsupZCxTh+E9rg94HO9nR0lc47I5RHNkXCqzwr2fqwR6UAfNZMEHOKbse2fhFWKLONmSJfvGpFzs32A/ILDWE7bx6vuR9EhJJO7zmCl1ssJ1rAwP6wxWlb7v0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618859965; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=fed/u7MVzry73SqP8iio3AZoUczbP2euKtzU1T6r66I=; b=O+ikvlwfTTc5QnkFBMZqWRtJp5ntuxFu6D/FYnYb7JyEuexUE5jHhyMtcpD/h1OpnNyEMk23t39QNI5ELJpq+4BBQPqSuDyFuwYxV5ztTlagUEBwW4HMu3o9gWNlOGV2aU/TW4h0fkJE/zr/b/roqL2x/kKfQR6Eth581XxSqYc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.49 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f49.google.com (mail-wr1-f49.google.com [209.85.221.49]) by mx.zohomail.com with SMTPS id 1618859965259107.60505891388505; Mon, 19 Apr 2021 12:19:25 -0700 (PDT) Received: by mail-wr1-f49.google.com with SMTP id g9so19153223wrx.0 for ; Mon, 19 Apr 2021 12:19:24 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.redhat.com (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id e9sm24923561wrs.84.2021.04.19.12.19.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Apr 2021 12:19:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fed/u7MVzry73SqP8iio3AZoUczbP2euKtzU1T6r66I=; b=SVPNoQy5C2O3nCxebE9YFtNTEr6CdeHOEVl08Qh8oQ1etTJyiwkYZH9rym8YEOcy/q Kht/G/jHkWKdLFgKKw3ZNmedE1B3z5b7W7Mfsob1B4biITfw8kAE4UrU+0JAkYFUoyMZ YktvRaJjjEHbUbNsZyJqotxZN5fMUag1Neh4UZlTYeCx4qzrlnCJpgSeYOGA0g1CPKW9 DR5IUL7T6O2ex+gh1Yqa4eMeFfa5BvsWZh4v8/4yt8P4Gn0vFKj0lL4OOeJcWS++0soh 4zBNxV6FwgZrzeQXpuMES1MgF6Z8leih9FhnZ6FzoBZArF112eevUU0l22327Ae1Iqdy Yz1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=fed/u7MVzry73SqP8iio3AZoUczbP2euKtzU1T6r66I=; b=F4sya50b7UDp6kNUsWPEm4N3mkEt16YXzCCmjE5ee0CnOGmdUPGQXdh4yEhGMQ08Ql uzC/aDktaWHP/b/gfUSZ2T02sxLnr+aiOkoOqsbMBzAIQuTjzCUecuvlmnUXlNIloF8m R8aD0dr18Swvjk1QeT7dRqwY0CMPPkTUvTUn6eWrMUnq5nWHRAp4xkgQYL822wgtdkrb /kCAOwpxoBcwH7sqX0pTztevtyknTQriwxHOMi+FdyhaKKxKLN8Mb3JP6qUw02puA1Zz HYYIJvt7ybiK5S+2NXWSxbKBe/Y7z+2Ja8mAAuuZUqYEcfGuvLOrNIwQ5Jd7SAbjzYxY a6oA== X-Gm-Message-State: AOAM531GZpXZli9EW+1d4RtzU3+lkYl733IjZs45eqVQOSsMCazBKynW 6bK9f3BCJAxcRHm0GZJR9L0= X-Google-Smtp-Source: ABdhPJzO+SOFeUAxD9HhFqvdVRQTCVfUWgSK1ecmQtsfv6MIyQPjn2ggfOUFTNEJ/1wYKzWPV/IGYw== X-Received: by 2002:adf:f40f:: with SMTP id g15mr16175927wro.46.1618859963596; Mon, 19 Apr 2021 12:19:23 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Aurelien Jarno , Huacai Chen Subject: [PATCH v3 12/30] target/mips: Introduce tcg-internal.h for TCG specific declarations Date: Mon, 19 Apr 2021 21:18:05 +0200 Message-Id: <20210419191823.1555482-13-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210419191823.1555482-1-f4bug@amsat.org> References: <20210419191823.1555482-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) We will gradually move TCG-specific declarations to a new local header: "tcg-internal.h". To keep review simple, first add this header with 2 TCG prototypes, which we are going to move in the next 2 commits. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/internal.h | 7 +++---- target/mips/tcg/tcg-internal.h | 20 ++++++++++++++++++++ 2 files changed, 23 insertions(+), 4 deletions(-) create mode 100644 target/mips/tcg/tcg-internal.h diff --git a/target/mips/internal.h b/target/mips/internal.h index 806d39fa6c3..9e86f6ad6b7 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -9,6 +9,9 @@ #define MIPS_INTERNAL_H =20 #include "exec/memattrs.h" +#ifdef CONFIG_TCG +#include "tcg/tcg-internal.h" +#endif =20 /* * MMU types, the first four entries have the same layout as the @@ -77,7 +80,6 @@ extern const char fregnames[32][4]; extern const struct mips_def_t mips_defs[]; extern const int mips_defs_number; =20 -void mips_cpu_do_interrupt(CPUState *cpu); bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); @@ -212,9 +214,6 @@ void cpu_mips_stop_count(CPUMIPSState *env); =20 /* helper.c */ void mmu_init(CPUMIPSState *env, const mips_def_t *def); -bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); =20 /* op_helper.c */ void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagema= sk); diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h new file mode 100644 index 00000000000..24438667f47 --- /dev/null +++ b/target/mips/tcg/tcg-internal.h @@ -0,0 +1,20 @@ +/* + * MIPS internal definitions and helpers (TCG accelerator) + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef MIPS_TCG_INTERNAL_H +#define MIPS_TCG_INTERNAL_H + +#include "hw/core/cpu.h" + +void mips_cpu_do_interrupt(CPUState *cpu); +bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); + +#endif --=20 2.26.3 From nobody Sat May 4 03:43:33 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.47 as permitted sender) client-ip=209.85.221.47; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f47.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.47 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1618859970; cv=none; d=zohomail.com; s=zohoarc; b=kBO49g9gAldxjOgELNKcRWNLkHVwcX7160jUCu0m39E3FTgbD/a9QWSbCNPzGImFLhh1cmNkQLAt2vzfg7KjAYqCI6epqXvJD2MEjPCjeCfxtlo2r2MkwswnSbQunbiMQG7r+a8raJ6ZbhlPhgAol0IUcFmKqN5grhYKhX0UkIE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618859970; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=wBgfHHnAxbNIphhMkiJAhztZRfqVBkkDkTzuqRjNmCs=; b=Lyjhqj6r5rn+aREZGenz/ht+VllHKpAVTmxx01hV2611LGPQkh1zLL8aDJLiNsLMs/OCHr6aWypaJLnFVX020kCFG3/3j/81bR4m4aK6O6pBQqqXfhIaOoPSKSoTxiZ1ROQUSNgu7oZbKABrb7unyewvsbPy0gfw7u14qbMEwfM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.47 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f47.google.com (mail-wr1-f47.google.com [209.85.221.47]) by mx.zohomail.com with SMTPS id 1618859970319448.1186397595494; Mon, 19 Apr 2021 12:19:30 -0700 (PDT) Received: by mail-wr1-f47.google.com with SMTP id h4so26141201wrt.12 for ; Mon, 19 Apr 2021 12:19:29 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.redhat.com (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id v7sm24597520wrs.2.2021.04.19.12.19.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Apr 2021 12:19:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wBgfHHnAxbNIphhMkiJAhztZRfqVBkkDkTzuqRjNmCs=; b=aWPqm2HMmqpaddzRrak+vsB4Sqm5KKw1x4SgeqMy5Ur3Bw12i4pvBZXIA5FLiBjaCl xxWaE4LT9gu9CwPsOzrXClwbOK6Hsl9xdN+muOKUhIo6EJkFg9UEc9WALLyCN9rz6XUe bQmitEf3gK59NpIjIHJSDfQWe39iBIqDJOrebjk+g1IwHRgh4DezYCgUbgxCw1yS67KT HTasrthhrKGK8C6BLyVo4bQEXfNsxPDFtWE6tNBalxEnBdOOLU9C+06oIeRp5G/m2N9v VJxE6K0+TlTrJ5NZUaTiPzTJw3EIk21z97prfPpFOlvfNqF3rXDCSRQzpuvsFF1YyGq/ wbUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=wBgfHHnAxbNIphhMkiJAhztZRfqVBkkDkTzuqRjNmCs=; b=h1N41Qe44OaTq/RqKGT/hK1JMvlerS1jB49d279vnF9SnBnxSChzjn1A+BO8jvpKY2 RC2Qcj7kGSYgZTIeCgy+Nq8tAClODG27EVnnnwCtREM/3iuQ5cYV0/jLH9gJgzupgJyD 8cl+EX9U7VnbHor60t4Dqcpc3uJvOKLp/HcUOo2HZzi+evrafvFtOzACzhr8Ia6iZbfy rngHQ+/dbqxaRKBaBiO4UQfi+IFiIczLggyk5wULfXn7+h1DV1EQ6mcCNn3LNEqfej2l 0e0zoTpshCSqZmlLnkyKITTX2Mju+Aj/2yK4dJ7FFGAqtLRAYzieNG7ABsLnaWi2zNsh 77zg== X-Gm-Message-State: AOAM532HjuIb9MlBTNMnt5eXCxDOnUPg64+SMB18+DBXEwGa5ptG0NHP HZB+HB8zNVxuXgjBGirKydY= X-Google-Smtp-Source: ABdhPJwYv7ArzhW5LrBH8XoCnOzN8H9I6ay4nkBGLGf9MTDPjNcqUN7/WUK6uTgBNzN0Sauq+zCnvw== X-Received: by 2002:a5d:4e81:: with SMTP id e1mr16259090wru.305.1618859968505; Mon, 19 Apr 2021 12:19:28 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Aurelien Jarno , Huacai Chen Subject: [PATCH v3 13/30] target/mips: Add simple user-mode mips_cpu_do_interrupt() Date: Mon, 19 Apr 2021 21:18:06 +0200 Message-Id: <20210419191823.1555482-14-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210419191823.1555482-1-f4bug@amsat.org> References: <20210419191823.1555482-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) The #ifdef'ry hides that the user-mode implementation of mips_cpu_do_interrupt() simply sets exception_index =3D EXCP_NONE. Add this simple implementation to tcg/user/tlb_helper.c, and the corresponding Meson machinery to build this file when user emulation is configured. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- v2: Renamed helper.c -> tlb_helper.c (rth) --- target/mips/tcg/user/tlb_helper.c | 28 ++++++++++++++++++++++++++++ target/mips/tlb_helper.c | 5 ----- target/mips/meson.build | 5 +++++ target/mips/tcg/meson.build | 3 +++ target/mips/tcg/user/meson.build | 3 +++ 5 files changed, 39 insertions(+), 5 deletions(-) create mode 100644 target/mips/tcg/user/tlb_helper.c create mode 100644 target/mips/tcg/meson.build create mode 100644 target/mips/tcg/user/meson.build diff --git a/target/mips/tcg/user/tlb_helper.c b/target/mips/tcg/user/tlb_h= elper.c new file mode 100644 index 00000000000..453b9e9b930 --- /dev/null +++ b/target/mips/tcg/user/tlb_helper.c @@ -0,0 +1,28 @@ +/* + * MIPS TLB (Translation lookaside buffer) helpers. + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ +#include "qemu/osdep.h" + +#include "cpu.h" +#include "exec/exec-all.h" +#include "internal.h" + +void mips_cpu_do_interrupt(CPUState *cs) +{ + cs->exception_index =3D EXCP_NONE; +} diff --git a/target/mips/tlb_helper.c b/target/mips/tlb_helper.c index 1ffdc1f8304..78720c4d20a 100644 --- a/target/mips/tlb_helper.c +++ b/target/mips/tlb_helper.c @@ -965,11 +965,8 @@ static inline void set_badinstr_registers(CPUMIPSState= *env) } } =20 -#endif /* !CONFIG_USER_ONLY */ - void mips_cpu_do_interrupt(CPUState *cs) { -#if !defined(CONFIG_USER_ONLY) MIPSCPU *cpu =3D MIPS_CPU(cs); CPUMIPSState *env =3D &cpu->env; bool update_badinstr =3D 0; @@ -1272,11 +1269,9 @@ void mips_cpu_do_interrupt(CPUState *cs) env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr, env->CP0_DEPC); } -#endif cs->exception_index =3D EXCP_NONE; } =20 -#if !defined(CONFIG_USER_ONLY) void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra) { CPUState *cs =3D env_cpu(env); diff --git a/target/mips/meson.build b/target/mips/meson.build index 15c2f835c68..ca3cc62cf7a 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -6,6 +6,7 @@ decodetree.process('tx79.decode', extra_args: '--static-decode=3Ddecode_= tx79'), ] =20 +mips_user_ss =3D ss.source_set() mips_ss =3D ss.source_set() mips_ss.add(files( 'cpu.c', @@ -34,6 +35,9 @@ ), if_false: files( 'mxu_translate.c', )) +if 'CONFIG_TCG' in config_all + subdir('tcg') +endif =20 mips_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) =20 @@ -52,3 +56,4 @@ =20 target_arch +=3D {'mips': mips_ss} target_softmmu_arch +=3D {'mips': mips_softmmu_ss} +target_user_arch +=3D {'mips': mips_user_ss} diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build new file mode 100644 index 00000000000..b74fa04303e --- /dev/null +++ b/target/mips/tcg/meson.build @@ -0,0 +1,3 @@ +if have_user + subdir('user') +endif diff --git a/target/mips/tcg/user/meson.build b/target/mips/tcg/user/meson.= build new file mode 100644 index 00000000000..79badcd3217 --- /dev/null +++ b/target/mips/tcg/user/meson.build @@ -0,0 +1,3 @@ +mips_user_ss.add(files( + 'tlb_helper.c', +)) --=20 2.26.3 From nobody Sat May 4 03:43:33 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.52 as permitted sender) client-ip=209.85.221.52; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f52.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.52 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1618859975; cv=none; d=zohomail.com; s=zohoarc; b=G7G0DBwC17z9/a0lYtHoXzbN3FjzMe/wEPfYsVQm8iP9M53q1EpurV9u4agLhjrjjlQXviKQFys3R8PHA4t7svFzVdwmIsC3qZPw0yCPu8BW5q1DrSxEyECMCxRnngEW+lqxRiUzghRSio1DoBSUwnGcsd2S59a2jJkL4wzMwN0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618859975; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=7OS6JG9BL3+LnpLCM/Z0MR7VlobeUEBPsxpBEJslEbA=; b=hTL75op0U/SL1zQAX902kFX6Msy/2wxtA/Mt4Z/VMmhmhvQ+CG7bNvoDD0U5b5nlEs+ouj5F76ACILTgW1uuVXm9FZmPEXl8hxlJdBp9jNo/9TTkN6gxnA2BJkPEo7+Jw7NONZngfydgkbWuNh6HNBKrI/KHKiTtX48bsRvHOis= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.52 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f52.google.com (mail-wr1-f52.google.com [209.85.221.52]) by mx.zohomail.com with SMTPS id 1618859975624160.24295250868454; Mon, 19 Apr 2021 12:19:35 -0700 (PDT) Received: by mail-wr1-f52.google.com with SMTP id x7so35153279wrw.10 for ; Mon, 19 Apr 2021 12:19:35 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.redhat.com (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id 18sm527650wmo.47.2021.04.19.12.19.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Apr 2021 12:19:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7OS6JG9BL3+LnpLCM/Z0MR7VlobeUEBPsxpBEJslEbA=; b=uyES6ySc2HcRVFh6U2kXt/V9WNKAAR8pc+c+OF30XeeknGfr7BSHuebRrzcpEHNohh Dj6xruh2R0kWVvKAYJdcFFKYZ3jch4ijO2Szp6ReotmOWBk0dbS4s72UfECOU+0qLnVh u0NOI4luX97VLX50+MAkgbLVq6M9EVZgSK35b9dHlXKIVumo1Di/DYmFs3U3RxFg3k/a FP4f3GYA0vz5Xqpe66B+f+Wigs8xGw3dSdIs485EZsxtEcZecHg8b5GadSOMAt7QUycx sEJ2UwNHX6KR8rVsrr5+smWmplNpnfAq1DAgLX9EnJVrx7rgvvdg6SpzhfMAWiVbolHV bqPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=7OS6JG9BL3+LnpLCM/Z0MR7VlobeUEBPsxpBEJslEbA=; b=cOR424FXkBtfIGN+LoOqhPUS+wnFWNkgJLSdm4kFGsFG+4myWd8v6KeDKc9R8CM37k ItOxrI6FkF0EXJ1lbvUeo4gn5o3lW7xgWSdVunF3hXNiNrhYRo93XrX+cGWNLoMdl+q8 jU5/YQAtB/eS4Wcx0Gs3LNbJtIGycU6FvxO+Sz2HPqV/x6q1dMdTyzUjBWf7xKadw9Mp 5F1UQzEyzOw/JxZCSLXHbBQ5WE3n28JKIBOCg/t94Lm0NZGMWBF7su2Hm7bjvx3h3I7q JgcQuYeWIDEPpoakRq1EaVTgDV4efC5ImTV+TPdzGuHZk85oYOa73mDAzfxZCzoFJLZ0 PD5A== X-Gm-Message-State: AOAM5302tPumw82FRAa+SKT20dONXVB16kO13KyCLPmBsihGmN6PA13s K6E00buAtxpkdDDNG3qaxA8= X-Google-Smtp-Source: ABdhPJzTXwljAEMpX/uUq4buorfznC+YSLNBmBrk2KnnduyMBDEOJzX9XGPSDfNJEH1WKatZLZxszw== X-Received: by 2002:adf:ce12:: with SMTP id p18mr16218911wrn.144.1618859973870; Mon, 19 Apr 2021 12:19:33 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Aurelien Jarno , Huacai Chen Subject: [PATCH v3 14/30] target/mips: Add simple user-mode mips_cpu_tlb_fill() Date: Mon, 19 Apr 2021 21:18:07 +0200 Message-Id: <20210419191823.1555482-15-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210419191823.1555482-1-f4bug@amsat.org> References: <20210419191823.1555482-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) tlb_helper.c's #ifdef'ry hides a quite simple user-mode implementation of mips_cpu_tlb_fill(). Copy the user-mode implementation (without #ifdef'ry) to tcg/user/helper.c and simplify tlb_helper.c's #ifdef'ry. This will allow us to restrict tlb_helper.c to sysemu. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/tcg/user/tlb_helper.c | 36 +++++++++++++++++++++++++++++++ target/mips/tlb_helper.c | 10 --------- 2 files changed, 36 insertions(+), 10 deletions(-) diff --git a/target/mips/tcg/user/tlb_helper.c b/target/mips/tcg/user/tlb_h= elper.c index 453b9e9b930..b835144b820 100644 --- a/target/mips/tcg/user/tlb_helper.c +++ b/target/mips/tcg/user/tlb_helper.c @@ -22,6 +22,42 @@ #include "exec/exec-all.h" #include "internal.h" =20 +static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, + MMUAccessType access_type) +{ + CPUState *cs =3D env_cpu(env); + + env->error_code =3D 0; + if (access_type =3D=3D MMU_INST_FETCH) { + env->error_code |=3D EXCP_INST_NOTAVAIL; + } + + /* Reference to kernel address from user mode or supervisor mode */ + /* Reference to supervisor address from user mode */ + if (access_type =3D=3D MMU_DATA_STORE) { + cs->exception_index =3D EXCP_AdES; + } else { + cs->exception_index =3D EXCP_AdEL; + } + + /* Raise exception */ + if (!(env->hflags & MIPS_HFLAG_DM)) { + env->CP0_BadVAddr =3D address; + } +} + +bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) +{ + MIPSCPU *cpu =3D MIPS_CPU(cs); + CPUMIPSState *env =3D &cpu->env; + + /* data access */ + raise_mmu_exception(env, address, access_type); + do_raise_exception_err(env, cs->exception_index, env->error_code, reta= ddr); +} + void mips_cpu_do_interrupt(CPUState *cs) { cs->exception_index =3D EXCP_NONE; diff --git a/target/mips/tlb_helper.c b/target/mips/tlb_helper.c index 78720c4d20a..afc019c80dd 100644 --- a/target/mips/tlb_helper.c +++ b/target/mips/tlb_helper.c @@ -403,8 +403,6 @@ void cpu_mips_tlb_flush(CPUMIPSState *env) env->tlb->tlb_in_use =3D env->tlb->nb_tlb; } =20 -#endif /* !CONFIG_USER_ONLY */ - static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, MMUAccessType access_type, int tlb_error) { @@ -484,8 +482,6 @@ static void raise_mmu_exception(CPUMIPSState *env, targ= et_ulong address, env->error_code =3D error_code; } =20 -#if !defined(CONFIG_USER_ONLY) - hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { MIPSCPU *cpu =3D MIPS_CPU(cs); @@ -833,7 +829,6 @@ refill: return true; } #endif -#endif /* !CONFIG_USER_ONLY */ =20 bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, @@ -841,14 +836,11 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, { MIPSCPU *cpu =3D MIPS_CPU(cs); CPUMIPSState *env =3D &cpu->env; -#if !defined(CONFIG_USER_ONLY) hwaddr physical; int prot; -#endif int ret =3D TLBRET_BADADDR; =20 /* data access */ -#if !defined(CONFIG_USER_ONLY) /* XXX: put correct access by using cpu_restore_state() correctly */ ret =3D get_physical_address(env, &physical, &prot, address, access_type, mmu_idx); @@ -896,13 +888,11 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, if (probe) { return false; } -#endif =20 raise_mmu_exception(env, address, access_type, ret); do_raise_exception_err(env, cs->exception_index, env->error_code, reta= ddr); } =20 -#ifndef CONFIG_USER_ONLY hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, MMUAccessType access_type, uintptr_t ret= addr) { --=20 2.26.3 From nobody Sat May 4 03:43:33 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.51 as permitted sender) client-ip=209.85.221.51; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f51.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.51 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1618859980; cv=none; d=zohomail.com; s=zohoarc; b=gCEAoCnVKl2jKLK3bUiAXLDY/43F9ESaXPznR5ZC9KrZqRNl/UKkB9lUqoxP8D6wx1Vc5ncjgUleELwMrc218+x9t/VSYjrR1eSLlRYc7BaTh0jZ0c9TCu/35mo5rQni3wJbxA/kNW421eE2PtYHx/m1ILqLq0dYDIo6OcN38JE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618859980; 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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id u14sm24627564wrq.65.2021.04.19.12.19.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Apr 2021 12:19:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rr++hNIFKJY6ZyDunycH0lT/NL/uhSgnj53A2ANYy+k=; b=IiI7U/ZizsqmsuSegGL7grLiAYx6E2ZEIWfYq8VKdbeIkDR1FZc7hnnSGHK015tm7X t9W1PsB9ZVxc3pSxShTWJoGq5kQmvBnKVf/msp5pxjgRjUD9SvMDJQKndfj1cFBK584O 1xIn8k+swPbZR2NPXBZBQEautA4MHboyIAffnTsTEIOk2Yk02zb85ycUAnxCabGpLp8A tsmpduskKeqBAjE3/2EgKhJM48q28GP/QzLvXQSqp1ExCgT6EjkHwRCBbFjw4FHzi6WB OG912gPq0Rmb02lR9wWb6vB/dj4I+aAA2mfzS03dA/NrklDvTRX87+ABNRnbC3KlufAU DsFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=rr++hNIFKJY6ZyDunycH0lT/NL/uhSgnj53A2ANYy+k=; b=Yx+JnJMa4Ibt9ZW8Oz8MLShnV25rou+9nM67fWCZ0tSC9DWz65mewsewvN8H461l5j FR+2o/gEypq1VP65JzpY5UQIzIFGgIaEpXS+1o9MVisY7Cz1i0f72R4waoH2RNY59sIL RZpHJlkgd6MuWymzQR3SsDAigy11hF0hJRZcow/RrO8FPMslxp+QADhGUFHWhmC1tkmG 8AJJ6eZ6apumyjg0NhpChJMsTX0/q5YwbbZ0JyqWI7sQidk0t6SAAROXOG9K/7cBvDRQ O3mSgcHIam26zhaaDdWhI/6/eXsZVGqr0OvoNtNO3sU2+V1aDcmcQ6+h8Jbmc8YNAAdi pWfQ== X-Gm-Message-State: AOAM530xaVSHFWXZvO1kh2f+U3aITy4yyYci0kZ4Is3CoovhRVruGCqU BPwHAuDRIR7H2JC63LEq1vQ= X-Google-Smtp-Source: ABdhPJxSyMWYyQ98HmzSLORTMBlW4QhHN/FZfqOIUO/t6VNll4GFX3yFHLBTPYIXgAsLl25p7MH8bw== X-Received: by 2002:adf:f302:: with SMTP id i2mr15672025wro.423.1618859978822; Mon, 19 Apr 2021 12:19:38 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Aurelien Jarno , Huacai Chen Subject: [PATCH v3 15/30] target/mips: Move cpu_signal_handler definition around Date: Mon, 19 Apr 2021 21:18:08 +0200 Message-Id: <20210419191823.1555482-16-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210419191823.1555482-1-f4bug@amsat.org> References: <20210419191823.1555482-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) We have 2 blocks guarded with #ifdef for sysemu, which are simply separated by the cpu_signal_handler definition. To simplify the following commits which involve various changes in internal.h, first join the sysemu-guarded blocks. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/internal.h | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 9e86f6ad6b7..b8d17788080 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -151,14 +151,13 @@ void mips_cpu_do_transaction_failed(CPUState *cs, hwa= ddr physaddr, MemTxResult response, uintptr_t retadd= r); hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, MMUAccessType access_type, uintptr_t ret= addr); -#endif + +extern const VMStateDescription vmstate_mips_cpu; + +#endif /* !CONFIG_USER_ONLY */ =20 #define cpu_signal_handler cpu_mips_signal_handler =20 -#ifndef CONFIG_USER_ONLY -extern const VMStateDescription vmstate_mips_cpu; -#endif - static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env) { return (env->CP0_Status & (1 << CP0St_IE)) && --=20 2.26.3 From nobody Sat May 4 03:43:33 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.49 as permitted sender) client-ip=209.85.128.49; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f49.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.49 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1618859985; cv=none; d=zohomail.com; s=zohoarc; b=AiehNoNELdE/PO2vGV6qY/6Og48jCMWNYngb+/GSCyvbc0cdWIp3RXDnP+9AcrGHO3AHsdhqt0bGFZpbVYwn6wBESE4Urq8AgjBnSi7XBqSi0p+CqicTecS2VL7hZOlmi+Agp5JCfSU4ILVrpyCxYJj5ToiSnZCfCnNor7ZJmdI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618859985; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=xKUW8gAMAxhtFOb8uojubp49vr/t6a7goYqTsVJzhpA=; b=NfPpTKuu7+N/wDzOmZ+uOYWljnFAXuBdwRk0YQHewQK133qFWocsZKguehiuRc5TjzHAoejp0Zqnc7kNLW0m0/q3FXquyyaWYB59Bkkj7tmb2S8plNiG/5q/W+hfqqUS54FbmiAoiIt4sDz0X9Bg6132RpzyVf4OILP0XAPcAcI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.49 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) by mx.zohomail.com with SMTPS id 1618859985312793.90264097411; Mon, 19 Apr 2021 12:19:45 -0700 (PDT) Received: by mail-wm1-f49.google.com with SMTP id y5-20020a05600c3645b0290132b13aaa3bso6922028wmq.1 for ; Mon, 19 Apr 2021 12:19:44 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.redhat.com (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id 61sm25889949wrm.52.2021.04.19.12.19.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Apr 2021 12:19:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xKUW8gAMAxhtFOb8uojubp49vr/t6a7goYqTsVJzhpA=; b=SBSCySL3R4vmKpg0/lpqQJjH/a9RjJQZx/4vdL0NHIslnaxxbCm7jy8BOUCGNYCYvZ 3EnDbHbpFuEa0uJheAhE/tDHdkmv8q4E5V4/No4HuBqSK1rswWBzsUfuV+PEuZE2i0XQ z3kGEfE0uyz1j2ugu3LglV8WkE+RcKSXDQhXj2Fu2jXtNpo+a2n0WTqFcnxFnB74z03Z OUgcUKxwsQKQQ2n1BFphDFLvJrA0D8vkAx+pi9tqBfqbTz2DE4xnYv3gDYTCm8T2bvbw 5gyCcWGeeRtJ65CqWh/b1eHw0rKzFdFL5hXSW8MF3gzBE8WotWtvbE1dTUFg3IEcNFfH hOBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=xKUW8gAMAxhtFOb8uojubp49vr/t6a7goYqTsVJzhpA=; b=s0uD1RRSPcb+YLPs0oJvw+eT/49R63/O88vbdu91nKtT42glveyl9M8UqSmnHwFjy6 Zj7WEd45O5dvYNSDkawX/3o4d5wYUZZIG+0SRp4MG12zjVBxU0DFhK5h3Z9zyhgGvu1i PvZQn7rnBF6OS2AnZVOOAToaQl0+GSPFz+Xd1Tmff0PprIBqYT6BN3TFswGgL92Z/pGd 8ZL5vtOSzZ5RA+AxsCVAF4HrjjEIfBQL+w1LZzZA4Z246yIqr6v6KGz6/SfIKrlh//pK Mrj/IStpi/T3RQ9a7SzYiJw+ftANU08sL2B+JbNDVHDJB82pbP3c6gyJD8KrIkJqJ6/l Le4A== X-Gm-Message-State: AOAM533fPDUjZh3j4rmqBwHC/WHLdbeG1HENY6swIIPB4V3bAf23G6R1 OZR21eIx9Hw2B0MZXe4cNts= X-Google-Smtp-Source: ABdhPJwpEUjFo1w72G+ZkdlzI5RZOgSAAvYzSgVtdZDTpFV6aZDt0nFzBfJtlVOXYX6TeZe3pNbYmA== X-Received: by 2002:a1c:658a:: with SMTP id z132mr556286wmb.39.1618859983551; Mon, 19 Apr 2021 12:19:43 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Aurelien Jarno , Huacai Chen Subject: [PATCH v3 16/30] target/mips: Move sysemu specific files under sysemu/ subfolder Date: Mon, 19 Apr 2021 21:18:09 +0200 Message-Id: <20210419191823.1555482-17-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210419191823.1555482-1-f4bug@amsat.org> References: <20210419191823.1555482-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Move sysemu-specific files under the new sysemu/ subfolder and adapt the Meson machinery. Update the KVM MIPS entry in MAINTAINERS. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- v2: Update MAINTAINERS --- target/mips/{ =3D> sysemu}/addr.c | 0 target/mips/{ =3D> sysemu}/cp0_timer.c | 0 target/mips/{ =3D> sysemu}/machine.c | 0 MAINTAINERS | 3 ++- target/mips/meson.build | 12 ++++++------ target/mips/sysemu/meson.build | 5 +++++ 6 files changed, 13 insertions(+), 7 deletions(-) rename target/mips/{ =3D> sysemu}/addr.c (100%) rename target/mips/{ =3D> sysemu}/cp0_timer.c (100%) rename target/mips/{ =3D> sysemu}/machine.c (100%) create mode 100644 target/mips/sysemu/meson.build diff --git a/target/mips/addr.c b/target/mips/sysemu/addr.c similarity index 100% rename from target/mips/addr.c rename to target/mips/sysemu/addr.c diff --git a/target/mips/cp0_timer.c b/target/mips/sysemu/cp0_timer.c similarity index 100% rename from target/mips/cp0_timer.c rename to target/mips/sysemu/cp0_timer.c diff --git a/target/mips/machine.c b/target/mips/sysemu/machine.c similarity index 100% rename from target/mips/machine.c rename to target/mips/sysemu/machine.c diff --git a/MAINTAINERS b/MAINTAINERS index 36055f14c59..0620326544e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -404,7 +404,8 @@ F: target/arm/kvm.c MIPS KVM CPUs M: Huacai Chen S: Odd Fixes -F: target/mips/kvm.c +F: target/mips/kvm* +F: target/mips/sysemu/ =20 PPC KVM CPUs M: David Gibson diff --git a/target/mips/meson.build b/target/mips/meson.build index ca3cc62cf7a..9a507937ece 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -7,6 +7,7 @@ ] =20 mips_user_ss =3D ss.source_set() +mips_softmmu_ss =3D ss.source_set() mips_ss =3D ss.source_set() mips_ss.add(files( 'cpu.c', @@ -14,6 +15,11 @@ 'gdbstub.c', 'msa.c', )) + +if have_system + subdir('sysemu') +endif + mips_tcg_ss =3D ss.source_set() mips_tcg_ss.add(gen) mips_tcg_ss.add(files( @@ -41,12 +47,6 @@ =20 mips_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) =20 -mips_softmmu_ss =3D ss.source_set() -mips_softmmu_ss.add(files( - 'addr.c', - 'cp0_timer.c', - 'machine.c', -)) mips_softmmu_ss.add(when: 'CONFIG_TCG', if_true: files( 'cp0_helper.c', 'mips-semi.c', diff --git a/target/mips/sysemu/meson.build b/target/mips/sysemu/meson.build new file mode 100644 index 00000000000..f2a1ff46081 --- /dev/null +++ b/target/mips/sysemu/meson.build @@ -0,0 +1,5 @@ +mips_softmmu_ss.add(files( + 'addr.c', + 'cp0_timer.c', + 'machine.c', +)) --=20 2.26.3 From nobody Sat May 4 03:43:33 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.47 as permitted sender) client-ip=209.85.221.47; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f47.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.47 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1618859990; cv=none; d=zohomail.com; s=zohoarc; b=fKCFZ7vlvkRSqVcTvTH2q56kACvMiTnwigQgIoN/lOh/YqM6XBygTuR4oecyvb5nhCtUapggvMEcSZX4SbV8LKo4BqyegKTDKtTTq2/As9nTpIIWmSJQZEI6P0pqF85sy9/pjHoKeJSMtgIJsgjHfuzqqn8t8BJ0HkZQlfCoGiA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618859990; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=yNDvbUydFK9tR28sNhFDU1b617V0SKHm+nWHgpMknSc=; b=nfTgedjn3fOAnlZzHkL4GTC6mCCD8DwvLaCBZRkL2NjJJ+YHSTryzO3NVdd5jgBVEXwrp0yBCCe1x0/bZHl0mcxY88MH8ztQ/joYZXfxH4vrq6v24aVaExYkkBHA1zhUMQFY7hE0HMDJ9AanYl8CGscykQLVDPTvCAU2/Acvpkc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.47 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f47.google.com (mail-wr1-f47.google.com [209.85.221.47]) by mx.zohomail.com with SMTPS id 1618859990274272.12972260585184; Mon, 19 Apr 2021 12:19:50 -0700 (PDT) Received: by mail-wr1-f47.google.com with SMTP id e7so26209576wrs.11 for ; Mon, 19 Apr 2021 12:19:49 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.redhat.com (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id h14sm28233160wrq.45.2021.04.19.12.19.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Apr 2021 12:19:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yNDvbUydFK9tR28sNhFDU1b617V0SKHm+nWHgpMknSc=; b=nkAv8Bx/EzGKsIqA358zbmsqe+rulW+yAF+/Z7BiH8E8qcjTdXU1uYl/fivP8BiHuQ HLNQsToOYPJD6gq2gyzEX5hkfWPtrXI0rVyMASfAMRTA0/3ixST+2NlbactVDdBClwQQ RZVgKKYm7Jn/aCjKDbjJSedyTzwHOpzROAjmg9GxuhKAT4/3NiFiyd9ErUnDPgHsWmNo b1yg1SC7m77r72kohev3ap82nsUEpj40hU8ImMgxiL1DFYSRHRUQU14z466Axsu32lCx 4imbHhGq33FKm5yZOALe/J4a54ZxHm85oFnasBO9GOJoe4mu+pg7018K0NAlPjNp9h61 AosA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=yNDvbUydFK9tR28sNhFDU1b617V0SKHm+nWHgpMknSc=; b=hAPN/qdcd1ITMsMOukSoSc1qNqg7kKuMBxhQWwOKUEwecibEO69ELnj5F3VEIdzgSe 5FJw9DdrzG95lL+P4F/ExaVZLHxL4Thhr1Vir0K//o0f/5M8Fk0IiKZ65tZVX6+hej3T 1UnvJSvfOG/UcJ08Ezi+jv/dKJgDIVioXxhEbGrFSKMHtu2xFEYHsgD09jwjlSZohkpy zGHhzCgHwB2HuZnZCTGxD9KfE5uebdeKZPQUHIaBehmU6WfhJ1TS7bZwWethMye3LLwQ zUZqCXyfSCIrGuW3dDBlWL++ZHwSTSHm4Qk8hnxICrw99rUs27hDdyZAN+al8odcMcMU On2w== X-Gm-Message-State: AOAM532LaUcC0qJDjcXyDfClMhm5BG9oxNageDV4DHCS3i0a4QdZkzuT Ca82AEFTwFSOft4gw9HHDno= X-Google-Smtp-Source: ABdhPJypW91IgiVRDZbDhuNpWI2t0XEt6OUZmS4TTBLtMVSlPVHiPYinWf/by2sWhxZ8Jd4sRSPJvg== X-Received: by 2002:a5d:640f:: with SMTP id z15mr16234077wru.221.1618859988347; Mon, 19 Apr 2021 12:19:48 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Aurelien Jarno , Huacai Chen Subject: [PATCH v3 17/30] target/mips: Move physical addressing code to sysemu/physaddr.c Date: Mon, 19 Apr 2021 21:18:10 +0200 Message-Id: <20210419191823.1555482-18-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210419191823.1555482-1-f4bug@amsat.org> References: <20210419191823.1555482-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Declare get_physical_address() with local scope and move it along with mips_cpu_get_phys_page_debug() to sysemu/physaddr.c new file. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- v2: phys.c -> physaddr.c in description (rth) --- target/mips/internal.h | 25 +++- target/mips/sysemu/physaddr.c | 257 +++++++++++++++++++++++++++++++++ target/mips/tlb_helper.c | 254 -------------------------------- target/mips/sysemu/meson.build | 1 + 4 files changed, 282 insertions(+), 255 deletions(-) create mode 100644 target/mips/sysemu/physaddr.c diff --git a/target/mips/internal.h b/target/mips/internal.h index b8d17788080..5e9228db3f1 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -81,15 +81,38 @@ extern const struct mips_def_t mips_defs[]; extern const int mips_defs_number; =20 bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); -hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); =20 +#define USEG_LIMIT ((target_ulong)(int32_t)0x7FFFFFFFUL) +#define KSEG0_BASE ((target_ulong)(int32_t)0x80000000UL) +#define KSEG1_BASE ((target_ulong)(int32_t)0xA0000000UL) +#define KSEG2_BASE ((target_ulong)(int32_t)0xC0000000UL) +#define KSEG3_BASE ((target_ulong)(int32_t)0xE0000000UL) + +#define KVM_KSEG0_BASE ((target_ulong)(int32_t)0x40000000UL) +#define KVM_KSEG2_BASE ((target_ulong)(int32_t)0x60000000UL) + #if !defined(CONFIG_USER_ONLY) =20 +enum { + TLBRET_XI =3D -6, + TLBRET_RI =3D -5, + TLBRET_DIRTY =3D -4, + TLBRET_INVALID =3D -3, + TLBRET_NOMATCH =3D -2, + TLBRET_BADADDR =3D -1, + TLBRET_MATCH =3D 0 +}; + +int get_physical_address(CPUMIPSState *env, hwaddr *physical, + int *prot, target_ulong real_address, + MMUAccessType access_type, int mmu_idx); +hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); + typedef struct r4k_tlb_t r4k_tlb_t; struct r4k_tlb_t { target_ulong VPN; diff --git a/target/mips/sysemu/physaddr.c b/target/mips/sysemu/physaddr.c new file mode 100644 index 00000000000..1918633aa1c --- /dev/null +++ b/target/mips/sysemu/physaddr.c @@ -0,0 +1,257 @@ +/* + * MIPS TLB (Translation lookaside buffer) helpers. + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ +#include "qemu/osdep.h" +#include "cpu.h" +#include "exec/exec-all.h" +#include "../internal.h" + +static int is_seg_am_mapped(unsigned int am, bool eu, int mmu_idx) +{ + /* + * Interpret access control mode and mmu_idx. + * AdE? TLB? + * AM K S U E K S U E + * UK 0 0 1 1 0 0 - - 0 + * MK 1 0 1 1 0 1 - - !eu + * MSK 2 0 0 1 0 1 1 - !eu + * MUSK 3 0 0 0 0 1 1 1 !eu + * MUSUK 4 0 0 0 0 0 1 1 0 + * USK 5 0 0 1 0 0 0 - 0 + * - 6 - - - - - - - - + * UUSK 7 0 0 0 0 0 0 0 0 + */ + int32_t adetlb_mask; + + switch (mmu_idx) { + case 3: /* ERL */ + /* If EU is set, always unmapped */ + if (eu) { + return 0; + } + /* fall through */ + case MIPS_HFLAG_KM: + /* Never AdE, TLB mapped if AM=3D{1,2,3} */ + adetlb_mask =3D 0x70000000; + goto check_tlb; + + case MIPS_HFLAG_SM: + /* AdE if AM=3D{0,1}, TLB mapped if AM=3D{2,3,4} */ + adetlb_mask =3D 0xc0380000; + goto check_ade; + + case MIPS_HFLAG_UM: + /* AdE if AM=3D{0,1,2,5}, TLB mapped if AM=3D{3,4} */ + adetlb_mask =3D 0xe4180000; + /* fall through */ + check_ade: + /* does this AM cause AdE in current execution mode */ + if ((adetlb_mask << am) < 0) { + return TLBRET_BADADDR; + } + adetlb_mask <<=3D 8; + /* fall through */ + check_tlb: + /* is this AM mapped in current execution mode */ + return ((adetlb_mask << am) < 0); + default: + assert(0); + return TLBRET_BADADDR; + }; +} + +static int get_seg_physical_address(CPUMIPSState *env, hwaddr *physical, + int *prot, target_ulong real_address, + MMUAccessType access_type, int mmu_idx, + unsigned int am, bool eu, + target_ulong segmask, + hwaddr physical_base) +{ + int mapped =3D is_seg_am_mapped(am, eu, mmu_idx); + + if (mapped < 0) { + /* is_seg_am_mapped can report TLBRET_BADADDR */ + return mapped; + } else if (mapped) { + /* The segment is TLB mapped */ + return env->tlb->map_address(env, physical, prot, real_address, + access_type); + } else { + /* The segment is unmapped */ + *physical =3D physical_base | (real_address & segmask); + *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + return TLBRET_MATCH; + } +} + +static int get_segctl_physical_address(CPUMIPSState *env, hwaddr *physical, + int *prot, target_ulong real_addres= s, + MMUAccessType access_type, int mmu_= idx, + uint16_t segctl, target_ulong segma= sk) +{ + unsigned int am =3D (segctl & CP0SC_AM_MASK) >> CP0SC_AM; + bool eu =3D (segctl >> CP0SC_EU) & 1; + hwaddr pa =3D ((hwaddr)segctl & CP0SC_PA_MASK) << 20; + + return get_seg_physical_address(env, physical, prot, real_address, + access_type, mmu_idx, am, eu, segmask, + pa & ~(hwaddr)segmask); +} + +int get_physical_address(CPUMIPSState *env, hwaddr *physical, + int *prot, target_ulong real_address, + MMUAccessType access_type, int mmu_idx) +{ + /* User mode can only access useg/xuseg */ +#if defined(TARGET_MIPS64) + int user_mode =3D mmu_idx =3D=3D MIPS_HFLAG_UM; + int supervisor_mode =3D mmu_idx =3D=3D MIPS_HFLAG_SM; + int kernel_mode =3D !user_mode && !supervisor_mode; + int UX =3D (env->CP0_Status & (1 << CP0St_UX)) !=3D 0; + int SX =3D (env->CP0_Status & (1 << CP0St_SX)) !=3D 0; + int KX =3D (env->CP0_Status & (1 << CP0St_KX)) !=3D 0; +#endif + int ret =3D TLBRET_MATCH; + /* effective address (modified for KVM T&E kernel segments) */ + target_ulong address =3D real_address; + + if (mips_um_ksegs_enabled()) { + /* KVM T&E adds guest kernel segments in useg */ + if (real_address >=3D KVM_KSEG0_BASE) { + if (real_address < KVM_KSEG2_BASE) { + /* kseg0 */ + address +=3D KSEG0_BASE - KVM_KSEG0_BASE; + } else if (real_address <=3D USEG_LIMIT) { + /* kseg2/3 */ + address +=3D KSEG2_BASE - KVM_KSEG2_BASE; + } + } + } + + if (address <=3D USEG_LIMIT) { + /* useg */ + uint16_t segctl; + + if (address >=3D 0x40000000UL) { + segctl =3D env->CP0_SegCtl2; + } else { + segctl =3D env->CP0_SegCtl2 >> 16; + } + ret =3D get_segctl_physical_address(env, physical, prot, + real_address, access_type, + mmu_idx, segctl, 0x3FFFFFFF); +#if defined(TARGET_MIPS64) + } else if (address < 0x4000000000000000ULL) { + /* xuseg */ + if (UX && address <=3D (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) { + ret =3D env->tlb->map_address(env, physical, prot, + real_address, access_type); + } else { + ret =3D TLBRET_BADADDR; + } + } else if (address < 0x8000000000000000ULL) { + /* xsseg */ + if ((supervisor_mode || kernel_mode) && + SX && address <=3D (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) { + ret =3D env->tlb->map_address(env, physical, prot, + real_address, access_type); + } else { + ret =3D TLBRET_BADADDR; + } + } else if (address < 0xC000000000000000ULL) { + /* xkphys */ + if ((address & 0x07FFFFFFFFFFFFFFULL) <=3D env->PAMask) { + /* KX/SX/UX bit to check for each xkphys EVA access mode */ + static const uint8_t am_ksux[8] =3D { + [CP0SC_AM_UK] =3D (1u << CP0St_KX), + [CP0SC_AM_MK] =3D (1u << CP0St_KX), + [CP0SC_AM_MSK] =3D (1u << CP0St_SX), + [CP0SC_AM_MUSK] =3D (1u << CP0St_UX), + [CP0SC_AM_MUSUK] =3D (1u << CP0St_UX), + [CP0SC_AM_USK] =3D (1u << CP0St_SX), + [6] =3D (1u << CP0St_KX), + [CP0SC_AM_UUSK] =3D (1u << CP0St_UX), + }; + unsigned int am =3D CP0SC_AM_UK; + unsigned int xr =3D (env->CP0_SegCtl2 & CP0SC2_XR_MASK) >> CP0= SC2_XR; + + if (xr & (1 << ((address >> 59) & 0x7))) { + am =3D (env->CP0_SegCtl1 & CP0SC1_XAM_MASK) >> CP0SC1_XAM; + } + /* Does CP0_Status.KX/SX/UX permit the access mode (am) */ + if (env->CP0_Status & am_ksux[am]) { + ret =3D get_seg_physical_address(env, physical, prot, + real_address, access_type, + mmu_idx, am, false, env->PA= Mask, + 0); + } else { + ret =3D TLBRET_BADADDR; + } + } else { + ret =3D TLBRET_BADADDR; + } + } else if (address < 0xFFFFFFFF80000000ULL) { + /* xkseg */ + if (kernel_mode && KX && + address <=3D (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) { + ret =3D env->tlb->map_address(env, physical, prot, + real_address, access_type); + } else { + ret =3D TLBRET_BADADDR; + } +#endif + } else if (address < KSEG1_BASE) { + /* kseg0 */ + ret =3D get_segctl_physical_address(env, physical, prot, real_addr= ess, + access_type, mmu_idx, + env->CP0_SegCtl1 >> 16, 0x1FFFFF= FF); + } else if (address < KSEG2_BASE) { + /* kseg1 */ + ret =3D get_segctl_physical_address(env, physical, prot, real_addr= ess, + access_type, mmu_idx, + env->CP0_SegCtl1, 0x1FFFFFFF); + } else if (address < KSEG3_BASE) { + /* sseg (kseg2) */ + ret =3D get_segctl_physical_address(env, physical, prot, real_addr= ess, + access_type, mmu_idx, + env->CP0_SegCtl0 >> 16, 0x1FFFFF= FF); + } else { + /* + * kseg3 + * XXX: debug segment is not emulated + */ + ret =3D get_segctl_physical_address(env, physical, prot, real_addr= ess, + access_type, mmu_idx, + env->CP0_SegCtl0, 0x1FFFFFFF); + } + return ret; +} + +hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) +{ + MIPSCPU *cpu =3D MIPS_CPU(cs); + CPUMIPSState *env =3D &cpu->env; + hwaddr phys_addr; + int prot; + + if (get_physical_address(env, &phys_addr, &prot, addr, MMU_DATA_LOAD, + cpu_mmu_index(env, false)) !=3D 0) { + return -1; + } + return phys_addr; +} diff --git a/target/mips/tlb_helper.c b/target/mips/tlb_helper.c index afc019c80dd..bfb08eaf506 100644 --- a/target/mips/tlb_helper.c +++ b/target/mips/tlb_helper.c @@ -25,16 +25,6 @@ #include "exec/log.h" #include "hw/mips/cpudevs.h" =20 -enum { - TLBRET_XI =3D -6, - TLBRET_RI =3D -5, - TLBRET_DIRTY =3D -4, - TLBRET_INVALID =3D -3, - TLBRET_NOMATCH =3D -2, - TLBRET_BADADDR =3D -1, - TLBRET_MATCH =3D 0 -}; - #if !defined(CONFIG_USER_ONLY) =20 /* no MMU emulation */ @@ -166,236 +156,6 @@ void mmu_init(CPUMIPSState *env, const mips_def_t *de= f) } } =20 -static int is_seg_am_mapped(unsigned int am, bool eu, int mmu_idx) -{ - /* - * Interpret access control mode and mmu_idx. - * AdE? TLB? - * AM K S U E K S U E - * UK 0 0 1 1 0 0 - - 0 - * MK 1 0 1 1 0 1 - - !eu - * MSK 2 0 0 1 0 1 1 - !eu - * MUSK 3 0 0 0 0 1 1 1 !eu - * MUSUK 4 0 0 0 0 0 1 1 0 - * USK 5 0 0 1 0 0 0 - 0 - * - 6 - - - - - - - - - * UUSK 7 0 0 0 0 0 0 0 0 - */ - int32_t adetlb_mask; - - switch (mmu_idx) { - case 3: /* ERL */ - /* If EU is set, always unmapped */ - if (eu) { - return 0; - } - /* fall through */ - case MIPS_HFLAG_KM: - /* Never AdE, TLB mapped if AM=3D{1,2,3} */ - adetlb_mask =3D 0x70000000; - goto check_tlb; - - case MIPS_HFLAG_SM: - /* AdE if AM=3D{0,1}, TLB mapped if AM=3D{2,3,4} */ - adetlb_mask =3D 0xc0380000; - goto check_ade; - - case MIPS_HFLAG_UM: - /* AdE if AM=3D{0,1,2,5}, TLB mapped if AM=3D{3,4} */ - adetlb_mask =3D 0xe4180000; - /* fall through */ - check_ade: - /* does this AM cause AdE in current execution mode */ - if ((adetlb_mask << am) < 0) { - return TLBRET_BADADDR; - } - adetlb_mask <<=3D 8; - /* fall through */ - check_tlb: - /* is this AM mapped in current execution mode */ - return ((adetlb_mask << am) < 0); - default: - assert(0); - return TLBRET_BADADDR; - }; -} - -static int get_seg_physical_address(CPUMIPSState *env, hwaddr *physical, - int *prot, target_ulong real_address, - MMUAccessType access_type, int mmu_idx, - unsigned int am, bool eu, - target_ulong segmask, - hwaddr physical_base) -{ - int mapped =3D is_seg_am_mapped(am, eu, mmu_idx); - - if (mapped < 0) { - /* is_seg_am_mapped can report TLBRET_BADADDR */ - return mapped; - } else if (mapped) { - /* The segment is TLB mapped */ - return env->tlb->map_address(env, physical, prot, real_address, - access_type); - } else { - /* The segment is unmapped */ - *physical =3D physical_base | (real_address & segmask); - *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; - return TLBRET_MATCH; - } -} - -static int get_segctl_physical_address(CPUMIPSState *env, hwaddr *physical, - int *prot, target_ulong real_addres= s, - MMUAccessType access_type, int mmu_= idx, - uint16_t segctl, target_ulong segma= sk) -{ - unsigned int am =3D (segctl & CP0SC_AM_MASK) >> CP0SC_AM; - bool eu =3D (segctl >> CP0SC_EU) & 1; - hwaddr pa =3D ((hwaddr)segctl & CP0SC_PA_MASK) << 20; - - return get_seg_physical_address(env, physical, prot, real_address, - access_type, mmu_idx, am, eu, segmask, - pa & ~(hwaddr)segmask); -} - -static int get_physical_address(CPUMIPSState *env, hwaddr *physical, - int *prot, target_ulong real_address, - MMUAccessType access_type, int mmu_idx) -{ - /* User mode can only access useg/xuseg */ -#if defined(TARGET_MIPS64) - int user_mode =3D mmu_idx =3D=3D MIPS_HFLAG_UM; - int supervisor_mode =3D mmu_idx =3D=3D MIPS_HFLAG_SM; - int kernel_mode =3D !user_mode && !supervisor_mode; - int UX =3D (env->CP0_Status & (1 << CP0St_UX)) !=3D 0; - int SX =3D (env->CP0_Status & (1 << CP0St_SX)) !=3D 0; - int KX =3D (env->CP0_Status & (1 << CP0St_KX)) !=3D 0; -#endif - int ret =3D TLBRET_MATCH; - /* effective address (modified for KVM T&E kernel segments) */ - target_ulong address =3D real_address; - -#define USEG_LIMIT ((target_ulong)(int32_t)0x7FFFFFFFUL) -#define KSEG0_BASE ((target_ulong)(int32_t)0x80000000UL) -#define KSEG1_BASE ((target_ulong)(int32_t)0xA0000000UL) -#define KSEG2_BASE ((target_ulong)(int32_t)0xC0000000UL) -#define KSEG3_BASE ((target_ulong)(int32_t)0xE0000000UL) - -#define KVM_KSEG0_BASE ((target_ulong)(int32_t)0x40000000UL) -#define KVM_KSEG2_BASE ((target_ulong)(int32_t)0x60000000UL) - - if (mips_um_ksegs_enabled()) { - /* KVM T&E adds guest kernel segments in useg */ - if (real_address >=3D KVM_KSEG0_BASE) { - if (real_address < KVM_KSEG2_BASE) { - /* kseg0 */ - address +=3D KSEG0_BASE - KVM_KSEG0_BASE; - } else if (real_address <=3D USEG_LIMIT) { - /* kseg2/3 */ - address +=3D KSEG2_BASE - KVM_KSEG2_BASE; - } - } - } - - if (address <=3D USEG_LIMIT) { - /* useg */ - uint16_t segctl; - - if (address >=3D 0x40000000UL) { - segctl =3D env->CP0_SegCtl2; - } else { - segctl =3D env->CP0_SegCtl2 >> 16; - } - ret =3D get_segctl_physical_address(env, physical, prot, - real_address, access_type, - mmu_idx, segctl, 0x3FFFFFFF); -#if defined(TARGET_MIPS64) - } else if (address < 0x4000000000000000ULL) { - /* xuseg */ - if (UX && address <=3D (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) { - ret =3D env->tlb->map_address(env, physical, prot, - real_address, access_type); - } else { - ret =3D TLBRET_BADADDR; - } - } else if (address < 0x8000000000000000ULL) { - /* xsseg */ - if ((supervisor_mode || kernel_mode) && - SX && address <=3D (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) { - ret =3D env->tlb->map_address(env, physical, prot, - real_address, access_type); - } else { - ret =3D TLBRET_BADADDR; - } - } else if (address < 0xC000000000000000ULL) { - /* xkphys */ - if ((address & 0x07FFFFFFFFFFFFFFULL) <=3D env->PAMask) { - /* KX/SX/UX bit to check for each xkphys EVA access mode */ - static const uint8_t am_ksux[8] =3D { - [CP0SC_AM_UK] =3D (1u << CP0St_KX), - [CP0SC_AM_MK] =3D (1u << CP0St_KX), - [CP0SC_AM_MSK] =3D (1u << CP0St_SX), - [CP0SC_AM_MUSK] =3D (1u << CP0St_UX), - [CP0SC_AM_MUSUK] =3D (1u << CP0St_UX), - [CP0SC_AM_USK] =3D (1u << CP0St_SX), - [6] =3D (1u << CP0St_KX), - [CP0SC_AM_UUSK] =3D (1u << CP0St_UX), - }; - unsigned int am =3D CP0SC_AM_UK; - unsigned int xr =3D (env->CP0_SegCtl2 & CP0SC2_XR_MASK) >> CP0= SC2_XR; - - if (xr & (1 << ((address >> 59) & 0x7))) { - am =3D (env->CP0_SegCtl1 & CP0SC1_XAM_MASK) >> CP0SC1_XAM; - } - /* Does CP0_Status.KX/SX/UX permit the access mode (am) */ - if (env->CP0_Status & am_ksux[am]) { - ret =3D get_seg_physical_address(env, physical, prot, - real_address, access_type, - mmu_idx, am, false, env->PA= Mask, - 0); - } else { - ret =3D TLBRET_BADADDR; - } - } else { - ret =3D TLBRET_BADADDR; - } - } else if (address < 0xFFFFFFFF80000000ULL) { - /* xkseg */ - if (kernel_mode && KX && - address <=3D (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) { - ret =3D env->tlb->map_address(env, physical, prot, - real_address, access_type); - } else { - ret =3D TLBRET_BADADDR; - } -#endif - } else if (address < KSEG1_BASE) { - /* kseg0 */ - ret =3D get_segctl_physical_address(env, physical, prot, real_addr= ess, - access_type, mmu_idx, - env->CP0_SegCtl1 >> 16, 0x1FFFFF= FF); - } else if (address < KSEG2_BASE) { - /* kseg1 */ - ret =3D get_segctl_physical_address(env, physical, prot, real_addr= ess, - access_type, mmu_idx, - env->CP0_SegCtl1, 0x1FFFFFFF); - } else if (address < KSEG3_BASE) { - /* sseg (kseg2) */ - ret =3D get_segctl_physical_address(env, physical, prot, real_addr= ess, - access_type, mmu_idx, - env->CP0_SegCtl0 >> 16, 0x1FFFFF= FF); - } else { - /* - * kseg3 - * XXX: debug segment is not emulated - */ - ret =3D get_segctl_physical_address(env, physical, prot, real_addr= ess, - access_type, mmu_idx, - env->CP0_SegCtl0, 0x1FFFFFFF); - } - return ret; -} - void cpu_mips_tlb_flush(CPUMIPSState *env) { /* Flush qemu's TLB and discard all shadowed entries. */ @@ -482,20 +242,6 @@ static void raise_mmu_exception(CPUMIPSState *env, tar= get_ulong address, env->error_code =3D error_code; } =20 -hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) -{ - MIPSCPU *cpu =3D MIPS_CPU(cs); - CPUMIPSState *env =3D &cpu->env; - hwaddr phys_addr; - int prot; - - if (get_physical_address(env, &phys_addr, &prot, addr, MMU_DATA_LOAD, - cpu_mmu_index(env, false)) !=3D 0) { - return -1; - } - return phys_addr; -} - #if !defined(TARGET_MIPS64) =20 /* diff --git a/target/mips/sysemu/meson.build b/target/mips/sysemu/meson.build index f2a1ff46081..925ceeaa449 100644 --- a/target/mips/sysemu/meson.build +++ b/target/mips/sysemu/meson.build @@ -2,4 +2,5 @@ 'addr.c', 'cp0_timer.c', 'machine.c', + 'physaddr.c', )) --=20 2.26.3 From nobody Sat May 4 03:43:33 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.54 as permitted sender) client-ip=209.85.128.54; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f54.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.54 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1618859994; cv=none; d=zohomail.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/internal.h | 4 ---- target/mips/tcg/tcg-internal.h | 9 +++++++++ 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 5e9228db3f1..0bce0950b2c 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -165,7 +165,6 @@ void r4k_helper_tlbr(CPUMIPSState *env); void r4k_helper_tlbinv(CPUMIPSState *env); void r4k_helper_tlbinvf(CPUMIPSState *env); void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra); -uint32_t cpu_mips_get_random(CPUMIPSState *env); =20 void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, @@ -237,9 +236,6 @@ void cpu_mips_stop_count(CPUMIPSState *env); /* helper.c */ void mmu_init(CPUMIPSState *env, const mips_def_t *def); =20 -/* op_helper.c */ -void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagema= sk); - static inline void mips_cpu_set_error_pc(CPUMIPSState *env, target_ulong error_pc) { diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h index 24438667f47..b65580af211 100644 --- a/target/mips/tcg/tcg-internal.h +++ b/target/mips/tcg/tcg-internal.h @@ -11,10 +11,19 @@ #define MIPS_TCG_INTERNAL_H =20 #include "hw/core/cpu.h" +#include "cpu.h" =20 void mips_cpu_do_interrupt(CPUState *cpu); bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); =20 +#if !defined(CONFIG_USER_ONLY) + +void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagema= sk); + +uint32_t cpu_mips_get_random(CPUMIPSState *env); + +#endif /* !CONFIG_USER_ONLY */ + #endif --=20 2.26.3 From nobody Sat May 4 03:43:33 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.48 as permitted sender) client-ip=209.85.128.48; envelope-from=philippe.mathieu.daude@gmail.com; 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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id b15sm481848wmj.46.2021.04.19.12.19.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Apr 2021 12:19:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6UxTKXRxuot4qtym0x1rtyheQvSg7jsP95LgFetkf9k=; b=UhueLCdQ78tp3NMhbTD3C7gSZsHKHx0AUbIJwBUxEeRSIkkmfuqBIigwhWdXGwkjuB Mw9rWD28oliXgxq5PMktNUH771v4eabDlk7lTLOSGovvatGDDlTZv2q+IirRgPC3ysu5 I3ZPUMUnRTcr/0gNEOElmkN7P5e+uJwZTBZItIHsOdfEMYWqfzCp9OpP1tbp6hEBUZNE H36Fym4naVnHCZxCLf8tWso4zT0DBd1a/2aj8EZKVYntZwqD6yCGhJhRCLsbZ+uj8E9n Lmv7s5X6I+OR9exltCSCXsaqSTdmzwaSReprO0pvUPYK6SkgfCyst5uh+VxHtbFMc69a 7lpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=6UxTKXRxuot4qtym0x1rtyheQvSg7jsP95LgFetkf9k=; b=NJmxHcKwIdd2viCzESdOBgFuHbUOQ2z5G/V6FP6Zl/jCxP3yIYDSicQeT2dU6b9Rfq DRQOwNTiPmO3BNpPJ8R7UQZIVwkygrgld2VEYDm4Pm4fLVx10lD7BvhAnmvBhkLmLvZr awSqx2VpoUocNcvGnqXt7EC9OkTvi6x/DxpRDNzQCMvrVhpKwR+VVsQPvfR/GML/zoml dDuICM65/qYo3xOmOA5Ys60s8u15maa72uoENMmvl9KsNJF2iguxHwmR7p21PkiiDg4v sRmU88e+PdPv6RzA2vg1NJxTbv8cW6dayznvEQMl/174bWGvsTDHf+lLXrGzEzp3dHUo zTgg== X-Gm-Message-State: AOAM530ka6Rzg1f9M4M7OfH+lV4EtrHqEKcbM7uw4gMxqv6YMQMOuazL VxHrHxc8OSGFfK1wum6wcpA= X-Google-Smtp-Source: ABdhPJxrtlPHWTAonOAN1MPm2sXS40r+PP8n7J7HDqsNNNL/UjJF2sgQ2Jx10ISbjBDbkKVYohUi2Q== X-Received: by 2002:a05:600c:190c:: with SMTP id j12mr607999wmq.18.1618859998021; Mon, 19 Apr 2021 12:19:58 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Aurelien Jarno , Huacai Chen Subject: [PATCH v3 19/30] target/mips: Move sysemu TCG-specific code to tcg/sysemu/ subfolder Date: Mon, 19 Apr 2021 21:18:12 +0200 Message-Id: <20210419191823.1555482-20-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210419191823.1555482-1-f4bug@amsat.org> References: <20210419191823.1555482-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Move cp0_helper.c and mips-semi.c to the new tcg/sysemu/ folder, adapting the Meson machinery. Move the opcode definitions to tcg/sysemu_helper.h.inc. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/helper.h | 166 +-------------------- target/mips/tcg/sysemu_helper.h.inc | 168 ++++++++++++++++++++++ target/mips/{ =3D> tcg/sysemu}/cp0_helper.c | 0 target/mips/{ =3D> tcg/sysemu}/mips-semi.c | 0 target/mips/meson.build | 5 - target/mips/tcg/meson.build | 3 + target/mips/tcg/sysemu/meson.build | 4 + 7 files changed, 179 insertions(+), 167 deletions(-) create mode 100644 target/mips/tcg/sysemu_helper.h.inc rename target/mips/{ =3D> tcg/sysemu}/cp0_helper.c (100%) rename target/mips/{ =3D> tcg/sysemu}/mips-semi.c (100%) create mode 100644 target/mips/tcg/sysemu/meson.build diff --git a/target/mips/helper.h b/target/mips/helper.h index 709494445dd..bc308e5db13 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -2,10 +2,6 @@ DEF_HELPER_3(raise_exception_err, noreturn, env, i32, int) DEF_HELPER_2(raise_exception, noreturn, env, i32) DEF_HELPER_1(raise_exception_debug, noreturn, env) =20 -#ifndef CONFIG_USER_ONLY -DEF_HELPER_1(do_semihosting, void, env) -#endif - #ifdef TARGET_MIPS64 DEF_HELPER_4(sdl, void, env, tl, tl, int) DEF_HELPER_4(sdr, void, env, tl, tl, int) @@ -42,164 +38,6 @@ DEF_HELPER_FLAGS_1(dbitswap, TCG_CALL_NO_RWG_SE, tl, tl) =20 DEF_HELPER_FLAGS_4(rotx, TCG_CALL_NO_RWG_SE, tl, tl, i32, i32, i32) =20 -#ifndef CONFIG_USER_ONLY -/* CP0 helpers */ -DEF_HELPER_1(mfc0_mvpcontrol, tl, env) -DEF_HELPER_1(mfc0_mvpconf0, tl, env) -DEF_HELPER_1(mfc0_mvpconf1, tl, env) -DEF_HELPER_1(mftc0_vpecontrol, tl, env) -DEF_HELPER_1(mftc0_vpeconf0, tl, env) -DEF_HELPER_1(mfc0_random, tl, env) -DEF_HELPER_1(mfc0_tcstatus, tl, env) -DEF_HELPER_1(mftc0_tcstatus, tl, env) -DEF_HELPER_1(mfc0_tcbind, tl, env) -DEF_HELPER_1(mftc0_tcbind, tl, env) -DEF_HELPER_1(mfc0_tcrestart, tl, env) -DEF_HELPER_1(mftc0_tcrestart, tl, env) -DEF_HELPER_1(mfc0_tchalt, tl, env) -DEF_HELPER_1(mftc0_tchalt, tl, env) -DEF_HELPER_1(mfc0_tccontext, tl, env) -DEF_HELPER_1(mftc0_tccontext, tl, env) -DEF_HELPER_1(mfc0_tcschedule, tl, env) -DEF_HELPER_1(mftc0_tcschedule, tl, env) -DEF_HELPER_1(mfc0_tcschefback, tl, env) -DEF_HELPER_1(mftc0_tcschefback, tl, env) -DEF_HELPER_1(mfc0_count, tl, env) -DEF_HELPER_1(mfc0_saar, tl, env) -DEF_HELPER_1(mfhc0_saar, tl, env) -DEF_HELPER_1(mftc0_entryhi, tl, env) -DEF_HELPER_1(mftc0_status, tl, env) -DEF_HELPER_1(mftc0_cause, tl, env) -DEF_HELPER_1(mftc0_epc, tl, env) -DEF_HELPER_1(mftc0_ebase, tl, env) -DEF_HELPER_2(mftc0_configx, tl, env, tl) -DEF_HELPER_1(mfc0_lladdr, tl, env) -DEF_HELPER_1(mfc0_maar, tl, env) -DEF_HELPER_1(mfhc0_maar, tl, env) -DEF_HELPER_2(mfc0_watchlo, tl, env, i32) -DEF_HELPER_2(mfc0_watchhi, tl, env, i32) -DEF_HELPER_2(mfhc0_watchhi, tl, env, i32) -DEF_HELPER_1(mfc0_debug, tl, env) -DEF_HELPER_1(mftc0_debug, tl, env) -#ifdef TARGET_MIPS64 -DEF_HELPER_1(dmfc0_tcrestart, tl, env) -DEF_HELPER_1(dmfc0_tchalt, tl, env) -DEF_HELPER_1(dmfc0_tccontext, tl, env) -DEF_HELPER_1(dmfc0_tcschedule, tl, env) -DEF_HELPER_1(dmfc0_tcschefback, tl, env) -DEF_HELPER_1(dmfc0_lladdr, tl, env) -DEF_HELPER_1(dmfc0_maar, tl, env) -DEF_HELPER_2(dmfc0_watchlo, tl, env, i32) -DEF_HELPER_2(dmfc0_watchhi, tl, env, i32) -DEF_HELPER_1(dmfc0_saar, tl, env) -#endif /* TARGET_MIPS64 */ - -DEF_HELPER_2(mtc0_index, void, env, tl) -DEF_HELPER_2(mtc0_mvpcontrol, void, env, tl) -DEF_HELPER_2(mtc0_vpecontrol, void, env, tl) -DEF_HELPER_2(mttc0_vpecontrol, void, env, tl) -DEF_HELPER_2(mtc0_vpeconf0, void, env, tl) -DEF_HELPER_2(mttc0_vpeconf0, void, env, tl) -DEF_HELPER_2(mtc0_vpeconf1, void, env, tl) -DEF_HELPER_2(mtc0_yqmask, void, env, tl) -DEF_HELPER_2(mtc0_vpeopt, void, env, tl) -DEF_HELPER_2(mtc0_entrylo0, void, env, tl) -DEF_HELPER_2(mtc0_tcstatus, void, env, tl) -DEF_HELPER_2(mttc0_tcstatus, void, env, tl) -DEF_HELPER_2(mtc0_tcbind, void, env, tl) -DEF_HELPER_2(mttc0_tcbind, void, env, tl) -DEF_HELPER_2(mtc0_tcrestart, void, env, tl) -DEF_HELPER_2(mttc0_tcrestart, void, env, tl) -DEF_HELPER_2(mtc0_tchalt, void, env, tl) -DEF_HELPER_2(mttc0_tchalt, void, env, tl) -DEF_HELPER_2(mtc0_tccontext, void, env, tl) -DEF_HELPER_2(mttc0_tccontext, void, env, tl) -DEF_HELPER_2(mtc0_tcschedule, void, env, tl) -DEF_HELPER_2(mttc0_tcschedule, void, env, tl) -DEF_HELPER_2(mtc0_tcschefback, void, env, tl) -DEF_HELPER_2(mttc0_tcschefback, void, env, tl) -DEF_HELPER_2(mtc0_entrylo1, void, env, tl) -DEF_HELPER_2(mtc0_context, void, env, tl) -DEF_HELPER_2(mtc0_memorymapid, void, env, tl) -DEF_HELPER_2(mtc0_pagemask, void, env, tl) -DEF_HELPER_2(mtc0_pagegrain, void, env, tl) -DEF_HELPER_2(mtc0_segctl0, void, env, tl) -DEF_HELPER_2(mtc0_segctl1, void, env, tl) -DEF_HELPER_2(mtc0_segctl2, void, env, tl) -DEF_HELPER_2(mtc0_pwfield, void, env, tl) -DEF_HELPER_2(mtc0_pwsize, void, env, tl) -DEF_HELPER_2(mtc0_wired, void, env, tl) -DEF_HELPER_2(mtc0_srsconf0, void, env, tl) -DEF_HELPER_2(mtc0_srsconf1, void, env, tl) -DEF_HELPER_2(mtc0_srsconf2, void, env, tl) -DEF_HELPER_2(mtc0_srsconf3, void, env, tl) -DEF_HELPER_2(mtc0_srsconf4, void, env, tl) -DEF_HELPER_2(mtc0_hwrena, void, env, tl) -DEF_HELPER_2(mtc0_pwctl, void, env, tl) -DEF_HELPER_2(mtc0_count, void, env, tl) -DEF_HELPER_2(mtc0_saari, void, env, tl) -DEF_HELPER_2(mtc0_saar, void, env, tl) -DEF_HELPER_2(mthc0_saar, void, env, tl) -DEF_HELPER_2(mtc0_entryhi, void, env, tl) -DEF_HELPER_2(mttc0_entryhi, void, env, tl) -DEF_HELPER_2(mtc0_compare, void, env, tl) -DEF_HELPER_2(mtc0_status, void, env, tl) -DEF_HELPER_2(mttc0_status, void, env, tl) -DEF_HELPER_2(mtc0_intctl, void, env, tl) -DEF_HELPER_2(mtc0_srsctl, void, env, tl) -DEF_HELPER_2(mtc0_cause, void, env, tl) -DEF_HELPER_2(mttc0_cause, void, env, tl) -DEF_HELPER_2(mtc0_ebase, void, env, tl) -DEF_HELPER_2(mttc0_ebase, void, env, tl) -DEF_HELPER_2(mtc0_config0, void, env, tl) -DEF_HELPER_2(mtc0_config2, void, env, tl) -DEF_HELPER_2(mtc0_config3, void, env, tl) -DEF_HELPER_2(mtc0_config4, void, env, tl) -DEF_HELPER_2(mtc0_config5, void, env, tl) -DEF_HELPER_2(mtc0_lladdr, void, env, tl) -DEF_HELPER_2(mtc0_maar, void, env, tl) -DEF_HELPER_2(mthc0_maar, void, env, tl) -DEF_HELPER_2(mtc0_maari, void, env, tl) -DEF_HELPER_3(mtc0_watchlo, void, env, tl, i32) -DEF_HELPER_3(mtc0_watchhi, void, env, tl, i32) -DEF_HELPER_3(mthc0_watchhi, void, env, tl, i32) -DEF_HELPER_2(mtc0_xcontext, void, env, tl) -DEF_HELPER_2(mtc0_framemask, void, env, tl) -DEF_HELPER_2(mtc0_debug, void, env, tl) -DEF_HELPER_2(mttc0_debug, void, env, tl) -DEF_HELPER_2(mtc0_performance0, void, env, tl) -DEF_HELPER_2(mtc0_errctl, void, env, tl) -DEF_HELPER_2(mtc0_taglo, void, env, tl) -DEF_HELPER_2(mtc0_datalo, void, env, tl) -DEF_HELPER_2(mtc0_taghi, void, env, tl) -DEF_HELPER_2(mtc0_datahi, void, env, tl) - -#if defined(TARGET_MIPS64) -DEF_HELPER_2(dmtc0_entrylo0, void, env, i64) -DEF_HELPER_2(dmtc0_entrylo1, void, env, i64) -#endif - -/* MIPS MT functions */ -DEF_HELPER_2(mftgpr, tl, env, i32) -DEF_HELPER_2(mftlo, tl, env, i32) -DEF_HELPER_2(mfthi, tl, env, i32) -DEF_HELPER_2(mftacx, tl, env, i32) -DEF_HELPER_1(mftdsp, tl, env) -DEF_HELPER_3(mttgpr, void, env, tl, i32) -DEF_HELPER_3(mttlo, void, env, tl, i32) -DEF_HELPER_3(mtthi, void, env, tl, i32) -DEF_HELPER_3(mttacx, void, env, tl, i32) -DEF_HELPER_2(mttdsp, void, env, tl) -DEF_HELPER_0(dmt, tl) -DEF_HELPER_0(emt, tl) -DEF_HELPER_1(dvpe, tl, env) -DEF_HELPER_1(evpe, tl, env) - -/* R6 Multi-threading */ -DEF_HELPER_1(dvp, tl, env) -DEF_HELPER_1(evp, tl, env) -#endif /* !CONFIG_USER_ONLY */ - /* microMIPS functions */ DEF_HELPER_4(lwm, void, env, tl, tl, i32) DEF_HELPER_4(swm, void, env, tl, tl, i32) @@ -783,4 +621,8 @@ DEF_HELPER_FLAGS_2(rddsp, 0, tl, tl, env) =20 DEF_HELPER_3(cache, void, env, tl, i32) =20 +#ifndef CONFIG_USER_ONLY +#include "tcg/sysemu_helper.h.inc" +#endif /* !CONFIG_USER_ONLY */ + #include "msa_helper.h.inc" diff --git a/target/mips/tcg/sysemu_helper.h.inc b/target/mips/tcg/sysemu_h= elper.h.inc new file mode 100644 index 00000000000..d136c4160a7 --- /dev/null +++ b/target/mips/tcg/sysemu_helper.h.inc @@ -0,0 +1,168 @@ +/* + * QEMU MIPS sysemu helpers + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * Copyright (c) 2006 Marius Groeger (FPU operations) + * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support) + * Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support) + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +DEF_HELPER_1(do_semihosting, void, env) + +/* CP0 helpers */ +DEF_HELPER_1(mfc0_mvpcontrol, tl, env) +DEF_HELPER_1(mfc0_mvpconf0, tl, env) +DEF_HELPER_1(mfc0_mvpconf1, tl, env) +DEF_HELPER_1(mftc0_vpecontrol, tl, env) +DEF_HELPER_1(mftc0_vpeconf0, tl, env) +DEF_HELPER_1(mfc0_random, tl, env) +DEF_HELPER_1(mfc0_tcstatus, tl, env) +DEF_HELPER_1(mftc0_tcstatus, tl, env) +DEF_HELPER_1(mfc0_tcbind, tl, env) +DEF_HELPER_1(mftc0_tcbind, tl, env) +DEF_HELPER_1(mfc0_tcrestart, tl, env) +DEF_HELPER_1(mftc0_tcrestart, tl, env) +DEF_HELPER_1(mfc0_tchalt, tl, env) +DEF_HELPER_1(mftc0_tchalt, tl, env) +DEF_HELPER_1(mfc0_tccontext, tl, env) +DEF_HELPER_1(mftc0_tccontext, tl, env) +DEF_HELPER_1(mfc0_tcschedule, tl, env) +DEF_HELPER_1(mftc0_tcschedule, tl, env) +DEF_HELPER_1(mfc0_tcschefback, tl, env) +DEF_HELPER_1(mftc0_tcschefback, tl, env) +DEF_HELPER_1(mfc0_count, tl, env) +DEF_HELPER_1(mfc0_saar, tl, env) +DEF_HELPER_1(mfhc0_saar, tl, env) +DEF_HELPER_1(mftc0_entryhi, tl, env) +DEF_HELPER_1(mftc0_status, tl, env) +DEF_HELPER_1(mftc0_cause, tl, env) +DEF_HELPER_1(mftc0_epc, tl, env) +DEF_HELPER_1(mftc0_ebase, tl, env) +DEF_HELPER_2(mftc0_configx, tl, env, tl) +DEF_HELPER_1(mfc0_lladdr, tl, env) +DEF_HELPER_1(mfc0_maar, tl, env) +DEF_HELPER_1(mfhc0_maar, tl, env) +DEF_HELPER_2(mfc0_watchlo, tl, env, i32) +DEF_HELPER_2(mfc0_watchhi, tl, env, i32) +DEF_HELPER_2(mfhc0_watchhi, tl, env, i32) +DEF_HELPER_1(mfc0_debug, tl, env) +DEF_HELPER_1(mftc0_debug, tl, env) +#ifdef TARGET_MIPS64 +DEF_HELPER_1(dmfc0_tcrestart, tl, env) +DEF_HELPER_1(dmfc0_tchalt, tl, env) +DEF_HELPER_1(dmfc0_tccontext, tl, env) +DEF_HELPER_1(dmfc0_tcschedule, tl, env) +DEF_HELPER_1(dmfc0_tcschefback, tl, env) +DEF_HELPER_1(dmfc0_lladdr, tl, env) +DEF_HELPER_1(dmfc0_maar, tl, env) +DEF_HELPER_2(dmfc0_watchlo, tl, env, i32) +DEF_HELPER_2(dmfc0_watchhi, tl, env, i32) +DEF_HELPER_1(dmfc0_saar, tl, env) +#endif /* TARGET_MIPS64 */ + +DEF_HELPER_2(mtc0_index, void, env, tl) +DEF_HELPER_2(mtc0_mvpcontrol, void, env, tl) +DEF_HELPER_2(mtc0_vpecontrol, void, env, tl) +DEF_HELPER_2(mttc0_vpecontrol, void, env, tl) +DEF_HELPER_2(mtc0_vpeconf0, void, env, tl) +DEF_HELPER_2(mttc0_vpeconf0, void, env, tl) +DEF_HELPER_2(mtc0_vpeconf1, void, env, tl) +DEF_HELPER_2(mtc0_yqmask, void, env, tl) +DEF_HELPER_2(mtc0_vpeopt, void, env, tl) +DEF_HELPER_2(mtc0_entrylo0, void, env, tl) +DEF_HELPER_2(mtc0_tcstatus, void, env, tl) +DEF_HELPER_2(mttc0_tcstatus, void, env, tl) +DEF_HELPER_2(mtc0_tcbind, void, env, tl) +DEF_HELPER_2(mttc0_tcbind, void, env, tl) +DEF_HELPER_2(mtc0_tcrestart, void, env, tl) +DEF_HELPER_2(mttc0_tcrestart, void, env, tl) +DEF_HELPER_2(mtc0_tchalt, void, env, tl) +DEF_HELPER_2(mttc0_tchalt, void, env, tl) +DEF_HELPER_2(mtc0_tccontext, void, env, tl) +DEF_HELPER_2(mttc0_tccontext, void, env, tl) +DEF_HELPER_2(mtc0_tcschedule, void, env, tl) +DEF_HELPER_2(mttc0_tcschedule, void, env, tl) +DEF_HELPER_2(mtc0_tcschefback, void, env, tl) +DEF_HELPER_2(mttc0_tcschefback, void, env, tl) +DEF_HELPER_2(mtc0_entrylo1, void, env, tl) +DEF_HELPER_2(mtc0_context, void, env, tl) +DEF_HELPER_2(mtc0_memorymapid, void, env, tl) +DEF_HELPER_2(mtc0_pagemask, void, env, tl) +DEF_HELPER_2(mtc0_pagegrain, void, env, tl) +DEF_HELPER_2(mtc0_segctl0, void, env, tl) +DEF_HELPER_2(mtc0_segctl1, void, env, tl) +DEF_HELPER_2(mtc0_segctl2, void, env, tl) +DEF_HELPER_2(mtc0_pwfield, void, env, tl) +DEF_HELPER_2(mtc0_pwsize, void, env, tl) +DEF_HELPER_2(mtc0_wired, void, env, tl) +DEF_HELPER_2(mtc0_srsconf0, void, env, tl) +DEF_HELPER_2(mtc0_srsconf1, void, env, tl) +DEF_HELPER_2(mtc0_srsconf2, void, env, tl) +DEF_HELPER_2(mtc0_srsconf3, void, env, tl) +DEF_HELPER_2(mtc0_srsconf4, void, env, tl) +DEF_HELPER_2(mtc0_hwrena, void, env, tl) +DEF_HELPER_2(mtc0_pwctl, void, env, tl) +DEF_HELPER_2(mtc0_count, void, env, tl) +DEF_HELPER_2(mtc0_saari, void, env, tl) +DEF_HELPER_2(mtc0_saar, void, env, tl) +DEF_HELPER_2(mthc0_saar, void, env, tl) +DEF_HELPER_2(mtc0_entryhi, void, env, tl) +DEF_HELPER_2(mttc0_entryhi, void, env, tl) +DEF_HELPER_2(mtc0_compare, void, env, tl) +DEF_HELPER_2(mtc0_status, void, env, tl) +DEF_HELPER_2(mttc0_status, void, env, tl) +DEF_HELPER_2(mtc0_intctl, void, env, tl) +DEF_HELPER_2(mtc0_srsctl, void, env, tl) +DEF_HELPER_2(mtc0_cause, void, env, tl) +DEF_HELPER_2(mttc0_cause, void, env, tl) +DEF_HELPER_2(mtc0_ebase, void, env, tl) +DEF_HELPER_2(mttc0_ebase, void, env, tl) +DEF_HELPER_2(mtc0_config0, void, env, tl) +DEF_HELPER_2(mtc0_config2, void, env, tl) +DEF_HELPER_2(mtc0_config3, void, env, tl) +DEF_HELPER_2(mtc0_config4, void, env, tl) +DEF_HELPER_2(mtc0_config5, void, env, tl) +DEF_HELPER_2(mtc0_lladdr, void, env, tl) +DEF_HELPER_2(mtc0_maar, void, env, tl) +DEF_HELPER_2(mthc0_maar, void, env, tl) +DEF_HELPER_2(mtc0_maari, void, env, tl) +DEF_HELPER_3(mtc0_watchlo, void, env, tl, i32) +DEF_HELPER_3(mtc0_watchhi, void, env, tl, i32) +DEF_HELPER_3(mthc0_watchhi, void, env, tl, i32) +DEF_HELPER_2(mtc0_xcontext, void, env, tl) +DEF_HELPER_2(mtc0_framemask, void, env, tl) +DEF_HELPER_2(mtc0_debug, void, env, tl) +DEF_HELPER_2(mttc0_debug, void, env, tl) +DEF_HELPER_2(mtc0_performance0, void, env, tl) +DEF_HELPER_2(mtc0_errctl, void, env, tl) +DEF_HELPER_2(mtc0_taglo, void, env, tl) +DEF_HELPER_2(mtc0_datalo, void, env, tl) +DEF_HELPER_2(mtc0_taghi, void, env, tl) +DEF_HELPER_2(mtc0_datahi, void, env, tl) + +#if defined(TARGET_MIPS64) +DEF_HELPER_2(dmtc0_entrylo0, void, env, i64) +DEF_HELPER_2(dmtc0_entrylo1, void, env, i64) +#endif + +/* MIPS MT functions */ +DEF_HELPER_2(mftgpr, tl, env, i32) +DEF_HELPER_2(mftlo, tl, env, i32) +DEF_HELPER_2(mfthi, tl, env, i32) +DEF_HELPER_2(mftacx, tl, env, i32) +DEF_HELPER_1(mftdsp, tl, env) +DEF_HELPER_3(mttgpr, void, env, tl, i32) +DEF_HELPER_3(mttlo, void, env, tl, i32) +DEF_HELPER_3(mtthi, void, env, tl, i32) +DEF_HELPER_3(mttacx, void, env, tl, i32) +DEF_HELPER_2(mttdsp, void, env, tl) +DEF_HELPER_0(dmt, tl) +DEF_HELPER_0(emt, tl) +DEF_HELPER_1(dvpe, tl, env) +DEF_HELPER_1(evpe, tl, env) + +/* R6 Multi-threading */ +DEF_HELPER_1(dvp, tl, env) +DEF_HELPER_1(evp, tl, env) diff --git a/target/mips/cp0_helper.c b/target/mips/tcg/sysemu/cp0_helper.c similarity index 100% rename from target/mips/cp0_helper.c rename to target/mips/tcg/sysemu/cp0_helper.c diff --git a/target/mips/mips-semi.c b/target/mips/tcg/sysemu/mips-semi.c similarity index 100% rename from target/mips/mips-semi.c rename to target/mips/tcg/sysemu/mips-semi.c diff --git a/target/mips/meson.build b/target/mips/meson.build index 9a507937ece..a55af1cd6cf 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -47,11 +47,6 @@ =20 mips_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) =20 -mips_softmmu_ss.add(when: 'CONFIG_TCG', if_true: files( - 'cp0_helper.c', - 'mips-semi.c', -)) - mips_ss.add_all(when: 'CONFIG_TCG', if_true: [mips_tcg_ss]) =20 target_arch +=3D {'mips': mips_ss} diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build index b74fa04303e..2cffc5a5ac6 100644 --- a/target/mips/tcg/meson.build +++ b/target/mips/tcg/meson.build @@ -1,3 +1,6 @@ if have_user subdir('user') endif +if have_system + subdir('sysemu') +endif diff --git a/target/mips/tcg/sysemu/meson.build b/target/mips/tcg/sysemu/me= son.build new file mode 100644 index 00000000000..5c3024e7760 --- /dev/null +++ b/target/mips/tcg/sysemu/meson.build @@ -0,0 +1,4 @@ +mips_softmmu_ss.add(files( + 'cp0_helper.c', + 'mips-semi.c', +)) --=20 2.26.3 From nobody Sat May 4 03:43:33 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.53 as permitted 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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id f6sm23205854wrt.19.2021.04.19.12.20.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Apr 2021 12:20:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UwCC1UpHM/jSWsuRMtR8URBWtsAsFHj4UD0F2s/h0Ok=; b=fv7qWImZs3AEUxNs+qc7ml/ZdGa28Yg5n5a8Tqz571jzDXQ7DxpFaRy08zzgw2kB8D lOMxNaMJgexxrFIKaaydstcayMI2IAYE95oA8iPFQ3XvYKzZYp18nby/aHsus+cKnplQ 310kwe1RZt/L90z2Xw86z5Ga0+5dAPKHJ99nejM3sE4LztOEQ+QIPIetCP02133aBsNZ SJiREfb5aJyPfM9lCSIemXs9yNw8fQozIUtm5a+sCODgKYoj3qMlliUv8SGbE5jKlnjt h18RA1ZIKos1rZQBeArSAJo+Ab9LqAC+RjucZrwBQ5fb2ObbmFZpLoXAqvaH2tKsJX7s 7+7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=UwCC1UpHM/jSWsuRMtR8URBWtsAsFHj4UD0F2s/h0Ok=; b=gyNeoQZFPL6eRIzIVGriqmWUnz7TGJEwW9uW5frej2RRpmwWVytuwjtr5R8LvfN9ct MjkJIEuyygjTNDcDimDbm8OP311sCu/5fR0mk4Fm2Oh3ZZBrHwVC/3L73ZBhLhv3W7t7 K1xag5J2NqslVsrxbL+HLx+31Uo0Sgx/5MOxmL7R2Axlgvh3qGd+phJGqir93ARqWmQU 9hQd2FN7C4+Ag++5+PNj7i4S0nBgLvzNkhtzg/yoVdYITyLFIQlEjO1jJWcOkMkWJIZK us3FFqi67tls/exN6KDq2BzN7urmho31q0O2ZaGioNBqoucwU+69mMQhk3b2W3UlIaGO jFrA== X-Gm-Message-State: AOAM531KOHUVvXNxsaLmzWZgavk8vy/lTVZaIEqFfuyCqkrYq/wAF31h FMgL2Pq08SjXJd7pZLYWv9c= X-Google-Smtp-Source: ABdhPJzoBqsZuthHYTUeH6znYQsbEnJI4YV/zEq802EjjBvOvezqMHTzjVvIn7wpQG8ZpF71juUj5A== X-Received: by 2002:a05:600c:49a4:: with SMTP id h36mr593878wmp.102.1618860002718; Mon, 19 Apr 2021 12:20:02 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Aurelien Jarno , Huacai Chen Subject: [PATCH v3 20/30] target/mips: Restrict mmu_init() to TCG Date: Mon, 19 Apr 2021 21:18:13 +0200 Message-Id: <20210419191823.1555482-21-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210419191823.1555482-1-f4bug@amsat.org> References: <20210419191823.1555482-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) mmu_init() is only required by TCG accelerator. Restrict its declaration and call to TCG. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/internal.h | 3 --- target/mips/tcg/tcg-internal.h | 2 ++ target/mips/cpu.c | 2 +- 3 files changed, 3 insertions(+), 4 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 0bce0950b2c..54e6f08f560 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -233,9 +233,6 @@ void cpu_mips_store_compare(CPUMIPSState *env, uint32_t= value); void cpu_mips_start_count(CPUMIPSState *env); void cpu_mips_stop_count(CPUMIPSState *env); =20 -/* helper.c */ -void mmu_init(CPUMIPSState *env, const mips_def_t *def); - static inline void mips_cpu_set_error_pc(CPUMIPSState *env, target_ulong error_pc) { diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h index b65580af211..70655bab45c 100644 --- a/target/mips/tcg/tcg-internal.h +++ b/target/mips/tcg/tcg-internal.h @@ -20,6 +20,8 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int s= ize, =20 #if !defined(CONFIG_USER_ONLY) =20 +void mmu_init(CPUMIPSState *env, const mips_def_t *def); + void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagema= sk); =20 uint32_t cpu_mips_get_random(CPUMIPSState *env); diff --git a/target/mips/cpu.c b/target/mips/cpu.c index fcbf95c85b9..acc149aa573 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -708,7 +708,7 @@ static void mips_cpu_realizefn(DeviceState *dev, Error = **errp) =20 env->exception_base =3D (int32_t)0xBFC00000; =20 -#ifndef CONFIG_USER_ONLY +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) mmu_init(env, env->cpu_model); #endif fpu_init(env, env->cpu_model); --=20 2.26.3 From nobody Sat May 4 03:43:33 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.52 as permitted sender) client-ip=209.85.221.52; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f52.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.52 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1618860009; cv=none; d=zohomail.com; s=zohoarc; b=i1eyzHTrS6QlmZOWIKMm9NONJWL7FfstGhRpx1Qm5fKBKX2cAjfe5eMjmPpYs6hCHDi9EP/h/bBEzxaZu2/5ZOwXbKtMun3T+isv0G75cGEqhWPGTikmYNn+sRTRox13AX3Uur8qCSz56Ka4/ry14uxQFo9LY4momVJx99WttqM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618860009; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=PmE6YNiEEWOqWH949FeQoKLVzK9sT0nBJARzY8QGy1E=; b=ngi1gXXhJzwWUY33rNEm5hTTD6w4cF/EIP19Sg9wVcRPV9W+4wax00dwQrwC85M7eL7pk6/5KNcnZpyqr6F1m8BqHDSxorXgGxu0l6Y0DiJhwtpvLBhfNeQqjcBgn8XKvmKUZMyu7x2TAEAP6OXBMjD532ccgi0YmwrHTiNfYgM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.52 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f52.google.com (mail-wr1-f52.google.com [209.85.221.52]) by mx.zohomail.com with SMTPS id 1618860009225652.618093032304; Mon, 19 Apr 2021 12:20:09 -0700 (PDT) Received: by mail-wr1-f52.google.com with SMTP id s7so35088320wru.6 for ; Mon, 19 Apr 2021 12:20:08 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.redhat.com (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id q17sm24541898wro.33.2021.04.19.12.20.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Apr 2021 12:20:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PmE6YNiEEWOqWH949FeQoKLVzK9sT0nBJARzY8QGy1E=; b=of3H/mr0kvHEQk4FH8Q8pYKw2VoI0FjESBgXvK+PdncK9KrUilUGC5t7VAxmgffepR AllM8P+a3xZuplYTO/DdWwIgmRI5Neb5aCFaX6d6E+58tb/kKctf9rsgbN//6NTTDLgO HSMdTs3Lz4K26gRYl+OWy+4+eVOYEj2OmeCk1TmusaenOjAd9mjJ0fsr4W5pkpXQ4tIq JkHDDcqnzf5DZ1YFpS/u7x4oHhtEKJ/UfqRqX5EcUOujOejYyoguql0apEywnJ6ycNbm pLrj/XZKaIKNUmLFc1a9bhohwbu7G+TEHZ1ct2xQo5RE228JuSJrP7qsN0Sdx1Pvpmug 07Bg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=PmE6YNiEEWOqWH949FeQoKLVzK9sT0nBJARzY8QGy1E=; b=e7WYzEd/7QytpO4ZM3RVPZz+D21yUugUuJGlHIviF4DI/Z7fIRl93khEBDX2YayOUP Pt9B1+xZ5XTkklZDqVAMDCdPUi76EEdwNMnf2ZufmnyC5doqz3RcGNDTuHjJ5Jashfse AcRifde1hCQSepAO1kOZLVQ/yqaEh7n8TrGovzcuTFl3Ic6f2xpRvr/0tho3h+v1Y0sy Q0Sqr1wWj9UJA194XdGnAOWXJZTUKotVvfrq5T5XryJ2uamIZ9n2JVulMMldiwWTi6yw 8kqyFgm7g7XO8Xiic5VVhNsz9i4ie2eeCmjFQ9WvFOZ44Jxqk2PLqum/YZ7EeCaE72n1 TTAw== X-Gm-Message-State: AOAM533RZTCf/ufkyajB3wdF/AtUcNyrbs60W0WFCl73RlvjEepbg1wx z5ETKon8xQaezJdfD628hTs= X-Google-Smtp-Source: ABdhPJxaMMccGaAl8RuELytqoeq1oOlhknL8mce5L3r7Y4JbTE0Dw/WBGwqWjQtIzlNayMBbOm33BA== X-Received: by 2002:a5d:47cc:: with SMTP id o12mr16092221wrc.227.1618860007509; Mon, 19 Apr 2021 12:20:07 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Aurelien Jarno , Huacai Chen Subject: [PATCH v3 21/30] target/mips: Move tlb_helper.c to tcg/sysemu/ Date: Mon, 19 Apr 2021 21:18:14 +0200 Message-Id: <20210419191823.1555482-22-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210419191823.1555482-1-f4bug@amsat.org> References: <20210419191823.1555482-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Move tlb_helper.c to the tcg/sysemu/ subdir, along with the following 3 declarations to tcg-internal.h: - cpu_mips_tlb_flush() - cpu_mips_translate_address() - r4k_invalidate_tlb() Simplify tlb_helper.c #ifdef'ry because files in tcg/sysemu/ are only build when sysemu mode is configured. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/internal.h | 5 ----- target/mips/tcg/tcg-internal.h | 5 +++++ target/mips/{ =3D> tcg/sysemu}/tlb_helper.c | 3 --- target/mips/meson.build | 1 - target/mips/tcg/sysemu/meson.build | 1 + 5 files changed, 6 insertions(+), 9 deletions(-) rename target/mips/{ =3D> tcg/sysemu}/tlb_helper.c (99%) diff --git a/target/mips/internal.h b/target/mips/internal.h index 54e6f08f560..df419760df0 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -164,16 +164,12 @@ void r4k_helper_tlbp(CPUMIPSState *env); void r4k_helper_tlbr(CPUMIPSState *env); void r4k_helper_tlbinv(CPUMIPSState *env); void r4k_helper_tlbinvf(CPUMIPSState *env); -void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra); =20 void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retadd= r); -hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, - MMUAccessType access_type, uintptr_t ret= addr); - extern const VMStateDescription vmstate_mips_cpu; =20 #endif /* !CONFIG_USER_ONLY */ @@ -424,7 +420,6 @@ static inline void compute_hflags(CPUMIPSState *env) } } =20 -void cpu_mips_tlb_flush(CPUMIPSState *env); void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc); void cpu_mips_store_status(CPUMIPSState *env, target_ulong val); void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val); diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h index 70655bab45c..a39ff45d58f 100644 --- a/target/mips/tcg/tcg-internal.h +++ b/target/mips/tcg/tcg-internal.h @@ -24,8 +24,13 @@ void mmu_init(CPUMIPSState *env, const mips_def_t *def); =20 void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagema= sk); =20 +void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra); uint32_t cpu_mips_get_random(CPUMIPSState *env); =20 +hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, + MMUAccessType access_type, uintptr_t ret= addr); +void cpu_mips_tlb_flush(CPUMIPSState *env); + #endif /* !CONFIG_USER_ONLY */ =20 #endif diff --git a/target/mips/tlb_helper.c b/target/mips/tcg/sysemu/tlb_helper.c similarity index 99% rename from target/mips/tlb_helper.c rename to target/mips/tcg/sysemu/tlb_helper.c index bfb08eaf506..bf242f5e65a 100644 --- a/target/mips/tlb_helper.c +++ b/target/mips/tcg/sysemu/tlb_helper.c @@ -25,8 +25,6 @@ #include "exec/log.h" #include "hw/mips/cpudevs.h" =20 -#if !defined(CONFIG_USER_ONLY) - /* no MMU emulation */ int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, target_ulong address, MMUAccessType access_type) @@ -1072,4 +1070,3 @@ void r4k_invalidate_tlb(CPUMIPSState *env, int idx, i= nt use_extra) } } } -#endif /* !CONFIG_USER_ONLY */ diff --git a/target/mips/meson.build b/target/mips/meson.build index a55af1cd6cf..ff5eb210dfd 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -31,7 +31,6 @@ 'msa_translate.c', 'op_helper.c', 'rel6_translate.c', - 'tlb_helper.c', 'translate.c', 'translate_addr_const.c', 'txx9_translate.c', diff --git a/target/mips/tcg/sysemu/meson.build b/target/mips/tcg/sysemu/me= son.build index 5c3024e7760..73ab9571ba6 100644 --- a/target/mips/tcg/sysemu/meson.build +++ b/target/mips/tcg/sysemu/meson.build @@ -1,4 +1,5 @@ mips_softmmu_ss.add(files( 'cp0_helper.c', 'mips-semi.c', + 'tlb_helper.c', )) --=20 2.26.3 From nobody Sat May 4 03:43:33 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.47 as permitted sender) client-ip=209.85.128.47; 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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id f6sm23206333wrt.19.2021.04.19.12.20.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Apr 2021 12:20:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uiRGPC8hJpSSu/BlNtbaRgowW+aTxxcCgHW1Tb9Qg8I=; b=SyBNtQ/i3AvzeUSxBP45Qkv/h3PE+RqZ2uRSldvZwVSjBYx0Lu3mZMcoTIQ7S1xNCi Niz3LYpgAl9Csd9lgIO9kgsN8CwmooVMbVF7wDXN+lRzISGUfKfnDnlR8rzAIY2r7uWP qpdBYbr8fdqfufoa4uUdpx79WSl/3eVdEoooFK9q7ZEFvXSz2Dagbse8+Bzjb0sMwgFC iyvjAKxALEAQjGdDJTlk2+FEcKrktdUrO1hGxddA1Q8u3Q5KIdo4qClPocd1c0Dxumu+ wxOV1NkoTRYETFt3D6LTrvn0otEu/PEPwhU70/LRLzVTgHwfOt4pW+mh/fSXL38xxIXZ VH3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=uiRGPC8hJpSSu/BlNtbaRgowW+aTxxcCgHW1Tb9Qg8I=; b=FuPFhITZX2YnCnZMhdgWEb89aypc0QgSCJPHhXxCBHUQE8Oc84UCCfvMiD8mrCN9dU 3TPv7+QKC6nNDSRQREN/AJg9z25dcqXDROi8sqYjh6lPmS5coixwjxrMidd5h3aEmAFr Petox1GcJ3vaEw7TaT47Z1gowYP3E4MYFlGM7X8+a8cBn+2UVRMES43Idm8r/CNvQ7UZ sf5ZoHOpf0YKIGk1BHZDGWhg2GU10opDldk5PqUU62SsXzPzyProlUU43hGGgcnciJ+f gL6+4QF6JoiweOkM7BzdEEDG1hFHLiZhFfI4YERXZx4715QggHiLfxFnTsqytbkHjsar uh/A== X-Gm-Message-State: AOAM531oTgRymk2/ywVT75+Uc+cPsb1NR7vviCT3We+Kt3v0vW/yCO4E oTMiBKnSefz3HWKG58avSNk= X-Google-Smtp-Source: ABdhPJzgSog+d1Q/wnTHYZH6tLUQIXxps0d7V5Htbd1Jk2+qe9O+oTB0G74unMCg1mad2fvcr+m1+g== X-Received: by 2002:a1c:e20a:: with SMTP id z10mr570824wmg.158.1618860012408; Mon, 19 Apr 2021 12:20:12 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Aurelien Jarno , Huacai Chen Subject: [PATCH v3 22/30] target/mips: Restrict CPUMIPSTLBContext::map_address() handlers scope Date: Mon, 19 Apr 2021 21:18:15 +0200 Message-Id: <20210419191823.1555482-23-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210419191823.1555482-1-f4bug@amsat.org> References: <20210419191823.1555482-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) The 3 map_address() handlers are local to tlb_helper.c, no need to have their prototype declared publically. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/internal.h | 6 ------ target/mips/tcg/sysemu/tlb_helper.c | 13 +++++++------ 2 files changed, 7 insertions(+), 12 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index df419760df0..a59e2f9007d 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -152,12 +152,6 @@ struct CPUMIPSTLBContext { } mmu; }; =20 -int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, - target_ulong address, MMUAccessType access_type); -int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, - target_ulong address, MMUAccessType access_type); -int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, - target_ulong address, MMUAccessType access_type); void r4k_helper_tlbwi(CPUMIPSState *env); void r4k_helper_tlbwr(CPUMIPSState *env); void r4k_helper_tlbp(CPUMIPSState *env); diff --git a/target/mips/tcg/sysemu/tlb_helper.c b/target/mips/tcg/sysemu/t= lb_helper.c index bf242f5e65a..a45146a2b21 100644 --- a/target/mips/tcg/sysemu/tlb_helper.c +++ b/target/mips/tcg/sysemu/tlb_helper.c @@ -26,8 +26,8 @@ #include "hw/mips/cpudevs.h" =20 /* no MMU emulation */ -int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, - target_ulong address, MMUAccessType access_type) +static int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *pr= ot, + target_ulong address, MMUAccessType access_t= ype) { *physical =3D address; *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; @@ -35,8 +35,9 @@ int no_mmu_map_address(CPUMIPSState *env, hwaddr *physica= l, int *prot, } =20 /* fixed mapping MMU emulation */ -int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, - target_ulong address, MMUAccessType access_type) +static int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, + int *prot, target_ulong address, + MMUAccessType access_type) { if (address <=3D (int32_t)0x7FFFFFFFUL) { if (!(env->CP0_Status & (1 << CP0St_ERL))) { @@ -55,8 +56,8 @@ int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *phys= ical, int *prot, } =20 /* MIPS32/MIPS64 R4000-style MMU emulation */ -int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, - target_ulong address, MMUAccessType access_type) +static int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, + target_ulong address, MMUAccessType access_type) { uint16_t ASID =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; uint32_t MMID =3D env->CP0_MemoryMapID; --=20 2.26.3 From nobody Sat May 4 03:43:33 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.52 as permitted sender) client-ip=209.85.128.52; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f52.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.52 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1618860019; cv=none; d=zohomail.com; s=zohoarc; b=K37SUnvFBc55dg7OfJP/2SpN3CiEIWBHb9RQ0hDowqwAAuw8FCmIUQ1ACR2mMd/hcGai+FToOS1gv3FSwAtHIxkdpBqj4MiRKK6mB/azOpHqnClRKfAPnz76bWQjplX7FVi2vlNSSgIEyVr6zHv5/CuWhVcMTieyrNV9ws1SM7M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618860019; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=2O/rfqAOfFA91W5zmHxQIZ6TpA3HwDBWMjRpiOJ2wYI=; b=llKqsGn4I+gv4Y9EowDZcxLDXtTL6/eTeQGBlGioQ6K878UsK5+wdkFrZXbilkfdz1JH+LpEZDoo9Q5XzskLzS1GTtlPxeCNaP89CWqRpI4MLSA4qxRy4O9p3ku2mIT7ytp6128FOlHS3CXdw7VzMLO8rkkQclrPbUnzbeiqJ80= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.52 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) by mx.zohomail.com with SMTPS id 1618860019053299.14807416117253; Mon, 19 Apr 2021 12:20:19 -0700 (PDT) Received: by mail-wm1-f52.google.com with SMTP id n4-20020a05600c4f84b029013151278decso7454253wmq.4 for ; Mon, 19 Apr 2021 12:20:18 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.redhat.com (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id s14sm24495293wrm.51.2021.04.19.12.20.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Apr 2021 12:20:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2O/rfqAOfFA91W5zmHxQIZ6TpA3HwDBWMjRpiOJ2wYI=; b=qQ/1NiHsuPs8qi0gdo6NBSxCWqaDhGHDxQT4VOfeN+zj8JmKelX0m532oOHWS3KkEl gqk5OvpTKTT02faai9tN2CtZ3ks2kkfIWCqvms08vw8bENP5+qNRUVFVKDf1uwYInKf6 RsAQaNmdKqlWceRtrL1GCwkCSrifhVMbWK73yH7sA005HQAwv+Pk1bYmjU1wh8lbuVta NUG6Q3R0XuwOAUBOcZ2O+izNTD9Nx310DCmUh7t31jgZMEgbFQtl8/I45+d6B/xHF2kk xFbkMLVKOl/viQqLSjnJxZkHcZbGSKVYCKkgz3oh91SCQ5PeE/EOK9StuFXLoT1s+pXT AOOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=2O/rfqAOfFA91W5zmHxQIZ6TpA3HwDBWMjRpiOJ2wYI=; b=EoHe7/oc1AjW+7pPn0+SbaB9HOEWOZwm+LmkwXR9RlgKa0lv284D5TCvnX1BRsQiFN /jvGRWDEcCqFMO2rWmU6qN7F3KpUPqJ42nJjsuXNvJzjjJ4VOgROFMDRNhyINhgG+adL 82I4qUPqkarm0MJ19EJktHVSGp1mJKTXGtB70KbswLMmneiZfT/Wg36zBBXODmecJyXO 8GK9jL2siaTcrFzxEazcpm2hL1RLF+P5j1im6GCfpDB+RZ2A8v/I9HnN5n3JRn71SrWA WZJbDrEDs68qVUBes5H4wwJ3O9Fh8zq9kIMC7KYZ36KRfbQzlW5UTkAECJXVsBYTYJ1S elRg== X-Gm-Message-State: AOAM530mgvffThW380J6C3f16YW+2lT+2j9NIcuvKYojYxvQ/BOOpSf3 FJL1mMWRzgiNry60WxPwwNw= X-Google-Smtp-Source: ABdhPJxEuQL/8ftwN7ca99xNgxSxxaPwn20OoWaU3lse7jwOUBmNxjyOyJHDeyMZq79tnykNka2aag== X-Received: by 2002:a1c:1d0d:: with SMTP id d13mr577334wmd.90.1618860017186; Mon, 19 Apr 2021 12:20:17 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Aurelien Jarno , Huacai Chen Subject: [PATCH v3 23/30] target/mips: Move Special opcodes to tcg/sysemu/special_helper.c Date: Mon, 19 Apr 2021 21:18:16 +0200 Message-Id: <20210419191823.1555482-24-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210419191823.1555482-1-f4bug@amsat.org> References: <20210419191823.1555482-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Move the Special opcodes helpers to tcg/sysemu/special_helper.c. Since mips_io_recompile_replay_branch() is set as CPUClass::io_recompile_replay_branch handler in cpu.c, we need to declare its prototype in "tcg-internal.h". Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/helper.h | 5 - target/mips/tcg/tcg-internal.h | 3 + target/mips/tcg/sysemu_helper.h.inc | 7 ++ target/mips/cpu.c | 17 --- target/mips/op_helper.c | 100 ----------------- target/mips/tcg/sysemu/special_helper.c | 140 ++++++++++++++++++++++++ target/mips/tcg/sysemu/meson.build | 1 + 7 files changed, 151 insertions(+), 122 deletions(-) create mode 100644 target/mips/tcg/sysemu/special_helper.c diff --git a/target/mips/helper.h b/target/mips/helper.h index bc308e5db13..4ee7916d8b2 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -210,11 +210,6 @@ DEF_HELPER_1(tlbp, void, env) DEF_HELPER_1(tlbr, void, env) DEF_HELPER_1(tlbinv, void, env) DEF_HELPER_1(tlbinvf, void, env) -DEF_HELPER_1(di, tl, env) -DEF_HELPER_1(ei, tl, env) -DEF_HELPER_1(eret, void, env) -DEF_HELPER_1(eretnc, void, env) -DEF_HELPER_1(deret, void, env) DEF_HELPER_3(ginvt, void, env, tl, i32) #endif /* !CONFIG_USER_ONLY */ DEF_HELPER_1(rdhwr_cpunum, tl, env) diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h index a39ff45d58f..73667b35778 100644 --- a/target/mips/tcg/tcg-internal.h +++ b/target/mips/tcg/tcg-internal.h @@ -10,6 +10,7 @@ #ifndef MIPS_TCG_INTERNAL_H #define MIPS_TCG_INTERNAL_H =20 +#include "tcg/tcg.h" #include "hw/core/cpu.h" #include "cpu.h" =20 @@ -27,6 +28,8 @@ void update_pagemask(CPUMIPSState *env, target_ulong arg1= , int32_t *pagemask); void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra); uint32_t cpu_mips_get_random(CPUMIPSState *env); =20 +bool mips_io_recompile_replay_branch(CPUState *cs, const TranslationBlock = *tb); + hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, MMUAccessType access_type, uintptr_t ret= addr); void cpu_mips_tlb_flush(CPUMIPSState *env); diff --git a/target/mips/tcg/sysemu_helper.h.inc b/target/mips/tcg/sysemu_h= elper.h.inc index d136c4160a7..38e55cbf118 100644 --- a/target/mips/tcg/sysemu_helper.h.inc +++ b/target/mips/tcg/sysemu_helper.h.inc @@ -166,3 +166,10 @@ DEF_HELPER_1(evpe, tl, env) /* R6 Multi-threading */ DEF_HELPER_1(dvp, tl, env) DEF_HELPER_1(evp, tl, env) + +/* Special */ +DEF_HELPER_1(di, tl, env) +DEF_HELPER_1(ei, tl, env) +DEF_HELPER_1(eret, void, env) +DEF_HELPER_1(eretnc, void, env) +DEF_HELPER_1(deret, void, env) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index acc149aa573..949b8ef94ea 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -342,23 +342,6 @@ static void mips_cpu_synchronize_from_tb(CPUState *cs, env->hflags &=3D ~MIPS_HFLAG_BMASK; env->hflags |=3D tb->flags & MIPS_HFLAG_BMASK; } - -# ifndef CONFIG_USER_ONLY -static bool mips_io_recompile_replay_branch(CPUState *cs, - const TranslationBlock *tb) -{ - MIPSCPU *cpu =3D MIPS_CPU(cs); - CPUMIPSState *env =3D &cpu->env; - - if ((env->hflags & MIPS_HFLAG_BMASK) !=3D 0 - && env->active_tc.PC !=3D tb->pc) { - env->active_tc.PC -=3D (env->hflags & MIPS_HFLAG_B16 ? 2 : 4); - env->hflags &=3D ~MIPS_HFLAG_BMASK; - return true; - } - return false; -} -# endif /* !CONFIG_USER_ONLY */ #endif /* CONFIG_TCG */ =20 static bool mips_cpu_has_work(CPUState *cs) diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 47d67053f4b..a077535194b 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -655,106 +655,6 @@ void helper_ginvt(CPUMIPSState *env, target_ulong arg= , uint32_t type) } } =20 -/* Specials */ -target_ulong helper_di(CPUMIPSState *env) -{ - target_ulong t0 =3D env->CP0_Status; - - env->CP0_Status =3D t0 & ~(1 << CP0St_IE); - return t0; -} - -target_ulong helper_ei(CPUMIPSState *env) -{ - target_ulong t0 =3D env->CP0_Status; - - env->CP0_Status =3D t0 | (1 << CP0St_IE); - return t0; -} - -static void debug_pre_eret(CPUMIPSState *env) -{ - if (qemu_loglevel_mask(CPU_LOG_EXEC)) { - qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, - env->active_tc.PC, env->CP0_EPC); - if (env->CP0_Status & (1 << CP0St_ERL)) { - qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC); - } - if (env->hflags & MIPS_HFLAG_DM) { - qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC); - } - qemu_log("\n"); - } -} - -static void debug_post_eret(CPUMIPSState *env) -{ - if (qemu_loglevel_mask(CPU_LOG_EXEC)) { - qemu_log(" =3D> PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, - env->active_tc.PC, env->CP0_EPC); - if (env->CP0_Status & (1 << CP0St_ERL)) { - qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC); - } - if (env->hflags & MIPS_HFLAG_DM) { - qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC); - } - switch (cpu_mmu_index(env, false)) { - case 3: - qemu_log(", ERL\n"); - break; - case MIPS_HFLAG_UM: - qemu_log(", UM\n"); - break; - case MIPS_HFLAG_SM: - qemu_log(", SM\n"); - break; - case MIPS_HFLAG_KM: - qemu_log("\n"); - break; - default: - cpu_abort(env_cpu(env), "Invalid MMU mode!\n"); - break; - } - } -} - -static inline void exception_return(CPUMIPSState *env) -{ - debug_pre_eret(env); - if (env->CP0_Status & (1 << CP0St_ERL)) { - mips_cpu_set_error_pc(env, env->CP0_ErrorEPC); - env->CP0_Status &=3D ~(1 << CP0St_ERL); - } else { - mips_cpu_set_error_pc(env, env->CP0_EPC); - env->CP0_Status &=3D ~(1 << CP0St_EXL); - } - compute_hflags(env); - debug_post_eret(env); -} - -void helper_eret(CPUMIPSState *env) -{ - exception_return(env); - env->CP0_LLAddr =3D 1; - env->lladdr =3D 1; -} - -void helper_eretnc(CPUMIPSState *env) -{ - exception_return(env); -} - -void helper_deret(CPUMIPSState *env) -{ - debug_pre_eret(env); - - env->hflags &=3D ~MIPS_HFLAG_DM; - compute_hflags(env); - - mips_cpu_set_error_pc(env, env->CP0_DEPC); - - debug_post_eret(env); -} #endif /* !CONFIG_USER_ONLY */ =20 static inline void check_hwrena(CPUMIPSState *env, int reg, uintptr_t pc) diff --git a/target/mips/tcg/sysemu/special_helper.c b/target/mips/tcg/syse= mu/special_helper.c new file mode 100644 index 00000000000..927a640d076 --- /dev/null +++ b/target/mips/tcg/sysemu/special_helper.c @@ -0,0 +1,140 @@ +/* + * QEMU MIPS emulation: Special opcode helpers + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + * + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "exec/helper-proto.h" +#include "exec/exec-all.h" +#include "internal.h" + +/* Specials */ +target_ulong helper_di(CPUMIPSState *env) +{ + target_ulong t0 =3D env->CP0_Status; + + env->CP0_Status =3D t0 & ~(1 << CP0St_IE); + return t0; +} + +target_ulong helper_ei(CPUMIPSState *env) +{ + target_ulong t0 =3D env->CP0_Status; + + env->CP0_Status =3D t0 | (1 << CP0St_IE); + return t0; +} + +static void debug_pre_eret(CPUMIPSState *env) +{ + if (qemu_loglevel_mask(CPU_LOG_EXEC)) { + qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, + env->active_tc.PC, env->CP0_EPC); + if (env->CP0_Status & (1 << CP0St_ERL)) { + qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC); + } + if (env->hflags & MIPS_HFLAG_DM) { + qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC); + } + qemu_log("\n"); + } +} + +static void debug_post_eret(CPUMIPSState *env) +{ + if (qemu_loglevel_mask(CPU_LOG_EXEC)) { + qemu_log(" =3D> PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, + env->active_tc.PC, env->CP0_EPC); + if (env->CP0_Status & (1 << CP0St_ERL)) { + qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC); + } + if (env->hflags & MIPS_HFLAG_DM) { + qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC); + } + switch (cpu_mmu_index(env, false)) { + case 3: + qemu_log(", ERL\n"); + break; + case MIPS_HFLAG_UM: + qemu_log(", UM\n"); + break; + case MIPS_HFLAG_SM: + qemu_log(", SM\n"); + break; + case MIPS_HFLAG_KM: + qemu_log("\n"); + break; + default: + cpu_abort(env_cpu(env), "Invalid MMU mode!\n"); + break; + } + } +} + +bool mips_io_recompile_replay_branch(CPUState *cs, const TranslationBlock = *tb) +{ + MIPSCPU *cpu =3D MIPS_CPU(cs); + CPUMIPSState *env =3D &cpu->env; + + if ((env->hflags & MIPS_HFLAG_BMASK) !=3D 0 + && env->active_tc.PC !=3D tb->pc) { + env->active_tc.PC -=3D (env->hflags & MIPS_HFLAG_B16 ? 2 : 4); + env->hflags &=3D ~MIPS_HFLAG_BMASK; + return true; + } + return false; +} + +static inline void exception_return(CPUMIPSState *env) +{ + debug_pre_eret(env); + if (env->CP0_Status & (1 << CP0St_ERL)) { + mips_cpu_set_error_pc(env, env->CP0_ErrorEPC); + env->CP0_Status &=3D ~(1 << CP0St_ERL); + } else { + mips_cpu_set_error_pc(env, env->CP0_EPC); + env->CP0_Status &=3D ~(1 << CP0St_EXL); + } + compute_hflags(env); + debug_post_eret(env); +} + +void helper_eret(CPUMIPSState *env) +{ + exception_return(env); + env->CP0_LLAddr =3D 1; + env->lladdr =3D 1; +} + +void helper_eretnc(CPUMIPSState *env) +{ + exception_return(env); +} + +void helper_deret(CPUMIPSState *env) +{ + debug_pre_eret(env); + + env->hflags &=3D ~MIPS_HFLAG_DM; + compute_hflags(env); + + mips_cpu_set_error_pc(env, env->CP0_DEPC); + + debug_post_eret(env); +} diff --git a/target/mips/tcg/sysemu/meson.build b/target/mips/tcg/sysemu/me= son.build index 73ab9571ba6..4da2c577b20 100644 --- a/target/mips/tcg/sysemu/meson.build +++ b/target/mips/tcg/sysemu/meson.build @@ -1,5 +1,6 @@ mips_softmmu_ss.add(files( 'cp0_helper.c', 'mips-semi.c', + 'special_helper.c', 'tlb_helper.c', )) --=20 2.26.3 From nobody Sat May 4 03:43:33 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.50 as permitted sender) client-ip=209.85.128.50; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f50.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.50 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1618860023; cv=none; d=zohomail.com; s=zohoarc; b=TcQeDSbyqsSj8mAI0XfHwEo2KcJrtwD2QTzai92/nArKLzlkDs7zAnvOVaIKDBLeitIjpY8/3Q0bbV0B9JKnPAHk5GalqsE6cwbrS/O+ONlUDsfrh4y5U0JTcbAelViZNJkSexfRXZrvnG8glX8A9CcRauHr/2iwk6d5CjJigFc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618860023; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=3GmUY9SDQTId+vurOXkEi+R4oq195U5WUEXrZHtw3SI=; b=bxfAL9QtwoqJYsC73kppJFcKcip7IdsG+L/j52WQDfY/rEzFT0M2KYOE7LLUppJJe83riX1oRt/MtpJiOedAFeOrHnFJMm/PLh7RG7CRp6QZCg20crzv5RV7QcZVScedSjq8CqtKfsQI7s69GKWrunOI1HtHonIaURAypk+LiXY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.50 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) by mx.zohomail.com with SMTPS id 1618860023831840.7820872774884; Mon, 19 Apr 2021 12:20:23 -0700 (PDT) Received: by mail-wm1-f50.google.com with SMTP id k128so18820721wmk.4 for ; Mon, 19 Apr 2021 12:20:23 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.redhat.com (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id n2sm576962wmb.32.2021.04.19.12.20.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Apr 2021 12:20:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3GmUY9SDQTId+vurOXkEi+R4oq195U5WUEXrZHtw3SI=; b=X4tfoBv7tBb5Qf0R7bkPWA26R6oo/e1rjXD7Xil9C7UGGl2D/slWuphIsOa7Ofxzcf BYAZzxCpWM5auKPNuvVQcyh92nwoY+9t9MUKmaGFn1mSm/XgGaBQ3dQ3/0oaK0LBtBhY f4ev6hHJ7Pb5GZhqBlkxeagOw1DtA0Yd2HEZbknriFJ2WcWJKxIi/BzmayUZnhNYPE9O mANc6JPAiei+m0Q9gSG/vhks8Z/BuCzE0m3roOj71wQE9Bf2nG90hWwzCwWzigVH9Fii eywuTPp37YIwQkdlMTmlQmLpfeMumEQI++Gt2M495EnmosZMrSdc4GS6QdBBlT4BK61F UlRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=3GmUY9SDQTId+vurOXkEi+R4oq195U5WUEXrZHtw3SI=; b=tPxtsLs+d1lHMytVtk3OSReXoD1rlFJlSgzxhIVBHjCDyV0bCws/CcYyzD/ooJ7VxH 5g+Nthe1Ot28/p/k0PeT0KoBZ0xUn2bDKlzCHG1u8bzhu3JQrRzupQNihKW2/W0tRoxz RSL54CC3JQXI2bROKisubv862CmcziuuLa/hQYS8WES2y81lyFjWxRqGHmOKm/K28hbo hga5nFXMhHbGNQMQrmhrElLz4I7beoE+gfCp5rEL8Row3EIIXhcEXNxV/aHkr55YSoQP lnmMlgD0vepujHLFNjWHe/iidl7cy1cGkKyrGFN6sLWVk5b/hicjyshF2kYlHLYVT3Nz 5siw== X-Gm-Message-State: AOAM531TYGlaZwj/pKTgNDdJDX7YQ+KMZxeKwigCdRxiSJ+4ZoXvFdqA A53zOStLwitOWVgqDBII5jI= X-Google-Smtp-Source: ABdhPJy4e9wEv3y24dXmX9Uq0hlcu8QOTBRWF1j3uCnN2j72Cb4F+M2GPANZglnWUPk9XCpAgx/ZCA== X-Received: by 2002:a1c:1b41:: with SMTP id b62mr580604wmb.170.1618860021999; Mon, 19 Apr 2021 12:20:21 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Aurelien Jarno , Huacai Chen Subject: [PATCH v3 24/30] target/mips: Move helper_cache() to tcg/sysemu/special_helper.c Date: Mon, 19 Apr 2021 21:18:17 +0200 Message-Id: <20210419191823.1555482-25-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210419191823.1555482-1-f4bug@amsat.org> References: <20210419191823.1555482-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Move helper_cache() to tcg/sysemu/special_helper.c. The CACHE opcode is privileged and is not accessible in user emulation. However we get a link failure when restricting the symbol to sysemu. For now, add a stub helper to satisfy linking, which abort if ever called. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- v2: Use STUB_HELPER() :) (rth) --- target/mips/helper.h | 2 -- target/mips/tcg/sysemu_helper.h.inc | 1 + target/mips/op_helper.c | 35 ------------------------- target/mips/tcg/sysemu/special_helper.c | 33 +++++++++++++++++++++++ target/mips/translate.c | 13 +++++++++ 5 files changed, 47 insertions(+), 37 deletions(-) diff --git a/target/mips/helper.h b/target/mips/helper.h index 4ee7916d8b2..d49620f9282 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -614,8 +614,6 @@ DEF_HELPER_FLAGS_3(dmthlip, 0, void, tl, tl, env) DEF_HELPER_FLAGS_3(wrdsp, 0, void, tl, tl, env) DEF_HELPER_FLAGS_2(rddsp, 0, tl, tl, env) =20 -DEF_HELPER_3(cache, void, env, tl, i32) - #ifndef CONFIG_USER_ONLY #include "tcg/sysemu_helper.h.inc" #endif /* !CONFIG_USER_ONLY */ diff --git a/target/mips/tcg/sysemu_helper.h.inc b/target/mips/tcg/sysemu_h= elper.h.inc index 38e55cbf118..1ccbf687237 100644 --- a/target/mips/tcg/sysemu_helper.h.inc +++ b/target/mips/tcg/sysemu_helper.h.inc @@ -173,3 +173,4 @@ DEF_HELPER_1(ei, tl, env) DEF_HELPER_1(eret, void, env) DEF_HELPER_1(eretnc, void, env) DEF_HELPER_1(deret, void, env) +DEF_HELPER_3(cache, void, env, tl, i32) diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index a077535194b..a7fe1de8c42 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -788,38 +788,3 @@ void mips_cpu_do_transaction_failed(CPUState *cs, hwad= dr physaddr, } } #endif /* !CONFIG_USER_ONLY */ - -void helper_cache(CPUMIPSState *env, target_ulong addr, uint32_t op) -{ -#ifndef CONFIG_USER_ONLY - static const char *const type_name[] =3D { - "Primary Instruction", - "Primary Data or Unified Primary", - "Tertiary", - "Secondary" - }; - uint32_t cache_type =3D extract32(op, 0, 2); - uint32_t cache_operation =3D extract32(op, 2, 3); - target_ulong index =3D addr & 0x1fffffff; - - switch (cache_operation) { - case 0b010: /* Index Store Tag */ - memory_region_dispatch_write(env->itc_tag, index, env->CP0_TagLo, - MO_64, MEMTXATTRS_UNSPECIFIED); - break; - case 0b001: /* Index Load Tag */ - memory_region_dispatch_read(env->itc_tag, index, &env->CP0_TagLo, - MO_64, MEMTXATTRS_UNSPECIFIED); - break; - case 0b000: /* Index Invalidate */ - case 0b100: /* Hit Invalidate */ - case 0b110: /* Hit Writeback */ - /* no-op */ - break; - default: - qemu_log_mask(LOG_UNIMP, "cache operation:%u (type: %s cache)\n", - cache_operation, type_name[cache_type]); - break; - } -#endif -} diff --git a/target/mips/tcg/sysemu/special_helper.c b/target/mips/tcg/syse= mu/special_helper.c index 927a640d076..ffd5d0086b6 100644 --- a/target/mips/tcg/sysemu/special_helper.c +++ b/target/mips/tcg/sysemu/special_helper.c @@ -138,3 +138,36 @@ void helper_deret(CPUMIPSState *env) =20 debug_post_eret(env); } + +void helper_cache(CPUMIPSState *env, target_ulong addr, uint32_t op) +{ + static const char *const type_name[] =3D { + "Primary Instruction", + "Primary Data or Unified Primary", + "Tertiary", + "Secondary" + }; + uint32_t cache_type =3D extract32(op, 0, 2); + uint32_t cache_operation =3D extract32(op, 2, 3); + target_ulong index =3D addr & 0x1fffffff; + + switch (cache_operation) { + case 0b010: /* Index Store Tag */ + memory_region_dispatch_write(env->itc_tag, index, env->CP0_TagLo, + MO_64, MEMTXATTRS_UNSPECIFIED); + break; + case 0b001: /* Index Load Tag */ + memory_region_dispatch_read(env->itc_tag, index, &env->CP0_TagLo, + MO_64, MEMTXATTRS_UNSPECIFIED); + break; + case 0b000: /* Index Invalidate */ + case 0b100: /* Hit Invalidate */ + case 0b110: /* Hit Writeback */ + /* no-op */ + break; + default: + qemu_log_mask(LOG_UNIMP, "cache operation:%u (type: %s cache)\n", + cache_operation, type_name[cache_type]); + break; + } +} diff --git a/target/mips/translate.c b/target/mips/translate.c index 8702f9220be..c2e60178d05 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -39,6 +39,19 @@ #include "fpu_helper.h" #include "translate.h" =20 +/* + * Many sysemu-only helpers are not reachable for user-only. + * Define stub generators here, so that we need not either sprinkle + * ifdefs through the translator, nor provide the helper function. + */ +#define STUB_HELPER(NAME, ...) \ + static inline void gen_helper_##NAME(__VA_ARGS__) \ + { qemu_build_not_reached(); } + +#ifdef CONFIG_USER_ONLY +STUB_HELPER(cache, TCGv_env env, TCGv val, TCGv_i32 reg) +#endif + enum { /* indirect opcode tables */ OPC_SPECIAL =3D (0x00 << 26), --=20 2.26.3 From nobody Sat May 4 03:43:33 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.51 as permitted sender) client-ip=209.85.221.51; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f51.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.51 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1618860029; cv=none; d=zohomail.com; s=zohoarc; b=fPXtYarIX5FzJesMNdB+n0K7w3aQL5HFJc6rfdMF6NBar/ub0J2AHc2tirLjlUKqGg+71CzY/K5lUzmWFpYICLBrL3N2EQH3isac6FJgTzZckHqgVsnctW6NNw79ZLhx81HSsG0UdwL23NiXdOOFoUhKxfLH1n3lp3h9htPM9SQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618860029; 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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id n3sm564941wmi.7.2021.04.19.12.20.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Apr 2021 12:20:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5xg1EuIwXiv8xTBX+TlAfNeq2+Lu7dNue+L1lhPZSRU=; b=h665FDXnP3ZnUolV7h2T4ySzh8i1XYWbPMnoXesfjNJkE46QbtnUmyVoFDFDAEWf8x 0uRLlHRVMn4gfdVcHEsORKaudDqVkQaXnS9hNuYdJN8QMiN8Tx2paR5WzlFFRO61Hu/r ZH/1czq4TxryrR/ldmeadMl0bQcyBxAUFXGV3g2vUszcaamcfBzqaPflDZyclq2FDaZe 92fBYD4T2fifw/DoyQbpVVyXFELRXmR9GJLwp98d2JkJIQqn4WPeM0P8/ft02eyBTrw4 nxcovKMKiyRVRa/8cvfYqd8WxcmYhsq+SNOmbAnLhQHgTc5phTbJA51kk18UryDjkSBm D0lw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=5xg1EuIwXiv8xTBX+TlAfNeq2+Lu7dNue+L1lhPZSRU=; b=mrZHj2mPvbccHE9xXNPMLpbClvz/12NgAJKY2nv8TZehRCIQKszj357gs7oSqczUOt lyQcAqfCgxZy9ARPzJFIn0gRFXfpLXxd8L4eeVBj5OwSbmRErDRJYPiESyMONV+SRecG e14qngztRKa5j/dGnAVSmutQgq/Qq+bDSsqWf3iy5RdADSq/IWTGgkBUrpUZG6mPHXKy 99Z8cyFVJJL3svZo7o5nlf/C0BlEFXTZTz6XjAPH8M15Il0z6nlLd0VF/WNmOX21HtCo mVpqXwxSEFXxi7xVe0hY7RW3sayoGhSJiVNrPRGjbtOMkhkMyuXADoXIHHsPpFFOCG/V rK+g== X-Gm-Message-State: AOAM532i03FcRgMHFU4Mi0Iz3378MreoOa04vdHd0akn/nBkdLubNjiS 4AJWxLTM03VEubKKWcVV2KI= X-Google-Smtp-Source: ABdhPJyy0y5Jlp9z1uZDzMp+fPBan9hcP4LTAW4K7q8mmrQCSyaKV6NDLAUAReZLKg4y95KBZdrt9Q== X-Received: by 2002:adf:f04d:: with SMTP id t13mr16184355wro.52.1618860026967; Mon, 19 Apr 2021 12:20:26 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Aurelien Jarno , Huacai Chen Subject: [PATCH v3 25/30] target/mips: Move TLB management helpers to tcg/sysemu/tlb_helper.c Date: Mon, 19 Apr 2021 21:18:18 +0200 Message-Id: <20210419191823.1555482-26-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210419191823.1555482-1-f4bug@amsat.org> References: <20210419191823.1555482-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Move TLB management helpers to tcg/sysemu/tlb_helper.c. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/helper.h | 10 - target/mips/internal.h | 7 - target/mips/tcg/sysemu_helper.h.inc | 9 + target/mips/op_helper.c | 333 ---------------------------- target/mips/tcg/sysemu/tlb_helper.c | 331 +++++++++++++++++++++++++++ 5 files changed, 340 insertions(+), 350 deletions(-) diff --git a/target/mips/helper.h b/target/mips/helper.h index d49620f9282..ba301ae160d 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -202,16 +202,6 @@ FOP_PROTO(sune) FOP_PROTO(sne) #undef FOP_PROTO =20 -/* Special functions */ -#ifndef CONFIG_USER_ONLY -DEF_HELPER_1(tlbwi, void, env) -DEF_HELPER_1(tlbwr, void, env) -DEF_HELPER_1(tlbp, void, env) -DEF_HELPER_1(tlbr, void, env) -DEF_HELPER_1(tlbinv, void, env) -DEF_HELPER_1(tlbinvf, void, env) -DEF_HELPER_3(ginvt, void, env, tl, i32) -#endif /* !CONFIG_USER_ONLY */ DEF_HELPER_1(rdhwr_cpunum, tl, env) DEF_HELPER_1(rdhwr_synci_step, tl, env) DEF_HELPER_1(rdhwr_cc, tl, env) diff --git a/target/mips/internal.h b/target/mips/internal.h index a59e2f9007d..88020e22365 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -152,13 +152,6 @@ struct CPUMIPSTLBContext { } mmu; }; =20 -void r4k_helper_tlbwi(CPUMIPSState *env); -void r4k_helper_tlbwr(CPUMIPSState *env); -void r4k_helper_tlbp(CPUMIPSState *env); -void r4k_helper_tlbr(CPUMIPSState *env); -void r4k_helper_tlbinv(CPUMIPSState *env); -void r4k_helper_tlbinvf(CPUMIPSState *env); - void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, diff --git a/target/mips/tcg/sysemu_helper.h.inc b/target/mips/tcg/sysemu_h= elper.h.inc index 1ccbf687237..4353a966f97 100644 --- a/target/mips/tcg/sysemu_helper.h.inc +++ b/target/mips/tcg/sysemu_helper.h.inc @@ -167,6 +167,15 @@ DEF_HELPER_1(evpe, tl, env) DEF_HELPER_1(dvp, tl, env) DEF_HELPER_1(evp, tl, env) =20 +/* TLB */ +DEF_HELPER_1(tlbwi, void, env) +DEF_HELPER_1(tlbwr, void, env) +DEF_HELPER_1(tlbp, void, env) +DEF_HELPER_1(tlbr, void, env) +DEF_HELPER_1(tlbinv, void, env) +DEF_HELPER_1(tlbinvf, void, env) +DEF_HELPER_3(ginvt, void, env, tl, i32) + /* Special */ DEF_HELPER_1(di, tl, env) DEF_HELPER_1(ei, tl, env) diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index a7fe1de8c42..cb2a7e96fc3 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -324,339 +324,6 @@ target_ulong helper_yield(CPUMIPSState *env, target_u= long arg) return env->CP0_YQMask; } =20 -#ifndef CONFIG_USER_ONLY -/* TLB management */ -static void r4k_mips_tlb_flush_extra(CPUMIPSState *env, int first) -{ - /* Discard entries from env->tlb[first] onwards. */ - while (env->tlb->tlb_in_use > first) { - r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0); - } -} - -static inline uint64_t get_tlb_pfn_from_entrylo(uint64_t entrylo) -{ -#if defined(TARGET_MIPS64) - return extract64(entrylo, 6, 54); -#else - return extract64(entrylo, 6, 24) | /* PFN */ - (extract64(entrylo, 32, 32) << 24); /* PFNX */ -#endif -} - -static void r4k_fill_tlb(CPUMIPSState *env, int idx) -{ - r4k_tlb_t *tlb; - uint64_t mask =3D env->CP0_PageMask >> (TARGET_PAGE_BITS + 1); - - /* XXX: detect conflicting TLBs and raise a MCHECK exception when need= ed */ - tlb =3D &env->tlb->mmu.r4k.tlb[idx]; - if (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) { - tlb->EHINV =3D 1; - return; - } - tlb->EHINV =3D 0; - tlb->VPN =3D env->CP0_EntryHi & (TARGET_PAGE_MASK << 1); -#if defined(TARGET_MIPS64) - tlb->VPN &=3D env->SEGMask; -#endif - tlb->ASID =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; - tlb->MMID =3D env->CP0_MemoryMapID; - tlb->PageMask =3D env->CP0_PageMask; - tlb->G =3D env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1; - tlb->V0 =3D (env->CP0_EntryLo0 & 2) !=3D 0; - tlb->D0 =3D (env->CP0_EntryLo0 & 4) !=3D 0; - tlb->C0 =3D (env->CP0_EntryLo0 >> 3) & 0x7; - tlb->XI0 =3D (env->CP0_EntryLo0 >> CP0EnLo_XI) & 1; - tlb->RI0 =3D (env->CP0_EntryLo0 >> CP0EnLo_RI) & 1; - tlb->PFN[0] =3D (get_tlb_pfn_from_entrylo(env->CP0_EntryLo0) & ~mask) = << 12; - tlb->V1 =3D (env->CP0_EntryLo1 & 2) !=3D 0; - tlb->D1 =3D (env->CP0_EntryLo1 & 4) !=3D 0; - tlb->C1 =3D (env->CP0_EntryLo1 >> 3) & 0x7; - tlb->XI1 =3D (env->CP0_EntryLo1 >> CP0EnLo_XI) & 1; - tlb->RI1 =3D (env->CP0_EntryLo1 >> CP0EnLo_RI) & 1; - tlb->PFN[1] =3D (get_tlb_pfn_from_entrylo(env->CP0_EntryLo1) & ~mask) = << 12; -} - -void r4k_helper_tlbinv(CPUMIPSState *env) -{ - bool mi =3D !!((env->CP0_Config5 >> CP0C5_MI) & 1); - uint16_t ASID =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; - uint32_t MMID =3D env->CP0_MemoryMapID; - uint32_t tlb_mmid; - r4k_tlb_t *tlb; - int idx; - - MMID =3D mi ? MMID : (uint32_t) ASID; - for (idx =3D 0; idx < env->tlb->nb_tlb; idx++) { - tlb =3D &env->tlb->mmu.r4k.tlb[idx]; - tlb_mmid =3D mi ? tlb->MMID : (uint32_t) tlb->ASID; - if (!tlb->G && tlb_mmid =3D=3D MMID) { - tlb->EHINV =3D 1; - } - } - cpu_mips_tlb_flush(env); -} - -void r4k_helper_tlbinvf(CPUMIPSState *env) -{ - int idx; - - for (idx =3D 0; idx < env->tlb->nb_tlb; idx++) { - env->tlb->mmu.r4k.tlb[idx].EHINV =3D 1; - } - cpu_mips_tlb_flush(env); -} - -void r4k_helper_tlbwi(CPUMIPSState *env) -{ - bool mi =3D !!((env->CP0_Config5 >> CP0C5_MI) & 1); - target_ulong VPN; - uint16_t ASID =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; - uint32_t MMID =3D env->CP0_MemoryMapID; - uint32_t tlb_mmid; - bool EHINV, G, V0, D0, V1, D1, XI0, XI1, RI0, RI1; - r4k_tlb_t *tlb; - int idx; - - MMID =3D mi ? MMID : (uint32_t) ASID; - - idx =3D (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb; - tlb =3D &env->tlb->mmu.r4k.tlb[idx]; - VPN =3D env->CP0_EntryHi & (TARGET_PAGE_MASK << 1); -#if defined(TARGET_MIPS64) - VPN &=3D env->SEGMask; -#endif - EHINV =3D (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) !=3D 0; - G =3D env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1; - V0 =3D (env->CP0_EntryLo0 & 2) !=3D 0; - D0 =3D (env->CP0_EntryLo0 & 4) !=3D 0; - XI0 =3D (env->CP0_EntryLo0 >> CP0EnLo_XI) &1; - RI0 =3D (env->CP0_EntryLo0 >> CP0EnLo_RI) &1; - V1 =3D (env->CP0_EntryLo1 & 2) !=3D 0; - D1 =3D (env->CP0_EntryLo1 & 4) !=3D 0; - XI1 =3D (env->CP0_EntryLo1 >> CP0EnLo_XI) &1; - RI1 =3D (env->CP0_EntryLo1 >> CP0EnLo_RI) &1; - - tlb_mmid =3D mi ? tlb->MMID : (uint32_t) tlb->ASID; - /* - * Discard cached TLB entries, unless tlbwi is just upgrading access - * permissions on the current entry. - */ - if (tlb->VPN !=3D VPN || tlb_mmid !=3D MMID || tlb->G !=3D G || - (!tlb->EHINV && EHINV) || - (tlb->V0 && !V0) || (tlb->D0 && !D0) || - (!tlb->XI0 && XI0) || (!tlb->RI0 && RI0) || - (tlb->V1 && !V1) || (tlb->D1 && !D1) || - (!tlb->XI1 && XI1) || (!tlb->RI1 && RI1)) { - r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb); - } - - r4k_invalidate_tlb(env, idx, 0); - r4k_fill_tlb(env, idx); -} - -void r4k_helper_tlbwr(CPUMIPSState *env) -{ - int r =3D cpu_mips_get_random(env); - - r4k_invalidate_tlb(env, r, 1); - r4k_fill_tlb(env, r); -} - -void r4k_helper_tlbp(CPUMIPSState *env) -{ - bool mi =3D !!((env->CP0_Config5 >> CP0C5_MI) & 1); - r4k_tlb_t *tlb; - target_ulong mask; - target_ulong tag; - target_ulong VPN; - uint16_t ASID =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; - uint32_t MMID =3D env->CP0_MemoryMapID; - uint32_t tlb_mmid; - int i; - - MMID =3D mi ? MMID : (uint32_t) ASID; - for (i =3D 0; i < env->tlb->nb_tlb; i++) { - tlb =3D &env->tlb->mmu.r4k.tlb[i]; - /* 1k pages are not supported. */ - mask =3D tlb->PageMask | ~(TARGET_PAGE_MASK << 1); - tag =3D env->CP0_EntryHi & ~mask; - VPN =3D tlb->VPN & ~mask; -#if defined(TARGET_MIPS64) - tag &=3D env->SEGMask; -#endif - tlb_mmid =3D mi ? tlb->MMID : (uint32_t) tlb->ASID; - /* Check ASID/MMID, virtual page number & size */ - if ((tlb->G =3D=3D 1 || tlb_mmid =3D=3D MMID) && VPN =3D=3D tag &&= !tlb->EHINV) { - /* TLB match */ - env->CP0_Index =3D i; - break; - } - } - if (i =3D=3D env->tlb->nb_tlb) { - /* No match. Discard any shadow entries, if any of them match. */ - for (i =3D env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) { - tlb =3D &env->tlb->mmu.r4k.tlb[i]; - /* 1k pages are not supported. */ - mask =3D tlb->PageMask | ~(TARGET_PAGE_MASK << 1); - tag =3D env->CP0_EntryHi & ~mask; - VPN =3D tlb->VPN & ~mask; -#if defined(TARGET_MIPS64) - tag &=3D env->SEGMask; -#endif - tlb_mmid =3D mi ? tlb->MMID : (uint32_t) tlb->ASID; - /* Check ASID/MMID, virtual page number & size */ - if ((tlb->G =3D=3D 1 || tlb_mmid =3D=3D MMID) && VPN =3D=3D ta= g) { - r4k_mips_tlb_flush_extra(env, i); - break; - } - } - - env->CP0_Index |=3D 0x80000000; - } -} - -static inline uint64_t get_entrylo_pfn_from_tlb(uint64_t tlb_pfn) -{ -#if defined(TARGET_MIPS64) - return tlb_pfn << 6; -#else - return (extract64(tlb_pfn, 0, 24) << 6) | /* PFN */ - (extract64(tlb_pfn, 24, 32) << 32); /* PFNX */ -#endif -} - -void r4k_helper_tlbr(CPUMIPSState *env) -{ - bool mi =3D !!((env->CP0_Config5 >> CP0C5_MI) & 1); - uint16_t ASID =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; - uint32_t MMID =3D env->CP0_MemoryMapID; - uint32_t tlb_mmid; - r4k_tlb_t *tlb; - int idx; - - MMID =3D mi ? MMID : (uint32_t) ASID; - idx =3D (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb; - tlb =3D &env->tlb->mmu.r4k.tlb[idx]; - - tlb_mmid =3D mi ? tlb->MMID : (uint32_t) tlb->ASID; - /* If this will change the current ASID/MMID, flush qemu's TLB. */ - if (MMID !=3D tlb_mmid) { - cpu_mips_tlb_flush(env); - } - - r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb); - - if (tlb->EHINV) { - env->CP0_EntryHi =3D 1 << CP0EnHi_EHINV; - env->CP0_PageMask =3D 0; - env->CP0_EntryLo0 =3D 0; - env->CP0_EntryLo1 =3D 0; - } else { - env->CP0_EntryHi =3D mi ? tlb->VPN : tlb->VPN | tlb->ASID; - env->CP0_MemoryMapID =3D tlb->MMID; - env->CP0_PageMask =3D tlb->PageMask; - env->CP0_EntryLo0 =3D tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) | - ((uint64_t)tlb->RI0 << CP0EnLo_RI) | - ((uint64_t)tlb->XI0 << CP0EnLo_XI) | (tlb->C0 << 3= ) | - get_entrylo_pfn_from_tlb(tlb->PFN[0] >> 12); - env->CP0_EntryLo1 =3D tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) | - ((uint64_t)tlb->RI1 << CP0EnLo_RI) | - ((uint64_t)tlb->XI1 << CP0EnLo_XI) | (tlb->C1 << 3= ) | - get_entrylo_pfn_from_tlb(tlb->PFN[1] >> 12); - } -} - -void helper_tlbwi(CPUMIPSState *env) -{ - env->tlb->helper_tlbwi(env); -} - -void helper_tlbwr(CPUMIPSState *env) -{ - env->tlb->helper_tlbwr(env); -} - -void helper_tlbp(CPUMIPSState *env) -{ - env->tlb->helper_tlbp(env); -} - -void helper_tlbr(CPUMIPSState *env) -{ - env->tlb->helper_tlbr(env); -} - -void helper_tlbinv(CPUMIPSState *env) -{ - env->tlb->helper_tlbinv(env); -} - -void helper_tlbinvf(CPUMIPSState *env) -{ - env->tlb->helper_tlbinvf(env); -} - -static void global_invalidate_tlb(CPUMIPSState *env, - uint32_t invMsgVPN2, - uint8_t invMsgR, - uint32_t invMsgMMid, - bool invAll, - bool invVAMMid, - bool invMMid, - bool invVA) -{ - - int idx; - r4k_tlb_t *tlb; - bool VAMatch; - bool MMidMatch; - - for (idx =3D 0; idx < env->tlb->nb_tlb; idx++) { - tlb =3D &env->tlb->mmu.r4k.tlb[idx]; - VAMatch =3D - (((tlb->VPN & ~tlb->PageMask) =3D=3D (invMsgVPN2 & ~tlb->PageM= ask)) -#ifdef TARGET_MIPS64 - && - (extract64(env->CP0_EntryHi, 62, 2) =3D=3D invMsgR) -#endif - ); - MMidMatch =3D tlb->MMID =3D=3D invMsgMMid; - if ((invAll && (idx > env->CP0_Wired)) || - (VAMatch && invVAMMid && (tlb->G || MMidMatch)) || - (VAMatch && invVA) || - (MMidMatch && !(tlb->G) && invMMid)) { - tlb->EHINV =3D 1; - } - } - cpu_mips_tlb_flush(env); -} - -void helper_ginvt(CPUMIPSState *env, target_ulong arg, uint32_t type) -{ - bool invAll =3D type =3D=3D 0; - bool invVA =3D type =3D=3D 1; - bool invMMid =3D type =3D=3D 2; - bool invVAMMid =3D type =3D=3D 3; - uint32_t invMsgVPN2 =3D arg & (TARGET_PAGE_MASK << 1); - uint8_t invMsgR =3D 0; - uint32_t invMsgMMid =3D env->CP0_MemoryMapID; - CPUState *other_cs =3D first_cpu; - -#ifdef TARGET_MIPS64 - invMsgR =3D extract64(arg, 62, 2); -#endif - - CPU_FOREACH(other_cs) { - MIPSCPU *other_cpu =3D MIPS_CPU(other_cs); - global_invalidate_tlb(&other_cpu->env, invMsgVPN2, invMsgR, invMsg= MMid, - invAll, invVAMMid, invMMid, invVA); - } -} - -#endif /* !CONFIG_USER_ONLY */ - static inline void check_hwrena(CPUMIPSState *env, int reg, uintptr_t pc) { if ((env->hflags & MIPS_HFLAG_CP0) || (env->CP0_HWREna & (1 << reg))) { diff --git a/target/mips/tcg/sysemu/tlb_helper.c b/target/mips/tcg/sysemu/t= lb_helper.c index a45146a2b21..259f780d19f 100644 --- a/target/mips/tcg/sysemu/tlb_helper.c +++ b/target/mips/tcg/sysemu/tlb_helper.c @@ -24,6 +24,337 @@ #include "exec/cpu_ldst.h" #include "exec/log.h" #include "hw/mips/cpudevs.h" +#include "exec/helper-proto.h" + +/* TLB management */ +static void r4k_mips_tlb_flush_extra(CPUMIPSState *env, int first) +{ + /* Discard entries from env->tlb[first] onwards. */ + while (env->tlb->tlb_in_use > first) { + r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0); + } +} + +static inline uint64_t get_tlb_pfn_from_entrylo(uint64_t entrylo) +{ +#if defined(TARGET_MIPS64) + return extract64(entrylo, 6, 54); +#else + return extract64(entrylo, 6, 24) | /* PFN */ + (extract64(entrylo, 32, 32) << 24); /* PFNX */ +#endif +} + +static void r4k_fill_tlb(CPUMIPSState *env, int idx) +{ + r4k_tlb_t *tlb; + uint64_t mask =3D env->CP0_PageMask >> (TARGET_PAGE_BITS + 1); + + /* XXX: detect conflicting TLBs and raise a MCHECK exception when need= ed */ + tlb =3D &env->tlb->mmu.r4k.tlb[idx]; + if (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) { + tlb->EHINV =3D 1; + return; + } + tlb->EHINV =3D 0; + tlb->VPN =3D env->CP0_EntryHi & (TARGET_PAGE_MASK << 1); +#if defined(TARGET_MIPS64) + tlb->VPN &=3D env->SEGMask; +#endif + tlb->ASID =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; + tlb->MMID =3D env->CP0_MemoryMapID; + tlb->PageMask =3D env->CP0_PageMask; + tlb->G =3D env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1; + tlb->V0 =3D (env->CP0_EntryLo0 & 2) !=3D 0; + tlb->D0 =3D (env->CP0_EntryLo0 & 4) !=3D 0; + tlb->C0 =3D (env->CP0_EntryLo0 >> 3) & 0x7; + tlb->XI0 =3D (env->CP0_EntryLo0 >> CP0EnLo_XI) & 1; + tlb->RI0 =3D (env->CP0_EntryLo0 >> CP0EnLo_RI) & 1; + tlb->PFN[0] =3D (get_tlb_pfn_from_entrylo(env->CP0_EntryLo0) & ~mask) = << 12; + tlb->V1 =3D (env->CP0_EntryLo1 & 2) !=3D 0; + tlb->D1 =3D (env->CP0_EntryLo1 & 4) !=3D 0; + tlb->C1 =3D (env->CP0_EntryLo1 >> 3) & 0x7; + tlb->XI1 =3D (env->CP0_EntryLo1 >> CP0EnLo_XI) & 1; + tlb->RI1 =3D (env->CP0_EntryLo1 >> CP0EnLo_RI) & 1; + tlb->PFN[1] =3D (get_tlb_pfn_from_entrylo(env->CP0_EntryLo1) & ~mask) = << 12; +} + +static void r4k_helper_tlbinv(CPUMIPSState *env) +{ + bool mi =3D !!((env->CP0_Config5 >> CP0C5_MI) & 1); + uint16_t ASID =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; + uint32_t MMID =3D env->CP0_MemoryMapID; + uint32_t tlb_mmid; + r4k_tlb_t *tlb; + int idx; + + MMID =3D mi ? MMID : (uint32_t) ASID; + for (idx =3D 0; idx < env->tlb->nb_tlb; idx++) { + tlb =3D &env->tlb->mmu.r4k.tlb[idx]; + tlb_mmid =3D mi ? tlb->MMID : (uint32_t) tlb->ASID; + if (!tlb->G && tlb_mmid =3D=3D MMID) { + tlb->EHINV =3D 1; + } + } + cpu_mips_tlb_flush(env); +} + +static void r4k_helper_tlbinvf(CPUMIPSState *env) +{ + int idx; + + for (idx =3D 0; idx < env->tlb->nb_tlb; idx++) { + env->tlb->mmu.r4k.tlb[idx].EHINV =3D 1; + } + cpu_mips_tlb_flush(env); +} + +static void r4k_helper_tlbwi(CPUMIPSState *env) +{ + bool mi =3D !!((env->CP0_Config5 >> CP0C5_MI) & 1); + target_ulong VPN; + uint16_t ASID =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; + uint32_t MMID =3D env->CP0_MemoryMapID; + uint32_t tlb_mmid; + bool EHINV, G, V0, D0, V1, D1, XI0, XI1, RI0, RI1; + r4k_tlb_t *tlb; + int idx; + + MMID =3D mi ? MMID : (uint32_t) ASID; + + idx =3D (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb; + tlb =3D &env->tlb->mmu.r4k.tlb[idx]; + VPN =3D env->CP0_EntryHi & (TARGET_PAGE_MASK << 1); +#if defined(TARGET_MIPS64) + VPN &=3D env->SEGMask; +#endif + EHINV =3D (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) !=3D 0; + G =3D env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1; + V0 =3D (env->CP0_EntryLo0 & 2) !=3D 0; + D0 =3D (env->CP0_EntryLo0 & 4) !=3D 0; + XI0 =3D (env->CP0_EntryLo0 >> CP0EnLo_XI) &1; + RI0 =3D (env->CP0_EntryLo0 >> CP0EnLo_RI) &1; + V1 =3D (env->CP0_EntryLo1 & 2) !=3D 0; + D1 =3D (env->CP0_EntryLo1 & 4) !=3D 0; + XI1 =3D (env->CP0_EntryLo1 >> CP0EnLo_XI) &1; + RI1 =3D (env->CP0_EntryLo1 >> CP0EnLo_RI) &1; + + tlb_mmid =3D mi ? tlb->MMID : (uint32_t) tlb->ASID; + /* + * Discard cached TLB entries, unless tlbwi is just upgrading access + * permissions on the current entry. + */ + if (tlb->VPN !=3D VPN || tlb_mmid !=3D MMID || tlb->G !=3D G || + (!tlb->EHINV && EHINV) || + (tlb->V0 && !V0) || (tlb->D0 && !D0) || + (!tlb->XI0 && XI0) || (!tlb->RI0 && RI0) || + (tlb->V1 && !V1) || (tlb->D1 && !D1) || + (!tlb->XI1 && XI1) || (!tlb->RI1 && RI1)) { + r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb); + } + + r4k_invalidate_tlb(env, idx, 0); + r4k_fill_tlb(env, idx); +} + +static void r4k_helper_tlbwr(CPUMIPSState *env) +{ + int r =3D cpu_mips_get_random(env); + + r4k_invalidate_tlb(env, r, 1); + r4k_fill_tlb(env, r); +} + +static void r4k_helper_tlbp(CPUMIPSState *env) +{ + bool mi =3D !!((env->CP0_Config5 >> CP0C5_MI) & 1); + r4k_tlb_t *tlb; + target_ulong mask; + target_ulong tag; + target_ulong VPN; + uint16_t ASID =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; + uint32_t MMID =3D env->CP0_MemoryMapID; + uint32_t tlb_mmid; + int i; + + MMID =3D mi ? MMID : (uint32_t) ASID; + for (i =3D 0; i < env->tlb->nb_tlb; i++) { + tlb =3D &env->tlb->mmu.r4k.tlb[i]; + /* 1k pages are not supported. */ + mask =3D tlb->PageMask | ~(TARGET_PAGE_MASK << 1); + tag =3D env->CP0_EntryHi & ~mask; + VPN =3D tlb->VPN & ~mask; +#if defined(TARGET_MIPS64) + tag &=3D env->SEGMask; +#endif + tlb_mmid =3D mi ? tlb->MMID : (uint32_t) tlb->ASID; + /* Check ASID/MMID, virtual page number & size */ + if ((tlb->G =3D=3D 1 || tlb_mmid =3D=3D MMID) && VPN =3D=3D tag &&= !tlb->EHINV) { + /* TLB match */ + env->CP0_Index =3D i; + break; + } + } + if (i =3D=3D env->tlb->nb_tlb) { + /* No match. Discard any shadow entries, if any of them match. */ + for (i =3D env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) { + tlb =3D &env->tlb->mmu.r4k.tlb[i]; + /* 1k pages are not supported. */ + mask =3D tlb->PageMask | ~(TARGET_PAGE_MASK << 1); + tag =3D env->CP0_EntryHi & ~mask; + VPN =3D tlb->VPN & ~mask; +#if defined(TARGET_MIPS64) + tag &=3D env->SEGMask; +#endif + tlb_mmid =3D mi ? tlb->MMID : (uint32_t) tlb->ASID; + /* Check ASID/MMID, virtual page number & size */ + if ((tlb->G =3D=3D 1 || tlb_mmid =3D=3D MMID) && VPN =3D=3D ta= g) { + r4k_mips_tlb_flush_extra(env, i); + break; + } + } + + env->CP0_Index |=3D 0x80000000; + } +} + +static inline uint64_t get_entrylo_pfn_from_tlb(uint64_t tlb_pfn) +{ +#if defined(TARGET_MIPS64) + return tlb_pfn << 6; +#else + return (extract64(tlb_pfn, 0, 24) << 6) | /* PFN */ + (extract64(tlb_pfn, 24, 32) << 32); /* PFNX */ +#endif +} + +static void r4k_helper_tlbr(CPUMIPSState *env) +{ + bool mi =3D !!((env->CP0_Config5 >> CP0C5_MI) & 1); + uint16_t ASID =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; + uint32_t MMID =3D env->CP0_MemoryMapID; + uint32_t tlb_mmid; + r4k_tlb_t *tlb; + int idx; + + MMID =3D mi ? MMID : (uint32_t) ASID; + idx =3D (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb; + tlb =3D &env->tlb->mmu.r4k.tlb[idx]; + + tlb_mmid =3D mi ? tlb->MMID : (uint32_t) tlb->ASID; + /* If this will change the current ASID/MMID, flush qemu's TLB. */ + if (MMID !=3D tlb_mmid) { + cpu_mips_tlb_flush(env); + } + + r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb); + + if (tlb->EHINV) { + env->CP0_EntryHi =3D 1 << CP0EnHi_EHINV; + env->CP0_PageMask =3D 0; + env->CP0_EntryLo0 =3D 0; + env->CP0_EntryLo1 =3D 0; + } else { + env->CP0_EntryHi =3D mi ? tlb->VPN : tlb->VPN | tlb->ASID; + env->CP0_MemoryMapID =3D tlb->MMID; + env->CP0_PageMask =3D tlb->PageMask; + env->CP0_EntryLo0 =3D tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) | + ((uint64_t)tlb->RI0 << CP0EnLo_RI) | + ((uint64_t)tlb->XI0 << CP0EnLo_XI) | (tlb->C0 << 3= ) | + get_entrylo_pfn_from_tlb(tlb->PFN[0] >> 12); + env->CP0_EntryLo1 =3D tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) | + ((uint64_t)tlb->RI1 << CP0EnLo_RI) | + ((uint64_t)tlb->XI1 << CP0EnLo_XI) | (tlb->C1 << 3= ) | + get_entrylo_pfn_from_tlb(tlb->PFN[1] >> 12); + } +} + +void helper_tlbwi(CPUMIPSState *env) +{ + env->tlb->helper_tlbwi(env); +} + +void helper_tlbwr(CPUMIPSState *env) +{ + env->tlb->helper_tlbwr(env); +} + +void helper_tlbp(CPUMIPSState *env) +{ + env->tlb->helper_tlbp(env); +} + +void helper_tlbr(CPUMIPSState *env) +{ + env->tlb->helper_tlbr(env); +} + +void helper_tlbinv(CPUMIPSState *env) +{ + env->tlb->helper_tlbinv(env); +} + +void helper_tlbinvf(CPUMIPSState *env) +{ + env->tlb->helper_tlbinvf(env); +} + +static void global_invalidate_tlb(CPUMIPSState *env, + uint32_t invMsgVPN2, + uint8_t invMsgR, + uint32_t invMsgMMid, + bool invAll, + bool invVAMMid, + bool invMMid, + bool invVA) +{ + + int idx; + r4k_tlb_t *tlb; + bool VAMatch; + bool MMidMatch; + + for (idx =3D 0; idx < env->tlb->nb_tlb; idx++) { + tlb =3D &env->tlb->mmu.r4k.tlb[idx]; + VAMatch =3D + (((tlb->VPN & ~tlb->PageMask) =3D=3D (invMsgVPN2 & ~tlb->PageM= ask)) +#ifdef TARGET_MIPS64 + && + (extract64(env->CP0_EntryHi, 62, 2) =3D=3D invMsgR) +#endif + ); + MMidMatch =3D tlb->MMID =3D=3D invMsgMMid; + if ((invAll && (idx > env->CP0_Wired)) || + (VAMatch && invVAMMid && (tlb->G || MMidMatch)) || + (VAMatch && invVA) || + (MMidMatch && !(tlb->G) && invMMid)) { + tlb->EHINV =3D 1; + } + } + cpu_mips_tlb_flush(env); +} + +void helper_ginvt(CPUMIPSState *env, target_ulong arg, uint32_t type) +{ + bool invAll =3D type =3D=3D 0; + bool invVA =3D type =3D=3D 1; + bool invMMid =3D type =3D=3D 2; + bool invVAMMid =3D type =3D=3D 3; + uint32_t invMsgVPN2 =3D arg & (TARGET_PAGE_MASK << 1); + uint8_t invMsgR =3D 0; + uint32_t invMsgMMid =3D env->CP0_MemoryMapID; + CPUState *other_cs =3D first_cpu; + +#ifdef TARGET_MIPS64 + invMsgR =3D extract64(arg, 62, 2); +#endif + + CPU_FOREACH(other_cs) { + MIPSCPU *other_cpu =3D MIPS_CPU(other_cs); + global_invalidate_tlb(&other_cpu->env, invMsgVPN2, invMsgR, invMsg= MMid, + invAll, invVAMMid, invMMid, invVA); + } +} =20 /* no MMU emulation */ static int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *pr= ot, --=20 2.26.3 From nobody Sat May 4 03:43:33 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.43 as permitted sender) client-ip=209.85.128.43; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f43.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.43 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1618860033; cv=none; d=zohomail.com; s=zohoarc; b=cq8q8RQ6O0RuHSRMRuU4zmvVmx9Uwq9AalPk9x0LpsQ4w85EWWyDRGGgoeTQalPGnWnmE2vOPCabPQERHlpwZNSMRj8imbwXp0yZDX5mT2iyC886QxDDPc6EAf541KMjOdQ+iB7qt2HeDHvYQUHJKr0oJYBsjQtMwqGjD0aSPwo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618860033; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=TQ8eLpDmyl2mh0xK7two8msco7MU2oruEcY2UGGQbg8=; b=DoHMtRrXPDPcz2knqzb/l223+hnuQU4I7N8vl76rLkwaFihRqT4sliV5OYnTqAonM0aOdK62Rcu+hadlJecckPooizlI99eWI94+r/kx81aXIHQIRhhMspXwnyVeOVhLSz6zQFDb0oxsWkg3LsyqpZ7qV8pUnfP5RjwxTrj6gxI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.43 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) by mx.zohomail.com with SMTPS id 1618860033671401.159371904355; Mon, 19 Apr 2021 12:20:33 -0700 (PDT) Received: by mail-wm1-f43.google.com with SMTP id f195-20020a1c1fcc0000b029012eb88126d7so8695500wmf.3 for ; Mon, 19 Apr 2021 12:20:33 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.redhat.com (39.red-81-40-121.staticip.rima-tde.net. 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/internal.h | 13 --- target/mips/tcg/tcg-internal.h | 14 +++ target/mips/cpu.c | 113 ---------------------- target/mips/exception.c | 167 +++++++++++++++++++++++++++++++++ target/mips/op_helper.c | 37 -------- target/mips/meson.build | 1 + 6 files changed, 182 insertions(+), 163 deletions(-) create mode 100644 target/mips/exception.c diff --git a/target/mips/internal.h b/target/mips/internal.h index 88020e22365..8158078b08b 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -80,7 +80,6 @@ extern const char fregnames[32][4]; extern const struct mips_def_t mips_defs[]; extern const int mips_defs_number; =20 -bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, @@ -411,16 +410,4 @@ void sync_c0_status(CPUMIPSState *env, CPUMIPSState *c= pu, int tc); void cpu_mips_store_status(CPUMIPSState *env, target_ulong val); void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val); =20 -const char *mips_exception_name(int32_t exception); - -void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t exce= ption, - int error_code, uintptr_t pc); - -static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env, - uint32_t exception, - uintptr_t pc) -{ - do_raise_exception_err(env, exception, 0, pc); -} - #endif diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h index 73667b35778..75aa3ef98ed 100644 --- a/target/mips/tcg/tcg-internal.h +++ b/target/mips/tcg/tcg-internal.h @@ -14,11 +14,25 @@ #include "hw/core/cpu.h" #include "cpu.h" =20 +void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb= ); void mips_cpu_do_interrupt(CPUState *cpu); +bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); =20 +const char *mips_exception_name(int32_t exception); + +void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t exce= ption, + int error_code, uintptr_t pc); + +static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env, + uint32_t exception, + uintptr_t pc) +{ + do_raise_exception_err(env, exception, 0, pc); +} + #if !defined(CONFIG_USER_ONLY) =20 void mmu_init(CPUMIPSState *env, const mips_def_t *def); diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 949b8ef94ea..61d0dd69751 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -218,112 +218,12 @@ static void mips_cpu_dump_state(CPUState *cs, FILE *= f, int flags) } } =20 -static const char * const excp_names[EXCP_LAST + 1] =3D { - [EXCP_RESET] =3D "reset", - [EXCP_SRESET] =3D "soft reset", - [EXCP_DSS] =3D "debug single step", - [EXCP_DINT] =3D "debug interrupt", - [EXCP_NMI] =3D "non-maskable interrupt", - [EXCP_MCHECK] =3D "machine check", - [EXCP_EXT_INTERRUPT] =3D "interrupt", - [EXCP_DFWATCH] =3D "deferred watchpoint", - [EXCP_DIB] =3D "debug instruction breakpoint", - [EXCP_IWATCH] =3D "instruction fetch watchpoint", - [EXCP_AdEL] =3D "address error load", - [EXCP_AdES] =3D "address error store", - [EXCP_TLBF] =3D "TLB refill", - [EXCP_IBE] =3D "instruction bus error", - [EXCP_DBp] =3D "debug breakpoint", - [EXCP_SYSCALL] =3D "syscall", - [EXCP_BREAK] =3D "break", - [EXCP_CpU] =3D "coprocessor unusable", - [EXCP_RI] =3D "reserved instruction", - [EXCP_OVERFLOW] =3D "arithmetic overflow", - [EXCP_TRAP] =3D "trap", - [EXCP_FPE] =3D "floating point", - [EXCP_DDBS] =3D "debug data break store", - [EXCP_DWATCH] =3D "data watchpoint", - [EXCP_LTLBL] =3D "TLB modify", - [EXCP_TLBL] =3D "TLB load", - [EXCP_TLBS] =3D "TLB store", - [EXCP_DBE] =3D "data bus error", - [EXCP_DDBL] =3D "debug data break load", - [EXCP_THREAD] =3D "thread", - [EXCP_MDMX] =3D "MDMX", - [EXCP_C2E] =3D "precise coprocessor 2", - [EXCP_CACHE] =3D "cache error", - [EXCP_TLBXI] =3D "TLB execute-inhibit", - [EXCP_TLBRI] =3D "TLB read-inhibit", - [EXCP_MSADIS] =3D "MSA disabled", - [EXCP_MSAFPE] =3D "MSA floating point", -}; - -const char *mips_exception_name(int32_t exception) -{ - if (exception < 0 || exception > EXCP_LAST) { - return "unknown"; - } - return excp_names[exception]; -} - void cpu_set_exception_base(int vp_index, target_ulong address) { MIPSCPU *vp =3D MIPS_CPU(qemu_get_cpu(vp_index)); vp->env.exception_base =3D address; } =20 -target_ulong exception_resume_pc(CPUMIPSState *env) -{ - target_ulong bad_pc; - target_ulong isa_mode; - - isa_mode =3D !!(env->hflags & MIPS_HFLAG_M16); - bad_pc =3D env->active_tc.PC | isa_mode; - if (env->hflags & MIPS_HFLAG_BMASK) { - /* - * If the exception was raised from a delay slot, come back to - * the jump. - */ - bad_pc -=3D (env->hflags & MIPS_HFLAG_B16 ? 2 : 4); - } - - return bad_pc; -} - -bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request) -{ - if (interrupt_request & CPU_INTERRUPT_HARD) { - MIPSCPU *cpu =3D MIPS_CPU(cs); - CPUMIPSState *env =3D &cpu->env; - - if (cpu_mips_hw_interrupts_enabled(env) && - cpu_mips_hw_interrupts_pending(env)) { - /* Raise it */ - cs->exception_index =3D EXCP_EXT_INTERRUPT; - env->error_code =3D 0; - mips_cpu_do_interrupt(cs); - return true; - } - } - return false; -} - -void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, - uint32_t exception, - int error_code, - uintptr_t pc) -{ - CPUState *cs =3D env_cpu(env); - - qemu_log_mask(CPU_LOG_INT, "%s: %d (%s) %d\n", - __func__, exception, mips_exception_name(exception), - error_code); - cs->exception_index =3D exception; - env->error_code =3D error_code; - - cpu_loop_exit_restore(cs, pc); -} - static void mips_cpu_set_pc(CPUState *cs, vaddr value) { MIPSCPU *cpu =3D MIPS_CPU(cs); @@ -331,19 +231,6 @@ static void mips_cpu_set_pc(CPUState *cs, vaddr value) mips_cpu_set_error_pc(&cpu->env, value); } =20 -#ifdef CONFIG_TCG -static void mips_cpu_synchronize_from_tb(CPUState *cs, - const TranslationBlock *tb) -{ - MIPSCPU *cpu =3D MIPS_CPU(cs); - CPUMIPSState *env =3D &cpu->env; - - env->active_tc.PC =3D tb->pc; - env->hflags &=3D ~MIPS_HFLAG_BMASK; - env->hflags |=3D tb->flags & MIPS_HFLAG_BMASK; -} -#endif /* CONFIG_TCG */ - static bool mips_cpu_has_work(CPUState *cs) { MIPSCPU *cpu =3D MIPS_CPU(cs); diff --git a/target/mips/exception.c b/target/mips/exception.c new file mode 100644 index 00000000000..4fb8b00711d --- /dev/null +++ b/target/mips/exception.c @@ -0,0 +1,167 @@ +/* + * MIPS Exceptions processing helpers for QEMU. + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + * + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "internal.h" +#include "exec/helper-proto.h" +#include "exec/exec-all.h" + +target_ulong exception_resume_pc(CPUMIPSState *env) +{ + target_ulong bad_pc; + target_ulong isa_mode; + + isa_mode =3D !!(env->hflags & MIPS_HFLAG_M16); + bad_pc =3D env->active_tc.PC | isa_mode; + if (env->hflags & MIPS_HFLAG_BMASK) { + /* + * If the exception was raised from a delay slot, come back to + * the jump. + */ + bad_pc -=3D (env->hflags & MIPS_HFLAG_B16 ? 2 : 4); + } + + return bad_pc; +} + +void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception, + int error_code) +{ + do_raise_exception_err(env, exception, error_code, 0); +} + +void helper_raise_exception(CPUMIPSState *env, uint32_t exception) +{ + do_raise_exception(env, exception, GETPC()); +} + +void helper_raise_exception_debug(CPUMIPSState *env) +{ + do_raise_exception(env, EXCP_DEBUG, 0); +} + +static void raise_exception(CPUMIPSState *env, uint32_t exception) +{ + do_raise_exception(env, exception, 0); +} + +void helper_wait(CPUMIPSState *env) +{ + CPUState *cs =3D env_cpu(env); + + cs->halted =3D 1; + cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE); + /* + * Last instruction in the block, PC was updated before + * - no need to recover PC and icount. + */ + raise_exception(env, EXCP_HLT); +} + +void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) +{ + MIPSCPU *cpu =3D MIPS_CPU(cs); + CPUMIPSState *env =3D &cpu->env; + + env->active_tc.PC =3D tb->pc; + env->hflags &=3D ~MIPS_HFLAG_BMASK; + env->hflags |=3D tb->flags & MIPS_HFLAG_BMASK; +} + +bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +{ + if (interrupt_request & CPU_INTERRUPT_HARD) { + MIPSCPU *cpu =3D MIPS_CPU(cs); + CPUMIPSState *env =3D &cpu->env; + + if (cpu_mips_hw_interrupts_enabled(env) && + cpu_mips_hw_interrupts_pending(env)) { + /* Raise it */ + cs->exception_index =3D EXCP_EXT_INTERRUPT; + env->error_code =3D 0; + mips_cpu_do_interrupt(cs); + return true; + } + } + return false; +} + +static const char * const excp_names[EXCP_LAST + 1] =3D { + [EXCP_RESET] =3D "reset", + [EXCP_SRESET] =3D "soft reset", + [EXCP_DSS] =3D "debug single step", + [EXCP_DINT] =3D "debug interrupt", + [EXCP_NMI] =3D "non-maskable interrupt", + [EXCP_MCHECK] =3D "machine check", + [EXCP_EXT_INTERRUPT] =3D "interrupt", + [EXCP_DFWATCH] =3D "deferred watchpoint", + [EXCP_DIB] =3D "debug instruction breakpoint", + [EXCP_IWATCH] =3D "instruction fetch watchpoint", + [EXCP_AdEL] =3D "address error load", + [EXCP_AdES] =3D "address error store", + [EXCP_TLBF] =3D "TLB refill", + [EXCP_IBE] =3D "instruction bus error", + [EXCP_DBp] =3D "debug breakpoint", + [EXCP_SYSCALL] =3D "syscall", + [EXCP_BREAK] =3D "break", + [EXCP_CpU] =3D "coprocessor unusable", + [EXCP_RI] =3D "reserved instruction", + [EXCP_OVERFLOW] =3D "arithmetic overflow", + [EXCP_TRAP] =3D "trap", + [EXCP_FPE] =3D "floating point", + [EXCP_DDBS] =3D "debug data break store", + [EXCP_DWATCH] =3D "data watchpoint", + [EXCP_LTLBL] =3D "TLB modify", + [EXCP_TLBL] =3D "TLB load", + [EXCP_TLBS] =3D "TLB store", + [EXCP_DBE] =3D "data bus error", + [EXCP_DDBL] =3D "debug data break load", + [EXCP_THREAD] =3D "thread", + [EXCP_MDMX] =3D "MDMX", + [EXCP_C2E] =3D "precise coprocessor 2", + [EXCP_CACHE] =3D "cache error", + [EXCP_TLBXI] =3D "TLB execute-inhibit", + [EXCP_TLBRI] =3D "TLB read-inhibit", + [EXCP_MSADIS] =3D "MSA disabled", + [EXCP_MSAFPE] =3D "MSA floating point", +}; + +const char *mips_exception_name(int32_t exception) +{ + if (exception < 0 || exception > EXCP_LAST) { + return "unknown"; + } + return excp_names[exception]; +} + +void do_raise_exception_err(CPUMIPSState *env, uint32_t exception, + int error_code, uintptr_t pc) +{ + CPUState *cs =3D env_cpu(env); + + qemu_log_mask(CPU_LOG_INT, "%s: %d (%s) %d\n", + __func__, exception, mips_exception_name(exception), + error_code); + cs->exception_index =3D exception; + env->error_code =3D error_code; + + cpu_loop_exit_restore(cs, pc); +} diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index cb2a7e96fc3..ce1549c9854 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -26,30 +26,6 @@ #include "exec/memop.h" #include "fpu_helper.h" =20 -/*************************************************************************= ****/ -/* Exceptions processing helpers */ - -void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception, - int error_code) -{ - do_raise_exception_err(env, exception, error_code, 0); -} - -void helper_raise_exception(CPUMIPSState *env, uint32_t exception) -{ - do_raise_exception(env, exception, GETPC()); -} - -void helper_raise_exception_debug(CPUMIPSState *env) -{ - do_raise_exception(env, EXCP_DEBUG, 0); -} - -static void raise_exception(CPUMIPSState *env, uint32_t exception) -{ - do_raise_exception(env, exception, 0); -} - /* 64 bits arithmetic for 32 bits hosts */ static inline uint64_t get_HILO(CPUMIPSState *env) { @@ -399,19 +375,6 @@ void helper_pmon(CPUMIPSState *env, int function) } } =20 -void helper_wait(CPUMIPSState *env) -{ - CPUState *cs =3D env_cpu(env); - - cs->halted =3D 1; - cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE); - /* - * Last instruction in the block, PC was updated before - * - no need to recover PC and icount. - */ - raise_exception(env, EXCP_HLT); -} - #if !defined(CONFIG_USER_ONLY) =20 void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr, diff --git a/target/mips/meson.build b/target/mips/meson.build index ff5eb210dfd..e08077bfc18 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -24,6 +24,7 @@ mips_tcg_ss.add(gen) mips_tcg_ss.add(files( 'dsp_helper.c', + 'exception.c', 'fpu_helper.c', 'ldst_helper.c', 'lmmi_helper.c', --=20 2.26.3 From nobody Sat May 4 03:43:33 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.42 as permitted sender) client-ip=209.85.221.42; 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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id f6sm523422wmf.28.2021.04.19.12.20.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Apr 2021 12:20:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=b7B2r8MngKg5MsGtmNycyg6sG5mdHfGJzIr6HUIH8KE=; b=k/Hr0Qf3V+J+mvACJxPwJnJiVjtFmWj3kDjyyYttyjuaza1xGVXxIp8dE2MkhE9l+j qz32iuqtUWxeYW5VTsM1NKhretliGHG91Jk/fE5eedkuF8wggnyn40tWNNRthCQCGNy5 RtEBerGtTg8M1aTSC+qfY4T+f9Beu1NxzZsWFKFhTqoRcrxnmbBe4EV4qN51loe8wpZX /bTqMPYk2h941n2wmEyX6qSnAGODCsszCOwHGbXI9/QrwgY+WQODL4+jmq9p1aeBF6ap 5rzGiYixUSxKpo0cUfC62HyvNp2pzQA+OyPuuBaqT0TgK1X+PLj0VFdWxW6qk9fFGh8z Bcqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=b7B2r8MngKg5MsGtmNycyg6sG5mdHfGJzIr6HUIH8KE=; b=DpzxVBplEh8KxKNnid0fEXTlzUqfkBydS7X2nFk3sntr3q/D8sCcrJW2vemCRcGQtP 2QtcdZxL7R/QU+fMJGkNEw89xybC86jw2JWoDNeML22YEz1aNanO8TNoVqeZR1VI9Mjs lRl566jNZzspfxlJw1SzBG3qEa7MF3AGx5NOloNeJzA9O9ow1GFAdZRKzNeotp00lrAy LtloEoR+4d9h7ZDuX47B+zxme+FNZM1MSz6paRUcWbF15lolLZUM8yY8OSdkg7rv9QTm XgK4wmBXfDFyJlwkKSgLdGqK98sI7l9G1jWDZo43aS/Xkg9SNR/HPQQ2MFs9QTAVYuzF 4DaA== X-Gm-Message-State: AOAM5317HB2lkwG33Mga5CU7HzJwT20GDBNna1iZOqE3z6bvLxqoK0J0 00YoYsJp98/6utCOYakxSEI= X-Google-Smtp-Source: ABdhPJwZGGvoXcKc4NXvP9vGRdddzRENY/XhMf6i4YkqTrAHuTyVuAKtVDSacWGc+NPZq5q87tv3YA== X-Received: by 2002:adf:cd8c:: with SMTP id q12mr16177765wrj.328.1618860036618; Mon, 19 Apr 2021 12:20:36 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Aurelien Jarno , Huacai Chen Subject: [PATCH v3 27/30] target/mips: Move CP0 helpers to sysemu/cp0.c Date: Mon, 19 Apr 2021 21:18:20 +0200 Message-Id: <20210419191823.1555482-28-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210419191823.1555482-1-f4bug@amsat.org> References: <20210419191823.1555482-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Opcodes accessing Coprocessor 0 are privileged. Move the CP0 helpers to sysemu/ and simplify the #ifdef'ry. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/internal.h | 9 +-- target/mips/cpu.c | 103 --------------------------- target/mips/sysemu/cp0.c | 123 +++++++++++++++++++++++++++++++++ target/mips/sysemu/meson.build | 1 + 4 files changed, 129 insertions(+), 107 deletions(-) create mode 100644 target/mips/sysemu/cp0.c diff --git a/target/mips/internal.h b/target/mips/internal.h index 8158078b08b..588e89cfcda 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -156,6 +156,11 @@ void mips_cpu_do_transaction_failed(CPUState *cs, hwad= dr physaddr, MMUAccessType access_type, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retadd= r); + +void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc); +void cpu_mips_store_status(CPUMIPSState *env, target_ulong val); +void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val); + extern const VMStateDescription vmstate_mips_cpu; =20 #endif /* !CONFIG_USER_ONLY */ @@ -406,8 +411,4 @@ static inline void compute_hflags(CPUMIPSState *env) } } =20 -void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc); -void cpu_mips_store_status(CPUMIPSState *env, target_ulong val); -void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val); - #endif diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 61d0dd69751..9dec912af98 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -42,109 +42,6 @@ const char regnames[32][4] =3D { "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", }; =20 -#if !defined(CONFIG_USER_ONLY) - -/* Called for updates to CP0_Status. */ -void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc) -{ - int32_t tcstatus, *tcst; - uint32_t v =3D cpu->CP0_Status; - uint32_t cu, mx, asid, ksu; - uint32_t mask =3D ((1 << CP0TCSt_TCU3) - | (1 << CP0TCSt_TCU2) - | (1 << CP0TCSt_TCU1) - | (1 << CP0TCSt_TCU0) - | (1 << CP0TCSt_TMX) - | (3 << CP0TCSt_TKSU) - | (0xff << CP0TCSt_TASID)); - - cu =3D (v >> CP0St_CU0) & 0xf; - mx =3D (v >> CP0St_MX) & 0x1; - ksu =3D (v >> CP0St_KSU) & 0x3; - asid =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; - - tcstatus =3D cu << CP0TCSt_TCU0; - tcstatus |=3D mx << CP0TCSt_TMX; - tcstatus |=3D ksu << CP0TCSt_TKSU; - tcstatus |=3D asid; - - if (tc =3D=3D cpu->current_tc) { - tcst =3D &cpu->active_tc.CP0_TCStatus; - } else { - tcst =3D &cpu->tcs[tc].CP0_TCStatus; - } - - *tcst &=3D ~mask; - *tcst |=3D tcstatus; - compute_hflags(cpu); -} - -void cpu_mips_store_status(CPUMIPSState *env, target_ulong val) -{ - uint32_t mask =3D env->CP0_Status_rw_bitmask; - target_ulong old =3D env->CP0_Status; - - if (env->insn_flags & ISA_MIPS_R6) { - bool has_supervisor =3D extract32(mask, CP0St_KSU, 2) =3D=3D 0x3; -#if defined(TARGET_MIPS64) - uint32_t ksux =3D (1 << CP0St_KX) & val; - ksux |=3D (ksux >> 1) & val; /* KX =3D 0 forces SX to be 0 */ - ksux |=3D (ksux >> 1) & val; /* SX =3D 0 forces UX to be 0 */ - val =3D (val & ~(7 << CP0St_UX)) | ksux; -#endif - if (has_supervisor && extract32(val, CP0St_KSU, 2) =3D=3D 0x3) { - mask &=3D ~(3 << CP0St_KSU); - } - mask &=3D ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val); - } - - env->CP0_Status =3D (old & ~mask) | (val & mask); -#if defined(TARGET_MIPS64) - if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) { - /* Access to at least one of the 64-bit segments has been disabled= */ - tlb_flush(env_cpu(env)); - } -#endif - if (ase_mt_available(env)) { - sync_c0_status(env, env, env->current_tc); - } else { - compute_hflags(env); - } -} - -void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val) -{ - uint32_t mask =3D 0x00C00300; - uint32_t old =3D env->CP0_Cause; - int i; - - if (env->insn_flags & ISA_MIPS_R2) { - mask |=3D 1 << CP0Ca_DC; - } - if (env->insn_flags & ISA_MIPS_R6) { - mask &=3D ~((1 << CP0Ca_WP) & val); - } - - env->CP0_Cause =3D (env->CP0_Cause & ~mask) | (val & mask); - - if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) { - if (env->CP0_Cause & (1 << CP0Ca_DC)) { - cpu_mips_stop_count(env); - } else { - cpu_mips_start_count(env); - } - } - - /* Set/reset software interrupts */ - for (i =3D 0 ; i < 2 ; i++) { - if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) { - cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i= ))); - } - } -} - -#endif /* !CONFIG_USER_ONLY */ - static void fpu_dump_fpr(fpr_t *fpr, FILE *f, bool is_fpu64) { if (is_fpu64) { diff --git a/target/mips/sysemu/cp0.c b/target/mips/sysemu/cp0.c new file mode 100644 index 00000000000..bae37f515bf --- /dev/null +++ b/target/mips/sysemu/cp0.c @@ -0,0 +1,123 @@ +/* + * QEMU MIPS CPU + * + * Copyright (c) 2012 SUSE LINUX Products GmbH + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see + * + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "internal.h" +#include "exec/exec-all.h" + +/* Called for updates to CP0_Status. */ +void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc) +{ + int32_t tcstatus, *tcst; + uint32_t v =3D cpu->CP0_Status; + uint32_t cu, mx, asid, ksu; + uint32_t mask =3D ((1 << CP0TCSt_TCU3) + | (1 << CP0TCSt_TCU2) + | (1 << CP0TCSt_TCU1) + | (1 << CP0TCSt_TCU0) + | (1 << CP0TCSt_TMX) + | (3 << CP0TCSt_TKSU) + | (0xff << CP0TCSt_TASID)); + + cu =3D (v >> CP0St_CU0) & 0xf; + mx =3D (v >> CP0St_MX) & 0x1; + ksu =3D (v >> CP0St_KSU) & 0x3; + asid =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; + + tcstatus =3D cu << CP0TCSt_TCU0; + tcstatus |=3D mx << CP0TCSt_TMX; + tcstatus |=3D ksu << CP0TCSt_TKSU; + tcstatus |=3D asid; + + if (tc =3D=3D cpu->current_tc) { + tcst =3D &cpu->active_tc.CP0_TCStatus; + } else { + tcst =3D &cpu->tcs[tc].CP0_TCStatus; + } + + *tcst &=3D ~mask; + *tcst |=3D tcstatus; + compute_hflags(cpu); +} + +void cpu_mips_store_status(CPUMIPSState *env, target_ulong val) +{ + uint32_t mask =3D env->CP0_Status_rw_bitmask; + target_ulong old =3D env->CP0_Status; + + if (env->insn_flags & ISA_MIPS_R6) { + bool has_supervisor =3D extract32(mask, CP0St_KSU, 2) =3D=3D 0x3; +#if defined(TARGET_MIPS64) + uint32_t ksux =3D (1 << CP0St_KX) & val; + ksux |=3D (ksux >> 1) & val; /* KX =3D 0 forces SX to be 0 */ + ksux |=3D (ksux >> 1) & val; /* SX =3D 0 forces UX to be 0 */ + val =3D (val & ~(7 << CP0St_UX)) | ksux; +#endif + if (has_supervisor && extract32(val, CP0St_KSU, 2) =3D=3D 0x3) { + mask &=3D ~(3 << CP0St_KSU); + } + mask &=3D ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val); + } + + env->CP0_Status =3D (old & ~mask) | (val & mask); +#if defined(TARGET_MIPS64) + if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) { + /* Access to at least one of the 64-bit segments has been disabled= */ + tlb_flush(env_cpu(env)); + } +#endif + if (ase_mt_available(env)) { + sync_c0_status(env, env, env->current_tc); + } else { + compute_hflags(env); + } +} + +void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val) +{ + uint32_t mask =3D 0x00C00300; + uint32_t old =3D env->CP0_Cause; + int i; + + if (env->insn_flags & ISA_MIPS_R2) { + mask |=3D 1 << CP0Ca_DC; + } + if (env->insn_flags & ISA_MIPS_R6) { + mask &=3D ~((1 << CP0Ca_WP) & val); + } + + env->CP0_Cause =3D (env->CP0_Cause & ~mask) | (val & mask); + + if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) { + if (env->CP0_Cause & (1 << CP0Ca_DC)) { + cpu_mips_stop_count(env); + } else { + cpu_mips_start_count(env); + } + } + + /* Set/reset software interrupts */ + for (i =3D 0 ; i < 2 ; i++) { + if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) { + cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i= ))); + } + } +} diff --git a/target/mips/sysemu/meson.build b/target/mips/sysemu/meson.build index 925ceeaa449..cefc2275828 100644 --- a/target/mips/sysemu/meson.build +++ b/target/mips/sysemu/meson.build @@ -1,5 +1,6 @@ mips_softmmu_ss.add(files( 'addr.c', + 'cp0.c', 'cp0_timer.c', 'machine.c', 'physaddr.c', --=20 2.26.3 From nobody Sat May 4 03:43:33 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.45 as permitted sender) client-ip=209.85.221.45; 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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id a15sm23531144wrr.53.2021.04.19.12.20.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Apr 2021 12:20:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cxGPIh4+cVzd6u/rBtmIlI2KI/hhBd7PuQJ55IrPowQ=; b=tqvYsbMYBX6jV1Ey3nPQY7TvjaehHDGM1LuBahIYADn1+ki5EdZgRxpb3MqjIj9SFC U13JSsMo2TF3tEmLO3S4ArxdGBgZqz0urhWjEwhiddjqep/nJkqG6/DycSGiFilh69Ng L4vkQnR70zg4fIRWUU6PdMtRSi8iZdxSYYzHpUHvhFXiHMTDk0K0+eSPhKnOy5FZ4ndQ L4ZQgybawIvk7Xvfc+s5RIA1//ZeETIGgw8+s8MIVqoIJtv5XkKdHnpz4xy+tjn7Dree YoEZpUwTE10orSGZlLNHhKHG396Oc0cmvL4/nN1sUVOScMTYvOn2FdgstSXvCjd36uqs uhCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=cxGPIh4+cVzd6u/rBtmIlI2KI/hhBd7PuQJ55IrPowQ=; b=lpDq9KgUX9SQCjk2uWSkzaTqEv9FKHpVDMpi8SVOBVxaQ46Te3Ksblf+LJgHtC4bH1 7wF/MaGYjwNXs7W96mGI+RSK777v/WzJTjSMKP5Kac3+YOOW/Ekwq5SIugpLnACXfemJ iYYp3jGX8FtZIlFA/hqW9diiXBVsroClJF7bGdFpjU84sv1UVYmjYWFiyQTpSNDuK1Uc HRhQ7gSPJptNqxzXoXxpkJ4qNJWKZToEP4MELqd72CFf4EQDdQOkwn4P4d51A49nNMru mqq+tuSjKam+HPROYl/TL3uIj8GDVPYsf79yWdOCH1vtOe5U2czXzOFML3mI7PUaIFar Ifgw== X-Gm-Message-State: AOAM532IxyCvkrOQKHRFXrSyGQ3WdxFzLDQnrlzAWyFeZOo673I9zy51 IyTYrhZyEKgrEHm8a+lIFOY= X-Google-Smtp-Source: ABdhPJxayzr6NMz1CdUf7vNlJCAnziLvIP+ZuohCpZ4oiJrWFYIUXFXPm4cX4/9xzIwVo7QXBQAUcQ== X-Received: by 2002:adf:f106:: with SMTP id r6mr15987379wro.214.1618860041468; Mon, 19 Apr 2021 12:20:41 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Aurelien Jarno , Huacai Chen Subject: [PATCH v3 28/30] target/mips: Move TCG source files under tcg/ sub directory Date: Mon, 19 Apr 2021 21:18:21 +0200 Message-Id: <20210419191823.1555482-29-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210419191823.1555482-1-f4bug@amsat.org> References: <20210419191823.1555482-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) To ease maintenance, move all TCG specific files under the tcg/ sub-directory. Adapt the Meson machinery. The following prototypes: - mips_tcg_init() - mips_cpu_do_unaligned_access() - mips_cpu_do_transaction_failed() can now be restricted to the "tcg-internal.h" header. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/helper.h | 2 +- target/mips/internal.h | 11 ------- target/mips/tcg/tcg-internal.h | 11 +++++++ target/mips/{ =3D> tcg}/msa_helper.h.inc | 0 target/mips/{ =3D> tcg}/mips32r6.decode | 0 target/mips/{ =3D> tcg}/mips64r6.decode | 0 target/mips/{ =3D> tcg}/msa32.decode | 0 target/mips/{ =3D> tcg}/msa64.decode | 0 target/mips/{ =3D> tcg}/tx79.decode | 0 target/mips/{ =3D> tcg}/dsp_helper.c | 0 target/mips/{ =3D> tcg}/exception.c | 0 target/mips/{ =3D> tcg}/fpu_helper.c | 0 target/mips/{ =3D> tcg}/ldst_helper.c | 0 target/mips/{ =3D> tcg}/lmmi_helper.c | 0 target/mips/{ =3D> tcg}/msa_helper.c | 0 target/mips/{ =3D> tcg}/msa_translate.c | 0 target/mips/{ =3D> tcg}/mxu_translate.c | 0 target/mips/{ =3D> tcg}/op_helper.c | 0 target/mips/{ =3D> tcg}/rel6_translate.c | 0 target/mips/{ =3D> tcg}/translate.c | 0 target/mips/{ =3D> tcg}/translate_addr_const.c | 0 target/mips/{ =3D> tcg}/tx79_translate.c | 0 target/mips/{ =3D> tcg}/txx9_translate.c | 0 target/mips/meson.build | 31 -------------------- target/mips/tcg/meson.build | 29 ++++++++++++++++++ 25 files changed, 41 insertions(+), 43 deletions(-) rename target/mips/{ =3D> tcg}/msa_helper.h.inc (100%) rename target/mips/{ =3D> tcg}/mips32r6.decode (100%) rename target/mips/{ =3D> tcg}/mips64r6.decode (100%) rename target/mips/{ =3D> tcg}/msa32.decode (100%) rename target/mips/{ =3D> tcg}/msa64.decode (100%) rename target/mips/{ =3D> tcg}/tx79.decode (100%) rename target/mips/{ =3D> tcg}/dsp_helper.c (100%) rename target/mips/{ =3D> tcg}/exception.c (100%) rename target/mips/{ =3D> tcg}/fpu_helper.c (100%) rename target/mips/{ =3D> tcg}/ldst_helper.c (100%) rename target/mips/{ =3D> tcg}/lmmi_helper.c (100%) rename target/mips/{ =3D> tcg}/msa_helper.c (100%) rename target/mips/{ =3D> tcg}/msa_translate.c (100%) rename target/mips/{ =3D> tcg}/mxu_translate.c (100%) rename target/mips/{ =3D> tcg}/op_helper.c (100%) rename target/mips/{ =3D> tcg}/rel6_translate.c (100%) rename target/mips/{ =3D> tcg}/translate.c (100%) rename target/mips/{ =3D> tcg}/translate_addr_const.c (100%) rename target/mips/{ =3D> tcg}/tx79_translate.c (100%) rename target/mips/{ =3D> tcg}/txx9_translate.c (100%) diff --git a/target/mips/helper.h b/target/mips/helper.h index ba301ae160d..a9c6c7d1a31 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -608,4 +608,4 @@ DEF_HELPER_FLAGS_2(rddsp, 0, tl, tl, env) #include "tcg/sysemu_helper.h.inc" #endif /* !CONFIG_USER_ONLY */ =20 -#include "msa_helper.h.inc" +#include "tcg/msa_helper.h.inc" diff --git a/target/mips/internal.h b/target/mips/internal.h index 588e89cfcda..c3c8eb0a177 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -82,9 +82,6 @@ extern const int mips_defs_number; =20 int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); -void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr); =20 #define USEG_LIMIT ((target_ulong)(int32_t)0x7FFFFFFFUL) #define KSEG0_BASE ((target_ulong)(int32_t)0x80000000UL) @@ -151,12 +148,6 @@ struct CPUMIPSTLBContext { } mmu; }; =20 -void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, - vaddr addr, unsigned size, - MMUAccessType access_type, - int mmu_idx, MemTxAttrs attrs, - MemTxResult response, uintptr_t retadd= r); - void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc); void cpu_mips_store_status(CPUMIPSState *env, target_ulong val); void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val); @@ -209,8 +200,6 @@ static inline bool cpu_mips_hw_interrupts_pending(CPUMI= PSState *env) return r; } =20 -void mips_tcg_init(void); - void msa_reset(CPUMIPSState *env); =20 /* cp0_timer.c */ diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h index 75aa3ef98ed..81b14eb219e 100644 --- a/target/mips/tcg/tcg-internal.h +++ b/target/mips/tcg/tcg-internal.h @@ -11,15 +11,21 @@ #define MIPS_TCG_INTERNAL_H =20 #include "tcg/tcg.h" +#include "exec/memattrs.h" #include "hw/core/cpu.h" #include "cpu.h" =20 +void mips_tcg_init(void); + void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb= ); void mips_cpu_do_interrupt(CPUState *cpu); bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); +void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr); =20 const char *mips_exception_name(int32_t exception); =20 @@ -46,6 +52,11 @@ bool mips_io_recompile_replay_branch(CPUState *cs, const= TranslationBlock *tb); =20 hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, MMUAccessType access_type, uintptr_t ret= addr); +void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, + vaddr addr, unsigned size, + MMUAccessType access_type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, uintptr_t retadd= r); void cpu_mips_tlb_flush(CPUMIPSState *env); =20 #endif /* !CONFIG_USER_ONLY */ diff --git a/target/mips/msa_helper.h.inc b/target/mips/tcg/msa_helper.h.inc similarity index 100% rename from target/mips/msa_helper.h.inc rename to target/mips/tcg/msa_helper.h.inc diff --git a/target/mips/mips32r6.decode b/target/mips/tcg/mips32r6.decode similarity index 100% rename from target/mips/mips32r6.decode rename to target/mips/tcg/mips32r6.decode diff --git a/target/mips/mips64r6.decode b/target/mips/tcg/mips64r6.decode similarity index 100% rename from target/mips/mips64r6.decode rename to target/mips/tcg/mips64r6.decode diff --git a/target/mips/msa32.decode b/target/mips/tcg/msa32.decode similarity index 100% rename from target/mips/msa32.decode rename to target/mips/tcg/msa32.decode diff --git a/target/mips/msa64.decode b/target/mips/tcg/msa64.decode similarity index 100% rename from target/mips/msa64.decode rename to target/mips/tcg/msa64.decode diff --git a/target/mips/tx79.decode b/target/mips/tcg/tx79.decode similarity index 100% rename from target/mips/tx79.decode rename to target/mips/tcg/tx79.decode diff --git a/target/mips/dsp_helper.c b/target/mips/tcg/dsp_helper.c similarity index 100% rename from target/mips/dsp_helper.c rename to target/mips/tcg/dsp_helper.c diff --git a/target/mips/exception.c b/target/mips/tcg/exception.c similarity index 100% rename from target/mips/exception.c rename to target/mips/tcg/exception.c diff --git a/target/mips/fpu_helper.c b/target/mips/tcg/fpu_helper.c similarity index 100% rename from target/mips/fpu_helper.c rename to target/mips/tcg/fpu_helper.c diff --git a/target/mips/ldst_helper.c b/target/mips/tcg/ldst_helper.c similarity index 100% rename from target/mips/ldst_helper.c rename to target/mips/tcg/ldst_helper.c diff --git a/target/mips/lmmi_helper.c b/target/mips/tcg/lmmi_helper.c similarity index 100% rename from target/mips/lmmi_helper.c rename to target/mips/tcg/lmmi_helper.c diff --git a/target/mips/msa_helper.c b/target/mips/tcg/msa_helper.c similarity index 100% rename from target/mips/msa_helper.c rename to target/mips/tcg/msa_helper.c diff --git a/target/mips/msa_translate.c b/target/mips/tcg/msa_translate.c similarity index 100% rename from target/mips/msa_translate.c rename to target/mips/tcg/msa_translate.c diff --git a/target/mips/mxu_translate.c b/target/mips/tcg/mxu_translate.c similarity index 100% rename from target/mips/mxu_translate.c rename to target/mips/tcg/mxu_translate.c diff --git a/target/mips/op_helper.c b/target/mips/tcg/op_helper.c similarity index 100% rename from target/mips/op_helper.c rename to target/mips/tcg/op_helper.c diff --git a/target/mips/rel6_translate.c b/target/mips/tcg/rel6_translate.c similarity index 100% rename from target/mips/rel6_translate.c rename to target/mips/tcg/rel6_translate.c diff --git a/target/mips/translate.c b/target/mips/tcg/translate.c similarity index 100% rename from target/mips/translate.c rename to target/mips/tcg/translate.c diff --git a/target/mips/translate_addr_const.c b/target/mips/tcg/translate= _addr_const.c similarity index 100% rename from target/mips/translate_addr_const.c rename to target/mips/tcg/translate_addr_const.c diff --git a/target/mips/tx79_translate.c b/target/mips/tcg/tx79_translate.c similarity index 100% rename from target/mips/tx79_translate.c rename to target/mips/tcg/tx79_translate.c diff --git a/target/mips/txx9_translate.c b/target/mips/tcg/txx9_translate.c similarity index 100% rename from target/mips/txx9_translate.c rename to target/mips/tcg/txx9_translate.c diff --git a/target/mips/meson.build b/target/mips/meson.build index e08077bfc18..2407a05d4c0 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -1,11 +1,3 @@ -gen =3D [ - decodetree.process('mips32r6.decode', extra_args: '--static-decode=3Ddec= ode_mips32r6'), - decodetree.process('mips64r6.decode', extra_args: '--static-decode=3Ddec= ode_mips64r6'), - decodetree.process('msa32.decode', extra_args: '--static-decode=3Ddecode= _msa32'), - decodetree.process('msa64.decode', extra_args: '--static-decode=3Ddecode= _msa64'), - decodetree.process('tx79.decode', extra_args: '--static-decode=3Ddecode_= tx79'), -] - mips_user_ss =3D ss.source_set() mips_softmmu_ss =3D ss.source_set() mips_ss =3D ss.source_set() @@ -20,35 +12,12 @@ subdir('sysemu') endif =20 -mips_tcg_ss =3D ss.source_set() -mips_tcg_ss.add(gen) -mips_tcg_ss.add(files( - 'dsp_helper.c', - 'exception.c', - 'fpu_helper.c', - 'ldst_helper.c', - 'lmmi_helper.c', - 'msa_helper.c', - 'msa_translate.c', - 'op_helper.c', - 'rel6_translate.c', - 'translate.c', - 'translate_addr_const.c', - 'txx9_translate.c', -)) -mips_tcg_ss.add(when: 'TARGET_MIPS64', if_true: files( - 'tx79_translate.c', -), if_false: files( - 'mxu_translate.c', -)) if 'CONFIG_TCG' in config_all subdir('tcg') endif =20 mips_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) =20 -mips_ss.add_all(when: 'CONFIG_TCG', if_true: [mips_tcg_ss]) - target_arch +=3D {'mips': mips_ss} target_softmmu_arch +=3D {'mips': mips_softmmu_ss} target_user_arch +=3D {'mips': mips_user_ss} diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build index 2cffc5a5ac6..5d8acbaf0d3 100644 --- a/target/mips/tcg/meson.build +++ b/target/mips/tcg/meson.build @@ -1,3 +1,32 @@ +gen =3D [ + decodetree.process('mips32r6.decode', extra_args: '--static-decode=3Ddec= ode_mips32r6'), + decodetree.process('mips64r6.decode', extra_args: '--static-decode=3Ddec= ode_mips64r6'), + decodetree.process('msa32.decode', extra_args: '--static-decode=3Ddecode= _msa32'), + decodetree.process('msa64.decode', extra_args: '--static-decode=3Ddecode= _msa64'), + decodetree.process('tx79.decode', extra_args: '--static-decode=3Ddecode_= tx79'), +] + +mips_ss.add(gen) +mips_ss.add(files( + 'dsp_helper.c', + 'exception.c', + 'fpu_helper.c', + 'ldst_helper.c', + 'lmmi_helper.c', + 'msa_helper.c', + 'msa_translate.c', + 'op_helper.c', + 'rel6_translate.c', + 'translate.c', + 'translate_addr_const.c', + 'txx9_translate.c', +)) +mips_ss.add(when: 'TARGET_MIPS64', if_true: files( + 'tx79_translate.c', +), if_false: files( + 'mxu_translate.c', +)) + if have_user subdir('user') endif --=20 2.26.3 From nobody Sat May 4 03:43:33 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.47 as permitted sender) client-ip=209.85.128.47; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f47.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.47 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1618860047; cv=none; d=zohomail.com; s=zohoarc; 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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id t6sm23638649wrx.38.2021.04.19.12.20.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Apr 2021 12:20:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=oEwKjogwzqew9LHnVJfSpLxM+9Yj6ci2FrJpneJ2XN0=; b=L51dCVtmKV690CQnkg35sQEgw13A406O7kYdTzP5ed0IpTGgVE9dZ1maaiqEpZRH11 UEsd09O/O1UCwL63FyQnPoit+h6FvZrnkjCQ3or3dOkxB3k89CZ9ocjASHLO7+jPI2hC nVvy6lzCEQh0ldkxMCrgUC1SDJMr1YhWeCFBFqU8lX8ni2nfV3+qizc4zgC2u03l7Uod L3cXUuek5NsGoPVc3hY2jZsq+dgOTx1pK1ya1OqscufBpprsuS8j6/lVhC2IwVUXy1pa RBQzdbw5xTltalTs+BQhyrKXVO9vlokZrNEVRf7CVQuBBt+Sf5FA4y4RUttsaXNDvszJ NjIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=oEwKjogwzqew9LHnVJfSpLxM+9Yj6ci2FrJpneJ2XN0=; b=OWxXoTS3hqknCQfAib7VD2kB9Irs+08cmfMjALlYZQPcJkzi/gK3L615ie2JYe2NFM K4M68+GzSdKboYJyHxMz9hIah47RqMRQSKkRaatMo4NJA847ZxP7IS8NjKEsAbVCSGry 2oVGA1fR9SXSqtXEz3K+ZT3SSel82JCnlEbT3cKzeGD4lZFH9sYVTIy8wX8zDa+7Wufd oCQqCL9fwFTIBucOzpZVgiPEvuJ//I8kWivd1mO1ypuMHl5I11m9rHr9fxUXVk5AgFdf Xc3v7jeBS5DpIQBifswuXEj/vqWHXxpF8hdnhXkOsPvmabi6JK+P0xK65hFoxWu7QoVq CwwA== X-Gm-Message-State: AOAM532ESpqb2i1vOag76kHRL8UCHPJiGQxlM1jLLHZskcjUTG4P+NDX 047dFEBuFnRkY9MShErCEpk= X-Google-Smtp-Source: ABdhPJw8nYfDufMydi3q2HvUqDE4fzI3us8Xjyb/Dgegu2hg4fD+L9qxh7480lRXlHROogvZpj+BgQ== X-Received: by 2002:a05:600c:379a:: with SMTP id o26mr578311wmr.66.1618860046177; Mon, 19 Apr 2021 12:20:46 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Aurelien Jarno , Huacai Chen Subject: [PATCH v3 29/30] hw/mips: Restrict non-virtualized machines to TCG Date: Mon, 19 Apr 2021 21:18:22 +0200 Message-Id: <20210419191823.1555482-30-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210419191823.1555482-1-f4bug@amsat.org> References: <20210419191823.1555482-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Only the malta and loongson3-virt machines support KVM. Restrict the other machines to TCG: - mipssim - magnum - pica61 - fuloong2e - boston Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/mips/meson.build | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/hw/mips/meson.build b/hw/mips/meson.build index 1195716dc73..dd0101ad4d8 100644 --- a/hw/mips/meson.build +++ b/hw/mips/meson.build @@ -1,12 +1,15 @@ mips_ss =3D ss.source_set() mips_ss.add(files('bootloader.c', 'mips_int.c')) mips_ss.add(when: 'CONFIG_FW_CFG_MIPS', if_true: files('fw_cfg.c')) -mips_ss.add(when: 'CONFIG_FULOONG', if_true: files('fuloong2e.c')) mips_ss.add(when: 'CONFIG_LOONGSON3V', if_true: files('loongson3_bootp.c',= 'loongson3_virt.c')) -mips_ss.add(when: 'CONFIG_JAZZ', if_true: files('jazz.c')) mips_ss.add(when: 'CONFIG_MALTA', if_true: files('gt64xxx_pci.c', 'malta.c= ')) -mips_ss.add(when: 'CONFIG_MIPSSIM', if_true: files('mipssim.c')) -mips_ss.add(when: 'CONFIG_MIPS_BOSTON', if_true: [files('boston.c'), fdt]) mips_ss.add(when: 'CONFIG_MIPS_CPS', if_true: files('cps.c')) =20 +if 'CONFIG_TCG' in config_all +mips_ss.add(when: 'CONFIG_JAZZ', if_true: files('jazz.c')) +mips_ss.add(when: 'CONFIG_MIPSSIM', if_true: files('mipssim.c')) +mips_ss.add(when: 'CONFIG_FULOONG', if_true: files('fuloong2e.c')) +mips_ss.add(when: 'CONFIG_MIPS_BOSTON', if_true: [files('boston.c'), fdt]) +endif + hw_arch +=3D {'mips': mips_ss} --=20 2.26.3 From nobody Sat May 4 03:43:33 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.50 as permitted sender) client-ip=209.85.128.50; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f50.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.50 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1618860052; cv=none; d=zohomail.com; s=zohoarc; b=Q39Jhj0Zhknjuaw8Aoq2PK+qAZwgfXIC7zCpSl0SmF5w9CnG9w6UbwL4Xro1LBwOkxTs+sxxMKSX7KCqX/32mPp/b+rNpXg3+Qr22Z1gUPTEFA3apOkj/knNbEEppX7VVKECvNaiHZ+feUM006qfcyuqnvmf1IEmD0DccxsGl9k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618860052; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=hAxtd3FVfWCgth1vFkPSMi25H2dRcEPTe7zUFtCCWjA=; b=APGFIffhyLh3av8lTJw7waNswK86JVRb4Cje2YcfVm67K3vpwlOSUTzXvKnmQp8w9wlKM0J7qrFq7C3GgHoAQ0wber8TMk6IOkVFAIHAPUvTvKzX4QBT34Qze31p4qNYojBU822A3kTtl0p7RcEWT0SWBEcvvl0QeHslYPKHqok= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.50 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) by mx.zohomail.com with SMTPS id 1618860052872485.31674056162126; Mon, 19 Apr 2021 12:20:52 -0700 (PDT) Received: by mail-wm1-f50.google.com with SMTP id d200-20020a1c1dd10000b02901384767d4a5so2724380wmd.3 for ; Mon, 19 Apr 2021 12:20:52 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.redhat.com (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id u8sm24104177wrr.42.2021.04.19.12.20.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Apr 2021 12:20:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hAxtd3FVfWCgth1vFkPSMi25H2dRcEPTe7zUFtCCWjA=; b=LkVDFduRReXyNjjidVVROEwIzHD0FERodXAlwrXdSNbV8cKH2+K5gmA/zMP1rh3Cwd Din7i3w3KR/Eft8MAfdY2XPHqrZwEAdU0Zte4pvlpltFsmypHJNTGdNV5oaBkupZDzxO p3K2RZteFeMbRB7DmqOm9ALgmPPBIMOck8SvoQnRqFHjWemMfEt8RPXydU274/MtcSOZ RRjJYnj3RoCj3ywZnxVBldqR8lL2HpKLuu58AdgsSXKWuRAwQ5WB+JeXF97uBsckf8Ap kNuctMcnqPZ2FcU/vj7UmcXOfQx9Bl5YN37kxHGJvmTehBGTTBo33huD0mb4GRYnYV6q ncIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=hAxtd3FVfWCgth1vFkPSMi25H2dRcEPTe7zUFtCCWjA=; b=bj8aEYWTNpooWqnNX2Lryi8JxzVztVtkeXMFocMAEhRTHwfCEURz4ewXZQRh65+QHo 7ya0qJvXKlfZ2RB1qd0tj0uOJNnODXXN5qvU5DCogxmA5ai8v62qSQxANHIe63RxWU2S QAHtwPehkeUNw0TMD87lVAO+0vJTI8jy/DoimFRsZm4ouLUatE65wX9N5trOZRy6rVAk EWI76MqXp4PTD4ymGOCZMXvTXyxcbVqS7GASOqc7SeqjdR6biJaIbL2Fs7umfrh1JE0g zZnFq9h0Sd5oixteuXG0PkJURKwDhyqiskpk3+lWuPsTUSzJd2E+8l2ApTFw/L1V/2JC 6Scw== X-Gm-Message-State: AOAM5330fB6OWxK5ekITtJpbi4Ec90/qgTOBs5ffFQgqK8NJRMs+ZAJE xOYozUJkboNu3UfOrOc4U1A= X-Google-Smtp-Source: ABdhPJyKHbINv4bwEC2o0hSiGbzTEQ2xMxyAUl2Bm1rfDBzjwX+NI9cErNU2Ba6IAVtLtfPnYeUKJA== X-Received: by 2002:a05:600c:35d1:: with SMTP id r17mr561973wmq.71.1618860051155; Mon, 19 Apr 2021 12:20:51 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Aurelien Jarno , Huacai Chen , Thomas Huth , Willian Rampazzo , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Wainer dos Santos Moschetta Subject: [PATCH v3 30/30] gitlab-ci: Add KVM mips64el cross-build jobs Date: Mon, 19 Apr 2021 21:18:23 +0200 Message-Id: <20210419191823.1555482-31-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210419191823.1555482-1-f4bug@amsat.org> References: <20210419191823.1555482-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Add a new job to cross-build the mips64el target without the TCG accelerator (IOW: only KVM accelerator enabled). Only build the mips64el target which is known to work and has users. Reviewed-by: Richard Henderson Acked-by: Thomas Huth Reviewed-by: Willian Rampazzo Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- .gitlab-ci.d/crossbuilds.yml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/.gitlab-ci.d/crossbuilds.yml b/.gitlab-ci.d/crossbuilds.yml index 2d95784ed51..e44e4b49a25 100644 --- a/.gitlab-ci.d/crossbuilds.yml +++ b/.gitlab-ci.d/crossbuilds.yml @@ -176,6 +176,14 @@ cross-s390x-kvm-only: IMAGE: debian-s390x-cross ACCEL_CONFIGURE_OPTS: --disable-tcg =20 +cross-mips64el-kvm-only: + extends: .cross_accel_build_job + needs: + job: mips64el-debian-cross-container + variables: + IMAGE: debian-mips64el-cross + ACCEL_CONFIGURE_OPTS: --disable-tcg --target-list=3Dmips64el-softmmu + cross-win32-system: extends: .cross_system_build_job needs: --=20 2.26.3