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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id v2sm20823806wrr.26.2021.04.18.15.51.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Apr 2021 15:51:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HEDVE1BH0ASPFbPC+pm0317mb0q/DhypvkeSRH/j5kw=; b=j5HMviWXgiuhhePk44fGd+vYX7jcoJRUn5ZXvkhDX7s+OXYrBn7JFrOWyWOEoUdtL2 HPGvSHw7vhlB7D0QyG6rQdevt9fDSXBi5VqQ43mTomyaLPjoOAvjVdC45eZRyuDBimJJ hhHZlTAtW3fEsY9HPBOBrk2BOXvUqIUAjI2HH6u+Gni5hbs6MaNZ7j3Ktq6AYL1B/sGr YZ353PoWxu4yurhOPuBJ+DZL9kVwVjW3lHt5pOLIaT3/hG0fTvkU7ZIT0BllU2U6UNq6 rFT2ivpbrovllw0wzIk9RIu0bnlfvx0A+Pykfx8j/Q15Kiqv9hl34QwEY1Yo6MRW82VJ MDrQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=HEDVE1BH0ASPFbPC+pm0317mb0q/DhypvkeSRH/j5kw=; b=jNgCpL9bLt3gWQASzPU2XM0bQeBklXslFGQ6Yisgr64D8M7z9EdnC8p01+vPHFub27 jM+ItTl1axD2CWnE7FRGL7WMd/M/GSWUK4072NdBQMYMCQm//Nk4zc0ehLPnyzvvmr5W MBQWitgVw/abh9s4M03/n0ODv9xbfDoQumH4+r6glL5cmDMQAFUlc217LL1FlDKszkfw GDbVGVlpMv60P6ZJ44KeJT2Vf7on74ImrUO8VIbmsdRObHT64FDD0fzz/csHywGC/XfG q+Np8nkpBs/E+SfqU4CV1Gh0m5o/AUhpPzm7JBXYTc06l1ZiaCnB1fPzuHCyskiWbswi BUHQ== X-Gm-Message-State: AOAM532JsKezfdmHvTArQRp8rvOwO/lAlx893qpu78SKsWWGqSZfWesL kAf12TTxVQACyMFTVPnNgUE= X-Google-Smtp-Source: ABdhPJxT/Ou/uWSCn05FrAaV0TAMsbpi9XvJysW0xZzOilGB45gu8driS+bsolC95SPFb6D5lONHGg== X-Received: by 2002:adf:f3c1:: with SMTP id g1mr11118156wrp.344.1618786289368; Sun, 18 Apr 2021 15:51:29 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen , Jiaxun Yang , Aleksandar Rikalo Subject: [PATCH v2 06/29] target/mips: Restrict mips_cpu_dump_state() to cpu.c Date: Mon, 19 Apr 2021 00:50:35 +0200 Message-Id: <20210418225058.1257014-7-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210418225058.1257014-1-f4bug@amsat.org> References: <20210418225058.1257014-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) As mips_cpu_dump_state() is only used once to initialize the CPUClass::dump_state handler, we can move it to cpu.c to keep it symbol local. Beside, this handler is used by all accelerators, while the translate.c file targets TCG. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/internal.h | 1 - target/mips/cpu.c | 77 +++++++++++++++++++++++++++++++++++++++++ target/mips/translate.c | 77 ----------------------------------------- 3 files changed, 77 insertions(+), 78 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 37f54a8b3fc..57072a941e7 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -79,7 +79,6 @@ extern const int mips_defs_number; =20 void mips_cpu_do_interrupt(CPUState *cpu); bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); -void mips_cpu_dump_state(CPUState *cpu, FILE *f, int flags); hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); diff --git a/target/mips/cpu.c b/target/mips/cpu.c index ed9552ebeb7..232f701b836 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -145,6 +145,83 @@ void cpu_mips_store_cause(CPUMIPSState *env, target_ul= ong val) =20 #endif /* !CONFIG_USER_ONLY */ =20 +static void fpu_dump_state(CPUMIPSState *env, FILE *f, int flags) +{ + int i; + int is_fpu64 =3D !!(env->hflags & MIPS_HFLAG_F64); + +#define printfpr(fp) \ + do { \ + if (is_fpu64) \ + qemu_fprintf(f, "w:%08x d:%016" PRIx64 \ + " fd:%13g fs:%13g psu: %13g\n", \ + (fp)->w[FP_ENDIAN_IDX], (fp)->d, \ + (double)(fp)->fd, \ + (double)(fp)->fs[FP_ENDIAN_IDX], \ + (double)(fp)->fs[!FP_ENDIAN_IDX]); \ + else { \ + fpr_t tmp; \ + tmp.w[FP_ENDIAN_IDX] =3D (fp)->w[FP_ENDIAN_IDX]; \ + tmp.w[!FP_ENDIAN_IDX] =3D ((fp) + 1)->w[FP_ENDIAN_IDX]; \ + qemu_fprintf(f, "w:%08x d:%016" PRIx64 \ + " fd:%13g fs:%13g psu:%13g\n", \ + tmp.w[FP_ENDIAN_IDX], tmp.d, \ + (double)tmp.fd, \ + (double)tmp.fs[FP_ENDIAN_IDX], \ + (double)tmp.fs[!FP_ENDIAN_IDX]); \ + } \ + } while (0) + + + qemu_fprintf(f, + "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%02= x\n", + env->active_fpu.fcr0, env->active_fpu.fcr31, is_fpu64, + get_float_exception_flags(&env->active_fpu.fp_status)); + for (i =3D 0; i < 32; (is_fpu64) ? i++ : (i +=3D 2)) { + qemu_fprintf(f, "%3s: ", fregnames[i]); + printfpr(&env->active_fpu.fpr[i]); + } + +#undef printfpr +} + +static void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags) +{ + MIPSCPU *cpu =3D MIPS_CPU(cs); + CPUMIPSState *env =3D &cpu->env; + int i; + + qemu_fprintf(f, "pc=3D0x" TARGET_FMT_lx " HI=3D0x" TARGET_FMT_lx + " LO=3D0x" TARGET_FMT_lx " ds %04x " + TARGET_FMT_lx " " TARGET_FMT_ld "\n", + env->active_tc.PC, env->active_tc.HI[0], env->active_tc.L= O[0], + env->hflags, env->btarget, env->bcond); + for (i =3D 0; i < 32; i++) { + if ((i & 3) =3D=3D 0) { + qemu_fprintf(f, "GPR%02d:", i); + } + qemu_fprintf(f, " %s " TARGET_FMT_lx, + regnames[i], env->active_tc.gpr[i]); + if ((i & 3) =3D=3D 3) { + qemu_fprintf(f, "\n"); + } + } + + qemu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" + TARGET_FMT_lx "\n", + env->CP0_Status, env->CP0_Cause, env->CP0_EPC); + qemu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x%016" + PRIx64 "\n", + env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr); + qemu_fprintf(f, " Config2 0x%08x Config3 0x%08x\n", + env->CP0_Config2, env->CP0_Config3); + qemu_fprintf(f, " Config4 0x%08x Config5 0x%08x\n", + env->CP0_Config4, env->CP0_Config5); + if ((flags & CPU_DUMP_FPU) && (env->hflags & MIPS_HFLAG_FPU)) { + fpu_dump_state(env, f, flags); + } +} + static const char * const excp_names[EXCP_LAST + 1] =3D { [EXCP_RESET] =3D "reset", [EXCP_SRESET] =3D "soft reset", diff --git a/target/mips/translate.c b/target/mips/translate.c index f99d4d4016d..8702f9220be 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -25579,83 +25579,6 @@ void gen_intermediate_code(CPUState *cs, Translati= onBlock *tb, int max_insns) translator_loop(&mips_tr_ops, &ctx.base, cs, tb, max_insns); } =20 -static void fpu_dump_state(CPUMIPSState *env, FILE * f, int flags) -{ - int i; - int is_fpu64 =3D !!(env->hflags & MIPS_HFLAG_F64); - -#define printfpr(fp) \ - do { \ - if (is_fpu64) \ - qemu_fprintf(f, "w:%08x d:%016" PRIx64 \ - " fd:%13g fs:%13g psu: %13g\n", \ - (fp)->w[FP_ENDIAN_IDX], (fp)->d, \ - (double)(fp)->fd, \ - (double)(fp)->fs[FP_ENDIAN_IDX], \ - (double)(fp)->fs[!FP_ENDIAN_IDX]); \ - else { \ - fpr_t tmp; \ - tmp.w[FP_ENDIAN_IDX] =3D (fp)->w[FP_ENDIAN_IDX]; \ - tmp.w[!FP_ENDIAN_IDX] =3D ((fp) + 1)->w[FP_ENDIAN_IDX]; \ - qemu_fprintf(f, "w:%08x d:%016" PRIx64 \ - " fd:%13g fs:%13g psu:%13g\n", \ - tmp.w[FP_ENDIAN_IDX], tmp.d, \ - (double)tmp.fd, \ - (double)tmp.fs[FP_ENDIAN_IDX], \ - (double)tmp.fs[!FP_ENDIAN_IDX]); \ - } \ - } while (0) - - - qemu_fprintf(f, - "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%02= x\n", - env->active_fpu.fcr0, env->active_fpu.fcr31, is_fpu64, - get_float_exception_flags(&env->active_fpu.fp_status)); - for (i =3D 0; i < 32; (is_fpu64) ? i++ : (i +=3D 2)) { - qemu_fprintf(f, "%3s: ", fregnames[i]); - printfpr(&env->active_fpu.fpr[i]); - } - -#undef printfpr -} - -void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags) -{ - MIPSCPU *cpu =3D MIPS_CPU(cs); - CPUMIPSState *env =3D &cpu->env; - int i; - - qemu_fprintf(f, "pc=3D0x" TARGET_FMT_lx " HI=3D0x" TARGET_FMT_lx - " LO=3D0x" TARGET_FMT_lx " ds %04x " - TARGET_FMT_lx " " TARGET_FMT_ld "\n", - env->active_tc.PC, env->active_tc.HI[0], env->active_tc.L= O[0], - env->hflags, env->btarget, env->bcond); - for (i =3D 0; i < 32; i++) { - if ((i & 3) =3D=3D 0) { - qemu_fprintf(f, "GPR%02d:", i); - } - qemu_fprintf(f, " %s " TARGET_FMT_lx, - regnames[i], env->active_tc.gpr[i]); - if ((i & 3) =3D=3D 3) { - qemu_fprintf(f, "\n"); - } - } - - qemu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" - TARGET_FMT_lx "\n", - env->CP0_Status, env->CP0_Cause, env->CP0_EPC); - qemu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x%016" - PRIx64 "\n", - env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr); - qemu_fprintf(f, " Config2 0x%08x Config3 0x%08x\n", - env->CP0_Config2, env->CP0_Config3); - qemu_fprintf(f, " Config4 0x%08x Config5 0x%08x\n", - env->CP0_Config4, env->CP0_Config5); - if ((flags & CPU_DUMP_FPU) && (env->hflags & MIPS_HFLAG_FPU)) { - fpu_dump_state(env, f, flags); - } -} - void mips_tcg_init(void) { int i; --=20 2.26.3