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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id e10sm2909692wrw.20.2021.04.18.15.51.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Apr 2021 15:51:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yMxvZRcRgCBUS8Ws91rPcuJR47xd/yHVMPRhORw6260=; b=ODjZoLxLlysxUamMLDw02jG4DUkqXVeCcPjRv7BZafYPcaysSeNe1RFriK99inXbQp 8N+5rptK4ZKrEuO44c291Gf4liUZc0vWBvrfSBz12OHZ1SP/jm8QhIRfm2VeR+PWmDrc ft7nKhYB6DkEfbq7DUMFPua4tFyT97Etjtb2VHapqYeqSoToRTM9/GYo1P+qtt6PmM1/ ObCtVWSeZ8KGw3+0X/goCTlR3J97SIu3phdVYywTK4B5gSdzk+c79IdYRiS2kpBtDZDx IksmvOSDfRgMpK95B7P3Ns7v4WC+n8cpGN+cTy+NMoOHQscQ/X53JOKcf0vRVhCaTkm7 C+Mw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=yMxvZRcRgCBUS8Ws91rPcuJR47xd/yHVMPRhORw6260=; b=X41sqWMXjVpI71NHwCzAs8Tn5g0xg1pDix/Uzr18M1UNdNPjDpowwSjV7XokAA6g15 XD8+p7TFPeIVZ0oXvlpuz0R9wPDpKitQOOf7c96NEoEsqPaa3LCiwrhXkMWVmjtjHh8i ZknSfOHP9/sTi2y4CdBgl5et/0LthVy+B/EG/gWN5ZBqDM2kIiHi0UY1KE3PLlUYgcE7 wtLZxnhH4uRBjBOqtNX/VAycp45b4+PzOQkA1Kfa+MrVf2n6WaJ4rl/oTMzcRqVP+Mur id/tyKaSYibjz9iBjtq/ZJxLTOxswUv7XOY3nAYBmPMgrvGWFU28RDuWWVS3jmFgx4vi kySQ== X-Gm-Message-State: AOAM532/3Z+SX/v2g6IFqojwMRtb4/824qEtLm1D8QAbJ8ak/zfLU3of ePY5CYPAVsTnevX64Voz2wk= X-Google-Smtp-Source: ABdhPJySJtW1YVVo4B57X0LsGyoPI557oaU8NxIUR5rJE43n5jtYYlZMMA7FDv/SBS96mjRJW7cAfQ== X-Received: by 2002:a5d:524e:: with SMTP id k14mr10784308wrc.282.1618786274763; Sun, 18 Apr 2021 15:51:14 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen , Jiaxun Yang , Aleksandar Rikalo Subject: [PATCH v2 03/29] target/mips: Move msa_reset() to new source file Date: Mon, 19 Apr 2021 00:50:32 +0200 Message-Id: <20210418225058.1257014-4-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210418225058.1257014-1-f4bug@amsat.org> References: <20210418225058.1257014-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) mips_cpu_reset() is used by all accelerators, and calls msa_reset(), which is defined in msa_helper.c. Beside msa_reset(), the rest of msa_helper.c is only useful to the TCG accelerator. To be able to restrict this helper file to TCG, we need to move msa_reset() out of it. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/msa.c | 60 ++++++++++++++++++++++++++++++++++++++++ target/mips/msa_helper.c | 36 ------------------------ target/mips/meson.build | 1 + 3 files changed, 61 insertions(+), 36 deletions(-) create mode 100644 target/mips/msa.c diff --git a/target/mips/msa.c b/target/mips/msa.c new file mode 100644 index 00000000000..61f1a9a5936 --- /dev/null +++ b/target/mips/msa.c @@ -0,0 +1,60 @@ +/* + * MIPS SIMD Architecture Module Instruction emulation helpers for QEMU. + * + * Copyright (c) 2014 Imagination Technologies + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "internal.h" +#include "fpu/softfloat.h" +#include "fpu_helper.h" + +void msa_reset(CPUMIPSState *env) +{ + if (!ase_msa_available(env)) { + return; + } + +#ifdef CONFIG_USER_ONLY + /* MSA access enabled */ + env->CP0_Config5 |=3D 1 << CP0C5_MSAEn; + env->CP0_Status |=3D (1 << CP0St_CU1) | (1 << CP0St_FR); +#endif + + /* + * MSA CSR: + * - non-signaling floating point exception mode off (NX bit is 0) + * - Cause, Enables, and Flags are all 0 + * - round to nearest / ties to even (RM bits are 0) + */ + env->active_tc.msacsr =3D 0; + + restore_msa_fp_status(env); + + /* tininess detected after rounding.*/ + set_float_detect_tininess(float_tininess_after_rounding, + &env->active_tc.msa_fp_status); + + /* clear float_status exception flags */ + set_float_exception_flags(0, &env->active_tc.msa_fp_status); + + /* clear float_status nan mode */ + set_default_nan_mode(0, &env->active_tc.msa_fp_status); + + /* set proper signanling bit meaning ("1" means "quiet") */ + set_snan_bit_is_one(0, &env->active_tc.msa_fp_status); +} diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index 4caefe29ad7..04af54f66d1 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -8595,39 +8595,3 @@ void helper_msa_st_d(CPUMIPSState *env, uint32_t wd, cpu_stq_data(env, addr + (1 << DF_DOUBLE), pwd->d[1]); #endif } - -void msa_reset(CPUMIPSState *env) -{ - if (!ase_msa_available(env)) { - return; - } - -#ifdef CONFIG_USER_ONLY - /* MSA access enabled */ - env->CP0_Config5 |=3D 1 << CP0C5_MSAEn; - env->CP0_Status |=3D (1 << CP0St_CU1) | (1 << CP0St_FR); -#endif - - /* - * MSA CSR: - * - non-signaling floating point exception mode off (NX bit is 0) - * - Cause, Enables, and Flags are all 0 - * - round to nearest / ties to even (RM bits are 0) - */ - env->active_tc.msacsr =3D 0; - - restore_msa_fp_status(env); - - /* tininess detected after rounding.*/ - set_float_detect_tininess(float_tininess_after_rounding, - &env->active_tc.msa_fp_status); - - /* clear float_status exception flags */ - set_float_exception_flags(0, &env->active_tc.msa_fp_status); - - /* clear float_status nan mode */ - set_default_nan_mode(0, &env->active_tc.msa_fp_status); - - /* set proper signanling bit meaning ("1" means "quiet") */ - set_snan_bit_is_one(0, &env->active_tc.msa_fp_status); -} diff --git a/target/mips/meson.build b/target/mips/meson.build index 5fcb211ca9a..daf5f1d55bc 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -11,6 +11,7 @@ 'cpu.c', 'fpu.c', 'gdbstub.c', + 'msa.c', )) mips_tcg_ss =3D ss.source_set() mips_tcg_ss.add(gen) --=20 2.26.3