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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id m67sm20080759wme.27.2021.04.18.15.51.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Apr 2021 15:51:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fGOvaajXfmrpLSnOyhpIroCQXe3e+OS5MF3gQarLZWU=; b=QNWivB0L78JT1kd7GTmkKb8wUPAPwNm5zXohZKxJy7IquaKDl/Yzg3BMgbLib0B0jS rdXs4YRgNy7VRtbf2GGRcs2LUZvCC3eo8KwLwS3x0wi+vXjfo42mr7NMTWc4nHudokLt 0LcgaYZoFdEY1wNGW1gNZHAJXOpjPvrOktyVvHLsFyS/AQCYKbSUpm3Llr9e11KuSTo0 OzEEmKvXuKv/tD6LIDg9onGEImOwXp/xaU9tDeIUDASwARMLPngfZFP+hj3tsZcQI7dg Wx3/F+Q3OeA+qrKlZgvQEKeJ2pj0DAfAZd59qKe+hnHtWMfodRBp3b3KfTJb2Eq18T+Z xcrQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=fGOvaajXfmrpLSnOyhpIroCQXe3e+OS5MF3gQarLZWU=; b=ASBEDBbY9dmGGXEyyx2s5xByHnvnLlTzbFP43TeWORX1+t1/7FVR/mS2uWUJghZPZz s9DqcN05wzrfd2CO7a5J4ofEUuUfrZYmo7Pd/yfXRBzlLtcqX0TmmpC7uTrq3m5t6ABv gvY9SUJ28TYhDP7xR8aMSFJ9KSb9Jn3RVpW7me+mqq02SrwjDYJucKi/pQqDbtCfLZoz mb+o0tvhfA1sF1vAd9GbDS8s7L46CsyL70xcRicZpjbG/ym++OQv7WvGTjWkrz5rfUkX t9nLXq3L57/S667RhavrVix7UIQlIM9jYbKGuQ/nPWth2hp82B7Q6RJiBLQFI1MQfDzS OcWA== X-Gm-Message-State: AOAM532JT+XtTsj0jlptBHWiyhQ9mI9GbJ+VpAC7tKCLAwL65fwkNy8l YbKwS4qoELJxM9a2po7QPoQ= X-Google-Smtp-Source: ABdhPJw5bdgj/nrcN8qxu7gCPBPkwh6PVJs0KKVqtV863IaReWsmB+Tf4JACO1OQvYO7hvjRWOCFig== X-Received: by 2002:adf:dc4f:: with SMTP id m15mr11099761wrj.420.1618786269900; Sun, 18 Apr 2021 15:51:09 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen , Jiaxun Yang , Aleksandar Rikalo Subject: [PATCH v2 02/29] target/mips: Move IEEE rounding mode array to new source file Date: Mon, 19 Apr 2021 00:50:31 +0200 Message-Id: <20210418225058.1257014-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210418225058.1257014-1-f4bug@amsat.org> References: <20210418225058.1257014-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) restore_msa_fp_status() is declared inlined in fpu_helper.h, and uses the ieee_rm[] array. Therefore any code calling restore_msa_fp_status() must have access to this ieee_rm[] array. kvm_mips_get_fpu_registers(), which is in target/mips/kvm.c, calls restore_msa_fp_status. Except this tiny array, the rest of fpu_helper.c is only useful for the TCG accelerator. To be able to restrict fpu_helper.c to TCG, we need to move the ieee_rm[] array to a new source file. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/fpu.c | 18 ++++++++++++++++++ target/mips/fpu_helper.c | 8 -------- target/mips/meson.build | 1 + 3 files changed, 19 insertions(+), 8 deletions(-) create mode 100644 target/mips/fpu.c diff --git a/target/mips/fpu.c b/target/mips/fpu.c new file mode 100644 index 00000000000..39a2f7fd22e --- /dev/null +++ b/target/mips/fpu.c @@ -0,0 +1,18 @@ +/* + * Helpers for emulation of FPU-related MIPS instructions. + * + * Copyright (C) 2004-2005 Jocelyn Mayer + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ +#include "qemu/osdep.h" +#include "fpu/softfloat-helpers.h" +#include "fpu_helper.h" + +/* convert MIPS rounding mode in FCR31 to IEEE library */ +const FloatRoundMode ieee_rm[4] =3D { + float_round_nearest_even, + float_round_to_zero, + float_round_up, + float_round_down +}; diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c index 6dd853259e2..8ce56ed7c81 100644 --- a/target/mips/fpu_helper.c +++ b/target/mips/fpu_helper.c @@ -38,14 +38,6 @@ #define FP_TO_INT32_OVERFLOW 0x7fffffff #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL =20 -/* convert MIPS rounding mode in FCR31 to IEEE library */ -const FloatRoundMode ieee_rm[4] =3D { - float_round_nearest_even, - float_round_to_zero, - float_round_up, - float_round_down -}; - target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg) { target_ulong arg1 =3D 0; diff --git a/target/mips/meson.build b/target/mips/meson.build index 3733d1200f7..5fcb211ca9a 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -9,6 +9,7 @@ mips_ss =3D ss.source_set() mips_ss.add(files( 'cpu.c', + 'fpu.c', 'gdbstub.c', )) mips_tcg_ss =3D ss.source_set() --=20 2.26.3