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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id l20sm17861921wmg.33.2021.04.18.15.53.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Apr 2021 15:53:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FVrIMG0ikRSFfBCOQgXFDL1QwI5kw8IQhpeNT3H1Bwg=; b=LrL0J3EdjTk1VA0k8jY2ji1Rem1FICxNZa3FeYtQDg3kuzUc+f1x6F2+OBfe+cuetr Jrphm30x7Ud3p0oSf1d9LBSXVvRKxu02MTLIBFjs/is8kGyiWGSe2ZxM8Drw+PKNWcbN S/vxSrjRMc9vnsP7X5hqsRfEjo+RTJ+WU7pML6xiompmSi8xryJT5I0YLPfzlHMQ/S2B S9eF+SaGp/oD7JldVRstnW59DsR/WPTN9Q1D/kWTzc2DrJXCDJN9rX7nYu4qPqggkvfY 75JBaf5IqWs+ZyDAej3P2f8OgoxmLclY2KvUaSQxoxl2sSK3Ben5/q7EXpBvQ/B9vNSP z7TQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=FVrIMG0ikRSFfBCOQgXFDL1QwI5kw8IQhpeNT3H1Bwg=; b=nOdpRWpf58Yu97Kv5goI7HW17psGppMZ7KpA/LWi4UhHOPyl7PckkVs5S2nTpxwvSf Crh1yju41PFzm1Px8ft/78Z4JBSdGC0TaUfdJ0AVneDOxsVZ5myRIFedhIltR+4DPfbV fqQHnhpSDnx5C6bnU0WlWq0qIOeTimLLlH1o2DyXwqkhhN470ocZten8KKOMwWRktfUP ozAPoNQq2pY28nhy7ePvQfcIy0VEJkiZ2Q/StayOQ/FO3nU2NtAdXu5+sxKfABhZG1ak enqh7O5QOwcbd3DKlvDNrOcejOqBOqvwA2jh/wyABFfwD7Bxmgs2BSLB/yeoqewj6m0M JFNA== X-Gm-Message-State: AOAM532sZeDwGT48pqRKKHeGdss448Wb/Vt08TPNh5XmXdCoL2wJxuB7 X0xL16KAUxSNYXSNkYr068A= X-Google-Smtp-Source: ABdhPJx4E1F1iSjvYkwlBYrq1MtAf04HjaLsv8ZmuixOJUaivMwlWUQfw6kNerfPven8NvwfHjMMkw== X-Received: by 2002:adf:fdc7:: with SMTP id i7mr10959979wrs.350.1618786389564; Sun, 18 Apr 2021 15:53:09 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen , Jiaxun Yang , Aleksandar Rikalo Subject: [PATCH v2 27/29] target/mips: Move TCG source files under tcg/ sub directory Date: Mon, 19 Apr 2021 00:50:56 +0200 Message-Id: <20210418225058.1257014-28-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210418225058.1257014-1-f4bug@amsat.org> References: <20210418225058.1257014-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) To ease maintenance, move all TCG specific files under the tcg/ sub-directory. Adapt the Meson machinery. The following prototypes: - mips_tcg_init() - mips_cpu_do_unaligned_access() - mips_cpu_do_transaction_failed() can now be restricted to the "tcg-internal.h" header. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/helper.h | 2 +- target/mips/internal.h | 11 ------- target/mips/tcg/tcg-internal.h | 11 +++++++ target/mips/{ =3D> tcg}/msa_helper.h.inc | 0 target/mips/{ =3D> tcg}/mips32r6.decode | 0 target/mips/{ =3D> tcg}/mips64r6.decode | 0 target/mips/{ =3D> tcg}/msa32.decode | 0 target/mips/{ =3D> tcg}/msa64.decode | 0 target/mips/{ =3D> tcg}/tx79.decode | 0 target/mips/{ =3D> tcg}/dsp_helper.c | 0 target/mips/{ =3D> tcg}/exception.c | 0 target/mips/{ =3D> tcg}/fpu_helper.c | 0 target/mips/{ =3D> tcg}/ldst_helper.c | 0 target/mips/{ =3D> tcg}/lmmi_helper.c | 0 target/mips/{ =3D> tcg}/msa_helper.c | 0 target/mips/{ =3D> tcg}/msa_translate.c | 0 target/mips/{ =3D> tcg}/mxu_translate.c | 0 target/mips/{ =3D> tcg}/op_helper.c | 0 target/mips/{ =3D> tcg}/rel6_translate.c | 0 target/mips/{ =3D> tcg}/translate.c | 0 target/mips/{ =3D> tcg}/translate_addr_const.c | 0 target/mips/{ =3D> tcg}/tx79_translate.c | 0 target/mips/{ =3D> tcg}/txx9_translate.c | 0 target/mips/meson.build | 31 -------------------- target/mips/tcg/meson.build | 29 ++++++++++++++++++ 25 files changed, 41 insertions(+), 43 deletions(-) rename target/mips/{ =3D> tcg}/msa_helper.h.inc (100%) rename target/mips/{ =3D> tcg}/mips32r6.decode (100%) rename target/mips/{ =3D> tcg}/mips64r6.decode (100%) rename target/mips/{ =3D> tcg}/msa32.decode (100%) rename target/mips/{ =3D> tcg}/msa64.decode (100%) rename target/mips/{ =3D> tcg}/tx79.decode (100%) rename target/mips/{ =3D> tcg}/dsp_helper.c (100%) rename target/mips/{ =3D> tcg}/exception.c (100%) rename target/mips/{ =3D> tcg}/fpu_helper.c (100%) rename target/mips/{ =3D> tcg}/ldst_helper.c (100%) rename target/mips/{ =3D> tcg}/lmmi_helper.c (100%) rename target/mips/{ =3D> tcg}/msa_helper.c (100%) rename target/mips/{ =3D> tcg}/msa_translate.c (100%) rename target/mips/{ =3D> tcg}/mxu_translate.c (100%) rename target/mips/{ =3D> tcg}/op_helper.c (100%) rename target/mips/{ =3D> tcg}/rel6_translate.c (100%) rename target/mips/{ =3D> tcg}/translate.c (100%) rename target/mips/{ =3D> tcg}/translate_addr_const.c (100%) rename target/mips/{ =3D> tcg}/tx79_translate.c (100%) rename target/mips/{ =3D> tcg}/txx9_translate.c (100%) diff --git a/target/mips/helper.h b/target/mips/helper.h index ba301ae160d..a9c6c7d1a31 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -608,4 +608,4 @@ DEF_HELPER_FLAGS_2(rddsp, 0, tl, tl, env) #include "tcg/sysemu_helper.h.inc" #endif /* !CONFIG_USER_ONLY */ =20 -#include "msa_helper.h.inc" +#include "tcg/msa_helper.h.inc" diff --git a/target/mips/internal.h b/target/mips/internal.h index 588e89cfcda..c3c8eb0a177 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -82,9 +82,6 @@ extern const int mips_defs_number; =20 int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); -void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr); =20 #define USEG_LIMIT ((target_ulong)(int32_t)0x7FFFFFFFUL) #define KSEG0_BASE ((target_ulong)(int32_t)0x80000000UL) @@ -151,12 +148,6 @@ struct CPUMIPSTLBContext { } mmu; }; =20 -void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, - vaddr addr, unsigned size, - MMUAccessType access_type, - int mmu_idx, MemTxAttrs attrs, - MemTxResult response, uintptr_t retadd= r); - void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc); void cpu_mips_store_status(CPUMIPSState *env, target_ulong val); void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val); @@ -209,8 +200,6 @@ static inline bool cpu_mips_hw_interrupts_pending(CPUMI= PSState *env) return r; } =20 -void mips_tcg_init(void); - void msa_reset(CPUMIPSState *env); =20 /* cp0_timer.c */ diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h index 70f0d5da436..ae9b35ff706 100644 --- a/target/mips/tcg/tcg-internal.h +++ b/target/mips/tcg/tcg-internal.h @@ -11,15 +11,21 @@ #define MIPS_TCG_INTERNAL_H =20 #include "tcg/tcg.h" +#include "exec/memattrs.h" #include "hw/core/cpu.h" #include "cpu.h" =20 +void mips_tcg_init(void); + void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb= ); void mips_cpu_do_interrupt(CPUState *cpu); bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); +void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr); =20 const char *mips_exception_name(int32_t exception); =20 @@ -46,6 +52,11 @@ bool mips_io_recompile_replay_branch(CPUState *cs, const= TranslationBlock *tb); =20 hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, MMUAccessType access_type); +void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, + vaddr addr, unsigned size, + MMUAccessType access_type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, uintptr_t retadd= r); void cpu_mips_tlb_flush(CPUMIPSState *env); =20 #endif /* !CONFIG_USER_ONLY */ diff --git a/target/mips/msa_helper.h.inc b/target/mips/tcg/msa_helper.h.inc similarity index 100% rename from target/mips/msa_helper.h.inc rename to target/mips/tcg/msa_helper.h.inc diff --git a/target/mips/mips32r6.decode b/target/mips/tcg/mips32r6.decode similarity index 100% rename from target/mips/mips32r6.decode rename to target/mips/tcg/mips32r6.decode diff --git a/target/mips/mips64r6.decode b/target/mips/tcg/mips64r6.decode similarity index 100% rename from target/mips/mips64r6.decode rename to target/mips/tcg/mips64r6.decode diff --git a/target/mips/msa32.decode b/target/mips/tcg/msa32.decode similarity index 100% rename from target/mips/msa32.decode rename to target/mips/tcg/msa32.decode diff --git a/target/mips/msa64.decode b/target/mips/tcg/msa64.decode similarity index 100% rename from target/mips/msa64.decode rename to target/mips/tcg/msa64.decode diff --git a/target/mips/tx79.decode b/target/mips/tcg/tx79.decode similarity index 100% rename from target/mips/tx79.decode rename to target/mips/tcg/tx79.decode diff --git a/target/mips/dsp_helper.c b/target/mips/tcg/dsp_helper.c similarity index 100% rename from target/mips/dsp_helper.c rename to target/mips/tcg/dsp_helper.c diff --git a/target/mips/exception.c b/target/mips/tcg/exception.c similarity index 100% rename from target/mips/exception.c rename to target/mips/tcg/exception.c diff --git a/target/mips/fpu_helper.c b/target/mips/tcg/fpu_helper.c similarity index 100% rename from target/mips/fpu_helper.c rename to target/mips/tcg/fpu_helper.c diff --git a/target/mips/ldst_helper.c b/target/mips/tcg/ldst_helper.c similarity index 100% rename from target/mips/ldst_helper.c rename to target/mips/tcg/ldst_helper.c diff --git a/target/mips/lmmi_helper.c b/target/mips/tcg/lmmi_helper.c similarity index 100% rename from target/mips/lmmi_helper.c rename to target/mips/tcg/lmmi_helper.c diff --git a/target/mips/msa_helper.c b/target/mips/tcg/msa_helper.c similarity index 100% rename from target/mips/msa_helper.c rename to target/mips/tcg/msa_helper.c diff --git a/target/mips/msa_translate.c b/target/mips/tcg/msa_translate.c similarity index 100% rename from target/mips/msa_translate.c rename to target/mips/tcg/msa_translate.c diff --git a/target/mips/mxu_translate.c b/target/mips/tcg/mxu_translate.c similarity index 100% rename from target/mips/mxu_translate.c rename to target/mips/tcg/mxu_translate.c diff --git a/target/mips/op_helper.c b/target/mips/tcg/op_helper.c similarity index 100% rename from target/mips/op_helper.c rename to target/mips/tcg/op_helper.c diff --git a/target/mips/rel6_translate.c b/target/mips/tcg/rel6_translate.c similarity index 100% rename from target/mips/rel6_translate.c rename to target/mips/tcg/rel6_translate.c diff --git a/target/mips/translate.c b/target/mips/tcg/translate.c similarity index 100% rename from target/mips/translate.c rename to target/mips/tcg/translate.c diff --git a/target/mips/translate_addr_const.c b/target/mips/tcg/translate= _addr_const.c similarity index 100% rename from target/mips/translate_addr_const.c rename to target/mips/tcg/translate_addr_const.c diff --git a/target/mips/tx79_translate.c b/target/mips/tcg/tx79_translate.c similarity index 100% rename from target/mips/tx79_translate.c rename to target/mips/tcg/tx79_translate.c diff --git a/target/mips/txx9_translate.c b/target/mips/tcg/txx9_translate.c similarity index 100% rename from target/mips/txx9_translate.c rename to target/mips/tcg/txx9_translate.c diff --git a/target/mips/meson.build b/target/mips/meson.build index e08077bfc18..2407a05d4c0 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -1,11 +1,3 @@ -gen =3D [ - decodetree.process('mips32r6.decode', extra_args: '--static-decode=3Ddec= ode_mips32r6'), - decodetree.process('mips64r6.decode', extra_args: '--static-decode=3Ddec= ode_mips64r6'), - decodetree.process('msa32.decode', extra_args: '--static-decode=3Ddecode= _msa32'), - decodetree.process('msa64.decode', extra_args: '--static-decode=3Ddecode= _msa64'), - decodetree.process('tx79.decode', extra_args: '--static-decode=3Ddecode_= tx79'), -] - mips_user_ss =3D ss.source_set() mips_softmmu_ss =3D ss.source_set() mips_ss =3D ss.source_set() @@ -20,35 +12,12 @@ subdir('sysemu') endif =20 -mips_tcg_ss =3D ss.source_set() -mips_tcg_ss.add(gen) -mips_tcg_ss.add(files( - 'dsp_helper.c', - 'exception.c', - 'fpu_helper.c', - 'ldst_helper.c', - 'lmmi_helper.c', - 'msa_helper.c', - 'msa_translate.c', - 'op_helper.c', - 'rel6_translate.c', - 'translate.c', - 'translate_addr_const.c', - 'txx9_translate.c', -)) -mips_tcg_ss.add(when: 'TARGET_MIPS64', if_true: files( - 'tx79_translate.c', -), if_false: files( - 'mxu_translate.c', -)) if 'CONFIG_TCG' in config_all subdir('tcg') endif =20 mips_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) =20 -mips_ss.add_all(when: 'CONFIG_TCG', if_true: [mips_tcg_ss]) - target_arch +=3D {'mips': mips_ss} target_softmmu_arch +=3D {'mips': mips_softmmu_ss} target_user_arch +=3D {'mips': mips_user_ss} diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build index 2cffc5a5ac6..5d8acbaf0d3 100644 --- a/target/mips/tcg/meson.build +++ b/target/mips/tcg/meson.build @@ -1,3 +1,32 @@ +gen =3D [ + decodetree.process('mips32r6.decode', extra_args: '--static-decode=3Ddec= ode_mips32r6'), + decodetree.process('mips64r6.decode', extra_args: '--static-decode=3Ddec= ode_mips64r6'), + decodetree.process('msa32.decode', extra_args: '--static-decode=3Ddecode= _msa32'), + decodetree.process('msa64.decode', extra_args: '--static-decode=3Ddecode= _msa64'), + decodetree.process('tx79.decode', extra_args: '--static-decode=3Ddecode_= tx79'), +] + +mips_ss.add(gen) +mips_ss.add(files( + 'dsp_helper.c', + 'exception.c', + 'fpu_helper.c', + 'ldst_helper.c', + 'lmmi_helper.c', + 'msa_helper.c', + 'msa_translate.c', + 'op_helper.c', + 'rel6_translate.c', + 'translate.c', + 'translate_addr_const.c', + 'txx9_translate.c', +)) +mips_ss.add(when: 'TARGET_MIPS64', if_true: files( + 'tx79_translate.c', +), if_false: files( + 'mxu_translate.c', +)) + if have_user subdir('user') endif --=20 2.26.3