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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id y11sm17854527wro.37.2021.04.18.15.51.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Apr 2021 15:51:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pi4Yqp/Ga3uNxjsupGFLY1gAQ5ebMQowaCuPTS7xonw=; b=s3oJf1vKnfi4dUxvvBvpxre7mRuvGFoFqaFwqySnq1W2YBHTM4nkYRX2BAHbUbDLmK ddgYa157N4N9Hmg+PaJeej7ikd+lH8GmWNF6ccUNR2jfdb2VJ1lE8N3TQEDRIs8WKQHj 9liQ/fXfPfC7Snr0XnT+OKIE+8gEPzwPGSm9jH1D/SZd++TNte3/9JQzSpPmLTF5tA1G ySkmLwI7x1Bb3liD4GhjXSX1kOouutn0TYk6AffdPFAl8QoCBE0JdNVUnX21FnOjUJ53 3p8qhQguEltoG5baZx2YeSRHdVZ54cNFbnxj2FOGQ31Xg7ywQNabX+dOpVD45ewunmXU rZ2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=pi4Yqp/Ga3uNxjsupGFLY1gAQ5ebMQowaCuPTS7xonw=; b=e/QCldds8rynP8DBdfsKiXM9UcBXN5+KFAooizZKdYZLoVMzvJdHbDVphE91tFRJNx bb/aPB/sSNjj+gdMheoQVnE4og2zKxR1iaODYjRQxjUBxoTDbHxcDKf538aX2olbU+4U w5m+LZ8LQ+/kY6DHCbDzBRH4daXZwc3lwORcETGJi52De3lCZB71W3JEc+rJyLAVbS28 2Tu+aQo7ohjFd2vTPxAGrsuADVYZe56JIEWd9Y9MPeUPO7AY/i8+fIESl3vhdM2YxoXW +pjOvoSWDxMpsSeKvmfwVV5GLmr9WcEIrOvhs4F1qYPLlBlLsSL61M4Ni5WR57fGM6Jo 21bg== X-Gm-Message-State: AOAM531p9OawdzDyxg2RsIyU9j8lOfZ30lsKUf80lU6Zl1wOdzZ8hpRG pzaRKECMh/cZN72F6BFrtmw= X-Google-Smtp-Source: ABdhPJxLlRZpUVdqJ1z9RmQ+auJac40lD4H6JfreeDo1JXGf3BvIb1PJjbvCGW0qpcbC8hEOq+quCQ== X-Received: by 2002:a1c:6244:: with SMTP id w65mr18640233wmb.27.1618786264978; Sun, 18 Apr 2021 15:51:04 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen , Jiaxun Yang , Aleksandar Rikalo Subject: [PATCH v2 01/29] target/mips: Simplify meson TCG rules Date: Mon, 19 Apr 2021 00:50:30 +0200 Message-Id: <20210418225058.1257014-2-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210418225058.1257014-1-f4bug@amsat.org> References: <20210418225058.1257014-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) We already have the mips_tcg_ss source set for TCG-specific files, use it for mxu_translate.c and tx79_translate.c to simplify a bit. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/meson.build | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/target/mips/meson.build b/target/mips/meson.build index 3b131c4a7f6..3733d1200f7 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -26,10 +26,9 @@ 'translate_addr_const.c', 'txx9_translate.c', )) -mips_ss.add(when: ['CONFIG_TCG', 'TARGET_MIPS64'], if_true: files( +mips_tcg_ss.add(when: 'TARGET_MIPS64', if_true: files( 'tx79_translate.c', -)) -mips_tcg_ss.add(when: 'TARGET_MIPS64', if_false: files( +), if_false: files( 'mxu_translate.c', )) =20 --=20 2.26.3 From nobody Mon Feb 9 10:44:55 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.44 as permitted sender) client-ip=209.85.221.44; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f44.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.44 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1618786271; cv=none; d=zohomail.com; s=zohoarc; b=iAFwUwOdB1z72MMSiz9RTn7yAXBRLS+3AqtQdz/4y3766V7JGEtd7zkwcEnp4lNuLB4YCSWjk7Q5nUwDW8LC9tNQivMXkuYTsPcR2MamauOHgSy8gvTymptQ0dm2C5Tva9Ov8Nlb6CSrkfh4efczHyH3bjCKeBOD6tCPvgFqnlc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618786271; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=fGOvaajXfmrpLSnOyhpIroCQXe3e+OS5MF3gQarLZWU=; b=bS9ff4UDiZ4VudYHgQKS9oSf3FpVP8Ip+ipqJVqXQOtl5n0Akq7QRCmal7lF8VvdApodnTnttfT1Twkiipvrlfip7kMbCRtrbWgJuXGs6YfXeokSw5x+NmeMgZX7AyXH2BPfpQBFmbhDdnfojuqZ7aNL3XYhKHR1xYo3NQjI/uo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.44 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-wr1-f44.google.com (mail-wr1-f44.google.com [209.85.221.44]) by mx.zohomail.com with SMTPS id 1618786271634179.4671381277691; Sun, 18 Apr 2021 15:51:11 -0700 (PDT) Received: by mail-wr1-f44.google.com with SMTP id e5so3379291wrg.7 for ; Sun, 18 Apr 2021 15:51:11 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id m67sm20080759wme.27.2021.04.18.15.51.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Apr 2021 15:51:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fGOvaajXfmrpLSnOyhpIroCQXe3e+OS5MF3gQarLZWU=; b=QNWivB0L78JT1kd7GTmkKb8wUPAPwNm5zXohZKxJy7IquaKDl/Yzg3BMgbLib0B0jS rdXs4YRgNy7VRtbf2GGRcs2LUZvCC3eo8KwLwS3x0wi+vXjfo42mr7NMTWc4nHudokLt 0LcgaYZoFdEY1wNGW1gNZHAJXOpjPvrOktyVvHLsFyS/AQCYKbSUpm3Llr9e11KuSTo0 OzEEmKvXuKv/tD6LIDg9onGEImOwXp/xaU9tDeIUDASwARMLPngfZFP+hj3tsZcQI7dg Wx3/F+Q3OeA+qrKlZgvQEKeJ2pj0DAfAZd59qKe+hnHtWMfodRBp3b3KfTJb2Eq18T+Z xcrQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=fGOvaajXfmrpLSnOyhpIroCQXe3e+OS5MF3gQarLZWU=; b=ASBEDBbY9dmGGXEyyx2s5xByHnvnLlTzbFP43TeWORX1+t1/7FVR/mS2uWUJghZPZz s9DqcN05wzrfd2CO7a5J4ofEUuUfrZYmo7Pd/yfXRBzlLtcqX0TmmpC7uTrq3m5t6ABv gvY9SUJ28TYhDP7xR8aMSFJ9KSb9Jn3RVpW7me+mqq02SrwjDYJucKi/pQqDbtCfLZoz mb+o0tvhfA1sF1vAd9GbDS8s7L46CsyL70xcRicZpjbG/ym++OQv7WvGTjWkrz5rfUkX t9nLXq3L57/S667RhavrVix7UIQlIM9jYbKGuQ/nPWth2hp82B7Q6RJiBLQFI1MQfDzS OcWA== X-Gm-Message-State: AOAM532JT+XtTsj0jlptBHWiyhQ9mI9GbJ+VpAC7tKCLAwL65fwkNy8l YbKwS4qoELJxM9a2po7QPoQ= X-Google-Smtp-Source: ABdhPJw5bdgj/nrcN8qxu7gCPBPkwh6PVJs0KKVqtV863IaReWsmB+Tf4JACO1OQvYO7hvjRWOCFig== X-Received: by 2002:adf:dc4f:: with SMTP id m15mr11099761wrj.420.1618786269900; Sun, 18 Apr 2021 15:51:09 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen , Jiaxun Yang , Aleksandar Rikalo Subject: [PATCH v2 02/29] target/mips: Move IEEE rounding mode array to new source file Date: Mon, 19 Apr 2021 00:50:31 +0200 Message-Id: <20210418225058.1257014-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210418225058.1257014-1-f4bug@amsat.org> References: <20210418225058.1257014-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) restore_msa_fp_status() is declared inlined in fpu_helper.h, and uses the ieee_rm[] array. Therefore any code calling restore_msa_fp_status() must have access to this ieee_rm[] array. kvm_mips_get_fpu_registers(), which is in target/mips/kvm.c, calls restore_msa_fp_status. Except this tiny array, the rest of fpu_helper.c is only useful for the TCG accelerator. To be able to restrict fpu_helper.c to TCG, we need to move the ieee_rm[] array to a new source file. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/fpu.c | 18 ++++++++++++++++++ target/mips/fpu_helper.c | 8 -------- target/mips/meson.build | 1 + 3 files changed, 19 insertions(+), 8 deletions(-) create mode 100644 target/mips/fpu.c diff --git a/target/mips/fpu.c b/target/mips/fpu.c new file mode 100644 index 00000000000..39a2f7fd22e --- /dev/null +++ b/target/mips/fpu.c @@ -0,0 +1,18 @@ +/* + * Helpers for emulation of FPU-related MIPS instructions. + * + * Copyright (C) 2004-2005 Jocelyn Mayer + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ +#include "qemu/osdep.h" +#include "fpu/softfloat-helpers.h" +#include "fpu_helper.h" + +/* convert MIPS rounding mode in FCR31 to IEEE library */ +const FloatRoundMode ieee_rm[4] =3D { + float_round_nearest_even, + float_round_to_zero, + float_round_up, + float_round_down +}; diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c index 6dd853259e2..8ce56ed7c81 100644 --- a/target/mips/fpu_helper.c +++ b/target/mips/fpu_helper.c @@ -38,14 +38,6 @@ #define FP_TO_INT32_OVERFLOW 0x7fffffff #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL =20 -/* convert MIPS rounding mode in FCR31 to IEEE library */ -const FloatRoundMode ieee_rm[4] =3D { - float_round_nearest_even, - float_round_to_zero, - float_round_up, - float_round_down -}; - target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg) { target_ulong arg1 =3D 0; diff --git a/target/mips/meson.build b/target/mips/meson.build index 3733d1200f7..5fcb211ca9a 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -9,6 +9,7 @@ mips_ss =3D ss.source_set() mips_ss.add(files( 'cpu.c', + 'fpu.c', 'gdbstub.c', )) mips_tcg_ss =3D ss.source_set() --=20 2.26.3 From nobody Mon Feb 9 10:44:55 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) client-ip=209.85.221.53; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f53.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1618786276; cv=none; d=zohomail.com; s=zohoarc; b=g1TVSWf8V/wcNOtkHZ7s0JoHB4hQU1vG/EhmVSrOV6MoVr4T/V8ZHflQ7hzdX4X3p1mESlJaRTxKvyA20un4ybnvpoVbtTpxR6CBehwllx3HIMZndNd1RnCiSBZAuwlDdnE6cgAumD3VIIxaUcH98+re3j+0WF+PV+OWxM/ltFM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618786276; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=yMxvZRcRgCBUS8Ws91rPcuJR47xd/yHVMPRhORw6260=; b=lm7W6w851fX3Mn13+oced8rRKQyBU/Kp/ttHVkX+TVuL1LkgyT5ZI0uHHNaM/maHsJzeyzGWPYFwoWniU7MTk4Eb1p7y6ldEgiNiMpq0bWYItNZ/Hqs4gvbpFm+rE2q7hwIyOXxMxQW0zz5A3RYFRsGC8q927mZ1GBTQ8p9QJb8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f53.google.com (mail-wr1-f53.google.com [209.85.221.53]) by mx.zohomail.com with SMTPS id 1618786276508308.50587823160913; Sun, 18 Apr 2021 15:51:16 -0700 (PDT) Received: by mail-wr1-f53.google.com with SMTP id m9so19282595wrx.3 for ; Sun, 18 Apr 2021 15:51:15 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id e10sm2909692wrw.20.2021.04.18.15.51.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Apr 2021 15:51:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yMxvZRcRgCBUS8Ws91rPcuJR47xd/yHVMPRhORw6260=; b=ODjZoLxLlysxUamMLDw02jG4DUkqXVeCcPjRv7BZafYPcaysSeNe1RFriK99inXbQp 8N+5rptK4ZKrEuO44c291Gf4liUZc0vWBvrfSBz12OHZ1SP/jm8QhIRfm2VeR+PWmDrc ft7nKhYB6DkEfbq7DUMFPua4tFyT97Etjtb2VHapqYeqSoToRTM9/GYo1P+qtt6PmM1/ ObCtVWSeZ8KGw3+0X/goCTlR3J97SIu3phdVYywTK4B5gSdzk+c79IdYRiS2kpBtDZDx IksmvOSDfRgMpK95B7P3Ns7v4WC+n8cpGN+cTy+NMoOHQscQ/X53JOKcf0vRVhCaTkm7 C+Mw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=yMxvZRcRgCBUS8Ws91rPcuJR47xd/yHVMPRhORw6260=; b=X41sqWMXjVpI71NHwCzAs8Tn5g0xg1pDix/Uzr18M1UNdNPjDpowwSjV7XokAA6g15 XD8+p7TFPeIVZ0oXvlpuz0R9wPDpKitQOOf7c96NEoEsqPaa3LCiwrhXkMWVmjtjHh8i ZknSfOHP9/sTi2y4CdBgl5et/0LthVy+B/EG/gWN5ZBqDM2kIiHi0UY1KE3PLlUYgcE7 wtLZxnhH4uRBjBOqtNX/VAycp45b4+PzOQkA1Kfa+MrVf2n6WaJ4rl/oTMzcRqVP+Mur id/tyKaSYibjz9iBjtq/ZJxLTOxswUv7XOY3nAYBmPMgrvGWFU28RDuWWVS3jmFgx4vi kySQ== X-Gm-Message-State: AOAM532/3Z+SX/v2g6IFqojwMRtb4/824qEtLm1D8QAbJ8ak/zfLU3of ePY5CYPAVsTnevX64Voz2wk= X-Google-Smtp-Source: ABdhPJySJtW1YVVo4B57X0LsGyoPI557oaU8NxIUR5rJE43n5jtYYlZMMA7FDv/SBS96mjRJW7cAfQ== X-Received: by 2002:a5d:524e:: with SMTP id k14mr10784308wrc.282.1618786274763; Sun, 18 Apr 2021 15:51:14 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen , Jiaxun Yang , Aleksandar Rikalo Subject: [PATCH v2 03/29] target/mips: Move msa_reset() to new source file Date: Mon, 19 Apr 2021 00:50:32 +0200 Message-Id: <20210418225058.1257014-4-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210418225058.1257014-1-f4bug@amsat.org> References: <20210418225058.1257014-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) mips_cpu_reset() is used by all accelerators, and calls msa_reset(), which is defined in msa_helper.c. Beside msa_reset(), the rest of msa_helper.c is only useful to the TCG accelerator. To be able to restrict this helper file to TCG, we need to move msa_reset() out of it. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/msa.c | 60 ++++++++++++++++++++++++++++++++++++++++ target/mips/msa_helper.c | 36 ------------------------ target/mips/meson.build | 1 + 3 files changed, 61 insertions(+), 36 deletions(-) create mode 100644 target/mips/msa.c diff --git a/target/mips/msa.c b/target/mips/msa.c new file mode 100644 index 00000000000..61f1a9a5936 --- /dev/null +++ b/target/mips/msa.c @@ -0,0 +1,60 @@ +/* + * MIPS SIMD Architecture Module Instruction emulation helpers for QEMU. + * + * Copyright (c) 2014 Imagination Technologies + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "internal.h" +#include "fpu/softfloat.h" +#include "fpu_helper.h" + +void msa_reset(CPUMIPSState *env) +{ + if (!ase_msa_available(env)) { + return; + } + +#ifdef CONFIG_USER_ONLY + /* MSA access enabled */ + env->CP0_Config5 |=3D 1 << CP0C5_MSAEn; + env->CP0_Status |=3D (1 << CP0St_CU1) | (1 << CP0St_FR); +#endif + + /* + * MSA CSR: + * - non-signaling floating point exception mode off (NX bit is 0) + * - Cause, Enables, and Flags are all 0 + * - round to nearest / ties to even (RM bits are 0) + */ + env->active_tc.msacsr =3D 0; + + restore_msa_fp_status(env); + + /* tininess detected after rounding.*/ + set_float_detect_tininess(float_tininess_after_rounding, + &env->active_tc.msa_fp_status); + + /* clear float_status exception flags */ + set_float_exception_flags(0, &env->active_tc.msa_fp_status); + + /* clear float_status nan mode */ + set_default_nan_mode(0, &env->active_tc.msa_fp_status); + + /* set proper signanling bit meaning ("1" means "quiet") */ + set_snan_bit_is_one(0, &env->active_tc.msa_fp_status); +} diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index 4caefe29ad7..04af54f66d1 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -8595,39 +8595,3 @@ void helper_msa_st_d(CPUMIPSState *env, uint32_t wd, cpu_stq_data(env, addr + (1 << DF_DOUBLE), pwd->d[1]); #endif } - -void msa_reset(CPUMIPSState *env) -{ - if (!ase_msa_available(env)) { - return; - } - -#ifdef CONFIG_USER_ONLY - /* MSA access enabled */ - env->CP0_Config5 |=3D 1 << CP0C5_MSAEn; - env->CP0_Status |=3D (1 << CP0St_CU1) | (1 << CP0St_FR); -#endif - - /* - * MSA CSR: - * - non-signaling floating point exception mode off (NX bit is 0) - * - Cause, Enables, and Flags are all 0 - * - round to nearest / ties to even (RM bits are 0) - */ - env->active_tc.msacsr =3D 0; - - restore_msa_fp_status(env); - - /* tininess detected after rounding.*/ - set_float_detect_tininess(float_tininess_after_rounding, - &env->active_tc.msa_fp_status); - - /* clear float_status exception flags */ - set_float_exception_flags(0, &env->active_tc.msa_fp_status); - - /* clear float_status nan mode */ - set_default_nan_mode(0, &env->active_tc.msa_fp_status); - - /* set proper signanling bit meaning ("1" means "quiet") */ - set_snan_bit_is_one(0, &env->active_tc.msa_fp_status); -} diff --git a/target/mips/meson.build b/target/mips/meson.build index 5fcb211ca9a..daf5f1d55bc 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -11,6 +11,7 @@ 'cpu.c', 'fpu.c', 'gdbstub.c', + 'msa.c', )) mips_tcg_ss =3D ss.source_set() mips_tcg_ss.add(gen) --=20 2.26.3 From nobody Mon Feb 9 10:44:55 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.48 as permitted sender) client-ip=209.85.221.48; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f48.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.48 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1618786281; cv=none; d=zohomail.com; s=zohoarc; b=bqUx/2oK2US22d02l9DDmJE2en/UO4gghCnAMpPv9pC7587Q8CBOBENdmk0S38XloELFnTIiB7Lih1poyA/7TyO0A7JefUzGNb4H2xOv0EA9wT8TA+GG2nA59/tJ5HjJGcnjVcYgOIfkXD/XQJhwCrvfwu8j8Z0wiORyh4oaWC0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618786281; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=JdLEvydvbX477BhH/ZmKV47FrIUBwZZqHvybwivTF10=; b=MgVXnIZ0nAZSjUNO0BrwM+u6XXCdeWXoRSTz2rt+3nN5QL7Pg3l5X6s94/x4dzF/efWs4yV7xEKLbUu6ntaasbyPXgLyeHdur8aFpvSpSSDnv/6X5d4IOD3q7OtqVnedxq5zq37s46QerQRdDUnWrJ4QW//XsW+PV1apAFUCtWI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.48 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-wr1-f48.google.com (mail-wr1-f48.google.com [209.85.221.48]) by mx.zohomail.com with SMTPS id 1618786281326218.18293946031235; Sun, 18 Apr 2021 15:51:21 -0700 (PDT) Received: by mail-wr1-f48.google.com with SMTP id m9so19282688wrx.3 for ; Sun, 18 Apr 2021 15:51:20 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id q10sm17322390wmc.31.2021.04.18.15.51.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Apr 2021 15:51:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JdLEvydvbX477BhH/ZmKV47FrIUBwZZqHvybwivTF10=; b=iJyETAjg7rFPWYhSshdHjxskFOSBgaHXqN6AGZ5xh6YL4h+2fpjQ+czNUjAJx4Kxc6 RxMoBDuoxaD/Qgbn5cdnudZDOIS19/6f7qMzPstXacvgDn8Icr3sby/OxyDrT90lRgUZ ahimevfwqw32sySf05QnwRbqRWxn6WiM+ykd4vbrbdEWSPOQn10Nk1YK/7wM/GPPmAXj AUgrWZKO408nEiagWeNOBr6i8MHLEU6IpIZ9X2yhQIsvM6phjYdntOE3Jdy4roAVr60v 3DZdtuRn44VnhpzWxZORVYWTNhV4SP77GEk/gKSBGhTwjvFghXQeVSpQiFN1HpGF0ZO3 CPRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=JdLEvydvbX477BhH/ZmKV47FrIUBwZZqHvybwivTF10=; b=M+tXI1UhTroJzS1dg3e0xOt6zQyjyURoymy+SHpiWvDRXFEV9ppCvmmaagbtCg8zNr akpsYt53YGgdJP5OTLs5lFo/OZ9yqGwardeo2KXnXRxQVCXjjhtWwlRQpddw3GE3go8U J8LSGtuQ01oyXTanVgyXgA3TB0Dp+6bWJu9mP69aCFnzDqt+8gWgoipErThHSHNoYK8/ P+2AgPz2q/RNC/+1WDGaKIgXX6fYdcybV0z//a3pViPn7SEfm2Ex8OcisQWY2VgBTILa nF2/iyvmApZQekMriassiMy9P7LwVIf+8YXjA3mu1i80KLKzxeyYipUMOhUAFViowQti f6MQ== X-Gm-Message-State: AOAM533XE29Lc64JoOJyryrFT5FBI3fvG4LI1BWGLzki24vbqV2QGNm5 BvSdb+3W5QfTisUoLelZbl0= X-Google-Smtp-Source: ABdhPJxEZHDe9gBlfvjpwWO9JdaHzT3mcQBpzxXsJDMNZ4rjASRBt8V5otHHRFMp7cFuOD5BvXscRA== X-Received: by 2002:a05:6000:1084:: with SMTP id y4mr11069734wrw.364.1618786279626; Sun, 18 Apr 2021 15:51:19 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen , Jiaxun Yang , Aleksandar Rikalo Subject: [PATCH v2 04/29] target/mips: Make CPU/FPU regnames[] arrays global Date: Mon, 19 Apr 2021 00:50:33 +0200 Message-Id: <20210418225058.1257014-5-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210418225058.1257014-1-f4bug@amsat.org> References: <20210418225058.1257014-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) The CPU/FPU regnames[] arrays is used in mips_tcg_init() and mips_cpu_dump_state(), which while being in translate.c is not specific to TCG. To be able to move mips_cpu_dump_state() to cpu.c, which is compiled for all accelerator, we need to make the regnames[] arrays global to target/mips/ by declaring them in "internal.h". Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/internal.h | 3 +++ target/mips/cpu.c | 7 +++++++ target/mips/fpu.c | 7 +++++++ target/mips/translate.c | 14 -------------- 4 files changed, 17 insertions(+), 14 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 99264b8bf6a..a8644f754a6 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -71,6 +71,9 @@ struct mips_def_t { int32_t SAARP; }; =20 +extern const char * const regnames[32]; +extern const char * const fregnames[32]; + extern const struct mips_def_t mips_defs[]; extern const int mips_defs_number; =20 diff --git a/target/mips/cpu.c b/target/mips/cpu.c index dce1e166bde..f354d18aec4 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -35,6 +35,13 @@ #include "qapi/qapi-commands-machine-target.h" #include "fpu_helper.h" =20 +const char * const regnames[32] =3D { + "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3", + "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", + "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", + "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", +}; + #if !defined(CONFIG_USER_ONLY) =20 /* Called for updates to CP0_Status. */ diff --git a/target/mips/fpu.c b/target/mips/fpu.c index 39a2f7fd22e..1447dba3fa3 100644 --- a/target/mips/fpu.c +++ b/target/mips/fpu.c @@ -16,3 +16,10 @@ const FloatRoundMode ieee_rm[4] =3D { float_round_up, float_round_down }; + +const char * const fregnames[32] =3D { + "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", + "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", + "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", + "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", +}; diff --git a/target/mips/translate.c b/target/mips/translate.c index 71fa5ec1973..f99d4d4016d 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1267,13 +1267,6 @@ TCGv_i64 fpu_f64[32]; #define DISAS_STOP DISAS_TARGET_0 #define DISAS_EXIT DISAS_TARGET_1 =20 -static const char * const regnames[] =3D { - "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3", - "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", - "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", - "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", -}; - static const char * const regnames_HI[] =3D { "HI0", "HI1", "HI2", "HI3", }; @@ -1282,13 +1275,6 @@ static const char * const regnames_LO[] =3D { "LO0", "LO1", "LO2", "LO3", }; =20 -static const char * const fregnames[] =3D { - "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", - "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", - "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", - "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", -}; - /* General purpose registers moves. */ void gen_load_gpr(TCGv t, int reg) { --=20 2.26.3 From nobody Mon Feb 9 10:44:55 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.54 as permitted sender) client-ip=209.85.128.54; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f54.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.54 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1618786286; cv=none; d=zohomail.com; s=zohoarc; b=K1K2NUSAsZv5RXP9Wi9qw92Z1jguoNa86ZE/KlYljXCXRoNwkwpxelMf/8n7fh6CpZyzSRyhwwKbJIh6Ykz34TelzzKtq2ScwlKFlWrJNPoGjaI7dSYyi1dr0/gaNjhUJ0JnVthHTJgZNfkTKslmxWegWomQ9bjtGjMIpwLxWCc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618786286; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=jK+gaco4qgdVhboeMerJ/bnvg6dnQ6kpU1z6QqW9e3M=; b=mpdmFtdrzBPqg+cUVFmdGJqNDmF33o89nNR7/ZZC2CTScUP+Ky4f65Jhizkth40vNZtZSTM4pjEax6S6VnJWXHfSdMzZfWMK271eU+RcHLS90LyUwIKAEuUkBBscaGF8tFfSO6AbOGpRJJ9m91H3zUgN6hAAVsEePBSQFt1/zkk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.54 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) by mx.zohomail.com with SMTPS id 1618786286067938.2124915119203; Sun, 18 Apr 2021 15:51:26 -0700 (PDT) Received: by mail-wm1-f54.google.com with SMTP id n4-20020a05600c4f84b029013151278decso5842677wmq.4 for ; Sun, 18 Apr 2021 15:51:25 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id s8sm20078938wrn.97.2021.04.18.15.51.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Apr 2021 15:51:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jK+gaco4qgdVhboeMerJ/bnvg6dnQ6kpU1z6QqW9e3M=; b=qDTKSS3yYHKeZqLSa02acBoYEFSwxIuxF8Og9DtujA78Ia0yEv6CqtrslinYEYiQ1Y Nsh4QyMLMf1mTr8nHhainDeHdZfjolgdMHBXaXUNMjnESwTVs0+q74jw+hpnDjg1zOIc 4ZvSd1PyPsYUeTJ7yVAZAV7KAHLLpK+SQmJTZUQSO5rJTUINtBzjkriPxl8vUEtvKCVA LzhvcoTcsubc6Pvyr0U/fMJJRFk8HnOinDBbSDMkOSOJ0cld8IIf3QZoKd0JBDay/7TP GwiK5AkTEp0BR3ODFveBCAHQPfFOkvDXGBTdoMU/KlaHummgVJ8PHYwRXkMH7ayHlE+I IFPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=jK+gaco4qgdVhboeMerJ/bnvg6dnQ6kpU1z6QqW9e3M=; b=LBXaPXhZ0jEAnq7lwR22Ukb2XsOOY8HZ3j9MY31iGZIpo8KX2gRXyUNTVtdPUuW1Ou V13ZHb4V9/RzOsjuYCUN+dYfhF7kuWI8Jd7MWSsJmUht9qEC6ispuI+KiXvbbVOzBuMx +2zyzAWNcrXGfYJyTGdR7FsG/i1Pf80rnyd/R/HKj87s/2rqvcvdbM0MYXmfTfQEcp8G Nuy5+oBlkKR5mJ9Avo0CXi1mFgGUa+yOx5/OTNIZhP/F2zJmehHk3YXPpq721DU/c6Zi qvcpkgism1UyhO9evJ5lYRvNXbivLwbdQn69YycXtI9tpBRjI4STSSzm09hv8D+nD2EU qWng== X-Gm-Message-State: AOAM532r9pBeX5xb4L3wJgegAdj45uFD1EsUnV1iKyxwqIE19yGW9Oy+ zJ4p8xzEXFAqKA3Y6/HzcaM= X-Google-Smtp-Source: ABdhPJzPZn1+qznD7pxRmhhGaKGxbfSkFQvS3abcU3jW1pv4y7JqS5NQ42P8SMQohdMT+8FRZOGPfA== X-Received: by 2002:a7b:c14a:: with SMTP id z10mr18127602wmi.75.1618786284406; Sun, 18 Apr 2021 15:51:24 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen , Jiaxun Yang , Aleksandar Rikalo Subject: [PATCH v2 05/29] target/mips: Optimize CPU/FPU regnames[] arrays Date: Mon, 19 Apr 2021 00:50:34 +0200 Message-Id: <20210418225058.1257014-6-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210418225058.1257014-1-f4bug@amsat.org> References: <20210418225058.1257014-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Since all entries are no more than 4 bytes (including nul terminator), can save space and pie runtime relocations by declaring regnames[] as array of 4 const char. Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/internal.h | 4 ++-- target/mips/cpu.c | 2 +- target/mips/fpu.c | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index a8644f754a6..37f54a8b3fc 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -71,8 +71,8 @@ struct mips_def_t { int32_t SAARP; }; =20 -extern const char * const regnames[32]; -extern const char * const fregnames[32]; +extern const char regnames[32][4]; +extern const char fregnames[32][4]; =20 extern const struct mips_def_t mips_defs[]; extern const int mips_defs_number; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index f354d18aec4..ed9552ebeb7 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -35,7 +35,7 @@ #include "qapi/qapi-commands-machine-target.h" #include "fpu_helper.h" =20 -const char * const regnames[32] =3D { +const char regnames[32][4] =3D { "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3", "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", diff --git a/target/mips/fpu.c b/target/mips/fpu.c index 1447dba3fa3..c7c487c1f9f 100644 --- a/target/mips/fpu.c +++ b/target/mips/fpu.c @@ -17,7 +17,7 @@ const FloatRoundMode ieee_rm[4] =3D { float_round_down }; =20 -const char * const fregnames[32] =3D { +const char fregnames[32][4] =3D { "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", --=20 2.26.3 From nobody Mon Feb 9 10:44:55 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) client-ip=209.85.221.53; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f53.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1618786291; cv=none; d=zohomail.com; s=zohoarc; b=QeKW77mJvTiJutAcYx9gGEwyNb2C/HMFwBQ3TXDqZeLi9IUgwBeJxedxlwjjR7GIbWzN2xS9uRf3W5TOJnJ6ugq8GJb3DfLe2vIfs1dF4FIg9YJ1FBE26yJVmFRdkTx9yZNQj75mbPk6mES+2/QMgyAHjSgbPbolPVc63E7r2Sc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618786291; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=HEDVE1BH0ASPFbPC+pm0317mb0q/DhypvkeSRH/j5kw=; b=jlniiBB9lg/CgJGqgCgCN1Y38d2NkXXxrb4jwzYmLvVyYJjuIwXCoH3c/S50LWi7/gKgQwxJpHCoOMZl8Dax62PrANIFaYwNU/vyU8HrFJpeBqqC2gVkataQU94Bxtii0GIU2P3VoXb3tAuJo8IIyGv8JIx3FMkc3v1YqVtVEYY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f53.google.com (mail-wr1-f53.google.com [209.85.221.53]) by mx.zohomail.com with SMTPS id 161878629121667.68507183390989; Sun, 18 Apr 2021 15:51:31 -0700 (PDT) Received: by mail-wr1-f53.google.com with SMTP id a4so32051541wrr.2 for ; Sun, 18 Apr 2021 15:51:30 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id v2sm20823806wrr.26.2021.04.18.15.51.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Apr 2021 15:51:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HEDVE1BH0ASPFbPC+pm0317mb0q/DhypvkeSRH/j5kw=; b=j5HMviWXgiuhhePk44fGd+vYX7jcoJRUn5ZXvkhDX7s+OXYrBn7JFrOWyWOEoUdtL2 HPGvSHw7vhlB7D0QyG6rQdevt9fDSXBi5VqQ43mTomyaLPjoOAvjVdC45eZRyuDBimJJ hhHZlTAtW3fEsY9HPBOBrk2BOXvUqIUAjI2HH6u+Gni5hbs6MaNZ7j3Ktq6AYL1B/sGr YZ353PoWxu4yurhOPuBJ+DZL9kVwVjW3lHt5pOLIaT3/hG0fTvkU7ZIT0BllU2U6UNq6 rFT2ivpbrovllw0wzIk9RIu0bnlfvx0A+Pykfx8j/Q15Kiqv9hl34QwEY1Yo6MRW82VJ MDrQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=HEDVE1BH0ASPFbPC+pm0317mb0q/DhypvkeSRH/j5kw=; b=jNgCpL9bLt3gWQASzPU2XM0bQeBklXslFGQ6Yisgr64D8M7z9EdnC8p01+vPHFub27 jM+ItTl1axD2CWnE7FRGL7WMd/M/GSWUK4072NdBQMYMCQm//Nk4zc0ehLPnyzvvmr5W MBQWitgVw/abh9s4M03/n0ODv9xbfDoQumH4+r6glL5cmDMQAFUlc217LL1FlDKszkfw GDbVGVlpMv60P6ZJ44KeJT2Vf7on74ImrUO8VIbmsdRObHT64FDD0fzz/csHywGC/XfG q+Np8nkpBs/E+SfqU4CV1Gh0m5o/AUhpPzm7JBXYTc06l1ZiaCnB1fPzuHCyskiWbswi BUHQ== X-Gm-Message-State: AOAM532JsKezfdmHvTArQRp8rvOwO/lAlx893qpu78SKsWWGqSZfWesL kAf12TTxVQACyMFTVPnNgUE= X-Google-Smtp-Source: ABdhPJxT/Ou/uWSCn05FrAaV0TAMsbpi9XvJysW0xZzOilGB45gu8driS+bsolC95SPFb6D5lONHGg== X-Received: by 2002:adf:f3c1:: with SMTP id g1mr11118156wrp.344.1618786289368; Sun, 18 Apr 2021 15:51:29 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen , Jiaxun Yang , Aleksandar Rikalo Subject: [PATCH v2 06/29] target/mips: Restrict mips_cpu_dump_state() to cpu.c Date: Mon, 19 Apr 2021 00:50:35 +0200 Message-Id: <20210418225058.1257014-7-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210418225058.1257014-1-f4bug@amsat.org> References: <20210418225058.1257014-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) As mips_cpu_dump_state() is only used once to initialize the CPUClass::dump_state handler, we can move it to cpu.c to keep it symbol local. Beside, this handler is used by all accelerators, while the translate.c file targets TCG. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/internal.h | 1 - target/mips/cpu.c | 77 +++++++++++++++++++++++++++++++++++++++++ target/mips/translate.c | 77 ----------------------------------------- 3 files changed, 77 insertions(+), 78 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 37f54a8b3fc..57072a941e7 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -79,7 +79,6 @@ extern const int mips_defs_number; =20 void mips_cpu_do_interrupt(CPUState *cpu); bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); -void mips_cpu_dump_state(CPUState *cpu, FILE *f, int flags); hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); diff --git a/target/mips/cpu.c b/target/mips/cpu.c index ed9552ebeb7..232f701b836 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -145,6 +145,83 @@ void cpu_mips_store_cause(CPUMIPSState *env, target_ul= ong val) =20 #endif /* !CONFIG_USER_ONLY */ =20 +static void fpu_dump_state(CPUMIPSState *env, FILE *f, int flags) +{ + int i; + int is_fpu64 =3D !!(env->hflags & MIPS_HFLAG_F64); + +#define printfpr(fp) \ + do { \ + if (is_fpu64) \ + qemu_fprintf(f, "w:%08x d:%016" PRIx64 \ + " fd:%13g fs:%13g psu: %13g\n", \ + (fp)->w[FP_ENDIAN_IDX], (fp)->d, \ + (double)(fp)->fd, \ + (double)(fp)->fs[FP_ENDIAN_IDX], \ + (double)(fp)->fs[!FP_ENDIAN_IDX]); \ + else { \ + fpr_t tmp; \ + tmp.w[FP_ENDIAN_IDX] =3D (fp)->w[FP_ENDIAN_IDX]; \ + tmp.w[!FP_ENDIAN_IDX] =3D ((fp) + 1)->w[FP_ENDIAN_IDX]; \ + qemu_fprintf(f, "w:%08x d:%016" PRIx64 \ + " fd:%13g fs:%13g psu:%13g\n", \ + tmp.w[FP_ENDIAN_IDX], tmp.d, \ + (double)tmp.fd, \ + (double)tmp.fs[FP_ENDIAN_IDX], \ + (double)tmp.fs[!FP_ENDIAN_IDX]); \ + } \ + } while (0) + + + qemu_fprintf(f, + "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%02= x\n", + env->active_fpu.fcr0, env->active_fpu.fcr31, is_fpu64, + get_float_exception_flags(&env->active_fpu.fp_status)); + for (i =3D 0; i < 32; (is_fpu64) ? i++ : (i +=3D 2)) { + qemu_fprintf(f, "%3s: ", fregnames[i]); + printfpr(&env->active_fpu.fpr[i]); + } + +#undef printfpr +} + +static void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags) +{ + MIPSCPU *cpu =3D MIPS_CPU(cs); + CPUMIPSState *env =3D &cpu->env; + int i; + + qemu_fprintf(f, "pc=3D0x" TARGET_FMT_lx " HI=3D0x" TARGET_FMT_lx + " LO=3D0x" TARGET_FMT_lx " ds %04x " + TARGET_FMT_lx " " TARGET_FMT_ld "\n", + env->active_tc.PC, env->active_tc.HI[0], env->active_tc.L= O[0], + env->hflags, env->btarget, env->bcond); + for (i =3D 0; i < 32; i++) { + if ((i & 3) =3D=3D 0) { + qemu_fprintf(f, "GPR%02d:", i); + } + qemu_fprintf(f, " %s " TARGET_FMT_lx, + regnames[i], env->active_tc.gpr[i]); + if ((i & 3) =3D=3D 3) { + qemu_fprintf(f, "\n"); + } + } + + qemu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" + TARGET_FMT_lx "\n", + env->CP0_Status, env->CP0_Cause, env->CP0_EPC); + qemu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x%016" + PRIx64 "\n", + env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr); + qemu_fprintf(f, " Config2 0x%08x Config3 0x%08x\n", + env->CP0_Config2, env->CP0_Config3); + qemu_fprintf(f, " Config4 0x%08x Config5 0x%08x\n", + env->CP0_Config4, env->CP0_Config5); + if ((flags & CPU_DUMP_FPU) && (env->hflags & MIPS_HFLAG_FPU)) { + fpu_dump_state(env, f, flags); + } +} + static const char * const excp_names[EXCP_LAST + 1] =3D { [EXCP_RESET] =3D "reset", [EXCP_SRESET] =3D "soft reset", diff --git a/target/mips/translate.c b/target/mips/translate.c index f99d4d4016d..8702f9220be 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -25579,83 +25579,6 @@ void gen_intermediate_code(CPUState *cs, Translati= onBlock *tb, int max_insns) translator_loop(&mips_tr_ops, &ctx.base, cs, tb, max_insns); } =20 -static void fpu_dump_state(CPUMIPSState *env, FILE * f, int flags) -{ - int i; - int is_fpu64 =3D !!(env->hflags & MIPS_HFLAG_F64); - -#define printfpr(fp) \ - do { \ - if (is_fpu64) \ - qemu_fprintf(f, "w:%08x d:%016" PRIx64 \ - " fd:%13g fs:%13g psu: %13g\n", \ - (fp)->w[FP_ENDIAN_IDX], (fp)->d, \ - (double)(fp)->fd, \ - (double)(fp)->fs[FP_ENDIAN_IDX], \ - (double)(fp)->fs[!FP_ENDIAN_IDX]); \ - else { \ - fpr_t tmp; \ - tmp.w[FP_ENDIAN_IDX] =3D (fp)->w[FP_ENDIAN_IDX]; \ - tmp.w[!FP_ENDIAN_IDX] =3D ((fp) + 1)->w[FP_ENDIAN_IDX]; \ - qemu_fprintf(f, "w:%08x d:%016" PRIx64 \ - " fd:%13g fs:%13g psu:%13g\n", \ - tmp.w[FP_ENDIAN_IDX], tmp.d, \ - (double)tmp.fd, \ - (double)tmp.fs[FP_ENDIAN_IDX], \ - (double)tmp.fs[!FP_ENDIAN_IDX]); \ - } \ - } while (0) - - - qemu_fprintf(f, - "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%02= x\n", - env->active_fpu.fcr0, env->active_fpu.fcr31, is_fpu64, - get_float_exception_flags(&env->active_fpu.fp_status)); - for (i =3D 0; i < 32; (is_fpu64) ? i++ : (i +=3D 2)) { - qemu_fprintf(f, "%3s: ", fregnames[i]); - printfpr(&env->active_fpu.fpr[i]); - } - -#undef printfpr -} - -void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags) -{ - MIPSCPU *cpu =3D MIPS_CPU(cs); - CPUMIPSState *env =3D &cpu->env; - int i; - - qemu_fprintf(f, "pc=3D0x" TARGET_FMT_lx " HI=3D0x" TARGET_FMT_lx - " LO=3D0x" TARGET_FMT_lx " ds %04x " - TARGET_FMT_lx " " TARGET_FMT_ld "\n", - env->active_tc.PC, env->active_tc.HI[0], env->active_tc.L= O[0], - env->hflags, env->btarget, env->bcond); - for (i =3D 0; i < 32; i++) { - if ((i & 3) =3D=3D 0) { - qemu_fprintf(f, "GPR%02d:", i); - } - qemu_fprintf(f, " %s " TARGET_FMT_lx, - regnames[i], env->active_tc.gpr[i]); - if ((i & 3) =3D=3D 3) { - qemu_fprintf(f, "\n"); - } - } - - qemu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" - TARGET_FMT_lx "\n", - env->CP0_Status, env->CP0_Cause, env->CP0_EPC); - qemu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x%016" - PRIx64 "\n", - env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr); - qemu_fprintf(f, " Config2 0x%08x Config3 0x%08x\n", - env->CP0_Config2, env->CP0_Config3); - qemu_fprintf(f, " Config4 0x%08x Config5 0x%08x\n", - env->CP0_Config4, env->CP0_Config5); - if ((flags & CPU_DUMP_FPU) && (env->hflags & MIPS_HFLAG_FPU)) { - fpu_dump_state(env, f, flags); - } -} - void mips_tcg_init(void) { int i; --=20 2.26.3 From nobody Mon Feb 9 10:44:55 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.51 as permitted sender) client-ip=209.85.128.51; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f51.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.51 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1618786295; cv=none; d=zohomail.com; s=zohoarc; b=B/aVaPrPfS7q3T00r5PnkGZ9FIwNZuWjXynq/wXh6NPEymCFJUs0amlnrx3kS+hFLNtpxI41ZuBuuRcOO6W4pT0cpyGoYxRC7q7XRjZl4TVT13zocIwn+GT9IVEi0AOgMtstXHuxaBGT5SBAsbl6R+ivxfTEUVZXWKhxu/Kxxto= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618786295; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=fTQ5LbmfBKa+DkChI03N3lX+fZBlTslCfIb2OafYz+c=; b=d4rutoE3tlwkDLfcqtAwnc3PXDJNlsg3Qp5F1HvW0GQ68eS8GwiQ6ZgH6gqsjPvWBMTb2OpO73XF+uLOkPpAA7f/zy/XX5ou6in+hce511J7jSeejWuG1gNc9lxUIKP9KE1/X5+qOloo7Qb7mknqFneMdcgTuitXRvNxPu0hyPw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.51 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) by mx.zohomail.com with SMTPS id 1618786295987972.3136704925188; Sun, 18 Apr 2021 15:51:35 -0700 (PDT) Received: by mail-wm1-f51.google.com with SMTP id o9-20020a1c41090000b029012c8dac9d47so10098879wma.1 for ; Sun, 18 Apr 2021 15:51:35 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id v4sm17235085wme.14.2021.04.18.15.51.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Apr 2021 15:51:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fTQ5LbmfBKa+DkChI03N3lX+fZBlTslCfIb2OafYz+c=; b=lVi3ifnZlBlVA9Tv1suzJAXIDD4rwQKhYoZ1+vj/HtpUnz62dPam8ae+PYQELQnYtC zl0vcqn9S7l8VeAf/Q8ZFv89JKNopf3e/r0WIHJuqVsZgCJKAp9cDoBnbhLB5440rpdO s0jCYQ7FplSaHg0liJj12OidmVRdaVbKO0KQrAp9REPKRcUDRs/ganE/DlSNceKzAeB1 fGhWlZjSfnuMiAmzkg9zQzQboAvE6T2fGS9XL3pnOaRSTadci7FRNscsTPI0cpyfAhPC CxkuZJHsJgfT43Y7iS38PKc21rpARw6H1Q4Ajc/JzrOc2D7eWUQ/XJnu0GpBjAySyBt0 g49A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=fTQ5LbmfBKa+DkChI03N3lX+fZBlTslCfIb2OafYz+c=; b=nqeOZLkOonehh60VIsHx/P277QukIAAon9xkSZYIvlWpxZMLTdZZrHRp0s0ZlYZEqd F7IpuUlsx4pmuMmdgP/RtQKPezIqBDhyRM665YpPwrZbSFKfSFEDJi1BE9/KLcoa8FL5 AKpnR6MlYPJhZDDj/mbpaOtyo4wxqvvA+3h2jeVdYu5mnhCesTs+nxDPIXJLU6FdyZuE J7Q1qVlDCWt5FdvhCrP238dCU6QHcK16VugB6uTSv8l38kQT4X/7SYWqKb7kR+waYk9I PV71bpnQJhLHASp046uyMNyEZPOkUwUBaC8wnwK41WaYbabNyJ2Ffw/RwhoWPZlP6e/L DOZA== X-Gm-Message-State: AOAM532iYLTD26JphGzLlBnaygt0ZfjFzpkki++5/fLCnbCEnb/yF4rC XGn2KYElcPhdS2r1msriazY= X-Google-Smtp-Source: ABdhPJy/9KW9kNiXZwJNCB8pRsy2QmigWiBuSPGGqPe1uEtPrGEQFQSHM2AYYljm5FQcWfu9FLcAKw== X-Received: by 2002:a1c:a182:: with SMTP id k124mr18974890wme.132.1618786294123; Sun, 18 Apr 2021 15:51:34 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen , Jiaxun Yang , Aleksandar Rikalo Subject: [PATCH v2 07/29] target/mips: Turn printfpr() macro into a proper function Date: Mon, 19 Apr 2021 00:50:36 +0200 Message-Id: <20210418225058.1257014-8-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210418225058.1257014-1-f4bug@amsat.org> References: <20210418225058.1257014-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Turn printfpr() macro into a proper function: fpu_dump_fpr(). Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/cpu.c | 48 ++++++++++++++++++++++------------------------- 1 file changed, 22 insertions(+), 26 deletions(-) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 232f701b836..90ae232c8b8 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -145,44 +145,40 @@ void cpu_mips_store_cause(CPUMIPSState *env, target_u= long val) =20 #endif /* !CONFIG_USER_ONLY */ =20 +static void fpu_dump_fpr(fpr_t *fpr, FILE *f, bool is_fpu64) +{ + if (is_fpu64) { + qemu_fprintf(f, "w:%08x d:%016" PRIx64 " fd:%13g fs:%13g psu: %13g= \n", + fpr->w[FP_ENDIAN_IDX], fpr->d, + (double)fpr->fd, + (double)fpr->fs[FP_ENDIAN_IDX], + (double)fpr->fs[!FP_ENDIAN_IDX]); + } else { + fpr_t tmp; + + tmp.w[FP_ENDIAN_IDX] =3D fpr->w[FP_ENDIAN_IDX]; + tmp.w[!FP_ENDIAN_IDX] =3D (fpr + 1)->w[FP_ENDIAN_IDX]; + qemu_fprintf(f, "w:%08x d:%016" PRIx64 " fd:%13g fs:%13g psu:%13g\= n", + tmp.w[FP_ENDIAN_IDX], tmp.d, + (double)tmp.fd, + (double)tmp.fs[FP_ENDIAN_IDX], + (double)tmp.fs[!FP_ENDIAN_IDX]); + } +} + static void fpu_dump_state(CPUMIPSState *env, FILE *f, int flags) { int i; int is_fpu64 =3D !!(env->hflags & MIPS_HFLAG_F64); =20 -#define printfpr(fp) \ - do { \ - if (is_fpu64) \ - qemu_fprintf(f, "w:%08x d:%016" PRIx64 \ - " fd:%13g fs:%13g psu: %13g\n", \ - (fp)->w[FP_ENDIAN_IDX], (fp)->d, \ - (double)(fp)->fd, \ - (double)(fp)->fs[FP_ENDIAN_IDX], \ - (double)(fp)->fs[!FP_ENDIAN_IDX]); \ - else { \ - fpr_t tmp; \ - tmp.w[FP_ENDIAN_IDX] =3D (fp)->w[FP_ENDIAN_IDX]; \ - tmp.w[!FP_ENDIAN_IDX] =3D ((fp) + 1)->w[FP_ENDIAN_IDX]; \ - qemu_fprintf(f, "w:%08x d:%016" PRIx64 \ - " fd:%13g fs:%13g psu:%13g\n", \ - tmp.w[FP_ENDIAN_IDX], tmp.d, \ - (double)tmp.fd, \ - (double)tmp.fs[FP_ENDIAN_IDX], \ - (double)tmp.fs[!FP_ENDIAN_IDX]); \ - } \ - } while (0) - - qemu_fprintf(f, "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%02= x\n", env->active_fpu.fcr0, env->active_fpu.fcr31, is_fpu64, get_float_exception_flags(&env->active_fpu.fp_status)); for (i =3D 0; i < 32; (is_fpu64) ? i++ : (i +=3D 2)) { qemu_fprintf(f, "%3s: ", fregnames[i]); - printfpr(&env->active_fpu.fpr[i]); + fpu_dump_fpr(&env->active_fpu.fpr[i], f, is_fpu64); } - -#undef printfpr } =20 static void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags) --=20 2.26.3 From nobody Mon Feb 9 10:44:55 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.42 as permitted sender) client-ip=209.85.128.42; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f42.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.42 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1618786300; cv=none; d=zohomail.com; s=zohoarc; b=Wio24G7U8Txzr/4pKal8T6geIfJY7To79pDyvytLV14JPwNuozmzckJebVNt3pBD8Tys/XI9DNfqIP3wWjmcVkuFcD9Hm+rwm2hIpLJnqHkDE/nRYO7yWjGr2m6cQf4qemQjNkNoD78fOch8vi67CaTueWFZ3PbTrcnGE3e0ys0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618786300; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=eApDsHd46Y+IQH1RVKAdhqg7h/PQQ2n3i/53YZQWS2A=; b=Rz45qirDjNGEaITYtTIMq7prPpEItNkaRQUnlRWcz3A6kDsX5I5IHYomy3GfkKmwi6h9+zu+mOqqOt+VQzOBoyv9WlFXYiPM/t5GI0G3V3fvcwSzOy741o1lWe0b+0b6hQ4oELGEOPrIdrIpOJ/Tb3G+gyAaw5GnWA1WxBWCUgc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.42 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) by mx.zohomail.com with SMTPS id 1618786300668164.52253245424117; Sun, 18 Apr 2021 15:51:40 -0700 (PDT) Received: by mail-wm1-f42.google.com with SMTP id y124-20020a1c32820000b029010c93864955so19479585wmy.5 for ; Sun, 18 Apr 2021 15:51:40 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id g1sm11974234wrd.69.2021.04.18.15.51.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Apr 2021 15:51:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=eApDsHd46Y+IQH1RVKAdhqg7h/PQQ2n3i/53YZQWS2A=; b=vf9RnpevS5eCvIeEyNHERCcax112QSw8ql2UJoWQFyeGdp+TOjrGtzcVPzGvWXU8VG gNnP3CZLN+w3LggnxFn70kL/7otB39I0uPG7393FoCeJI7Cwk06G1a6N13tq40jEPWiK lEAXLwCCw01JmN8S6zPvZLf88mm3SZ4vAyedQu/C2Sw5aT29m2xe1Qgphnn7OSGHCiHf b0c52gyxXI4OZ0bB7e+rW5HzvT7yeEZCPprlARP/opbOUfmWWsbRuXhEnQvqwb4P+NQe Y26OKtgCJQDxUMBDopjVgqmeAHU18v9WeOtYh/epEclis+ioK10OlbG6cI9FC24+3961 7oGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=eApDsHd46Y+IQH1RVKAdhqg7h/PQQ2n3i/53YZQWS2A=; b=B/N/SbeCjnWNr1xH91PIqWinZxs1tD62wrpkf3JXqQLrBT22Ph8Iv6JRbDCJDBF7Zu 3l0iav9NUgKmSA/KZSnGYhHk0WChaPDSYOTWwaAT57Zmy7H7ftHkRGQdLeUFrn1tADmL /d54FteoAg7BFgTHY6rCJTeM+/u0VmFXXVA8q5hsQhmNmUaZxriaD6L/dLXqP5DTZBc9 Dc8oA8jXkBRpWHro/gORRqWEPfht16lPf8bWkT9ft4vvcu5Ysa7lb7MnQbN9/80ixMeD e9XE6fvnnYS12kQ/89ZXUOAFXVRTwiJatynbCFoX6yqD1k2fKl6QFjdxrk57CYYez4br FVzg== X-Gm-Message-State: AOAM532hnpewxMgbD+al9OUMMe8KvWvTn4Zr40Hj21rvP1oR4Q4Wcx6v 7MNiGtnf79h1mOvvpB9LkCs= X-Google-Smtp-Source: ABdhPJxc3gpTfccsrhccs0SFJ+us3BRh4TD5MfNQq4sX84yzYhNgNK00eWhbgvIb8F+RPXtpN2fPWQ== X-Received: by 2002:a1c:e309:: with SMTP id a9mr18296700wmh.63.1618786298949; Sun, 18 Apr 2021 15:51:38 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen , Jiaxun Yang , Aleksandar Rikalo Subject: [PATCH v2 08/29] target/mips: Declare mips_cpu_set_error_pc() inlined in "internal.h" Date: Mon, 19 Apr 2021 00:50:37 +0200 Message-Id: <20210418225058.1257014-9-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210418225058.1257014-1-f4bug@amsat.org> References: <20210418225058.1257014-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Rename set_pc() as mips_cpu_set_error_pc(), declare it inlined and use it in cpu.c and op_helper.c. Reported-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/internal.h | 11 +++++++++++ target/mips/cpu.c | 8 +------- target/mips/op_helper.c | 16 +++------------- 3 files changed, 15 insertions(+), 20 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 57072a941e7..81671d567d0 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -219,6 +219,17 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, /* op_helper.c */ void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagema= sk); =20 +static inline void mips_cpu_set_error_pc(CPUMIPSState *env, + target_ulong error_pc) +{ + env->active_tc.PC =3D error_pc & ~(target_ulong)1; + if (error_pc & 1) { + env->hflags |=3D MIPS_HFLAG_M16; + } else { + env->hflags &=3D ~(MIPS_HFLAG_M16); + } +} + static inline void restore_pamask(CPUMIPSState *env) { if (env->hflags & MIPS_HFLAG_ELPA) { diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 90ae232c8b8..fcbf95c85b9 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -327,14 +327,8 @@ void QEMU_NORETURN do_raise_exception_err(CPUMIPSState= *env, static void mips_cpu_set_pc(CPUState *cs, vaddr value) { MIPSCPU *cpu =3D MIPS_CPU(cs); - CPUMIPSState *env =3D &cpu->env; =20 - env->active_tc.PC =3D value & ~(target_ulong)1; - if (value & 1) { - env->hflags |=3D MIPS_HFLAG_M16; - } else { - env->hflags &=3D ~(MIPS_HFLAG_M16); - } + mips_cpu_set_error_pc(&cpu->env, value); } =20 #ifdef CONFIG_TCG diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index b80e8f75401..f7da8c83aee 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -993,24 +993,14 @@ static void debug_post_eret(CPUMIPSState *env) } } =20 -static void set_pc(CPUMIPSState *env, target_ulong error_pc) -{ - env->active_tc.PC =3D error_pc & ~(target_ulong)1; - if (error_pc & 1) { - env->hflags |=3D MIPS_HFLAG_M16; - } else { - env->hflags &=3D ~(MIPS_HFLAG_M16); - } -} - static inline void exception_return(CPUMIPSState *env) { debug_pre_eret(env); if (env->CP0_Status & (1 << CP0St_ERL)) { - set_pc(env, env->CP0_ErrorEPC); + mips_cpu_set_error_pc(env, env->CP0_ErrorEPC); env->CP0_Status &=3D ~(1 << CP0St_ERL); } else { - set_pc(env, env->CP0_EPC); + mips_cpu_set_error_pc(env, env->CP0_EPC); env->CP0_Status &=3D ~(1 << CP0St_EXL); } compute_hflags(env); @@ -1036,7 +1026,7 @@ void helper_deret(CPUMIPSState *env) env->hflags &=3D ~MIPS_HFLAG_DM; compute_hflags(env); =20 - set_pc(env, env->CP0_DEPC); + mips_cpu_set_error_pc(env, env->CP0_DEPC); =20 debug_post_eret(env); } --=20 2.26.3 From nobody Mon Feb 9 10:44:55 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.54 as permitted sender) client-ip=209.85.128.54; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f54.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.54 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1618786305; cv=none; d=zohomail.com; s=zohoarc; b=CBIJmsviEt4+WQ1MbVYo8/qXiLL+rTyL6qYXJeObLpbQmD2Jd7XygUCH+63CZtZAL/v+dp6NyvvTHlrQjP2NwQopEZElqMTk/zt0C156SlGUkDCkx2Up1ndkzgvNjywOrMrWgrtEMfHEMvYyrmJMonaxV6/4WQSucHQZ/rBRxf4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618786305; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=CDlJGgkanCp3pGkR4GJUQnLJyGVV/Q5nrIpN5KpjiX8=; b=kxPMHYU5uJo5KFdQtuVdDyYky2ikZ20q3GtCz/PJpaIOuHx0xem5dMbozGyy2ZIc8kv86sHBgQAwX9+43ED0I4zk6SG6xFEinKEMGJ+VJzsEBYm6AMbKaLvUJt/sabegc5W0KPB/S01h1SkGM70lytYfibvaytn9UcCDHGLHJkk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.54 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) by mx.zohomail.com with SMTPS id 1618786305837889.7762753980853; Sun, 18 Apr 2021 15:51:45 -0700 (PDT) Received: by mail-wm1-f54.google.com with SMTP id d200-20020a1c1dd10000b02901384767d4a5so997409wmd.3 for ; Sun, 18 Apr 2021 15:51:44 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id o1sm21014649wrw.95.2021.04.18.15.51.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Apr 2021 15:51:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CDlJGgkanCp3pGkR4GJUQnLJyGVV/Q5nrIpN5KpjiX8=; b=hULS8EjPOiHQ70/5EIZFdsmj0srygOO1eI/f4DOjr1U84CYFfsMZ7kQOMosZTHN+VV oq2EOZRx3wp3mUS870y5gfIB3JlC9pkJChFlNXHiAlHePHsaBe8iKWYOn8d9IRMrpxIr r/Vss46aqsKIO2GEjirpEOT6x0NB5BxdwD7g1JNgv3BVmdYLqz85CD1LYupMOcMiwXfl cNLb3Rj2ImqOWBXSjYoZJZt1DuukypldnBQItf5FSp7spScj3BsHUBuKDYavrjg07hQi mrCHVZM/zs8ASbtm1PUjQ6ZXKaRBYpMvv+rfkQOvynh0EsCN/TU4RCb8JPFnN0IfQKMk EwUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=CDlJGgkanCp3pGkR4GJUQnLJyGVV/Q5nrIpN5KpjiX8=; b=faVMlhIoCBYNikFcxCudUlq7FHPR5PS2QsRdpz2EcuqYdLij/PbyNSJBntEJCsBIOb FRrVGx1sLSG7+mgO+mhhVeQ2aaa4C/moa43WyaZ/1frnnCPS+5u7auTlHYqhDEfu6EQ3 GD6jzZJfqtcPSem0V8m1Kr3Of/oDPTPYh0fytXjSYVAV0SOC8SzV1pI+JaDpRpExpsgD iti3tyeVhyd+BFGi0ByDNpddiqhP+JH2w8z256NvLu9dtDlqywua+1tUQbRph8D5+tnh aIaogyGDETHvVWvAUQ60rOuBcbIITMu0eoL+jS19uh2hJkop1TA8GZqMi3epSoIKS3WG iFhQ== X-Gm-Message-State: AOAM530H+Inb3QmLUTe5HNHYwuuxLOtSlFw3H8v9wIKQw07CbrfLzHXQ Vi6+mt7rbICKEGzecc0s5f0= X-Google-Smtp-Source: ABdhPJzBxtvoj1IGX3bQkcqRcvmqTk6b1TV7KirdcnUwQMMPg5LsM+86IyMfZmdR81cOEoL4W6fWvA== X-Received: by 2002:a7b:cc86:: with SMTP id p6mr18607528wma.164.1618786303659; Sun, 18 Apr 2021 15:51:43 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen , Jiaxun Yang , Aleksandar Rikalo Subject: [PATCH v2 09/29] target/mips: Extract load/store helpers to ldst_helper.c Date: Mon, 19 Apr 2021 00:50:38 +0200 Message-Id: <20210418225058.1257014-10-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210418225058.1257014-1-f4bug@amsat.org> References: <20210418225058.1257014-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/ldst_helper.c | 304 ++++++++++++++++++++++++++++++++++++++ target/mips/op_helper.c | 274 ---------------------------------- target/mips/meson.build | 1 + 3 files changed, 305 insertions(+), 274 deletions(-) create mode 100644 target/mips/ldst_helper.c diff --git a/target/mips/ldst_helper.c b/target/mips/ldst_helper.c new file mode 100644 index 00000000000..3fbcc3509ab --- /dev/null +++ b/target/mips/ldst_helper.c @@ -0,0 +1,304 @@ +/* + * MIPS emulation load/store helpers for QEMU. + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * + * SPDX-License-Identifier: LGPL-2.1-or-later + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + * + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "exec/helper-proto.h" +#include "exec/exec-all.h" +#include "exec/memop.h" +#include "internal.h" + +#ifndef CONFIG_USER_ONLY + +static inline hwaddr do_translate_address(CPUMIPSState *env, + target_ulong address, + MMUAccessType access_type, + uintptr_t retaddr) +{ + hwaddr paddr; + CPUState *cs =3D env_cpu(env); + + paddr =3D cpu_mips_translate_address(env, address, access_type); + + if (paddr =3D=3D -1LL) { + cpu_loop_exit_restore(cs, retaddr); + } else { + return paddr; + } +} + +#define HELPER_LD_ATOMIC(name, insn, almask, do_cast) = \ +target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_id= x) \ +{ = \ + if (arg & almask) { = \ + if (!(env->hflags & MIPS_HFLAG_DM)) { = \ + env->CP0_BadVAddr =3D arg; = \ + } = \ + do_raise_exception(env, EXCP_AdEL, GETPC()); = \ + } = \ + env->CP0_LLAddr =3D do_translate_address(env, arg, MMU_DATA_LOAD, GETP= C()); \ + env->lladdr =3D arg; = \ + env->llval =3D do_cast cpu_##insn##_mmuidx_ra(env, arg, mem_idx, GETPC= ()); \ + return env->llval; = \ +} +HELPER_LD_ATOMIC(ll, ldl, 0x3, (target_long)(int32_t)) +#ifdef TARGET_MIPS64 +HELPER_LD_ATOMIC(lld, ldq, 0x7, (target_ulong)) +#endif +#undef HELPER_LD_ATOMIC + +#endif /* !CONFIG_USER_ONLY */ + +#ifdef TARGET_WORDS_BIGENDIAN +#define GET_LMASK(v) ((v) & 3) +#define GET_OFFSET(addr, offset) (addr + (offset)) +#else +#define GET_LMASK(v) (((v) & 3) ^ 3) +#define GET_OFFSET(addr, offset) (addr - (offset)) +#endif + +void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, + int mem_idx) +{ + cpu_stb_mmuidx_ra(env, arg2, (uint8_t)(arg1 >> 24), mem_idx, GETPC()); + + if (GET_LMASK(arg2) <=3D 2) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), + mem_idx, GETPC()); + } + + if (GET_LMASK(arg2) <=3D 1) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), + mem_idx, GETPC()); + } + + if (GET_LMASK(arg2) =3D=3D 0) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, + mem_idx, GETPC()); + } +} + +void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, + int mem_idx) +{ + cpu_stb_mmuidx_ra(env, arg2, (uint8_t)arg1, mem_idx, GETPC()); + + if (GET_LMASK(arg2) >=3D 1) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), + mem_idx, GETPC()); + } + + if (GET_LMASK(arg2) >=3D 2) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), + mem_idx, GETPC()); + } + + if (GET_LMASK(arg2) =3D=3D 3) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), + mem_idx, GETPC()); + } +} + +#if defined(TARGET_MIPS64) +/* + * "half" load and stores. We must do the memory access inline, + * or fault handling won't work. + */ +#ifdef TARGET_WORDS_BIGENDIAN +#define GET_LMASK64(v) ((v) & 7) +#else +#define GET_LMASK64(v) (((v) & 7) ^ 7) +#endif + +void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, + int mem_idx) +{ + cpu_stb_mmuidx_ra(env, arg2, (uint8_t)(arg1 >> 56), mem_idx, GETPC()); + + if (GET_LMASK64(arg2) <=3D 6) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), + mem_idx, GETPC()); + } + + if (GET_LMASK64(arg2) <=3D 5) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), + mem_idx, GETPC()); + } + + if (GET_LMASK64(arg2) <=3D 4) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), + mem_idx, GETPC()); + } + + if (GET_LMASK64(arg2) <=3D 3) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), + mem_idx, GETPC()); + } + + if (GET_LMASK64(arg2) <=3D 2) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), + mem_idx, GETPC()); + } + + if (GET_LMASK64(arg2) <=3D 1) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), + mem_idx, GETPC()); + } + + if (GET_LMASK64(arg2) <=3D 0) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, + mem_idx, GETPC()); + } +} + +void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, + int mem_idx) +{ + cpu_stb_mmuidx_ra(env, arg2, (uint8_t)arg1, mem_idx, GETPC()); + + if (GET_LMASK64(arg2) >=3D 1) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), + mem_idx, GETPC()); + } + + if (GET_LMASK64(arg2) >=3D 2) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), + mem_idx, GETPC()); + } + + if (GET_LMASK64(arg2) >=3D 3) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), + mem_idx, GETPC()); + } + + if (GET_LMASK64(arg2) >=3D 4) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), + mem_idx, GETPC()); + } + + if (GET_LMASK64(arg2) >=3D 5) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), + mem_idx, GETPC()); + } + + if (GET_LMASK64(arg2) >=3D 6) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), + mem_idx, GETPC()); + } + + if (GET_LMASK64(arg2) =3D=3D 7) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), + mem_idx, GETPC()); + } +} +#endif /* TARGET_MIPS64 */ + +static const int multiple_regs[] =3D { 16, 17, 18, 19, 20, 21, 22, 23, 30 = }; + +void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, + uint32_t mem_idx) +{ + target_ulong base_reglist =3D reglist & 0xf; + target_ulong do_r31 =3D reglist & 0x10; + + if (base_reglist > 0 && base_reglist <=3D ARRAY_SIZE(multiple_regs)) { + target_ulong i; + + for (i =3D 0; i < base_reglist; i++) { + env->active_tc.gpr[multiple_regs[i]] =3D + (target_long)cpu_ldl_mmuidx_ra(env, addr, mem_idx, GETPC()= ); + addr +=3D 4; + } + } + + if (do_r31) { + env->active_tc.gpr[31] =3D + (target_long)cpu_ldl_mmuidx_ra(env, addr, mem_idx, GETPC()); + } +} + +void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, + uint32_t mem_idx) +{ + target_ulong base_reglist =3D reglist & 0xf; + target_ulong do_r31 =3D reglist & 0x10; + + if (base_reglist > 0 && base_reglist <=3D ARRAY_SIZE(multiple_regs)) { + target_ulong i; + + for (i =3D 0; i < base_reglist; i++) { + cpu_stw_mmuidx_ra(env, addr, env->active_tc.gpr[multiple_regs[= i]], + mem_idx, GETPC()); + addr +=3D 4; + } + } + + if (do_r31) { + cpu_stw_mmuidx_ra(env, addr, env->active_tc.gpr[31], mem_idx, GETP= C()); + } +} + +#if defined(TARGET_MIPS64) +void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, + uint32_t mem_idx) +{ + target_ulong base_reglist =3D reglist & 0xf; + target_ulong do_r31 =3D reglist & 0x10; + + if (base_reglist > 0 && base_reglist <=3D ARRAY_SIZE(multiple_regs)) { + target_ulong i; + + for (i =3D 0; i < base_reglist; i++) { + env->active_tc.gpr[multiple_regs[i]] =3D + cpu_ldq_mmuidx_ra(env, addr, mem_idx, GETPC()); + addr +=3D 8; + } + } + + if (do_r31) { + env->active_tc.gpr[31] =3D + cpu_ldq_mmuidx_ra(env, addr, mem_idx, GETPC()); + } +} + +void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, + uint32_t mem_idx) +{ + target_ulong base_reglist =3D reglist & 0xf; + target_ulong do_r31 =3D reglist & 0x10; + + if (base_reglist > 0 && base_reglist <=3D ARRAY_SIZE(multiple_regs)) { + target_ulong i; + + for (i =3D 0; i < base_reglist; i++) { + cpu_stq_mmuidx_ra(env, addr, env->active_tc.gpr[multiple_regs[= i]], + mem_idx, GETPC()); + addr +=3D 8; + } + } + + if (do_r31) { + cpu_stq_mmuidx_ra(env, addr, env->active_tc.gpr[31], mem_idx, GETP= C()); + } +} + +#endif /* TARGET_MIPS64 */ diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index f7da8c83aee..9b6f570c897 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -285,280 +285,6 @@ target_ulong helper_rotx(target_ulong rs, uint32_t sh= ift, uint32_t shiftx, return (int64_t)(int32_t)(uint32_t)tmp5; } =20 -#ifndef CONFIG_USER_ONLY - -static inline hwaddr do_translate_address(CPUMIPSState *env, - target_ulong address, - MMUAccessType access_type, - uintptr_t retaddr) -{ - hwaddr paddr; - CPUState *cs =3D env_cpu(env); - - paddr =3D cpu_mips_translate_address(env, address, access_type); - - if (paddr =3D=3D -1LL) { - cpu_loop_exit_restore(cs, retaddr); - } else { - return paddr; - } -} - -#define HELPER_LD_ATOMIC(name, insn, almask, do_cast) = \ -target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_id= x) \ -{ = \ - if (arg & almask) { = \ - if (!(env->hflags & MIPS_HFLAG_DM)) { = \ - env->CP0_BadVAddr =3D arg; = \ - } = \ - do_raise_exception(env, EXCP_AdEL, GETPC()); = \ - } = \ - env->CP0_LLAddr =3D do_translate_address(env, arg, MMU_DATA_LOAD, GETP= C()); \ - env->lladdr =3D arg; = \ - env->llval =3D do_cast cpu_##insn##_mmuidx_ra(env, arg, mem_idx, GETPC= ()); \ - return env->llval; = \ -} -HELPER_LD_ATOMIC(ll, ldl, 0x3, (target_long)(int32_t)) -#ifdef TARGET_MIPS64 -HELPER_LD_ATOMIC(lld, ldq, 0x7, (target_ulong)) -#endif -#undef HELPER_LD_ATOMIC -#endif - -#ifdef TARGET_WORDS_BIGENDIAN -#define GET_LMASK(v) ((v) & 3) -#define GET_OFFSET(addr, offset) (addr + (offset)) -#else -#define GET_LMASK(v) (((v) & 3) ^ 3) -#define GET_OFFSET(addr, offset) (addr - (offset)) -#endif - -void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, - int mem_idx) -{ - cpu_stb_mmuidx_ra(env, arg2, (uint8_t)(arg1 >> 24), mem_idx, GETPC()); - - if (GET_LMASK(arg2) <=3D 2) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), - mem_idx, GETPC()); - } - - if (GET_LMASK(arg2) <=3D 1) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), - mem_idx, GETPC()); - } - - if (GET_LMASK(arg2) =3D=3D 0) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, - mem_idx, GETPC()); - } -} - -void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, - int mem_idx) -{ - cpu_stb_mmuidx_ra(env, arg2, (uint8_t)arg1, mem_idx, GETPC()); - - if (GET_LMASK(arg2) >=3D 1) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), - mem_idx, GETPC()); - } - - if (GET_LMASK(arg2) >=3D 2) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), - mem_idx, GETPC()); - } - - if (GET_LMASK(arg2) =3D=3D 3) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), - mem_idx, GETPC()); - } -} - -#if defined(TARGET_MIPS64) -/* - * "half" load and stores. We must do the memory access inline, - * or fault handling won't work. - */ -#ifdef TARGET_WORDS_BIGENDIAN -#define GET_LMASK64(v) ((v) & 7) -#else -#define GET_LMASK64(v) (((v) & 7) ^ 7) -#endif - -void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, - int mem_idx) -{ - cpu_stb_mmuidx_ra(env, arg2, (uint8_t)(arg1 >> 56), mem_idx, GETPC()); - - if (GET_LMASK64(arg2) <=3D 6) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), - mem_idx, GETPC()); - } - - if (GET_LMASK64(arg2) <=3D 5) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), - mem_idx, GETPC()); - } - - if (GET_LMASK64(arg2) <=3D 4) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), - mem_idx, GETPC()); - } - - if (GET_LMASK64(arg2) <=3D 3) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), - mem_idx, GETPC()); - } - - if (GET_LMASK64(arg2) <=3D 2) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), - mem_idx, GETPC()); - } - - if (GET_LMASK64(arg2) <=3D 1) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), - mem_idx, GETPC()); - } - - if (GET_LMASK64(arg2) <=3D 0) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, - mem_idx, GETPC()); - } -} - -void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, - int mem_idx) -{ - cpu_stb_mmuidx_ra(env, arg2, (uint8_t)arg1, mem_idx, GETPC()); - - if (GET_LMASK64(arg2) >=3D 1) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), - mem_idx, GETPC()); - } - - if (GET_LMASK64(arg2) >=3D 2) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), - mem_idx, GETPC()); - } - - if (GET_LMASK64(arg2) >=3D 3) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), - mem_idx, GETPC()); - } - - if (GET_LMASK64(arg2) >=3D 4) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), - mem_idx, GETPC()); - } - - if (GET_LMASK64(arg2) >=3D 5) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), - mem_idx, GETPC()); - } - - if (GET_LMASK64(arg2) >=3D 6) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), - mem_idx, GETPC()); - } - - if (GET_LMASK64(arg2) =3D=3D 7) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), - mem_idx, GETPC()); - } -} -#endif /* TARGET_MIPS64 */ - -static const int multiple_regs[] =3D { 16, 17, 18, 19, 20, 21, 22, 23, 30 = }; - -void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, - uint32_t mem_idx) -{ - target_ulong base_reglist =3D reglist & 0xf; - target_ulong do_r31 =3D reglist & 0x10; - - if (base_reglist > 0 && base_reglist <=3D ARRAY_SIZE(multiple_regs)) { - target_ulong i; - - for (i =3D 0; i < base_reglist; i++) { - env->active_tc.gpr[multiple_regs[i]] =3D - (target_long)cpu_ldl_mmuidx_ra(env, addr, mem_idx, GETPC()= ); - addr +=3D 4; - } - } - - if (do_r31) { - env->active_tc.gpr[31] =3D - (target_long)cpu_ldl_mmuidx_ra(env, addr, mem_idx, GETPC()); - } -} - -void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, - uint32_t mem_idx) -{ - target_ulong base_reglist =3D reglist & 0xf; - target_ulong do_r31 =3D reglist & 0x10; - - if (base_reglist > 0 && base_reglist <=3D ARRAY_SIZE(multiple_regs)) { - target_ulong i; - - for (i =3D 0; i < base_reglist; i++) { - cpu_stw_mmuidx_ra(env, addr, env->active_tc.gpr[multiple_regs[= i]], - mem_idx, GETPC()); - addr +=3D 4; - } - } - - if (do_r31) { - cpu_stw_mmuidx_ra(env, addr, env->active_tc.gpr[31], mem_idx, GETP= C()); - } -} - -#if defined(TARGET_MIPS64) -void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, - uint32_t mem_idx) -{ - target_ulong base_reglist =3D reglist & 0xf; - target_ulong do_r31 =3D reglist & 0x10; - - if (base_reglist > 0 && base_reglist <=3D ARRAY_SIZE(multiple_regs)) { - target_ulong i; - - for (i =3D 0; i < base_reglist; i++) { - env->active_tc.gpr[multiple_regs[i]] =3D - cpu_ldq_mmuidx_ra(env, addr, mem_idx, GETPC()); - addr +=3D 8; - } - } - - if (do_r31) { - env->active_tc.gpr[31] =3D - cpu_ldq_mmuidx_ra(env, addr, mem_idx, GETPC()); - } -} - -void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, - uint32_t mem_idx) -{ - target_ulong base_reglist =3D reglist & 0xf; - target_ulong do_r31 =3D reglist & 0x10; - - if (base_reglist > 0 && base_reglist <=3D ARRAY_SIZE(multiple_regs)) { - target_ulong i; - - for (i =3D 0; i < base_reglist; i++) { - cpu_stq_mmuidx_ra(env, addr, env->active_tc.gpr[multiple_regs[= i]], - mem_idx, GETPC()); - addr +=3D 8; - } - } - - if (do_r31) { - cpu_stq_mmuidx_ra(env, addr, env->active_tc.gpr[31], mem_idx, GETP= C()); - } -} -#endif - =20 void helper_fork(target_ulong arg1, target_ulong arg2) { diff --git a/target/mips/meson.build b/target/mips/meson.build index daf5f1d55bc..15c2f835c68 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -18,6 +18,7 @@ mips_tcg_ss.add(files( 'dsp_helper.c', 'fpu_helper.c', + 'ldst_helper.c', 'lmmi_helper.c', 'msa_helper.c', 'msa_translate.c', --=20 2.26.3 From nobody Mon Feb 9 10:44:55 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.52 as permitted sender) client-ip=209.85.128.52; envelope-from=philippe.mathieu.daude@gmail.com; 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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id u6sm19127327wml.23.2021.04.18.15.51.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Apr 2021 15:51:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cJdBKLIJjo1FmzN1QJg7i4Ge0av2J5mMxKO6UU2xPVo=; b=oLru24v/zcZWzUaNRH1jCGVsMjsheo/erIlq+h/g0NMuvdm4JbgxexJMzOxBboW5kc MI+u4m3l9CCsDiy0/boI3SLc67qzl82pR1zdT7YM/hwzt4GA0H40ez5Q9E8QklwrqEL5 BJdjpJtWRz8Uv70lLkCVZdplG54IBfyyrV8zFyuKQU6zujlsnR9ng1fHKCLNI3TMMHht hd0KRgtMg8IuK6G0anYRGNxW1bJ75XiM/E0MnupehQby4v9jH0eebqEDHsvSBgIPDJeW NmONNKJSXOKA1n6GWTy3oVV4vRp+0ts73RHVcZK2ot9N2NH0iFFbV8Y/Lcl9htB4YNx5 IW7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=cJdBKLIJjo1FmzN1QJg7i4Ge0av2J5mMxKO6UU2xPVo=; b=TdjMcVGLCKBNpFPlAskjxUvfehFuu2FoU3/J6NKW+2uuEgi+CK+tsGFg8+YvxOl+OV 8JocRHtb6NrfeQM3pkw+3BIzTgoCN3QfUghz+gHokRHKPeMfBkgygcHNd7TQ6nkogTSI qdpCQZmTe2yn/49W9zTiw55Aahaz4r5ujciHCh2Uz2vSrIUf23qtcytquWDFk1o6yrKl jMyIWzcLy5+2ykGdUxwyIzKp0G+cxsevgN1KDde3qM6jBpis5PRw9BKy1DJpVarPpXnL wPbP8gu5fM3uQLSnekC9lz+EiMUtFOU2Ud290MAwdJxcR+Nl20K8n+IQXvBH1u9FSRtt 86RQ== X-Gm-Message-State: AOAM5318LqnKS0aTMuTsJSgpLAXgaWZi19KuWI/xH9aX2Wat5XfZZMeD CMTXtmKPZvpnvJJgQPJpfBQ= X-Google-Smtp-Source: ABdhPJxZw8CHQt0JuPprvDTIQus1iPDp13zHWwYjySmSpmEySKmc5fteRKbBr6Np7dGG5G2NDpzCWw== X-Received: by 2002:a1c:23d0:: with SMTP id j199mr18698947wmj.74.1618786308414; Sun, 18 Apr 2021 15:51:48 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen , Jiaxun Yang , Aleksandar Rikalo , Paolo Bonzini Subject: [PATCH v2 10/29] meson: Introduce meson_user_arch source set for arch-specific user-mode Date: Mon, 19 Apr 2021 00:50:39 +0200 Message-Id: <20210418225058.1257014-11-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210418225058.1257014-1-f4bug@amsat.org> References: <20210418225058.1257014-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Similarly to the 'target_softmmu_arch' source set which allows to restrict target-specific sources to system emulation, add the equivalent 'target_user_arch' set for user emulation. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- v2: meson_user_arch -> target_user_arch in description (rth) Cc: Paolo Bonzini --- meson.build | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/meson.build b/meson.build index d8bb1ec5aa9..1ffdc9e6c4e 100644 --- a/meson.build +++ b/meson.build @@ -1751,6 +1751,7 @@ hw_arch =3D {} target_arch =3D {} target_softmmu_arch =3D {} +target_user_arch =3D {} =20 ############### # Trace files # @@ -2168,6 +2169,11 @@ abi =3D config_target['TARGET_ABI_DIR'] target_type=3D'user' qemu_target_name =3D 'qemu-' + target_name + if arch in target_user_arch + t =3D target_user_arch[arch].apply(config_target, strict: false) + arch_srcs +=3D t.sources() + arch_deps +=3D t.dependencies() + endif if 'CONFIG_LINUX_USER' in config_target base_dir =3D 'linux-user' target_inc +=3D include_directories('linux-user/host/' / config_host= ['ARCH']) --=20 2.26.3 From nobody Mon Feb 9 10:44:55 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.51 as permitted sender) client-ip=209.85.221.51; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f51.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.51 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1618786314; cv=none; d=zohomail.com; s=zohoarc; b=Lsw5JMzVV6jMuf6/fDWx++8M9Pi1KDDFDJ9cZ0xCIN+0iP8AcrBipo7GyRhQBYmrrSwBaLSEb+nUZqYKzkoaazOlmXO5qLzgcGC/y2twxcGXKQtqvHJ4GXlEGmW1Oz9OQ42pPyvVrr0DTpPiFTjB3Tn7y+2OZxYYF0KgCjRjDKk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618786314; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=aKAXT5WXCLfQhQzehi2fhE4zxpaOOl0wCkh4/8PNfro=; b=VyAluoGuoYHsc3zdDQkiWfwlkV29/eD0kt81EFndIEj3G6tmdT3ff976boLH6SABNiPh2X079JCGanwmrM21v/qZ5F/D/WU8pJTko+Yy3vwybGi5YPXNQbgRfJcT+MrkGZ1RZe7hS062sODZNCGo+yf4/7ld0pFzreiFZQmpriY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.51 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f51.google.com (mail-wr1-f51.google.com [209.85.221.51]) by mx.zohomail.com with SMTPS id 1618786314903657.0645608025808; Sun, 18 Apr 2021 15:51:54 -0700 (PDT) Received: by mail-wr1-f51.google.com with SMTP id s7so31941720wru.6 for ; Sun, 18 Apr 2021 15:51:54 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id d10sm6914472wri.41.2021.04.18.15.51.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Apr 2021 15:51:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=aKAXT5WXCLfQhQzehi2fhE4zxpaOOl0wCkh4/8PNfro=; b=faqXsieM1n8o+pfoKdPBxi5uu4eaXqnzTirrSPJUjh2mvy3OTe03iI3CIdEqfLzp7t 4lm6Xg0oMACaRYkkq2A6BleknTtcR3RS3ZYad+QS0EEcFtcmRFnv6G0Qbbp2aEaGSBSX /YZ32rZOS7mX3N/p5G2B8ViVaC8Uvmb86iUyu2ZijZAm/HOQXvKlGd5DqWOQY4S3k629 a6ysN472Nf7awGTyrbtBaBNgoxB6xrc/VYhnpcSirQy2SB96gg5A83dNux23WngDzyPE hABIZFYDIztNzD4cLgvXpEgq7bJaLeswWIqKXRGTJq8RvmOW+r4/YAfqeI8KgAnuK9rC eRQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=aKAXT5WXCLfQhQzehi2fhE4zxpaOOl0wCkh4/8PNfro=; b=MOc+VGkoOpGkp6uYFMtZJFJ8G0cnYJFdUzRvX1QK9gtKAl8weZn+s8C117vHjAAykD h6GOtEtAXxYilgwAMyNjisbdzYe/T0sz2WKqpY33kSROUiQNBAKkl8nqMqvoj8zQzAll djStFLjvaeej6DVVXV7UNCWhtB8/DMKfH5wYjhJZp3VGRlkiJ/TG6eRnyqpp2yC1tFbs kZgorNM1H4to6WxodC1cjhfpDB3c05tlqhiRkf4aKTOmEs9+yUGMd6PSJSHcCaYjzqVn +Jp+gl0YkKt4Tu3iiSZEAvFPi8qaWguc3HzHwqptFbL84nIuaPTtaEFWo4uDoyAvFA9n i86A== X-Gm-Message-State: AOAM5314N9Bd/TVMh9SZEL7gLBahjgcNh0qpjtwGRavp+eb0aKuzAoIG 4PGFyVY5WpGYbjccm8cZbqY= X-Google-Smtp-Source: ABdhPJwm5n7ej8XFdeMYgFsyPmKvAT2zTXB8W5vkqsmIRAwRrop/FXJ/5kcNZVFAq6zAljc/DtsUeA== X-Received: by 2002:a05:6000:d0:: with SMTP id q16mr11179666wrx.335.1618786313226; Sun, 18 Apr 2021 15:51:53 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen , Jiaxun Yang , Aleksandar Rikalo Subject: [PATCH v2 11/29] target/mips: Introduce tcg-internal.h for TCG specific declarations Date: Mon, 19 Apr 2021 00:50:40 +0200 Message-Id: <20210418225058.1257014-12-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210418225058.1257014-1-f4bug@amsat.org> References: <20210418225058.1257014-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) We will gradually move TCG-specific declarations to a new local header: "tcg-internal.h". To keep review simple, first add this header with 2 TCG prototypes, which we are going to move in the next 2 commits. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/internal.h | 7 +++---- target/mips/tcg/tcg-internal.h | 20 ++++++++++++++++++++ 2 files changed, 23 insertions(+), 4 deletions(-) create mode 100644 target/mips/tcg/tcg-internal.h diff --git a/target/mips/internal.h b/target/mips/internal.h index 81671d567d0..284ef8d1e1a 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -9,6 +9,9 @@ #define MIPS_INTERNAL_H =20 #include "exec/memattrs.h" +#ifdef CONFIG_TCG +#include "tcg/tcg-internal.h" +#endif =20 /* * MMU types, the first four entries have the same layout as the @@ -77,7 +80,6 @@ extern const char fregnames[32][4]; extern const struct mips_def_t mips_defs[]; extern const int mips_defs_number; =20 -void mips_cpu_do_interrupt(CPUState *cpu); bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); @@ -212,9 +214,6 @@ void cpu_mips_stop_count(CPUMIPSState *env); =20 /* helper.c */ void mmu_init(CPUMIPSState *env, const mips_def_t *def); -bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); =20 /* op_helper.c */ void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagema= sk); diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h new file mode 100644 index 00000000000..24438667f47 --- /dev/null +++ b/target/mips/tcg/tcg-internal.h @@ -0,0 +1,20 @@ +/* + * MIPS internal definitions and helpers (TCG accelerator) + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef MIPS_TCG_INTERNAL_H +#define MIPS_TCG_INTERNAL_H + +#include "hw/core/cpu.h" + +void mips_cpu_do_interrupt(CPUState *cpu); +bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); + +#endif --=20 2.26.3 From nobody Mon Feb 9 10:44:55 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.52 as permitted sender) client-ip=209.85.128.52; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f52.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.52 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1618786319; cv=none; d=zohomail.com; s=zohoarc; b=CoVIX+nBb+/kmkSe5qZcCJNTAy14mPZFIkbgurslvO/WszrCfeVySOKTPmcy8Y6MWZ1KRg1s4afalmUbLNjBp7qvS1wtZ2FyyLR4RtpdPHdtW8Skvo5qvDj8M8AYzPcvOx8R7UsV0Gk8hgSUUlKmq79maQgbF4uXsUl7llBqT+Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618786319; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=zDauNKvsnr925xHMPAyQPYL2wWfv0cJQoAYwcXW7WSA=; b=a/LCvjaNc+Vd7NMQgTKl/JsdoHcXMs4Nn0gm+kTu5+pLm8lVKKN927+jByGZNhQUx6PYyCYyR/ZxYZiHNJS0e6I9P9V5eVbiB5uiBw3ySwl26BSd1sU0ZJlKZu8UnvTDvM3Yp1DH9/JvEPHhlCqUia11aelhjOXoFtfWSReSyyk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.52 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) by mx.zohomail.com with SMTPS id 1618786319567652.1083559098137; Sun, 18 Apr 2021 15:51:59 -0700 (PDT) Received: by mail-wm1-f52.google.com with SMTP id k4-20020a7bc4040000b02901331d89fb83so4942718wmi.5 for ; Sun, 18 Apr 2021 15:51:59 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id b187sm17334211wmh.17.2021.04.18.15.51.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Apr 2021 15:51:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zDauNKvsnr925xHMPAyQPYL2wWfv0cJQoAYwcXW7WSA=; b=VkLB+NYgS5sTQ6UyCjzoNuZIaauqAa+NhOljpsxtYW85p5E9XxlY1Vm02swMszdYV+ XPMCzLyu6CMvNdXpRsUD2cAuUS9vZ3tqUCIXgZWOUqhV6d4bR4uEi0jXkr3zWVmq4PI8 2PKN7KZD3LUvCH3nquczO6O8k/2p7SRGW3DFGLGuEtrFXCHdU3ZGvzwuv4yenrtdZBm0 JHsIoIAPBQ10qiyXcrsYg2shudz+x3hCXCtR0PGiz3b4JeBKU5F85h09aPdKJiyjOjuc K0i5FHeDjDBmEgAQDDCQBQGPF0af6XDdcLx/JI7JK5qybtjqofy/nnnt2PKdXbe9Lz/k TF0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=zDauNKvsnr925xHMPAyQPYL2wWfv0cJQoAYwcXW7WSA=; b=kvKaF/P74PRYOOzdooD7okK6thqUm84f0W/CLLU080FiWMiev08hXmS4nHy6zSIgFk 3DrzG2HUC6H2fT0ULZPL4ZurLE/slXKu6UZtfcunjPOpdLmltmtGk4y/qD79HEidla7G dVsXhJvuTP8dWf8nSBcQ4VUiRsoS3pBvUy6dHGJEc3IHPp0RQo3tdXHNgWwX3gK+074L xYMnpXL3mGrbhcgh3ErgYXOCIT5dhTUdWVWEj3bb/d9tYQQ4KgIqT4fYRTwZb5/f1Kdc j7WCgHFufI+khDivyC756Jitnq+L9GLlSwqYSFp9ZY34aPw3Nhrwi5gWvWvWU/YfVlGH x2OQ== X-Gm-Message-State: AOAM530jn0NGnc/wir6B3dlvICALUZSdB3wzrgvOsJbRkxy6iMOrYAWf Qgj8a/UB9efS8iTbX5H+0JU= X-Google-Smtp-Source: ABdhPJx0s2Um4TLIWmEQvnQv1kvnMhnriZdO+qDZabUA5FAl2qEQFJj3DN+Jzc7Sd1qQgoCc5+419g== X-Received: by 2002:a1c:4045:: with SMTP id n66mr18199239wma.94.1618786317868; Sun, 18 Apr 2021 15:51:57 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen , Jiaxun Yang , Aleksandar Rikalo Subject: [PATCH v2 12/29] target/mips: Add simple user-mode mips_cpu_do_interrupt() Date: Mon, 19 Apr 2021 00:50:41 +0200 Message-Id: <20210418225058.1257014-13-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210418225058.1257014-1-f4bug@amsat.org> References: <20210418225058.1257014-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) The #ifdef'ry hides that the user-mode implementation of mips_cpu_do_interrupt() simply sets exception_index =3D EXCP_NONE. Add this simple implementation to tcg/user/tlb_helper.c, and the corresponding Meson machinery to build this file when user emulation is configured. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- v2: Renamed helper.c -> tlb_helper.c (rth) --- target/mips/tcg/user/tlb_helper.c | 28 ++++++++++++++++++++++++++++ target/mips/tlb_helper.c | 5 ----- target/mips/meson.build | 5 +++++ target/mips/tcg/meson.build | 3 +++ target/mips/tcg/user/meson.build | 3 +++ 5 files changed, 39 insertions(+), 5 deletions(-) create mode 100644 target/mips/tcg/user/tlb_helper.c create mode 100644 target/mips/tcg/meson.build create mode 100644 target/mips/tcg/user/meson.build diff --git a/target/mips/tcg/user/tlb_helper.c b/target/mips/tcg/user/tlb_h= elper.c new file mode 100644 index 00000000000..453b9e9b930 --- /dev/null +++ b/target/mips/tcg/user/tlb_helper.c @@ -0,0 +1,28 @@ +/* + * MIPS TLB (Translation lookaside buffer) helpers. + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ +#include "qemu/osdep.h" + +#include "cpu.h" +#include "exec/exec-all.h" +#include "internal.h" + +void mips_cpu_do_interrupt(CPUState *cs) +{ + cs->exception_index =3D EXCP_NONE; +} diff --git a/target/mips/tlb_helper.c b/target/mips/tlb_helper.c index 8d3ea497803..46e9555c9ab 100644 --- a/target/mips/tlb_helper.c +++ b/target/mips/tlb_helper.c @@ -964,11 +964,8 @@ static inline void set_badinstr_registers(CPUMIPSState= *env) } } =20 -#endif /* !CONFIG_USER_ONLY */ - void mips_cpu_do_interrupt(CPUState *cs) { -#if !defined(CONFIG_USER_ONLY) MIPSCPU *cpu =3D MIPS_CPU(cs); CPUMIPSState *env =3D &cpu->env; bool update_badinstr =3D 0; @@ -1271,11 +1268,9 @@ void mips_cpu_do_interrupt(CPUState *cs) env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr, env->CP0_DEPC); } -#endif cs->exception_index =3D EXCP_NONE; } =20 -#if !defined(CONFIG_USER_ONLY) void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra) { CPUState *cs =3D env_cpu(env); diff --git a/target/mips/meson.build b/target/mips/meson.build index 15c2f835c68..ca3cc62cf7a 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -6,6 +6,7 @@ decodetree.process('tx79.decode', extra_args: '--static-decode=3Ddecode_= tx79'), ] =20 +mips_user_ss =3D ss.source_set() mips_ss =3D ss.source_set() mips_ss.add(files( 'cpu.c', @@ -34,6 +35,9 @@ ), if_false: files( 'mxu_translate.c', )) +if 'CONFIG_TCG' in config_all + subdir('tcg') +endif =20 mips_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) =20 @@ -52,3 +56,4 @@ =20 target_arch +=3D {'mips': mips_ss} target_softmmu_arch +=3D {'mips': mips_softmmu_ss} +target_user_arch +=3D {'mips': mips_user_ss} diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build new file mode 100644 index 00000000000..b74fa04303e --- /dev/null +++ b/target/mips/tcg/meson.build @@ -0,0 +1,3 @@ +if have_user + subdir('user') +endif diff --git a/target/mips/tcg/user/meson.build b/target/mips/tcg/user/meson.= build new file mode 100644 index 00000000000..79badcd3217 --- /dev/null +++ b/target/mips/tcg/user/meson.build @@ -0,0 +1,3 @@ +mips_user_ss.add(files( + 'tlb_helper.c', +)) --=20 2.26.3 From nobody Mon Feb 9 10:44:55 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.48 as permitted sender) client-ip=209.85.221.48; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f48.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.48 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1618786324; cv=none; d=zohomail.com; s=zohoarc; b=KqV2f1vzkraa8X+/DWXMue+zXFUcwbT+RIXFRTzJXDOV5pdCUz/eONBmXivZLhYEBuT1Z+TaiHM8d2DM/axbkseRzeSu79LRtFfRwZRddtaV5ddbZU95s2LhIKmCnO/I8mvc3POynQThdNVYsJNBmpoymlS0XuWWCXaMkUqGRt8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618786324; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=datf5MqDXzTdtBuicfwMzr05e14ZOFgxgW39dQgUMC0=; b=chunn36Ir/slJZNONmCiMZJecnMz0kX2PHeoPt4mGyWW9pmzZSEC2ctlswJZU8jKP7+jCUsOlc9cfQwPEDJGSvWtUKIH1p5PM9GxA5BxY+u0A3kVSQfvM9BM5Hl2XGnfa6HVK0ZQIRjCVpENjTqot8D11CwBMdWyZoWiomnzviI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.48 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f48.google.com (mail-wr1-f48.google.com [209.85.221.48]) by mx.zohomail.com with SMTPS id 1618786324404897.4750819067997; Sun, 18 Apr 2021 15:52:04 -0700 (PDT) Received: by mail-wr1-f48.google.com with SMTP id e7so23069655wrs.11 for ; Sun, 18 Apr 2021 15:52:03 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id h5sm1748956wmq.23.2021.04.18.15.52.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Apr 2021 15:52:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=datf5MqDXzTdtBuicfwMzr05e14ZOFgxgW39dQgUMC0=; b=ZkCsJjG3uiVdvVAO0QW7FkSOsTdF/qS7VpdqZfgXb+GRv9fXwDWSjcWwgtU6dBzNsO 34mNNwgftJEEWpQ+/j4ZbQwV4TjAJ09QN1rTq5Dz39hlwEQUjTpbYkCRUrgSqbeTeGwm PreTgbMoTc/wLPcf+HC+5z4+p+aqGWVTmU7cqUmITU14sG0BMZEmqizGzWGU4xwNuB5B FFyMDjM/athOMdQb5KouCCGofE/PitrjsJjoK9A0gSa4Y3ElP83G+qeLbXwfSRX9Ll9x UHPnycVjjsQVMyhWCMHQ2cE+fasifqy5qQtipHH0o1TJt4yPd/mXV9QAV0CEbc2PpXCQ y5Gw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=datf5MqDXzTdtBuicfwMzr05e14ZOFgxgW39dQgUMC0=; b=iwjhbeHia1NrXtSCXukW1L3zm+fXWoZCA537O/fM8Hlkdx9eGhLXTE7GTKhl91UVob U/k8S228WeNh0kB7ieOiB2qs/5tSyzOS1FgDDJD50mpBgCnl5p2owU0EvPk8/q6wQXnE Imq4OW3wdTm+BImGLl/1MHh6szgBrPq3u1yNYNmttUKJa/D8WNdpuXI2ltfIyHbT/hLi NKicxRmjuaAGjdBqqCyOLjdVwKMH6Su1pHW62dZjsEapTIjViDMTzIGFJKZKdkqpGdAP KweyIEqknhF2b2plZQmy5f0kGXUr3NqV08n5nEEulg6uzFiih8h35VpRbvhU1+VpN77i StgQ== X-Gm-Message-State: AOAM532wdkahikADzH8sIQuD5s9dwY813bwUtWPGxRmE2RyFHdokxIms OLv1aKtVQldIuOO1RJEvQIMk5T6xSZADAA== X-Google-Smtp-Source: ABdhPJxvmcU5OBqfK6Mx9Hml2P7Xl83UEeA9IkY227tL3WJEGvOBuF1FuSsSQT+7tvCm9eHnXKWhaw== X-Received: by 2002:adf:fecd:: with SMTP id q13mr10988321wrs.7.1618786322576; Sun, 18 Apr 2021 15:52:02 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen , Jiaxun Yang , Aleksandar Rikalo Subject: [PATCH v2 13/29] target/mips: Add simple user-mode mips_cpu_tlb_fill() Date: Mon, 19 Apr 2021 00:50:42 +0200 Message-Id: <20210418225058.1257014-14-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210418225058.1257014-1-f4bug@amsat.org> References: <20210418225058.1257014-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) tlb_helper.c's #ifdef'ry hides a quite simple user-mode implementation of mips_cpu_tlb_fill(). Copy the user-mode implementation (without #ifdef'ry) to tcg/user/helper.c and simplify tlb_helper.c's #ifdef'ry. This will allow us to restrict tlb_helper.c to sysemu. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/tcg/user/tlb_helper.c | 36 +++++++++++++++++++++++++++++++ target/mips/tlb_helper.c | 10 --------- 2 files changed, 36 insertions(+), 10 deletions(-) diff --git a/target/mips/tcg/user/tlb_helper.c b/target/mips/tcg/user/tlb_h= elper.c index 453b9e9b930..b835144b820 100644 --- a/target/mips/tcg/user/tlb_helper.c +++ b/target/mips/tcg/user/tlb_helper.c @@ -22,6 +22,42 @@ #include "exec/exec-all.h" #include "internal.h" =20 +static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, + MMUAccessType access_type) +{ + CPUState *cs =3D env_cpu(env); + + env->error_code =3D 0; + if (access_type =3D=3D MMU_INST_FETCH) { + env->error_code |=3D EXCP_INST_NOTAVAIL; + } + + /* Reference to kernel address from user mode or supervisor mode */ + /* Reference to supervisor address from user mode */ + if (access_type =3D=3D MMU_DATA_STORE) { + cs->exception_index =3D EXCP_AdES; + } else { + cs->exception_index =3D EXCP_AdEL; + } + + /* Raise exception */ + if (!(env->hflags & MIPS_HFLAG_DM)) { + env->CP0_BadVAddr =3D address; + } +} + +bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) +{ + MIPSCPU *cpu =3D MIPS_CPU(cs); + CPUMIPSState *env =3D &cpu->env; + + /* data access */ + raise_mmu_exception(env, address, access_type); + do_raise_exception_err(env, cs->exception_index, env->error_code, reta= ddr); +} + void mips_cpu_do_interrupt(CPUState *cs) { cs->exception_index =3D EXCP_NONE; diff --git a/target/mips/tlb_helper.c b/target/mips/tlb_helper.c index 46e9555c9ab..bb4b503ff72 100644 --- a/target/mips/tlb_helper.c +++ b/target/mips/tlb_helper.c @@ -403,8 +403,6 @@ void cpu_mips_tlb_flush(CPUMIPSState *env) env->tlb->tlb_in_use =3D env->tlb->nb_tlb; } =20 -#endif /* !CONFIG_USER_ONLY */ - static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, MMUAccessType access_type, int tlb_error) { @@ -484,8 +482,6 @@ static void raise_mmu_exception(CPUMIPSState *env, targ= et_ulong address, env->error_code =3D error_code; } =20 -#if !defined(CONFIG_USER_ONLY) - hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { MIPSCPU *cpu =3D MIPS_CPU(cs); @@ -833,7 +829,6 @@ refill: return true; } #endif -#endif /* !CONFIG_USER_ONLY */ =20 bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, @@ -841,14 +836,11 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, { MIPSCPU *cpu =3D MIPS_CPU(cs); CPUMIPSState *env =3D &cpu->env; -#if !defined(CONFIG_USER_ONLY) hwaddr physical; int prot; -#endif int ret =3D TLBRET_BADADDR; =20 /* data access */ -#if !defined(CONFIG_USER_ONLY) /* XXX: put correct access by using cpu_restore_state() correctly */ ret =3D get_physical_address(env, &physical, &prot, address, access_type, mmu_idx); @@ -896,13 +888,11 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, if (probe) { return false; } -#endif =20 raise_mmu_exception(env, address, access_type, ret); do_raise_exception_err(env, cs->exception_index, env->error_code, reta= ddr); } =20 -#ifndef CONFIG_USER_ONLY hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, MMUAccessType access_type) { --=20 2.26.3 From nobody Mon Feb 9 10:44:55 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.51 as permitted sender) client-ip=209.85.221.51; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f51.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.51 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1618786329; cv=none; d=zohomail.com; s=zohoarc; b=YggGd+JubgQ1ahnJFurB5CCBhoNYU4wxIsIzhkJPuu9phiOw6+ALBrGzJD6vub7z0Ug7EEJuZPcUXdXT4sHyk2fl9hXstq3WtkVcHWrgZACmBmjPypFiV4aXvrYVFun+5qliDk8wc1cD3jk1kNPiMN0+vA5/YpjD1Vfdbfdwt/Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618786329; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; 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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id t184sm17522308wmf.26.2021.04.18.15.52.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Apr 2021 15:52:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=g/Zr2GZmHwcpc4Ys5R+RUKW49Msx4MkT58HWFtOoOSo=; b=dmu9JYz/g2jvMguiuBDrMv1vfCP8eN40dRDae+sXsxnAi9UdhR6UwgR6tqX5ZSkhbh RduaqQREGNYUaXeSGF2HskWR1A/WtZtCWVVMjXfHdqWEebnt4r8VCkWgvLjUuFj7iFD0 rQt6eecLpOQNjBFkhxvnb2SeSD79KzamGya/xnkXONwPjBjNswLXpHQ6Ies6TneX9oiN PbvfXIs+R1kzcy/zoPzkDwWAa5zh9ef+AeWQTTJLPdZCovh5E/wx4+gsSZomgkkVeuCN zaOOQsQhTKRxSGJR5Dal406SUWPfJjUag/C6iAYnA4TEJZokvOhZX4ptXwVOnStTevNr hlLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=g/Zr2GZmHwcpc4Ys5R+RUKW49Msx4MkT58HWFtOoOSo=; b=I5ECG+OWrf9PlikuCUUlPYsqpfTaNV9jcx/WRyoWW5yAaH9h+i7fTUn0y9v1XEaVKT VseIhSh+vkk+r/fTSF9VbE1MPG3hOO5uWAkbH2iCuiuOLrggk/Sgm4ey9K9Np2194ieY gKntT+eDkLKYJ8lnNS+7v9IuMU8w/fhn0YA0QAxKVR1LsnP/56Ceyp7deHCceGhy8cpE zUK6ASqN9cqN26LwXW23h20nQK3eiZe9tjo+eMe2PLgFPgoVPUsUVlHlzVonC+Qcry0F FrCXh4d9S+tdfwynxrmmCv6oUcGl2dvZs23X8Gq04Gop7PO8DJB/jdojarJHO/lqHW9y p+2w== X-Gm-Message-State: AOAM531IPTXWkHKVZ9nMdsOD6VfFyAZl7nkoyL5pubChtksMk/gZzXyx P9MA80KnD8K2tadZn7uaObiGkJyMQHM5aA== X-Google-Smtp-Source: ABdhPJypTlRUyP3BcA5bFgx0wGg9zfXFIyQttRBSlmw1pXrqbks208Ry2mrp55eo1x6V6OoTnVYCJg== X-Received: by 2002:a5d:4912:: with SMTP id x18mr11459975wrq.198.1618786327349; Sun, 18 Apr 2021 15:52:07 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen , Jiaxun Yang , Aleksandar Rikalo Subject: [PATCH v2 14/29] target/mips: Move cpu_signal_handler definition around Date: Mon, 19 Apr 2021 00:50:43 +0200 Message-Id: <20210418225058.1257014-15-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210418225058.1257014-1-f4bug@amsat.org> References: <20210418225058.1257014-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) We have 2 blocks guarded with #ifdef for sysemu, which are simply separated by the cpu_signal_handler definition. To simplify the following commits which involve various changes in internal.h, first join the sysemu-guarded blocks. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/internal.h | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 284ef8d1e1a..8deb0703a34 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -151,14 +151,13 @@ void mips_cpu_do_transaction_failed(CPUState *cs, hwa= ddr physaddr, MemTxResult response, uintptr_t retadd= r); hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, MMUAccessType access_type); -#endif + +extern const VMStateDescription vmstate_mips_cpu; + +#endif /* !CONFIG_USER_ONLY */ =20 #define cpu_signal_handler cpu_mips_signal_handler =20 -#ifndef CONFIG_USER_ONLY -extern const VMStateDescription vmstate_mips_cpu; -#endif - static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env) { return (env->CP0_Status & (1 << CP0St_IE)) && --=20 2.26.3 From nobody Mon Feb 9 10:44:55 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.52 as permitted sender) client-ip=209.85.221.52; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f52.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.52 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1618786334; cv=none; d=zohomail.com; s=zohoarc; b=LIKKbCllj+rn3MwfXQtpGlrTS5+HuAnKPGC07oReMtDNTIp9VB6nalC9SDNkFDFuiOwXm03BYlPk+q1foZoFAkKHwwysXwUoaJvoTCW7LcXep3xA7CFll4E2YU464tOCeSmathZ8kb56Gwf5s93BhlvaiUtmkIdb3m2MCAuHlsA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618786334; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=xKUW8gAMAxhtFOb8uojubp49vr/t6a7goYqTsVJzhpA=; b=GmFq8YLQxp7sSh8NcWvf0D9LruG/O8+Sd/d/Z1TZiU2G2dMDOVSJUEoXr5yApJucTu/sKbi4N1MIC1RyeUZNHtGfQjhaYfIFxPu0FKzMqKTxb/VI9zk0rUo2/c2FLldNhDUSGn+pOAqVW8snJX/aazjkdQiSCP0KAIOeM2kUbK8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.52 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f52.google.com (mail-wr1-f52.google.com [209.85.221.52]) by mx.zohomail.com with SMTPS id 1618786334198512.1069121311675; Sun, 18 Apr 2021 15:52:14 -0700 (PDT) Received: by mail-wr1-f52.google.com with SMTP id m9so19283541wrx.3 for ; Sun, 18 Apr 2021 15:52:13 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id o4sm173390wrn.81.2021.04.18.15.52.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Apr 2021 15:52:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xKUW8gAMAxhtFOb8uojubp49vr/t6a7goYqTsVJzhpA=; b=Br4VhlotSFKwfy1zcV6R+apuqIeF4OZk2ZdszZeT1izWbx2jzkkCufRXH2eJizf5G4 vx6kPhEhKCWpjbFLQxBn1ib7pqQCgorooKQHvr9miaVUvO3IXGVogDlc9H6BJRmoBP5a aqVR0BZOtpAlotwrW2LSuR3k5BPoLqie7xFRlpsRHGtla+kEtWm2RcdrzI4j/lXPVSA9 NsR79jIMCIbnwr0OYUJUvbcEfUQCHk79PvExda53fvuZQOG4fg+tzVGaNd9uk8OWwpMf f7p1dAoZTypIQ3hh3W+8TnPjPvn96I9HxGsK4CmPoeN3fQ4EgFGjJkLlpFJ1aZnmwWB0 XCtQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=xKUW8gAMAxhtFOb8uojubp49vr/t6a7goYqTsVJzhpA=; b=czhXD5MdNA/wyOsR/2UXiqSPEuU+vvdXZr7jd/2gvWZAkChMGFEZLgiEV7i0a+qcJ4 eJ56rwMfTAc+Eq8XytN23l1hqMIwb35G0JNM1C6ClKpWswlF98aR3Idk4ZNXm6gXVZQz 2T1G4961WSukvPGql/9N9C9HOBv/A6iyLLT6q7tJtfDMdjilR4fIJvtIQh6VVUKfx+cx b/1GKaZXh3DbCVkMoPwAjxQlVKDP4LwKt3z+IWjbNJ097Ij1oGUGpsk5pKYQrBGA4T+L sc14KdZbfo/X/PMrGPaucdGvXDjvseKIEY+OqCrbyDIoH8B86nbES2HALimzg6lKhlx4 /JEg== X-Gm-Message-State: AOAM531DNcV3BcqlPJZmg/ddYblqw8XQ432o92GO417rOLANoS6R+o/C kxbYAMruJfWp7vuTN2j4IdISLLJhSCXxJg== X-Google-Smtp-Source: ABdhPJyXug3UJ1O4hk124+dasIkuzLbFMgdDQtaksxywbJ179SlkwpuCW34RLYQiGJqhPvMC2BWoTw== X-Received: by 2002:a05:6000:1567:: with SMTP id 7mr10843494wrz.47.1618786332387; Sun, 18 Apr 2021 15:52:12 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen , Jiaxun Yang , Aleksandar Rikalo Subject: [PATCH v2 15/29] target/mips: Move sysemu specific files under sysemu/ subfolder Date: Mon, 19 Apr 2021 00:50:44 +0200 Message-Id: <20210418225058.1257014-16-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210418225058.1257014-1-f4bug@amsat.org> References: <20210418225058.1257014-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Move sysemu-specific files under the new sysemu/ subfolder and adapt the Meson machinery. Update the KVM MIPS entry in MAINTAINERS. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- v2: Update MAINTAINERS --- target/mips/{ =3D> sysemu}/addr.c | 0 target/mips/{ =3D> sysemu}/cp0_timer.c | 0 target/mips/{ =3D> sysemu}/machine.c | 0 MAINTAINERS | 3 ++- target/mips/meson.build | 12 ++++++------ target/mips/sysemu/meson.build | 5 +++++ 6 files changed, 13 insertions(+), 7 deletions(-) rename target/mips/{ =3D> sysemu}/addr.c (100%) rename target/mips/{ =3D> sysemu}/cp0_timer.c (100%) rename target/mips/{ =3D> sysemu}/machine.c (100%) create mode 100644 target/mips/sysemu/meson.build diff --git a/target/mips/addr.c b/target/mips/sysemu/addr.c similarity index 100% rename from target/mips/addr.c rename to target/mips/sysemu/addr.c diff --git a/target/mips/cp0_timer.c b/target/mips/sysemu/cp0_timer.c similarity index 100% rename from target/mips/cp0_timer.c rename to target/mips/sysemu/cp0_timer.c diff --git a/target/mips/machine.c b/target/mips/sysemu/machine.c similarity index 100% rename from target/mips/machine.c rename to target/mips/sysemu/machine.c diff --git a/MAINTAINERS b/MAINTAINERS index 36055f14c59..0620326544e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -404,7 +404,8 @@ F: target/arm/kvm.c MIPS KVM CPUs M: Huacai Chen S: Odd Fixes -F: target/mips/kvm.c +F: target/mips/kvm* +F: target/mips/sysemu/ =20 PPC KVM CPUs M: David Gibson diff --git a/target/mips/meson.build b/target/mips/meson.build index ca3cc62cf7a..9a507937ece 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -7,6 +7,7 @@ ] =20 mips_user_ss =3D ss.source_set() +mips_softmmu_ss =3D ss.source_set() mips_ss =3D ss.source_set() mips_ss.add(files( 'cpu.c', @@ -14,6 +15,11 @@ 'gdbstub.c', 'msa.c', )) + +if have_system + subdir('sysemu') +endif + mips_tcg_ss =3D ss.source_set() mips_tcg_ss.add(gen) mips_tcg_ss.add(files( @@ -41,12 +47,6 @@ =20 mips_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) =20 -mips_softmmu_ss =3D ss.source_set() -mips_softmmu_ss.add(files( - 'addr.c', - 'cp0_timer.c', - 'machine.c', -)) mips_softmmu_ss.add(when: 'CONFIG_TCG', if_true: files( 'cp0_helper.c', 'mips-semi.c', diff --git a/target/mips/sysemu/meson.build b/target/mips/sysemu/meson.build new file mode 100644 index 00000000000..f2a1ff46081 --- /dev/null +++ b/target/mips/sysemu/meson.build @@ -0,0 +1,5 @@ +mips_softmmu_ss.add(files( + 'addr.c', + 'cp0_timer.c', + 'machine.c', +)) --=20 2.26.3 From nobody Mon Feb 9 10:44:55 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.52 as permitted sender) client-ip=209.85.221.52; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f52.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.52 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1618786339; cv=none; d=zohomail.com; s=zohoarc; b=Ro7qlqRkpB1VoZTkfhJwQKnPCTSO6s1BfvK7zzlXEI9rsP1pZBaKwscp6DnbMiZbmwTGWzKV6fPTvGoRncQILPQDDbqLuhMz3SUMg7J2iezhCDCSiYUn1B8fOk+3BpxQolxaHD+3qOMabzK4q4c2FfcpUBdUyRhoXCsLgNflcE4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618786339; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=vkdtZxG/eCROTnaqA1SQ9FO2PMMQu/MSFWpJzcLGmgE=; b=BVkACmlk5ueQRr5BvJ4+y2wASUZ479lxavAXye06SmulDYMMe8OJYdTdeRTNaVvQUG0snFwOIZgcOOzpajeHA3RUU6Uph+5DfhJn0QIImfxHycPJvYJvTYji1pdOOFi/QqCWUNFK0zEKChwSbYfaMuKRxgkz0va56AokHXPGdOE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.52 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f52.google.com (mail-wr1-f52.google.com [209.85.221.52]) by mx.zohomail.com with SMTPS id 1618786339044791.0119731737865; Sun, 18 Apr 2021 15:52:19 -0700 (PDT) Received: by mail-wr1-f52.google.com with SMTP id a4so32052245wrr.2 for ; Sun, 18 Apr 2021 15:52:18 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id q18sm19619221wrs.25.2021.04.18.15.52.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Apr 2021 15:52:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vkdtZxG/eCROTnaqA1SQ9FO2PMMQu/MSFWpJzcLGmgE=; b=eFK0irJL9FEjfJuqh6NltM9IU1CFnJQWNjL4QUNgviP7VWcZKSlg6SWvujMfSVD8Wh wD/TZqcvTQVOQkeqB4byclcLfPZN8/pF8rkLJVh15hiI4CnqbyFS10IHuNs394r2wmrS iUTf4NMLR5WMA+Y9d0hpM5V+6Z4C6TlMdo+bmmLqT/8XrvGp9RP7+8PYVnv1JAh6HLrs FlBg2o+7rz0FqwVNmGGEZ3AWe7JwjoxcdbINZWMDIhayRPJFeZoitC8Ep3ik14eEXRia 8J3KDFGMxaR/jORIS2neE+oWk24HCWeO0nMKlUkBi8Uy5tQvcEcGm5kU5dPbf/AnS8N3 /8oA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=vkdtZxG/eCROTnaqA1SQ9FO2PMMQu/MSFWpJzcLGmgE=; b=P1y+V/xtAUyv6ot0qQhZg2xw/kf1uV7HpeSzzFCwxKEquWZm5dJsCgw++p1JSd3tUs xk54eP5/CpEYeGuey/An8WciLXJWHrr3jPuTrARM1Lrzwkf3wveGu1aknGok8hMuh88K z22izFDnNn18UJxRtqiDEyQFjdTDJ9tUeoLuifteLb7yY3hb54P52TZUxfh00qVYXrrT /vl1IVKhQiJbA5WCFDiF0aDNdRdYQ9IzClSuXAZ4rL8ifKWk8nPr5qPHjMSiyu0zGRuX g3CSoWR1B/A7Ade2AEbgJ9YtTJGXNDFZCTw6jtXV+sTQfGHlG7l952v633DYDiXVJ+Z5 ZlBg== X-Gm-Message-State: AOAM5339eKB1H6Ye64KYolqyLegrC3rWtSBIBBuPf+0csllrFiOzTSwJ 05hijkLFxXhPqIDsjbW1b0g= X-Google-Smtp-Source: ABdhPJzXln50VrkYzNcoeTjP2ATEsy5EOXDexefPU7YSyv9I19hQ9MGHhUWIWFG4sN5uJBAoYzbAUg== X-Received: by 2002:adf:fecd:: with SMTP id q13mr10989033wrs.7.1618786337070; Sun, 18 Apr 2021 15:52:17 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen , Jiaxun Yang , Aleksandar Rikalo Subject: [PATCH v2 16/29] target/mips: Move physical addressing code to sysemu/physaddr.c Date: Mon, 19 Apr 2021 00:50:45 +0200 Message-Id: <20210418225058.1257014-17-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210418225058.1257014-1-f4bug@amsat.org> References: <20210418225058.1257014-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Declare get_physical_address() with local scope and move it along with mips_cpu_get_phys_page_debug() to sysemu/physaddr.c new file. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- v2: phys.c -> physaddr.c in description (rth) --- target/mips/internal.h | 25 +++- target/mips/sysemu/physaddr.c | 257 +++++++++++++++++++++++++++++++++ target/mips/tlb_helper.c | 254 -------------------------------- target/mips/sysemu/meson.build | 1 + 4 files changed, 282 insertions(+), 255 deletions(-) create mode 100644 target/mips/sysemu/physaddr.c diff --git a/target/mips/internal.h b/target/mips/internal.h index 8deb0703a34..8789ffb319f 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -81,15 +81,38 @@ extern const struct mips_def_t mips_defs[]; extern const int mips_defs_number; =20 bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); -hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); =20 +#define USEG_LIMIT ((target_ulong)(int32_t)0x7FFFFFFFUL) +#define KSEG0_BASE ((target_ulong)(int32_t)0x80000000UL) +#define KSEG1_BASE ((target_ulong)(int32_t)0xA0000000UL) +#define KSEG2_BASE ((target_ulong)(int32_t)0xC0000000UL) +#define KSEG3_BASE ((target_ulong)(int32_t)0xE0000000UL) + +#define KVM_KSEG0_BASE ((target_ulong)(int32_t)0x40000000UL) +#define KVM_KSEG2_BASE ((target_ulong)(int32_t)0x60000000UL) + #if !defined(CONFIG_USER_ONLY) =20 +enum { + TLBRET_XI =3D -6, + TLBRET_RI =3D -5, + TLBRET_DIRTY =3D -4, + TLBRET_INVALID =3D -3, + TLBRET_NOMATCH =3D -2, + TLBRET_BADADDR =3D -1, + TLBRET_MATCH =3D 0 +}; + +int get_physical_address(CPUMIPSState *env, hwaddr *physical, + int *prot, target_ulong real_address, + MMUAccessType access_type, int mmu_idx); +hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); + typedef struct r4k_tlb_t r4k_tlb_t; struct r4k_tlb_t { target_ulong VPN; diff --git a/target/mips/sysemu/physaddr.c b/target/mips/sysemu/physaddr.c new file mode 100644 index 00000000000..1918633aa1c --- /dev/null +++ b/target/mips/sysemu/physaddr.c @@ -0,0 +1,257 @@ +/* + * MIPS TLB (Translation lookaside buffer) helpers. + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ +#include "qemu/osdep.h" +#include "cpu.h" +#include "exec/exec-all.h" +#include "../internal.h" + +static int is_seg_am_mapped(unsigned int am, bool eu, int mmu_idx) +{ + /* + * Interpret access control mode and mmu_idx. + * AdE? TLB? + * AM K S U E K S U E + * UK 0 0 1 1 0 0 - - 0 + * MK 1 0 1 1 0 1 - - !eu + * MSK 2 0 0 1 0 1 1 - !eu + * MUSK 3 0 0 0 0 1 1 1 !eu + * MUSUK 4 0 0 0 0 0 1 1 0 + * USK 5 0 0 1 0 0 0 - 0 + * - 6 - - - - - - - - + * UUSK 7 0 0 0 0 0 0 0 0 + */ + int32_t adetlb_mask; + + switch (mmu_idx) { + case 3: /* ERL */ + /* If EU is set, always unmapped */ + if (eu) { + return 0; + } + /* fall through */ + case MIPS_HFLAG_KM: + /* Never AdE, TLB mapped if AM=3D{1,2,3} */ + adetlb_mask =3D 0x70000000; + goto check_tlb; + + case MIPS_HFLAG_SM: + /* AdE if AM=3D{0,1}, TLB mapped if AM=3D{2,3,4} */ + adetlb_mask =3D 0xc0380000; + goto check_ade; + + case MIPS_HFLAG_UM: + /* AdE if AM=3D{0,1,2,5}, TLB mapped if AM=3D{3,4} */ + adetlb_mask =3D 0xe4180000; + /* fall through */ + check_ade: + /* does this AM cause AdE in current execution mode */ + if ((adetlb_mask << am) < 0) { + return TLBRET_BADADDR; + } + adetlb_mask <<=3D 8; + /* fall through */ + check_tlb: + /* is this AM mapped in current execution mode */ + return ((adetlb_mask << am) < 0); + default: + assert(0); + return TLBRET_BADADDR; + }; +} + +static int get_seg_physical_address(CPUMIPSState *env, hwaddr *physical, + int *prot, target_ulong real_address, + MMUAccessType access_type, int mmu_idx, + unsigned int am, bool eu, + target_ulong segmask, + hwaddr physical_base) +{ + int mapped =3D is_seg_am_mapped(am, eu, mmu_idx); + + if (mapped < 0) { + /* is_seg_am_mapped can report TLBRET_BADADDR */ + return mapped; + } else if (mapped) { + /* The segment is TLB mapped */ + return env->tlb->map_address(env, physical, prot, real_address, + access_type); + } else { + /* The segment is unmapped */ + *physical =3D physical_base | (real_address & segmask); + *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + return TLBRET_MATCH; + } +} + +static int get_segctl_physical_address(CPUMIPSState *env, hwaddr *physical, + int *prot, target_ulong real_addres= s, + MMUAccessType access_type, int mmu_= idx, + uint16_t segctl, target_ulong segma= sk) +{ + unsigned int am =3D (segctl & CP0SC_AM_MASK) >> CP0SC_AM; + bool eu =3D (segctl >> CP0SC_EU) & 1; + hwaddr pa =3D ((hwaddr)segctl & CP0SC_PA_MASK) << 20; + + return get_seg_physical_address(env, physical, prot, real_address, + access_type, mmu_idx, am, eu, segmask, + pa & ~(hwaddr)segmask); +} + +int get_physical_address(CPUMIPSState *env, hwaddr *physical, + int *prot, target_ulong real_address, + MMUAccessType access_type, int mmu_idx) +{ + /* User mode can only access useg/xuseg */ +#if defined(TARGET_MIPS64) + int user_mode =3D mmu_idx =3D=3D MIPS_HFLAG_UM; + int supervisor_mode =3D mmu_idx =3D=3D MIPS_HFLAG_SM; + int kernel_mode =3D !user_mode && !supervisor_mode; + int UX =3D (env->CP0_Status & (1 << CP0St_UX)) !=3D 0; + int SX =3D (env->CP0_Status & (1 << CP0St_SX)) !=3D 0; + int KX =3D (env->CP0_Status & (1 << CP0St_KX)) !=3D 0; +#endif + int ret =3D TLBRET_MATCH; + /* effective address (modified for KVM T&E kernel segments) */ + target_ulong address =3D real_address; + + if (mips_um_ksegs_enabled()) { + /* KVM T&E adds guest kernel segments in useg */ + if (real_address >=3D KVM_KSEG0_BASE) { + if (real_address < KVM_KSEG2_BASE) { + /* kseg0 */ + address +=3D KSEG0_BASE - KVM_KSEG0_BASE; + } else if (real_address <=3D USEG_LIMIT) { + /* kseg2/3 */ + address +=3D KSEG2_BASE - KVM_KSEG2_BASE; + } + } + } + + if (address <=3D USEG_LIMIT) { + /* useg */ + uint16_t segctl; + + if (address >=3D 0x40000000UL) { + segctl =3D env->CP0_SegCtl2; + } else { + segctl =3D env->CP0_SegCtl2 >> 16; + } + ret =3D get_segctl_physical_address(env, physical, prot, + real_address, access_type, + mmu_idx, segctl, 0x3FFFFFFF); +#if defined(TARGET_MIPS64) + } else if (address < 0x4000000000000000ULL) { + /* xuseg */ + if (UX && address <=3D (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) { + ret =3D env->tlb->map_address(env, physical, prot, + real_address, access_type); + } else { + ret =3D TLBRET_BADADDR; + } + } else if (address < 0x8000000000000000ULL) { + /* xsseg */ + if ((supervisor_mode || kernel_mode) && + SX && address <=3D (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) { + ret =3D env->tlb->map_address(env, physical, prot, + real_address, access_type); + } else { + ret =3D TLBRET_BADADDR; + } + } else if (address < 0xC000000000000000ULL) { + /* xkphys */ + if ((address & 0x07FFFFFFFFFFFFFFULL) <=3D env->PAMask) { + /* KX/SX/UX bit to check for each xkphys EVA access mode */ + static const uint8_t am_ksux[8] =3D { + [CP0SC_AM_UK] =3D (1u << CP0St_KX), + [CP0SC_AM_MK] =3D (1u << CP0St_KX), + [CP0SC_AM_MSK] =3D (1u << CP0St_SX), + [CP0SC_AM_MUSK] =3D (1u << CP0St_UX), + [CP0SC_AM_MUSUK] =3D (1u << CP0St_UX), + [CP0SC_AM_USK] =3D (1u << CP0St_SX), + [6] =3D (1u << CP0St_KX), + [CP0SC_AM_UUSK] =3D (1u << CP0St_UX), + }; + unsigned int am =3D CP0SC_AM_UK; + unsigned int xr =3D (env->CP0_SegCtl2 & CP0SC2_XR_MASK) >> CP0= SC2_XR; + + if (xr & (1 << ((address >> 59) & 0x7))) { + am =3D (env->CP0_SegCtl1 & CP0SC1_XAM_MASK) >> CP0SC1_XAM; + } + /* Does CP0_Status.KX/SX/UX permit the access mode (am) */ + if (env->CP0_Status & am_ksux[am]) { + ret =3D get_seg_physical_address(env, physical, prot, + real_address, access_type, + mmu_idx, am, false, env->PA= Mask, + 0); + } else { + ret =3D TLBRET_BADADDR; + } + } else { + ret =3D TLBRET_BADADDR; + } + } else if (address < 0xFFFFFFFF80000000ULL) { + /* xkseg */ + if (kernel_mode && KX && + address <=3D (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) { + ret =3D env->tlb->map_address(env, physical, prot, + real_address, access_type); + } else { + ret =3D TLBRET_BADADDR; + } +#endif + } else if (address < KSEG1_BASE) { + /* kseg0 */ + ret =3D get_segctl_physical_address(env, physical, prot, real_addr= ess, + access_type, mmu_idx, + env->CP0_SegCtl1 >> 16, 0x1FFFFF= FF); + } else if (address < KSEG2_BASE) { + /* kseg1 */ + ret =3D get_segctl_physical_address(env, physical, prot, real_addr= ess, + access_type, mmu_idx, + env->CP0_SegCtl1, 0x1FFFFFFF); + } else if (address < KSEG3_BASE) { + /* sseg (kseg2) */ + ret =3D get_segctl_physical_address(env, physical, prot, real_addr= ess, + access_type, mmu_idx, + env->CP0_SegCtl0 >> 16, 0x1FFFFF= FF); + } else { + /* + * kseg3 + * XXX: debug segment is not emulated + */ + ret =3D get_segctl_physical_address(env, physical, prot, real_addr= ess, + access_type, mmu_idx, + env->CP0_SegCtl0, 0x1FFFFFFF); + } + return ret; +} + +hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) +{ + MIPSCPU *cpu =3D MIPS_CPU(cs); + CPUMIPSState *env =3D &cpu->env; + hwaddr phys_addr; + int prot; + + if (get_physical_address(env, &phys_addr, &prot, addr, MMU_DATA_LOAD, + cpu_mmu_index(env, false)) !=3D 0) { + return -1; + } + return phys_addr; +} diff --git a/target/mips/tlb_helper.c b/target/mips/tlb_helper.c index bb4b503ff72..2304fff4c42 100644 --- a/target/mips/tlb_helper.c +++ b/target/mips/tlb_helper.c @@ -25,16 +25,6 @@ #include "exec/log.h" #include "hw/mips/cpudevs.h" =20 -enum { - TLBRET_XI =3D -6, - TLBRET_RI =3D -5, - TLBRET_DIRTY =3D -4, - TLBRET_INVALID =3D -3, - TLBRET_NOMATCH =3D -2, - TLBRET_BADADDR =3D -1, - TLBRET_MATCH =3D 0 -}; - #if !defined(CONFIG_USER_ONLY) =20 /* no MMU emulation */ @@ -166,236 +156,6 @@ void mmu_init(CPUMIPSState *env, const mips_def_t *de= f) } } =20 -static int is_seg_am_mapped(unsigned int am, bool eu, int mmu_idx) -{ - /* - * Interpret access control mode and mmu_idx. - * AdE? TLB? - * AM K S U E K S U E - * UK 0 0 1 1 0 0 - - 0 - * MK 1 0 1 1 0 1 - - !eu - * MSK 2 0 0 1 0 1 1 - !eu - * MUSK 3 0 0 0 0 1 1 1 !eu - * MUSUK 4 0 0 0 0 0 1 1 0 - * USK 5 0 0 1 0 0 0 - 0 - * - 6 - - - - - - - - - * UUSK 7 0 0 0 0 0 0 0 0 - */ - int32_t adetlb_mask; - - switch (mmu_idx) { - case 3: /* ERL */ - /* If EU is set, always unmapped */ - if (eu) { - return 0; - } - /* fall through */ - case MIPS_HFLAG_KM: - /* Never AdE, TLB mapped if AM=3D{1,2,3} */ - adetlb_mask =3D 0x70000000; - goto check_tlb; - - case MIPS_HFLAG_SM: - /* AdE if AM=3D{0,1}, TLB mapped if AM=3D{2,3,4} */ - adetlb_mask =3D 0xc0380000; - goto check_ade; - - case MIPS_HFLAG_UM: - /* AdE if AM=3D{0,1,2,5}, TLB mapped if AM=3D{3,4} */ - adetlb_mask =3D 0xe4180000; - /* fall through */ - check_ade: - /* does this AM cause AdE in current execution mode */ - if ((adetlb_mask << am) < 0) { - return TLBRET_BADADDR; - } - adetlb_mask <<=3D 8; - /* fall through */ - check_tlb: - /* is this AM mapped in current execution mode */ - return ((adetlb_mask << am) < 0); - default: - assert(0); - return TLBRET_BADADDR; - }; -} - -static int get_seg_physical_address(CPUMIPSState *env, hwaddr *physical, - int *prot, target_ulong real_address, - MMUAccessType access_type, int mmu_idx, - unsigned int am, bool eu, - target_ulong segmask, - hwaddr physical_base) -{ - int mapped =3D is_seg_am_mapped(am, eu, mmu_idx); - - if (mapped < 0) { - /* is_seg_am_mapped can report TLBRET_BADADDR */ - return mapped; - } else if (mapped) { - /* The segment is TLB mapped */ - return env->tlb->map_address(env, physical, prot, real_address, - access_type); - } else { - /* The segment is unmapped */ - *physical =3D physical_base | (real_address & segmask); - *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; - return TLBRET_MATCH; - } -} - -static int get_segctl_physical_address(CPUMIPSState *env, hwaddr *physical, - int *prot, target_ulong real_addres= s, - MMUAccessType access_type, int mmu_= idx, - uint16_t segctl, target_ulong segma= sk) -{ - unsigned int am =3D (segctl & CP0SC_AM_MASK) >> CP0SC_AM; - bool eu =3D (segctl >> CP0SC_EU) & 1; - hwaddr pa =3D ((hwaddr)segctl & CP0SC_PA_MASK) << 20; - - return get_seg_physical_address(env, physical, prot, real_address, - access_type, mmu_idx, am, eu, segmask, - pa & ~(hwaddr)segmask); -} - -static int get_physical_address(CPUMIPSState *env, hwaddr *physical, - int *prot, target_ulong real_address, - MMUAccessType access_type, int mmu_idx) -{ - /* User mode can only access useg/xuseg */ -#if defined(TARGET_MIPS64) - int user_mode =3D mmu_idx =3D=3D MIPS_HFLAG_UM; - int supervisor_mode =3D mmu_idx =3D=3D MIPS_HFLAG_SM; - int kernel_mode =3D !user_mode && !supervisor_mode; - int UX =3D (env->CP0_Status & (1 << CP0St_UX)) !=3D 0; - int SX =3D (env->CP0_Status & (1 << CP0St_SX)) !=3D 0; - int KX =3D (env->CP0_Status & (1 << CP0St_KX)) !=3D 0; -#endif - int ret =3D TLBRET_MATCH; - /* effective address (modified for KVM T&E kernel segments) */ - target_ulong address =3D real_address; - -#define USEG_LIMIT ((target_ulong)(int32_t)0x7FFFFFFFUL) -#define KSEG0_BASE ((target_ulong)(int32_t)0x80000000UL) -#define KSEG1_BASE ((target_ulong)(int32_t)0xA0000000UL) -#define KSEG2_BASE ((target_ulong)(int32_t)0xC0000000UL) -#define KSEG3_BASE ((target_ulong)(int32_t)0xE0000000UL) - -#define KVM_KSEG0_BASE ((target_ulong)(int32_t)0x40000000UL) -#define KVM_KSEG2_BASE ((target_ulong)(int32_t)0x60000000UL) - - if (mips_um_ksegs_enabled()) { - /* KVM T&E adds guest kernel segments in useg */ - if (real_address >=3D KVM_KSEG0_BASE) { - if (real_address < KVM_KSEG2_BASE) { - /* kseg0 */ - address +=3D KSEG0_BASE - KVM_KSEG0_BASE; - } else if (real_address <=3D USEG_LIMIT) { - /* kseg2/3 */ - address +=3D KSEG2_BASE - KVM_KSEG2_BASE; - } - } - } - - if (address <=3D USEG_LIMIT) { - /* useg */ - uint16_t segctl; - - if (address >=3D 0x40000000UL) { - segctl =3D env->CP0_SegCtl2; - } else { - segctl =3D env->CP0_SegCtl2 >> 16; - } - ret =3D get_segctl_physical_address(env, physical, prot, - real_address, access_type, - mmu_idx, segctl, 0x3FFFFFFF); -#if defined(TARGET_MIPS64) - } else if (address < 0x4000000000000000ULL) { - /* xuseg */ - if (UX && address <=3D (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) { - ret =3D env->tlb->map_address(env, physical, prot, - real_address, access_type); - } else { - ret =3D TLBRET_BADADDR; - } - } else if (address < 0x8000000000000000ULL) { - /* xsseg */ - if ((supervisor_mode || kernel_mode) && - SX && address <=3D (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) { - ret =3D env->tlb->map_address(env, physical, prot, - real_address, access_type); - } else { - ret =3D TLBRET_BADADDR; - } - } else if (address < 0xC000000000000000ULL) { - /* xkphys */ - if ((address & 0x07FFFFFFFFFFFFFFULL) <=3D env->PAMask) { - /* KX/SX/UX bit to check for each xkphys EVA access mode */ - static const uint8_t am_ksux[8] =3D { - [CP0SC_AM_UK] =3D (1u << CP0St_KX), - [CP0SC_AM_MK] =3D (1u << CP0St_KX), - [CP0SC_AM_MSK] =3D (1u << CP0St_SX), - [CP0SC_AM_MUSK] =3D (1u << CP0St_UX), - [CP0SC_AM_MUSUK] =3D (1u << CP0St_UX), - [CP0SC_AM_USK] =3D (1u << CP0St_SX), - [6] =3D (1u << CP0St_KX), - [CP0SC_AM_UUSK] =3D (1u << CP0St_UX), - }; - unsigned int am =3D CP0SC_AM_UK; - unsigned int xr =3D (env->CP0_SegCtl2 & CP0SC2_XR_MASK) >> CP0= SC2_XR; - - if (xr & (1 << ((address >> 59) & 0x7))) { - am =3D (env->CP0_SegCtl1 & CP0SC1_XAM_MASK) >> CP0SC1_XAM; - } - /* Does CP0_Status.KX/SX/UX permit the access mode (am) */ - if (env->CP0_Status & am_ksux[am]) { - ret =3D get_seg_physical_address(env, physical, prot, - real_address, access_type, - mmu_idx, am, false, env->PA= Mask, - 0); - } else { - ret =3D TLBRET_BADADDR; - } - } else { - ret =3D TLBRET_BADADDR; - } - } else if (address < 0xFFFFFFFF80000000ULL) { - /* xkseg */ - if (kernel_mode && KX && - address <=3D (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) { - ret =3D env->tlb->map_address(env, physical, prot, - real_address, access_type); - } else { - ret =3D TLBRET_BADADDR; - } -#endif - } else if (address < KSEG1_BASE) { - /* kseg0 */ - ret =3D get_segctl_physical_address(env, physical, prot, real_addr= ess, - access_type, mmu_idx, - env->CP0_SegCtl1 >> 16, 0x1FFFFF= FF); - } else if (address < KSEG2_BASE) { - /* kseg1 */ - ret =3D get_segctl_physical_address(env, physical, prot, real_addr= ess, - access_type, mmu_idx, - env->CP0_SegCtl1, 0x1FFFFFFF); - } else if (address < KSEG3_BASE) { - /* sseg (kseg2) */ - ret =3D get_segctl_physical_address(env, physical, prot, real_addr= ess, - access_type, mmu_idx, - env->CP0_SegCtl0 >> 16, 0x1FFFFF= FF); - } else { - /* - * kseg3 - * XXX: debug segment is not emulated - */ - ret =3D get_segctl_physical_address(env, physical, prot, real_addr= ess, - access_type, mmu_idx, - env->CP0_SegCtl0, 0x1FFFFFFF); - } - return ret; -} - void cpu_mips_tlb_flush(CPUMIPSState *env) { /* Flush qemu's TLB and discard all shadowed entries. */ @@ -482,20 +242,6 @@ static void raise_mmu_exception(CPUMIPSState *env, tar= get_ulong address, env->error_code =3D error_code; } =20 -hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) -{ - MIPSCPU *cpu =3D MIPS_CPU(cs); - CPUMIPSState *env =3D &cpu->env; - hwaddr phys_addr; - int prot; - - if (get_physical_address(env, &phys_addr, &prot, addr, MMU_DATA_LOAD, - cpu_mmu_index(env, false)) !=3D 0) { - return -1; - } - return phys_addr; -} - #if !defined(TARGET_MIPS64) =20 /* diff --git a/target/mips/sysemu/meson.build b/target/mips/sysemu/meson.build index f2a1ff46081..925ceeaa449 100644 --- a/target/mips/sysemu/meson.build +++ b/target/mips/sysemu/meson.build @@ -2,4 +2,5 @@ 'addr.c', 'cp0_timer.c', 'machine.c', + 'physaddr.c', )) --=20 2.26.3 From nobody Mon Feb 9 10:44:55 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) client-ip=209.85.221.53; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f53.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1618786343; cv=none; d=zohomail.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/internal.h | 4 ---- target/mips/tcg/tcg-internal.h | 9 +++++++++ 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 8789ffb319f..d7980ba9a94 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -165,7 +165,6 @@ void r4k_helper_tlbr(CPUMIPSState *env); void r4k_helper_tlbinv(CPUMIPSState *env); void r4k_helper_tlbinvf(CPUMIPSState *env); void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra); -uint32_t cpu_mips_get_random(CPUMIPSState *env); =20 void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, @@ -237,9 +236,6 @@ void cpu_mips_stop_count(CPUMIPSState *env); /* helper.c */ void mmu_init(CPUMIPSState *env, const mips_def_t *def); =20 -/* op_helper.c */ -void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagema= sk); - static inline void mips_cpu_set_error_pc(CPUMIPSState *env, target_ulong error_pc) { diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h index 24438667f47..b65580af211 100644 --- a/target/mips/tcg/tcg-internal.h +++ b/target/mips/tcg/tcg-internal.h @@ -11,10 +11,19 @@ #define MIPS_TCG_INTERNAL_H =20 #include "hw/core/cpu.h" +#include "cpu.h" =20 void mips_cpu_do_interrupt(CPUState *cpu); bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); =20 +#if !defined(CONFIG_USER_ONLY) + +void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagema= sk); + +uint32_t cpu_mips_get_random(CPUMIPSState *env); + +#endif /* !CONFIG_USER_ONLY */ + #endif --=20 2.26.3 From nobody Mon Feb 9 10:44:55 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.49 as permitted sender) client-ip=209.85.221.49; envelope-from=philippe.mathieu.daude@gmail.com; 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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id n3sm17438556wmi.7.2021.04.18.15.52.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Apr 2021 15:52:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6UxTKXRxuot4qtym0x1rtyheQvSg7jsP95LgFetkf9k=; b=ndxV8z7/aMOQDhlGCFpDvxfC7xouFF7US4fjgahMh264gtqMAmj+5p9jgPDYh+5AIQ /5I3FPLd7qo1el+BlHkNZXU22U5PPTjLO/m+h397j58hUB2BW5zQFkrnBO9ueda8Y+3h clT/eUzg1FVT1ktu5YbB1p6j9/hdV2rrfa5pA6Qdm6BFRX2LEH5BqiQJmLGZHc0OYqgI 1VpKmv6rlrftx6PfaAef+ww6l/R47iE/HnEzGEJ6DpDYtTIKaC57VZEkl5YakL14iRhP jsLs5U5afj3mD7g7aC79ZI0UFCkXBYz4N/5z7zgNDbMiTXaYIw5gxNKxQzTtznAxD/ef AnRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=6UxTKXRxuot4qtym0x1rtyheQvSg7jsP95LgFetkf9k=; b=kW5SkZtMJD8pA9R2cqTo3vjVgp30loztRIvuw1VJTSD9GDzXGNUObQ7+nrOAQKoAmL hMdcgAl7czpmNPsGkn7m3n+5fWsyhz9PgpWOAdh9vhHBa7hHgdX9IYrGUjukaK8+3ljq OfFprV5C3D5xCrC7lGCmwmmTz89WebIAispvi9ilx53EQ/PSklv7eNQPMqDrpwrE4Lmi z9CIHu5yiy4zLP2pgb4mMqGQ5NuC8Pszen+LpLCis+IEuxCSlkpm+/91BwOXO0jJM6iX stA+PjrpWSluEiiw6k2CeGdXN04eYaBK5ilc3Yc5vprHqttOKGn75h1vdC2Gs4pEWZNh zVHQ== X-Gm-Message-State: AOAM531uQORFx/F818m1YYNFdxkt/FJyRwumsE72sjWAqDS7piEtcxTb aTVRnIgv39sJwGLPRoOCWdc= X-Google-Smtp-Source: ABdhPJxcC+/wbMI7hTedGkvFGolYINRjvgkj0PfyorIKRgODDtlAIuYO3l/bRj7yUyuYFjndR+TCxQ== X-Received: by 2002:a5d:400d:: with SMTP id n13mr10823558wrp.372.1618786346335; Sun, 18 Apr 2021 15:52:26 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen , Jiaxun Yang , Aleksandar Rikalo Subject: [PATCH v2 18/29] target/mips: Move sysemu TCG-specific code to tcg/sysemu/ subfolder Date: Mon, 19 Apr 2021 00:50:47 +0200 Message-Id: <20210418225058.1257014-19-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210418225058.1257014-1-f4bug@amsat.org> References: <20210418225058.1257014-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Move cp0_helper.c and mips-semi.c to the new tcg/sysemu/ folder, adapting the Meson machinery. Move the opcode definitions to tcg/sysemu_helper.h.inc. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/helper.h | 166 +-------------------- target/mips/tcg/sysemu_helper.h.inc | 168 ++++++++++++++++++++++ target/mips/{ =3D> tcg/sysemu}/cp0_helper.c | 0 target/mips/{ =3D> tcg/sysemu}/mips-semi.c | 0 target/mips/meson.build | 5 - target/mips/tcg/meson.build | 3 + target/mips/tcg/sysemu/meson.build | 4 + 7 files changed, 179 insertions(+), 167 deletions(-) create mode 100644 target/mips/tcg/sysemu_helper.h.inc rename target/mips/{ =3D> tcg/sysemu}/cp0_helper.c (100%) rename target/mips/{ =3D> tcg/sysemu}/mips-semi.c (100%) create mode 100644 target/mips/tcg/sysemu/meson.build diff --git a/target/mips/helper.h b/target/mips/helper.h index 709494445dd..bc308e5db13 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -2,10 +2,6 @@ DEF_HELPER_3(raise_exception_err, noreturn, env, i32, int) DEF_HELPER_2(raise_exception, noreturn, env, i32) DEF_HELPER_1(raise_exception_debug, noreturn, env) =20 -#ifndef CONFIG_USER_ONLY -DEF_HELPER_1(do_semihosting, void, env) -#endif - #ifdef TARGET_MIPS64 DEF_HELPER_4(sdl, void, env, tl, tl, int) DEF_HELPER_4(sdr, void, env, tl, tl, int) @@ -42,164 +38,6 @@ DEF_HELPER_FLAGS_1(dbitswap, TCG_CALL_NO_RWG_SE, tl, tl) =20 DEF_HELPER_FLAGS_4(rotx, TCG_CALL_NO_RWG_SE, tl, tl, i32, i32, i32) =20 -#ifndef CONFIG_USER_ONLY -/* CP0 helpers */ -DEF_HELPER_1(mfc0_mvpcontrol, tl, env) -DEF_HELPER_1(mfc0_mvpconf0, tl, env) -DEF_HELPER_1(mfc0_mvpconf1, tl, env) -DEF_HELPER_1(mftc0_vpecontrol, tl, env) -DEF_HELPER_1(mftc0_vpeconf0, tl, env) -DEF_HELPER_1(mfc0_random, tl, env) -DEF_HELPER_1(mfc0_tcstatus, tl, env) -DEF_HELPER_1(mftc0_tcstatus, tl, env) -DEF_HELPER_1(mfc0_tcbind, tl, env) -DEF_HELPER_1(mftc0_tcbind, tl, env) -DEF_HELPER_1(mfc0_tcrestart, tl, env) -DEF_HELPER_1(mftc0_tcrestart, tl, env) -DEF_HELPER_1(mfc0_tchalt, tl, env) -DEF_HELPER_1(mftc0_tchalt, tl, env) -DEF_HELPER_1(mfc0_tccontext, tl, env) -DEF_HELPER_1(mftc0_tccontext, tl, env) -DEF_HELPER_1(mfc0_tcschedule, tl, env) -DEF_HELPER_1(mftc0_tcschedule, tl, env) -DEF_HELPER_1(mfc0_tcschefback, tl, env) -DEF_HELPER_1(mftc0_tcschefback, tl, env) -DEF_HELPER_1(mfc0_count, tl, env) -DEF_HELPER_1(mfc0_saar, tl, env) -DEF_HELPER_1(mfhc0_saar, tl, env) -DEF_HELPER_1(mftc0_entryhi, tl, env) -DEF_HELPER_1(mftc0_status, tl, env) -DEF_HELPER_1(mftc0_cause, tl, env) -DEF_HELPER_1(mftc0_epc, tl, env) -DEF_HELPER_1(mftc0_ebase, tl, env) -DEF_HELPER_2(mftc0_configx, tl, env, tl) -DEF_HELPER_1(mfc0_lladdr, tl, env) -DEF_HELPER_1(mfc0_maar, tl, env) -DEF_HELPER_1(mfhc0_maar, tl, env) -DEF_HELPER_2(mfc0_watchlo, tl, env, i32) -DEF_HELPER_2(mfc0_watchhi, tl, env, i32) -DEF_HELPER_2(mfhc0_watchhi, tl, env, i32) -DEF_HELPER_1(mfc0_debug, tl, env) -DEF_HELPER_1(mftc0_debug, tl, env) -#ifdef TARGET_MIPS64 -DEF_HELPER_1(dmfc0_tcrestart, tl, env) -DEF_HELPER_1(dmfc0_tchalt, tl, env) -DEF_HELPER_1(dmfc0_tccontext, tl, env) -DEF_HELPER_1(dmfc0_tcschedule, tl, env) -DEF_HELPER_1(dmfc0_tcschefback, tl, env) -DEF_HELPER_1(dmfc0_lladdr, tl, env) -DEF_HELPER_1(dmfc0_maar, tl, env) -DEF_HELPER_2(dmfc0_watchlo, tl, env, i32) -DEF_HELPER_2(dmfc0_watchhi, tl, env, i32) -DEF_HELPER_1(dmfc0_saar, tl, env) -#endif /* TARGET_MIPS64 */ - -DEF_HELPER_2(mtc0_index, void, env, tl) -DEF_HELPER_2(mtc0_mvpcontrol, void, env, tl) -DEF_HELPER_2(mtc0_vpecontrol, void, env, tl) -DEF_HELPER_2(mttc0_vpecontrol, void, env, tl) -DEF_HELPER_2(mtc0_vpeconf0, void, env, tl) -DEF_HELPER_2(mttc0_vpeconf0, void, env, tl) -DEF_HELPER_2(mtc0_vpeconf1, void, env, tl) -DEF_HELPER_2(mtc0_yqmask, void, env, tl) -DEF_HELPER_2(mtc0_vpeopt, void, env, tl) -DEF_HELPER_2(mtc0_entrylo0, void, env, tl) -DEF_HELPER_2(mtc0_tcstatus, void, env, tl) -DEF_HELPER_2(mttc0_tcstatus, void, env, tl) -DEF_HELPER_2(mtc0_tcbind, void, env, tl) -DEF_HELPER_2(mttc0_tcbind, void, env, tl) -DEF_HELPER_2(mtc0_tcrestart, void, env, tl) -DEF_HELPER_2(mttc0_tcrestart, void, env, tl) -DEF_HELPER_2(mtc0_tchalt, void, env, tl) -DEF_HELPER_2(mttc0_tchalt, void, env, tl) -DEF_HELPER_2(mtc0_tccontext, void, env, tl) -DEF_HELPER_2(mttc0_tccontext, void, env, tl) -DEF_HELPER_2(mtc0_tcschedule, void, env, tl) -DEF_HELPER_2(mttc0_tcschedule, void, env, tl) -DEF_HELPER_2(mtc0_tcschefback, void, env, tl) -DEF_HELPER_2(mttc0_tcschefback, void, env, tl) -DEF_HELPER_2(mtc0_entrylo1, void, env, tl) -DEF_HELPER_2(mtc0_context, void, env, tl) -DEF_HELPER_2(mtc0_memorymapid, void, env, tl) -DEF_HELPER_2(mtc0_pagemask, void, env, tl) -DEF_HELPER_2(mtc0_pagegrain, void, env, tl) -DEF_HELPER_2(mtc0_segctl0, void, env, tl) -DEF_HELPER_2(mtc0_segctl1, void, env, tl) -DEF_HELPER_2(mtc0_segctl2, void, env, tl) -DEF_HELPER_2(mtc0_pwfield, void, env, tl) -DEF_HELPER_2(mtc0_pwsize, void, env, tl) -DEF_HELPER_2(mtc0_wired, void, env, tl) -DEF_HELPER_2(mtc0_srsconf0, void, env, tl) -DEF_HELPER_2(mtc0_srsconf1, void, env, tl) -DEF_HELPER_2(mtc0_srsconf2, void, env, tl) -DEF_HELPER_2(mtc0_srsconf3, void, env, tl) -DEF_HELPER_2(mtc0_srsconf4, void, env, tl) -DEF_HELPER_2(mtc0_hwrena, void, env, tl) -DEF_HELPER_2(mtc0_pwctl, void, env, tl) -DEF_HELPER_2(mtc0_count, void, env, tl) -DEF_HELPER_2(mtc0_saari, void, env, tl) -DEF_HELPER_2(mtc0_saar, void, env, tl) -DEF_HELPER_2(mthc0_saar, void, env, tl) -DEF_HELPER_2(mtc0_entryhi, void, env, tl) -DEF_HELPER_2(mttc0_entryhi, void, env, tl) -DEF_HELPER_2(mtc0_compare, void, env, tl) -DEF_HELPER_2(mtc0_status, void, env, tl) -DEF_HELPER_2(mttc0_status, void, env, tl) -DEF_HELPER_2(mtc0_intctl, void, env, tl) -DEF_HELPER_2(mtc0_srsctl, void, env, tl) -DEF_HELPER_2(mtc0_cause, void, env, tl) -DEF_HELPER_2(mttc0_cause, void, env, tl) -DEF_HELPER_2(mtc0_ebase, void, env, tl) -DEF_HELPER_2(mttc0_ebase, void, env, tl) -DEF_HELPER_2(mtc0_config0, void, env, tl) -DEF_HELPER_2(mtc0_config2, void, env, tl) -DEF_HELPER_2(mtc0_config3, void, env, tl) -DEF_HELPER_2(mtc0_config4, void, env, tl) -DEF_HELPER_2(mtc0_config5, void, env, tl) -DEF_HELPER_2(mtc0_lladdr, void, env, tl) -DEF_HELPER_2(mtc0_maar, void, env, tl) -DEF_HELPER_2(mthc0_maar, void, env, tl) -DEF_HELPER_2(mtc0_maari, void, env, tl) -DEF_HELPER_3(mtc0_watchlo, void, env, tl, i32) -DEF_HELPER_3(mtc0_watchhi, void, env, tl, i32) -DEF_HELPER_3(mthc0_watchhi, void, env, tl, i32) -DEF_HELPER_2(mtc0_xcontext, void, env, tl) -DEF_HELPER_2(mtc0_framemask, void, env, tl) -DEF_HELPER_2(mtc0_debug, void, env, tl) -DEF_HELPER_2(mttc0_debug, void, env, tl) -DEF_HELPER_2(mtc0_performance0, void, env, tl) -DEF_HELPER_2(mtc0_errctl, void, env, tl) -DEF_HELPER_2(mtc0_taglo, void, env, tl) -DEF_HELPER_2(mtc0_datalo, void, env, tl) -DEF_HELPER_2(mtc0_taghi, void, env, tl) -DEF_HELPER_2(mtc0_datahi, void, env, tl) - -#if defined(TARGET_MIPS64) -DEF_HELPER_2(dmtc0_entrylo0, void, env, i64) -DEF_HELPER_2(dmtc0_entrylo1, void, env, i64) -#endif - -/* MIPS MT functions */ -DEF_HELPER_2(mftgpr, tl, env, i32) -DEF_HELPER_2(mftlo, tl, env, i32) -DEF_HELPER_2(mfthi, tl, env, i32) -DEF_HELPER_2(mftacx, tl, env, i32) -DEF_HELPER_1(mftdsp, tl, env) -DEF_HELPER_3(mttgpr, void, env, tl, i32) -DEF_HELPER_3(mttlo, void, env, tl, i32) -DEF_HELPER_3(mtthi, void, env, tl, i32) -DEF_HELPER_3(mttacx, void, env, tl, i32) -DEF_HELPER_2(mttdsp, void, env, tl) -DEF_HELPER_0(dmt, tl) -DEF_HELPER_0(emt, tl) -DEF_HELPER_1(dvpe, tl, env) -DEF_HELPER_1(evpe, tl, env) - -/* R6 Multi-threading */ -DEF_HELPER_1(dvp, tl, env) -DEF_HELPER_1(evp, tl, env) -#endif /* !CONFIG_USER_ONLY */ - /* microMIPS functions */ DEF_HELPER_4(lwm, void, env, tl, tl, i32) DEF_HELPER_4(swm, void, env, tl, tl, i32) @@ -783,4 +621,8 @@ DEF_HELPER_FLAGS_2(rddsp, 0, tl, tl, env) =20 DEF_HELPER_3(cache, void, env, tl, i32) =20 +#ifndef CONFIG_USER_ONLY +#include "tcg/sysemu_helper.h.inc" +#endif /* !CONFIG_USER_ONLY */ + #include "msa_helper.h.inc" diff --git a/target/mips/tcg/sysemu_helper.h.inc b/target/mips/tcg/sysemu_h= elper.h.inc new file mode 100644 index 00000000000..d136c4160a7 --- /dev/null +++ b/target/mips/tcg/sysemu_helper.h.inc @@ -0,0 +1,168 @@ +/* + * QEMU MIPS sysemu helpers + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * Copyright (c) 2006 Marius Groeger (FPU operations) + * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support) + * Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support) + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +DEF_HELPER_1(do_semihosting, void, env) + +/* CP0 helpers */ +DEF_HELPER_1(mfc0_mvpcontrol, tl, env) +DEF_HELPER_1(mfc0_mvpconf0, tl, env) +DEF_HELPER_1(mfc0_mvpconf1, tl, env) +DEF_HELPER_1(mftc0_vpecontrol, tl, env) +DEF_HELPER_1(mftc0_vpeconf0, tl, env) +DEF_HELPER_1(mfc0_random, tl, env) +DEF_HELPER_1(mfc0_tcstatus, tl, env) +DEF_HELPER_1(mftc0_tcstatus, tl, env) +DEF_HELPER_1(mfc0_tcbind, tl, env) +DEF_HELPER_1(mftc0_tcbind, tl, env) +DEF_HELPER_1(mfc0_tcrestart, tl, env) +DEF_HELPER_1(mftc0_tcrestart, tl, env) +DEF_HELPER_1(mfc0_tchalt, tl, env) +DEF_HELPER_1(mftc0_tchalt, tl, env) +DEF_HELPER_1(mfc0_tccontext, tl, env) +DEF_HELPER_1(mftc0_tccontext, tl, env) +DEF_HELPER_1(mfc0_tcschedule, tl, env) +DEF_HELPER_1(mftc0_tcschedule, tl, env) +DEF_HELPER_1(mfc0_tcschefback, tl, env) +DEF_HELPER_1(mftc0_tcschefback, tl, env) +DEF_HELPER_1(mfc0_count, tl, env) +DEF_HELPER_1(mfc0_saar, tl, env) +DEF_HELPER_1(mfhc0_saar, tl, env) +DEF_HELPER_1(mftc0_entryhi, tl, env) +DEF_HELPER_1(mftc0_status, tl, env) +DEF_HELPER_1(mftc0_cause, tl, env) +DEF_HELPER_1(mftc0_epc, tl, env) +DEF_HELPER_1(mftc0_ebase, tl, env) +DEF_HELPER_2(mftc0_configx, tl, env, tl) +DEF_HELPER_1(mfc0_lladdr, tl, env) +DEF_HELPER_1(mfc0_maar, tl, env) +DEF_HELPER_1(mfhc0_maar, tl, env) +DEF_HELPER_2(mfc0_watchlo, tl, env, i32) +DEF_HELPER_2(mfc0_watchhi, tl, env, i32) +DEF_HELPER_2(mfhc0_watchhi, tl, env, i32) +DEF_HELPER_1(mfc0_debug, tl, env) +DEF_HELPER_1(mftc0_debug, tl, env) +#ifdef TARGET_MIPS64 +DEF_HELPER_1(dmfc0_tcrestart, tl, env) +DEF_HELPER_1(dmfc0_tchalt, tl, env) +DEF_HELPER_1(dmfc0_tccontext, tl, env) +DEF_HELPER_1(dmfc0_tcschedule, tl, env) +DEF_HELPER_1(dmfc0_tcschefback, tl, env) +DEF_HELPER_1(dmfc0_lladdr, tl, env) +DEF_HELPER_1(dmfc0_maar, tl, env) +DEF_HELPER_2(dmfc0_watchlo, tl, env, i32) +DEF_HELPER_2(dmfc0_watchhi, tl, env, i32) +DEF_HELPER_1(dmfc0_saar, tl, env) +#endif /* TARGET_MIPS64 */ + +DEF_HELPER_2(mtc0_index, void, env, tl) +DEF_HELPER_2(mtc0_mvpcontrol, void, env, tl) +DEF_HELPER_2(mtc0_vpecontrol, void, env, tl) +DEF_HELPER_2(mttc0_vpecontrol, void, env, tl) +DEF_HELPER_2(mtc0_vpeconf0, void, env, tl) +DEF_HELPER_2(mttc0_vpeconf0, void, env, tl) +DEF_HELPER_2(mtc0_vpeconf1, void, env, tl) +DEF_HELPER_2(mtc0_yqmask, void, env, tl) +DEF_HELPER_2(mtc0_vpeopt, void, env, tl) +DEF_HELPER_2(mtc0_entrylo0, void, env, tl) +DEF_HELPER_2(mtc0_tcstatus, void, env, tl) +DEF_HELPER_2(mttc0_tcstatus, void, env, tl) +DEF_HELPER_2(mtc0_tcbind, void, env, tl) +DEF_HELPER_2(mttc0_tcbind, void, env, tl) +DEF_HELPER_2(mtc0_tcrestart, void, env, tl) +DEF_HELPER_2(mttc0_tcrestart, void, env, tl) +DEF_HELPER_2(mtc0_tchalt, void, env, tl) +DEF_HELPER_2(mttc0_tchalt, void, env, tl) +DEF_HELPER_2(mtc0_tccontext, void, env, tl) +DEF_HELPER_2(mttc0_tccontext, void, env, tl) +DEF_HELPER_2(mtc0_tcschedule, void, env, tl) +DEF_HELPER_2(mttc0_tcschedule, void, env, tl) +DEF_HELPER_2(mtc0_tcschefback, void, env, tl) +DEF_HELPER_2(mttc0_tcschefback, void, env, tl) +DEF_HELPER_2(mtc0_entrylo1, void, env, tl) +DEF_HELPER_2(mtc0_context, void, env, tl) +DEF_HELPER_2(mtc0_memorymapid, void, env, tl) +DEF_HELPER_2(mtc0_pagemask, void, env, tl) +DEF_HELPER_2(mtc0_pagegrain, void, env, tl) +DEF_HELPER_2(mtc0_segctl0, void, env, tl) +DEF_HELPER_2(mtc0_segctl1, void, env, tl) +DEF_HELPER_2(mtc0_segctl2, void, env, tl) +DEF_HELPER_2(mtc0_pwfield, void, env, tl) +DEF_HELPER_2(mtc0_pwsize, void, env, tl) +DEF_HELPER_2(mtc0_wired, void, env, tl) +DEF_HELPER_2(mtc0_srsconf0, void, env, tl) +DEF_HELPER_2(mtc0_srsconf1, void, env, tl) +DEF_HELPER_2(mtc0_srsconf2, void, env, tl) +DEF_HELPER_2(mtc0_srsconf3, void, env, tl) +DEF_HELPER_2(mtc0_srsconf4, void, env, tl) +DEF_HELPER_2(mtc0_hwrena, void, env, tl) +DEF_HELPER_2(mtc0_pwctl, void, env, tl) +DEF_HELPER_2(mtc0_count, void, env, tl) +DEF_HELPER_2(mtc0_saari, void, env, tl) +DEF_HELPER_2(mtc0_saar, void, env, tl) +DEF_HELPER_2(mthc0_saar, void, env, tl) +DEF_HELPER_2(mtc0_entryhi, void, env, tl) +DEF_HELPER_2(mttc0_entryhi, void, env, tl) +DEF_HELPER_2(mtc0_compare, void, env, tl) +DEF_HELPER_2(mtc0_status, void, env, tl) +DEF_HELPER_2(mttc0_status, void, env, tl) +DEF_HELPER_2(mtc0_intctl, void, env, tl) +DEF_HELPER_2(mtc0_srsctl, void, env, tl) +DEF_HELPER_2(mtc0_cause, void, env, tl) +DEF_HELPER_2(mttc0_cause, void, env, tl) +DEF_HELPER_2(mtc0_ebase, void, env, tl) +DEF_HELPER_2(mttc0_ebase, void, env, tl) +DEF_HELPER_2(mtc0_config0, void, env, tl) +DEF_HELPER_2(mtc0_config2, void, env, tl) +DEF_HELPER_2(mtc0_config3, void, env, tl) +DEF_HELPER_2(mtc0_config4, void, env, tl) +DEF_HELPER_2(mtc0_config5, void, env, tl) +DEF_HELPER_2(mtc0_lladdr, void, env, tl) +DEF_HELPER_2(mtc0_maar, void, env, tl) +DEF_HELPER_2(mthc0_maar, void, env, tl) +DEF_HELPER_2(mtc0_maari, void, env, tl) +DEF_HELPER_3(mtc0_watchlo, void, env, tl, i32) +DEF_HELPER_3(mtc0_watchhi, void, env, tl, i32) +DEF_HELPER_3(mthc0_watchhi, void, env, tl, i32) +DEF_HELPER_2(mtc0_xcontext, void, env, tl) +DEF_HELPER_2(mtc0_framemask, void, env, tl) +DEF_HELPER_2(mtc0_debug, void, env, tl) +DEF_HELPER_2(mttc0_debug, void, env, tl) +DEF_HELPER_2(mtc0_performance0, void, env, tl) +DEF_HELPER_2(mtc0_errctl, void, env, tl) +DEF_HELPER_2(mtc0_taglo, void, env, tl) +DEF_HELPER_2(mtc0_datalo, void, env, tl) +DEF_HELPER_2(mtc0_taghi, void, env, tl) +DEF_HELPER_2(mtc0_datahi, void, env, tl) + +#if defined(TARGET_MIPS64) +DEF_HELPER_2(dmtc0_entrylo0, void, env, i64) +DEF_HELPER_2(dmtc0_entrylo1, void, env, i64) +#endif + +/* MIPS MT functions */ +DEF_HELPER_2(mftgpr, tl, env, i32) +DEF_HELPER_2(mftlo, tl, env, i32) +DEF_HELPER_2(mfthi, tl, env, i32) +DEF_HELPER_2(mftacx, tl, env, i32) +DEF_HELPER_1(mftdsp, tl, env) +DEF_HELPER_3(mttgpr, void, env, tl, i32) +DEF_HELPER_3(mttlo, void, env, tl, i32) +DEF_HELPER_3(mtthi, void, env, tl, i32) +DEF_HELPER_3(mttacx, void, env, tl, i32) +DEF_HELPER_2(mttdsp, void, env, tl) +DEF_HELPER_0(dmt, tl) +DEF_HELPER_0(emt, tl) +DEF_HELPER_1(dvpe, tl, env) +DEF_HELPER_1(evpe, tl, env) + +/* R6 Multi-threading */ +DEF_HELPER_1(dvp, tl, env) +DEF_HELPER_1(evp, tl, env) diff --git a/target/mips/cp0_helper.c b/target/mips/tcg/sysemu/cp0_helper.c similarity index 100% rename from target/mips/cp0_helper.c rename to target/mips/tcg/sysemu/cp0_helper.c diff --git a/target/mips/mips-semi.c b/target/mips/tcg/sysemu/mips-semi.c similarity index 100% rename from target/mips/mips-semi.c rename to target/mips/tcg/sysemu/mips-semi.c diff --git a/target/mips/meson.build b/target/mips/meson.build index 9a507937ece..a55af1cd6cf 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -47,11 +47,6 @@ =20 mips_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) =20 -mips_softmmu_ss.add(when: 'CONFIG_TCG', if_true: files( - 'cp0_helper.c', - 'mips-semi.c', -)) - mips_ss.add_all(when: 'CONFIG_TCG', if_true: [mips_tcg_ss]) =20 target_arch +=3D {'mips': mips_ss} diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build index b74fa04303e..2cffc5a5ac6 100644 --- a/target/mips/tcg/meson.build +++ b/target/mips/tcg/meson.build @@ -1,3 +1,6 @@ if have_user subdir('user') endif +if have_system + subdir('sysemu') +endif diff --git a/target/mips/tcg/sysemu/meson.build b/target/mips/tcg/sysemu/me= son.build new file mode 100644 index 00000000000..5c3024e7760 --- /dev/null +++ b/target/mips/tcg/sysemu/meson.build @@ -0,0 +1,4 @@ +mips_softmmu_ss.add(files( + 'cp0_helper.c', + 'mips-semi.c', +)) --=20 2.26.3 From nobody Mon Feb 9 10:44:55 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.46 as permitted sender) client-ip=209.85.128.46; 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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id l25sm12908901wmi.17.2021.04.18.15.52.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Apr 2021 15:52:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0RTWbP4MmlnppIWfa0PRIL4VrYTBFtlHQvR22xPFBSg=; b=ghKd8DfPOOGJNDSa6uPiKOKKbh1tiINtd7eUpl23wEoKPhu2mNV/kUbepxJPtZ5rmt Y7BDc11t2Vsu2nU9B7/9yErqsWRLE6oR/PG3PBHQcELa6Yy3RHSRp9DGPaU91REJe8Za q6IYgTm1Z5cA3HHBPh8cE5uaYfqJX27Udpyd39gbiypCpz/824DHp1CLBMPN4WheLRuF B/pHN6c0mX0tgXXNVUZ55Z+VGOzweh6MyFlDIUm8wyUZtHEai29nCVBSG4LArsw5u7c5 BqGMa2aWY10uOEeF53lZ1BZtEuNr93GlT/0iyuhY4YPTUvaz4r69PWXw8wm49OMtrwOX PlIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=0RTWbP4MmlnppIWfa0PRIL4VrYTBFtlHQvR22xPFBSg=; b=GKwDV6CRkwKS/LuiX0ipBOMa8DRfCSrRwlN8iD/sebZB3CbtJDkA+HppntCSSJo7AV NHpPanqZ4PHmIzYCwi3CEp+FrgL37H3Xpt/SEwdSpBhvzH9Eo0ohWYfpvrHwAFIt421U RsX7FqIuk2lQ1qwEwt2qIqmXswwn0EavV+JwBeVgD15k9W9B7hHb+lNYXGrNojDlty+v 1HdLhTpsOPzr64KbR0cmzpBsBuMUAR66s4i0Q5fkdMetQqCi62zqyFjFQtytSdm1SeFt +n4LTfc2J1jn8pIZS2DD+KhloBtVwHQ9Vtm5z/5PQTw9S81ZFKDa3BxrchzC+G03nkif uWEg== X-Gm-Message-State: AOAM5302F8997cAAFJLgfB6ANxxU0TMQcOd0q4GHjN1njyUfSqIJfil6 xvN+33TC+H/BzPHTWC8G78s= X-Google-Smtp-Source: ABdhPJykJCH7zuiWqXWwE5JjOOWpN/WSfI4RoaZ62b6Q228eS3xsw9DCJf1aRh2Sn6VZENtv3ZARog== X-Received: by 2002:a1c:7f4a:: with SMTP id a71mr18680917wmd.1.1618786351062; Sun, 18 Apr 2021 15:52:31 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen , Jiaxun Yang , Aleksandar Rikalo Subject: [PATCH v2 19/29] target/mips: Restrict mmu_init() to TCG Date: Mon, 19 Apr 2021 00:50:48 +0200 Message-Id: <20210418225058.1257014-20-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210418225058.1257014-1-f4bug@amsat.org> References: <20210418225058.1257014-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) mmu_init() is only required by TCG accelerator. Restrict its declaration and call to TCG. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/internal.h | 3 --- target/mips/tcg/tcg-internal.h | 2 ++ target/mips/cpu.c | 2 +- 3 files changed, 3 insertions(+), 4 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index d7980ba9a94..548fd73c7cc 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -233,9 +233,6 @@ void cpu_mips_store_compare(CPUMIPSState *env, uint32_t= value); void cpu_mips_start_count(CPUMIPSState *env); void cpu_mips_stop_count(CPUMIPSState *env); =20 -/* helper.c */ -void mmu_init(CPUMIPSState *env, const mips_def_t *def); - static inline void mips_cpu_set_error_pc(CPUMIPSState *env, target_ulong error_pc) { diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h index b65580af211..70655bab45c 100644 --- a/target/mips/tcg/tcg-internal.h +++ b/target/mips/tcg/tcg-internal.h @@ -20,6 +20,8 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int s= ize, =20 #if !defined(CONFIG_USER_ONLY) =20 +void mmu_init(CPUMIPSState *env, const mips_def_t *def); + void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagema= sk); =20 uint32_t cpu_mips_get_random(CPUMIPSState *env); diff --git a/target/mips/cpu.c b/target/mips/cpu.c index fcbf95c85b9..acc149aa573 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -708,7 +708,7 @@ static void mips_cpu_realizefn(DeviceState *dev, Error = **errp) =20 env->exception_base =3D (int32_t)0xBFC00000; =20 -#ifndef CONFIG_USER_ONLY +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) mmu_init(env, env->cpu_model); #endif fpu_init(env, env->cpu_model); --=20 2.26.3 From nobody Mon Feb 9 10:44:55 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.54 as permitted sender) client-ip=209.85.221.54; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f54.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.54 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1618786357; cv=none; d=zohomail.com; s=zohoarc; b=bgt7bDYpnQ4fRFdzBpN1250PpNDuKlGKPhUVNN/COvpIzPB5Vn+AaWC87zbiQqz+XQNrscKLYEw+uBfaVKbtf0vT55Nr9Q+RW9T6VaoxcR+I7DjaJ8gPoaSeMC7J8aMoSy93na/fY4pdToihwsLY7sZo1nHJUxnjzBnlPI68C+Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618786357; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=TAbY18OM7gttE1UARviOncxkoGhS2U97Q+ixee8Sfbc=; b=YER6eFnbqRDdgSETaFeE0ZQ3ZAKjCEM0y7vT5bGPTtCbQjdgYi1Br89D4bbMGenZ1WIeeAQKUXJfvJUTeUHF00frFEC7eCKHRse7c1Qv/Kr/P9hFfsf13XAUWUOf/AaziNBvo8Qmf05QjBCITj3NKm602bMTA7e6hcpkRmSAwCY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.54 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-wr1-f54.google.com (mail-wr1-f54.google.com [209.85.221.54]) by mx.zohomail.com with SMTPS id 1618786357428840.1289698999683; Sun, 18 Apr 2021 15:52:37 -0700 (PDT) Received: by mail-wr1-f54.google.com with SMTP id x7so32014012wrw.10 for ; Sun, 18 Apr 2021 15:52:36 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id l14sm8914511wrv.94.2021.04.18.15.52.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Apr 2021 15:52:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TAbY18OM7gttE1UARviOncxkoGhS2U97Q+ixee8Sfbc=; b=XD9ZklHGPdgc24woebTt+5K+V2VrdgQ1N5yLKdN4gs8/oA9Q+kRsj9jwTC2wuknwP3 7AH4j3akdo5/51eimBJzmWq+mB5tgDCrovLX9Y2p25w7EPz0Gfk9RWVgfWoYboBGEg+U Ttm698GMQC0YHPnf7gTSp5kHFO6fse49j8IYxMN0clZcfpuQkgEkcerPvsa4/F4mHp8a tCiK96J1pUnRBqgMQlvpJGZFi3ANrpAdSXUiuUmBWmoOt5VKjIzzxgEkqXbFTsO6/6Py nlrLxVcYXLkVDLuhHu+xMt2roWKWrhCRN0FGnMq5OWPQc8jkda6IydQOCwjGA0VsglPL BTPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=TAbY18OM7gttE1UARviOncxkoGhS2U97Q+ixee8Sfbc=; b=Y5J/SYfO4QfBZZoZSAvKEuex5lWIjCzuN+lVZXqLw3K6V7zqHL5HUkIQZ2ZE6vNl8f 75R3Bt1mHROm5wOe81DXonLKL+SflU0AMmGskVZQHR7/5xUfPdmZexsVLc5zaCfoVqSZ xri5gC45q9/HgDQ0cwoPE9KgGbTP2itAJClMkD9m1AJWzxFpBMP02pMMyflBLBVUwNr0 e5OY7gf3B+BzmWW+Ubfk/Qz4JeLQI5fVqN22y318Yj2HJ8jKmHwcYWbLzVAF/yhvzppn Gy4YXxheQ9cHNAuMTNZK79NpzoQYrhqgFs/26VIy7kCUOK2NQa+H2y6MkLcQpiHveHGv yH3w== X-Gm-Message-State: AOAM530MM6zIwXEsPXpgVcWZgPDf5BhgXR9iQcWO0iqWaPpwDD+5U+qX zPD0B4tYX7a9kqQGxzRm9LGgvkW5OkhVyg== X-Google-Smtp-Source: ABdhPJwKUqv8LY+FkVqrx/XvqSCW1cPI5aQ5ForHbuhikMTeo5glWwuWRsq1sorAQfAzbOmGH2NSXg== X-Received: by 2002:adf:8b02:: with SMTP id n2mr10652458wra.259.1618786355733; Sun, 18 Apr 2021 15:52:35 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen , Jiaxun Yang , Aleksandar Rikalo Subject: [PATCH v2 20/29] target/mips: Move tlb_helper.c to tcg/sysemu/ Date: Mon, 19 Apr 2021 00:50:49 +0200 Message-Id: <20210418225058.1257014-21-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210418225058.1257014-1-f4bug@amsat.org> References: <20210418225058.1257014-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Move tlb_helper.c to the tcg/sysemu/ subdir, along with the following 3 declarations to tcg-internal.h: - cpu_mips_tlb_flush() - cpu_mips_translate_address() - r4k_invalidate_tlb() Simplify tlb_helper.c #ifdef'ry because files in tcg/sysemu/ are only build when sysemu mode is configured. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/internal.h | 5 ----- target/mips/tcg/tcg-internal.h | 5 +++++ target/mips/{ =3D> tcg/sysemu}/tlb_helper.c | 3 --- target/mips/meson.build | 1 - target/mips/tcg/sysemu/meson.build | 1 + 5 files changed, 6 insertions(+), 9 deletions(-) rename target/mips/{ =3D> tcg/sysemu}/tlb_helper.c (99%) diff --git a/target/mips/internal.h b/target/mips/internal.h index 548fd73c7cc..df419760df0 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -164,16 +164,12 @@ void r4k_helper_tlbp(CPUMIPSState *env); void r4k_helper_tlbr(CPUMIPSState *env); void r4k_helper_tlbinv(CPUMIPSState *env); void r4k_helper_tlbinvf(CPUMIPSState *env); -void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra); =20 void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retadd= r); -hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, - MMUAccessType access_type); - extern const VMStateDescription vmstate_mips_cpu; =20 #endif /* !CONFIG_USER_ONLY */ @@ -424,7 +420,6 @@ static inline void compute_hflags(CPUMIPSState *env) } } =20 -void cpu_mips_tlb_flush(CPUMIPSState *env); void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc); void cpu_mips_store_status(CPUMIPSState *env, target_ulong val); void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val); diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h index 70655bab45c..6615151cba2 100644 --- a/target/mips/tcg/tcg-internal.h +++ b/target/mips/tcg/tcg-internal.h @@ -24,8 +24,13 @@ void mmu_init(CPUMIPSState *env, const mips_def_t *def); =20 void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagema= sk); =20 +void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra); uint32_t cpu_mips_get_random(CPUMIPSState *env); =20 +hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, + MMUAccessType access_type); +void cpu_mips_tlb_flush(CPUMIPSState *env); + #endif /* !CONFIG_USER_ONLY */ =20 #endif diff --git a/target/mips/tlb_helper.c b/target/mips/tcg/sysemu/tlb_helper.c similarity index 99% rename from target/mips/tlb_helper.c rename to target/mips/tcg/sysemu/tlb_helper.c index 2304fff4c42..82cfb0a9135 100644 --- a/target/mips/tlb_helper.c +++ b/target/mips/tcg/sysemu/tlb_helper.c @@ -25,8 +25,6 @@ #include "exec/log.h" #include "hw/mips/cpudevs.h" =20 -#if !defined(CONFIG_USER_ONLY) - /* no MMU emulation */ int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, target_ulong address, MMUAccessType access_type) @@ -1071,4 +1069,3 @@ void r4k_invalidate_tlb(CPUMIPSState *env, int idx, i= nt use_extra) } } } -#endif /* !CONFIG_USER_ONLY */ diff --git a/target/mips/meson.build b/target/mips/meson.build index a55af1cd6cf..ff5eb210dfd 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -31,7 +31,6 @@ 'msa_translate.c', 'op_helper.c', 'rel6_translate.c', - 'tlb_helper.c', 'translate.c', 'translate_addr_const.c', 'txx9_translate.c', diff --git a/target/mips/tcg/sysemu/meson.build b/target/mips/tcg/sysemu/me= son.build index 5c3024e7760..73ab9571ba6 100644 --- a/target/mips/tcg/sysemu/meson.build +++ b/target/mips/tcg/sysemu/meson.build @@ -1,4 +1,5 @@ mips_softmmu_ss.add(files( 'cp0_helper.c', 'mips-semi.c', + 'tlb_helper.c', )) --=20 2.26.3 From nobody Mon Feb 9 10:44:55 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.46 as permitted sender) client-ip=209.85.128.46; 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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id m14sm1077463wmq.44.2021.04.18.15.52.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Apr 2021 15:52:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Iu+6LDjF0QAs/zLJz5W09HL+Jkckai0YrVB0wfaf53c=; b=XDqiMM1T65Z6hMwGrVA2cPPPiVN4y0x4v4w3afG/QavgXfmclYbHJKOk3uF0oBivPJ 4mrXIueyHdUaUsXVCsia3s+hZ08fLbzOcPYrhy2d5BvZ2XyqFb/SN4oazhiSENAiUN0p X6UlReiqQzJ+5J+EFkzI6HQSmy7WQZ7QyqXQmM3YDL5pOnAG9Kb9a8NIOAKCBRJucy6H +gyoKin29BfEN45ddF0zH6C52ybKNjCXmMRdkiDl85s4vlJ0GGgm5GtdK8M+rd8+Wmg0 Wdv1uwwNW5Urss8Zl46Wl01aGPv55lXgOkgr04NuokKWebLKR4y7HfivW+pqwscTvpZY z2Ew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=Iu+6LDjF0QAs/zLJz5W09HL+Jkckai0YrVB0wfaf53c=; b=BGlUfIYWgZINVryDO1GCm4rFXeCVvX2d/yrVwIHsJV0huxvGpNykeScp9mGkGHZ/H9 NX6ZlSJB5yFh69himeT2Yn9O2Yl6XB1u4Wtx/ev0R9ClZarKeqMDvw2zsOImA4kVqrWK boFXNJQV0HXDBVwtY4D9iVbETIaEF1BBuWk9GofRNswVSFevUWB6TG9hVw/uF4M2bQCm HQ0muDOUBJPyrt/0DdOIvjDrzQoKst4CG5RwrqDj9FE1d431v9dqAqXJg8o6pO5wy6ng 0HF0Uyu62WSae1fB6RjERIS8jzJR4tO1WeYCDwKNGln4KfUToIZ2j9CDZc5kTj3DRhPZ Czog== X-Gm-Message-State: AOAM532N+dze/suQKRHWJp/Pgu4ZpGtH1bA/ZcTf3ZaWrQFLTwaU+Mc2 QQ2aFteeKrCcFotR4IF+Ru8= X-Google-Smtp-Source: ABdhPJyzwJyaPEjhYiDmDqOhznBjrAzJM5iB584bIp3vKJNWVotHczd2JDhDjklrf6o4Bw1S36/D3g== X-Received: by 2002:a1c:2786:: with SMTP id n128mr19022928wmn.82.1618786360415; Sun, 18 Apr 2021 15:52:40 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen , Jiaxun Yang , Aleksandar Rikalo Subject: [PATCH v2 21/29] target/mips: Restrict CPUMIPSTLBContext::map_address() handlers scope Date: Mon, 19 Apr 2021 00:50:50 +0200 Message-Id: <20210418225058.1257014-22-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210418225058.1257014-1-f4bug@amsat.org> References: <20210418225058.1257014-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) The 3 map_address() handlers are local to tlb_helper.c, no need to have their prototype declared publically. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/internal.h | 6 ------ target/mips/tcg/sysemu/tlb_helper.c | 13 +++++++------ 2 files changed, 7 insertions(+), 12 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index df419760df0..a59e2f9007d 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -152,12 +152,6 @@ struct CPUMIPSTLBContext { } mmu; }; =20 -int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, - target_ulong address, MMUAccessType access_type); -int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, - target_ulong address, MMUAccessType access_type); -int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, - target_ulong address, MMUAccessType access_type); void r4k_helper_tlbwi(CPUMIPSState *env); void r4k_helper_tlbwr(CPUMIPSState *env); void r4k_helper_tlbp(CPUMIPSState *env); diff --git a/target/mips/tcg/sysemu/tlb_helper.c b/target/mips/tcg/sysemu/t= lb_helper.c index 82cfb0a9135..cbb4ccf0dac 100644 --- a/target/mips/tcg/sysemu/tlb_helper.c +++ b/target/mips/tcg/sysemu/tlb_helper.c @@ -26,8 +26,8 @@ #include "hw/mips/cpudevs.h" =20 /* no MMU emulation */ -int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, - target_ulong address, MMUAccessType access_type) +static int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *pr= ot, + target_ulong address, MMUAccessType access_t= ype) { *physical =3D address; *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; @@ -35,8 +35,9 @@ int no_mmu_map_address(CPUMIPSState *env, hwaddr *physica= l, int *prot, } =20 /* fixed mapping MMU emulation */ -int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, - target_ulong address, MMUAccessType access_type) +static int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, + int *prot, target_ulong address, + MMUAccessType access_type) { if (address <=3D (int32_t)0x7FFFFFFFUL) { if (!(env->CP0_Status & (1 << CP0St_ERL))) { @@ -55,8 +56,8 @@ int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *phys= ical, int *prot, } =20 /* MIPS32/MIPS64 R4000-style MMU emulation */ -int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, - target_ulong address, MMUAccessType access_type) +static int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, + target_ulong address, MMUAccessType access_type) { uint16_t ASID =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; uint32_t MMID =3D env->CP0_MemoryMapID; --=20 2.26.3 From nobody Mon Feb 9 10:44:55 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.51 as permitted sender) client-ip=209.85.221.51; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f51.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.51 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1618786367; cv=none; d=zohomail.com; s=zohoarc; b=Dt1JhDVbEqStQyDZDiI5bdlNxX3UPAIsv7Kooya8owS5dyMEXVoXb/sg3ffRfn1no7DOO9hnwq2YnnuscdDv/AA5un9RyKQOT2VmSupf0HM2bYYvEl8l6M/mdTgMAhmHGYuKVdgVJS/bc6mGsc+lrxJxeHQ+KeXHb2bFW6KsPvA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618786367; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=hYy/t7i6kODzY1BSbB9g1s+o8ye/dmGSCHqvaGwnVBI=; b=JJ5Un4fZc/BGK6JoUoxO/O6Kqc2g/RjOTJ1T++Eo52Z75fyJkMtKV9TXPxN6IlNRYsEfWsiMNunvIqXFDGGMcBfiSPu0Xq74y9uWOdR+0Voso8pKsIp4VnXTSC/3dDsc2XFFgrEHXc7pvRCrJuoWPsNlmGatPOOTTU8vRl4c9BY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.51 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f51.google.com (mail-wr1-f51.google.com [209.85.221.51]) by mx.zohomail.com with SMTPS id 1618786367151201.3967966814514; Sun, 18 Apr 2021 15:52:47 -0700 (PDT) Received: by mail-wr1-f51.google.com with SMTP id k26so15622818wrc.8 for ; Sun, 18 Apr 2021 15:52:46 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id s64sm17722275wmf.2.2021.04.18.15.52.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Apr 2021 15:52:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hYy/t7i6kODzY1BSbB9g1s+o8ye/dmGSCHqvaGwnVBI=; b=pqkg2yYpEB6FPdtT3wWXVWsiroIWoApa8S+eB73xP9fhRMhq2p8CPCaJev52cJdneH VHm7dpI+Ln+jNZm38np/LH9q7+v0Dbm1rjjpkSkJfSw+b/CBSsxs19ScawTg3S7oMQZt WAzIInk3jFZhzrchgHybofb1zxyqa1IGA+b4uqOwZVI2eekB2g8uLYESqXT2LazN4R9a TfPsMsD6EOxSgf1LTpEHPsKxae+BCnF9FV5qYetZpA6Bv4ytMaopXPaZ23JbuOUHY2er p8WWgKjIR96tCkdCSsyGp2KLRVpMrKyknova1Xz8cCpbfmjMOuibB+Ml8RRnHDoJnTJi jgOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=hYy/t7i6kODzY1BSbB9g1s+o8ye/dmGSCHqvaGwnVBI=; b=jutOfa+5DRgUbBmxjzXTFAlr8y+WHGzFLe70cfStv5LwgStgRhdsJUi6VZs+FPhuvi Qbhy1uEQzRGOHOFQLjGDiguoLjkY4HODoTLfZYluWtwu3W0ajTJCnkTpB95g1heDLfdQ JCjKeTfgZupVzwqPgpsXCSGC9Zjje3aI/ZHc4/PyUzyat7Fzapb0Oha5Jv3YX2vjg/mZ eL0vnts7LKyu6iyvWnd1pq2FuBtqp4kI0XiYPPEIRqjwGe86LiM0MLmi6rDlQ61+yw9s pC0t/Eki4XUBP3xAfKAVCIEfVB/n1OuaOeSTGCCWJmQ54L5g3o6OhsaC6WGX1zEh2R7g MHTg== X-Gm-Message-State: AOAM530G5pe89+d0Ma7JyUenOG/rprJ5PhvPaNeE7WelCJWxLAN3CDzj ZDbQhBSrfkYTWsQHCXbU0Nk= X-Google-Smtp-Source: ABdhPJzOifIpAGHkor6g2ToVSiBji2hV7OH1qjwm+PGlK6mSjV+8kfv6f+DnE2P5d0yH0veJOlicFQ== X-Received: by 2002:a05:6000:18cd:: with SMTP id w13mr10952329wrq.20.1618786365400; Sun, 18 Apr 2021 15:52:45 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen , Jiaxun Yang , Aleksandar Rikalo Subject: [PATCH v2 22/29] target/mips: Move Special opcodes to tcg/sysemu/special_helper.c Date: Mon, 19 Apr 2021 00:50:51 +0200 Message-Id: <20210418225058.1257014-23-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210418225058.1257014-1-f4bug@amsat.org> References: <20210418225058.1257014-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Move the Special opcodes helpers to tcg/sysemu/special_helper.c. Since mips_io_recompile_replay_branch() is set as CPUClass::io_recompile_replay_branch handler in cpu.c, we need to declare its prototype in "tcg-internal.h". Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/helper.h | 5 - target/mips/tcg/tcg-internal.h | 3 + target/mips/tcg/sysemu_helper.h.inc | 7 ++ target/mips/cpu.c | 17 --- target/mips/op_helper.c | 100 ----------------- target/mips/tcg/sysemu/special_helper.c | 140 ++++++++++++++++++++++++ target/mips/tcg/sysemu/meson.build | 1 + 7 files changed, 151 insertions(+), 122 deletions(-) create mode 100644 target/mips/tcg/sysemu/special_helper.c diff --git a/target/mips/helper.h b/target/mips/helper.h index bc308e5db13..4ee7916d8b2 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -210,11 +210,6 @@ DEF_HELPER_1(tlbp, void, env) DEF_HELPER_1(tlbr, void, env) DEF_HELPER_1(tlbinv, void, env) DEF_HELPER_1(tlbinvf, void, env) -DEF_HELPER_1(di, tl, env) -DEF_HELPER_1(ei, tl, env) -DEF_HELPER_1(eret, void, env) -DEF_HELPER_1(eretnc, void, env) -DEF_HELPER_1(deret, void, env) DEF_HELPER_3(ginvt, void, env, tl, i32) #endif /* !CONFIG_USER_ONLY */ DEF_HELPER_1(rdhwr_cpunum, tl, env) diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h index 6615151cba2..e507dd1630f 100644 --- a/target/mips/tcg/tcg-internal.h +++ b/target/mips/tcg/tcg-internal.h @@ -10,6 +10,7 @@ #ifndef MIPS_TCG_INTERNAL_H #define MIPS_TCG_INTERNAL_H =20 +#include "tcg/tcg.h" #include "hw/core/cpu.h" #include "cpu.h" =20 @@ -27,6 +28,8 @@ void update_pagemask(CPUMIPSState *env, target_ulong arg1= , int32_t *pagemask); void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra); uint32_t cpu_mips_get_random(CPUMIPSState *env); =20 +bool mips_io_recompile_replay_branch(CPUState *cs, const TranslationBlock = *tb); + hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, MMUAccessType access_type); void cpu_mips_tlb_flush(CPUMIPSState *env); diff --git a/target/mips/tcg/sysemu_helper.h.inc b/target/mips/tcg/sysemu_h= elper.h.inc index d136c4160a7..38e55cbf118 100644 --- a/target/mips/tcg/sysemu_helper.h.inc +++ b/target/mips/tcg/sysemu_helper.h.inc @@ -166,3 +166,10 @@ DEF_HELPER_1(evpe, tl, env) /* R6 Multi-threading */ DEF_HELPER_1(dvp, tl, env) DEF_HELPER_1(evp, tl, env) + +/* Special */ +DEF_HELPER_1(di, tl, env) +DEF_HELPER_1(ei, tl, env) +DEF_HELPER_1(eret, void, env) +DEF_HELPER_1(eretnc, void, env) +DEF_HELPER_1(deret, void, env) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index acc149aa573..949b8ef94ea 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -342,23 +342,6 @@ static void mips_cpu_synchronize_from_tb(CPUState *cs, env->hflags &=3D ~MIPS_HFLAG_BMASK; env->hflags |=3D tb->flags & MIPS_HFLAG_BMASK; } - -# ifndef CONFIG_USER_ONLY -static bool mips_io_recompile_replay_branch(CPUState *cs, - const TranslationBlock *tb) -{ - MIPSCPU *cpu =3D MIPS_CPU(cs); - CPUMIPSState *env =3D &cpu->env; - - if ((env->hflags & MIPS_HFLAG_BMASK) !=3D 0 - && env->active_tc.PC !=3D tb->pc) { - env->active_tc.PC -=3D (env->hflags & MIPS_HFLAG_B16 ? 2 : 4); - env->hflags &=3D ~MIPS_HFLAG_BMASK; - return true; - } - return false; -} -# endif /* !CONFIG_USER_ONLY */ #endif /* CONFIG_TCG */ =20 static bool mips_cpu_has_work(CPUState *cs) diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 9b6f570c897..3903545831f 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -656,106 +656,6 @@ void helper_ginvt(CPUMIPSState *env, target_ulong arg= , uint32_t type) } } =20 -/* Specials */ -target_ulong helper_di(CPUMIPSState *env) -{ - target_ulong t0 =3D env->CP0_Status; - - env->CP0_Status =3D t0 & ~(1 << CP0St_IE); - return t0; -} - -target_ulong helper_ei(CPUMIPSState *env) -{ - target_ulong t0 =3D env->CP0_Status; - - env->CP0_Status =3D t0 | (1 << CP0St_IE); - return t0; -} - -static void debug_pre_eret(CPUMIPSState *env) -{ - if (qemu_loglevel_mask(CPU_LOG_EXEC)) { - qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, - env->active_tc.PC, env->CP0_EPC); - if (env->CP0_Status & (1 << CP0St_ERL)) { - qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC); - } - if (env->hflags & MIPS_HFLAG_DM) { - qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC); - } - qemu_log("\n"); - } -} - -static void debug_post_eret(CPUMIPSState *env) -{ - if (qemu_loglevel_mask(CPU_LOG_EXEC)) { - qemu_log(" =3D> PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, - env->active_tc.PC, env->CP0_EPC); - if (env->CP0_Status & (1 << CP0St_ERL)) { - qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC); - } - if (env->hflags & MIPS_HFLAG_DM) { - qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC); - } - switch (cpu_mmu_index(env, false)) { - case 3: - qemu_log(", ERL\n"); - break; - case MIPS_HFLAG_UM: - qemu_log(", UM\n"); - break; - case MIPS_HFLAG_SM: - qemu_log(", SM\n"); - break; - case MIPS_HFLAG_KM: - qemu_log("\n"); - break; - default: - cpu_abort(env_cpu(env), "Invalid MMU mode!\n"); - break; - } - } -} - -static inline void exception_return(CPUMIPSState *env) -{ - debug_pre_eret(env); - if (env->CP0_Status & (1 << CP0St_ERL)) { - mips_cpu_set_error_pc(env, env->CP0_ErrorEPC); - env->CP0_Status &=3D ~(1 << CP0St_ERL); - } else { - mips_cpu_set_error_pc(env, env->CP0_EPC); - env->CP0_Status &=3D ~(1 << CP0St_EXL); - } - compute_hflags(env); - debug_post_eret(env); -} - -void helper_eret(CPUMIPSState *env) -{ - exception_return(env); - env->CP0_LLAddr =3D 1; - env->lladdr =3D 1; -} - -void helper_eretnc(CPUMIPSState *env) -{ - exception_return(env); -} - -void helper_deret(CPUMIPSState *env) -{ - debug_pre_eret(env); - - env->hflags &=3D ~MIPS_HFLAG_DM; - compute_hflags(env); - - mips_cpu_set_error_pc(env, env->CP0_DEPC); - - debug_post_eret(env); -} #endif /* !CONFIG_USER_ONLY */ =20 static inline void check_hwrena(CPUMIPSState *env, int reg, uintptr_t pc) diff --git a/target/mips/tcg/sysemu/special_helper.c b/target/mips/tcg/syse= mu/special_helper.c new file mode 100644 index 00000000000..927a640d076 --- /dev/null +++ b/target/mips/tcg/sysemu/special_helper.c @@ -0,0 +1,140 @@ +/* + * QEMU MIPS emulation: Special opcode helpers + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + * + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "exec/helper-proto.h" +#include "exec/exec-all.h" +#include "internal.h" + +/* Specials */ +target_ulong helper_di(CPUMIPSState *env) +{ + target_ulong t0 =3D env->CP0_Status; + + env->CP0_Status =3D t0 & ~(1 << CP0St_IE); + return t0; +} + +target_ulong helper_ei(CPUMIPSState *env) +{ + target_ulong t0 =3D env->CP0_Status; + + env->CP0_Status =3D t0 | (1 << CP0St_IE); + return t0; +} + +static void debug_pre_eret(CPUMIPSState *env) +{ + if (qemu_loglevel_mask(CPU_LOG_EXEC)) { + qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, + env->active_tc.PC, env->CP0_EPC); + if (env->CP0_Status & (1 << CP0St_ERL)) { + qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC); + } + if (env->hflags & MIPS_HFLAG_DM) { + qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC); + } + qemu_log("\n"); + } +} + +static void debug_post_eret(CPUMIPSState *env) +{ + if (qemu_loglevel_mask(CPU_LOG_EXEC)) { + qemu_log(" =3D> PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, + env->active_tc.PC, env->CP0_EPC); + if (env->CP0_Status & (1 << CP0St_ERL)) { + qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC); + } + if (env->hflags & MIPS_HFLAG_DM) { + qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC); + } + switch (cpu_mmu_index(env, false)) { + case 3: + qemu_log(", ERL\n"); + break; + case MIPS_HFLAG_UM: + qemu_log(", UM\n"); + break; + case MIPS_HFLAG_SM: + qemu_log(", SM\n"); + break; + case MIPS_HFLAG_KM: + qemu_log("\n"); + break; + default: + cpu_abort(env_cpu(env), "Invalid MMU mode!\n"); + break; + } + } +} + +bool mips_io_recompile_replay_branch(CPUState *cs, const TranslationBlock = *tb) +{ + MIPSCPU *cpu =3D MIPS_CPU(cs); + CPUMIPSState *env =3D &cpu->env; + + if ((env->hflags & MIPS_HFLAG_BMASK) !=3D 0 + && env->active_tc.PC !=3D tb->pc) { + env->active_tc.PC -=3D (env->hflags & MIPS_HFLAG_B16 ? 2 : 4); + env->hflags &=3D ~MIPS_HFLAG_BMASK; + return true; + } + return false; +} + +static inline void exception_return(CPUMIPSState *env) +{ + debug_pre_eret(env); + if (env->CP0_Status & (1 << CP0St_ERL)) { + mips_cpu_set_error_pc(env, env->CP0_ErrorEPC); + env->CP0_Status &=3D ~(1 << CP0St_ERL); + } else { + mips_cpu_set_error_pc(env, env->CP0_EPC); + env->CP0_Status &=3D ~(1 << CP0St_EXL); + } + compute_hflags(env); + debug_post_eret(env); +} + +void helper_eret(CPUMIPSState *env) +{ + exception_return(env); + env->CP0_LLAddr =3D 1; + env->lladdr =3D 1; +} + +void helper_eretnc(CPUMIPSState *env) +{ + exception_return(env); +} + +void helper_deret(CPUMIPSState *env) +{ + debug_pre_eret(env); + + env->hflags &=3D ~MIPS_HFLAG_DM; + compute_hflags(env); + + mips_cpu_set_error_pc(env, env->CP0_DEPC); + + debug_post_eret(env); +} diff --git a/target/mips/tcg/sysemu/meson.build b/target/mips/tcg/sysemu/me= son.build index 73ab9571ba6..4da2c577b20 100644 --- a/target/mips/tcg/sysemu/meson.build +++ b/target/mips/tcg/sysemu/meson.build @@ -1,5 +1,6 @@ mips_softmmu_ss.add(files( 'cp0_helper.c', 'mips-semi.c', + 'special_helper.c', 'tlb_helper.c', )) --=20 2.26.3 From nobody Mon Feb 9 10:44:55 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.43 as permitted sender) client-ip=209.85.128.43; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f43.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.43 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1618786371; cv=none; d=zohomail.com; s=zohoarc; b=QlhCsLcCbfrbB8KdTzvvJnd+cetX+VGif0ChenrlktLPiDXPCGQShE07Z620YxhgSVrj008+iP8arAxMOYDYV88qzsAFXoVKUjgVWajeka8H4SLCioW3oma+GRdCJ7UZm4RzmAwnTtzpiSQQAKal5il0EcubWY+zQa+w1ayrhzQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618786371; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=DEUZZa6TPysdlpTKdZmp6fZ5ZT/Oyxs4IvMyuZ4EHDg=; b=X91Zq0iFaFugBbKtx1xhL0kbZFOqDqXIg2qInYo9vhilu6cELKvyzVroAhSMGe5lK4QOs8/OxBwYXEOvGqQGf6h9jMb0Tu/Gv+NmApInSDGT2bu0VI1pZ3mr6wZXbk9EF/daWyaS9T9v4RKuLlOyL2NXkMsRAGaURXU8xqwacKw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.43 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) by mx.zohomail.com with SMTPS id 1618786371972838.4630908805509; Sun, 18 Apr 2021 15:52:51 -0700 (PDT) Received: by mail-wm1-f43.google.com with SMTP id n127so5364807wmb.5 for ; Sun, 18 Apr 2021 15:52:51 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id i20sm16062364wmq.29.2021.04.18.15.52.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Apr 2021 15:52:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DEUZZa6TPysdlpTKdZmp6fZ5ZT/Oyxs4IvMyuZ4EHDg=; b=vWPM4ToF+41u0SsYslxiZ+Forynw77xHcxDWuZc/LGgnMgCplxGd0JBpxj5wo6tQsu OpdUSi1Xryc4IWw+K5DYmc1km3SQKXTnnFUDIoAwis00CcwzaAmY2JEjMuLj1reSLtw2 5/Ee5CTOCjrYcdhIIf2G20HxvkGhSi8UhvRYXG9Kqj7270+nWUSRVjIQcgwNdetJgOMK ntVlJ48ZlMV2cBK6ya3H+5cpn75m27DAzzqNwgL4XVaay7YoV/tJ4Ue3BxooSygaDGI7 H8uNDy4FxBQy4ITKtV9DSswMlJ0/Wuw7AecQoaAPy6D4eWVQw/yb4//zMEiuXFB2EHTo 3jgQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=DEUZZa6TPysdlpTKdZmp6fZ5ZT/Oyxs4IvMyuZ4EHDg=; b=RvZDdd7bViaYIGA8O3ht2mml/TIJxJjzVt8ow0XzpqFYtV92JyyUDJrnrVZFP8tTKf ZzMUXZM5Scs/0JDXTXxUDyAdNzds+du5Po+jA7yzwaWV7zfW5e1N4nuHGi9rFg7ahlHc m1tSmNEdk7F3Xk8bIOejA0aYZE0K1HsTZMo5c0hF7gyz6zgQubDA6qeJsaioA0JQ1Yu4 sfnt6snajzH41ThuZOECi+ItSPOWHK3bsUnHKsNH60ffbnHbmkdH4MHkPf+29qYncR8q nMnRdgKdttw/3DqViUZX7zMvJLEyoyoMmeQXTEAkNz/fYvWq3lyG3zVbZWPanh3cIbJc Lq8g== X-Gm-Message-State: AOAM530yRuXsc7ww9R3U1Opl0liDtvE2j7emK8OqsfWPFTGH7CcC7fYR IXhjS8YYMlwtQLHQ24OCpSA= X-Google-Smtp-Source: ABdhPJxZ/SaP1wbaY9daa7O+e33yi5Ta3NnpnTQMxMPx6sOY0upYMVO8dYLoIpEuXQkQkyEqW1WPfg== X-Received: by 2002:a05:600c:3544:: with SMTP id i4mr18070036wmq.38.1618786370272; Sun, 18 Apr 2021 15:52:50 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen , Jiaxun Yang , Aleksandar Rikalo Subject: [PATCH v2 23/29] target/mips: Move helper_cache() to tcg/sysemu/special_helper.c Date: Mon, 19 Apr 2021 00:50:52 +0200 Message-Id: <20210418225058.1257014-24-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210418225058.1257014-1-f4bug@amsat.org> References: <20210418225058.1257014-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Move helper_cache() to tcg/sysemu/special_helper.c. The CACHE opcode is privileged and is not accessible in user emulation. However we get a link failure when restricting the symbol to sysemu. For now, add a stub helper to satisfy linking, which abort if ever called. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- v2: Use STUB_HELPER() :) (rth) --- target/mips/helper.h | 2 -- target/mips/tcg/sysemu_helper.h.inc | 1 + target/mips/op_helper.c | 35 ------------------------- target/mips/tcg/sysemu/special_helper.c | 33 +++++++++++++++++++++++ target/mips/translate.c | 13 +++++++++ 5 files changed, 47 insertions(+), 37 deletions(-) diff --git a/target/mips/helper.h b/target/mips/helper.h index 4ee7916d8b2..d49620f9282 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -614,8 +614,6 @@ DEF_HELPER_FLAGS_3(dmthlip, 0, void, tl, tl, env) DEF_HELPER_FLAGS_3(wrdsp, 0, void, tl, tl, env) DEF_HELPER_FLAGS_2(rddsp, 0, tl, tl, env) =20 -DEF_HELPER_3(cache, void, env, tl, i32) - #ifndef CONFIG_USER_ONLY #include "tcg/sysemu_helper.h.inc" #endif /* !CONFIG_USER_ONLY */ diff --git a/target/mips/tcg/sysemu_helper.h.inc b/target/mips/tcg/sysemu_h= elper.h.inc index 38e55cbf118..1ccbf687237 100644 --- a/target/mips/tcg/sysemu_helper.h.inc +++ b/target/mips/tcg/sysemu_helper.h.inc @@ -173,3 +173,4 @@ DEF_HELPER_1(ei, tl, env) DEF_HELPER_1(eret, void, env) DEF_HELPER_1(eretnc, void, env) DEF_HELPER_1(deret, void, env) +DEF_HELPER_3(cache, void, env, tl, i32) diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 3903545831f..659c4d15668 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -789,38 +789,3 @@ void mips_cpu_do_transaction_failed(CPUState *cs, hwad= dr physaddr, } } #endif /* !CONFIG_USER_ONLY */ - -void helper_cache(CPUMIPSState *env, target_ulong addr, uint32_t op) -{ -#ifndef CONFIG_USER_ONLY - static const char *const type_name[] =3D { - "Primary Instruction", - "Primary Data or Unified Primary", - "Tertiary", - "Secondary" - }; - uint32_t cache_type =3D extract32(op, 0, 2); - uint32_t cache_operation =3D extract32(op, 2, 3); - target_ulong index =3D addr & 0x1fffffff; - - switch (cache_operation) { - case 0b010: /* Index Store Tag */ - memory_region_dispatch_write(env->itc_tag, index, env->CP0_TagLo, - MO_64, MEMTXATTRS_UNSPECIFIED); - break; - case 0b001: /* Index Load Tag */ - memory_region_dispatch_read(env->itc_tag, index, &env->CP0_TagLo, - MO_64, MEMTXATTRS_UNSPECIFIED); - break; - case 0b000: /* Index Invalidate */ - case 0b100: /* Hit Invalidate */ - case 0b110: /* Hit Writeback */ - /* no-op */ - break; - default: - qemu_log_mask(LOG_UNIMP, "cache operation:%u (type: %s cache)\n", - cache_operation, type_name[cache_type]); - break; - } -#endif -} diff --git a/target/mips/tcg/sysemu/special_helper.c b/target/mips/tcg/syse= mu/special_helper.c index 927a640d076..ffd5d0086b6 100644 --- a/target/mips/tcg/sysemu/special_helper.c +++ b/target/mips/tcg/sysemu/special_helper.c @@ -138,3 +138,36 @@ void helper_deret(CPUMIPSState *env) =20 debug_post_eret(env); } + +void helper_cache(CPUMIPSState *env, target_ulong addr, uint32_t op) +{ + static const char *const type_name[] =3D { + "Primary Instruction", + "Primary Data or Unified Primary", + "Tertiary", + "Secondary" + }; + uint32_t cache_type =3D extract32(op, 0, 2); + uint32_t cache_operation =3D extract32(op, 2, 3); + target_ulong index =3D addr & 0x1fffffff; + + switch (cache_operation) { + case 0b010: /* Index Store Tag */ + memory_region_dispatch_write(env->itc_tag, index, env->CP0_TagLo, + MO_64, MEMTXATTRS_UNSPECIFIED); + break; + case 0b001: /* Index Load Tag */ + memory_region_dispatch_read(env->itc_tag, index, &env->CP0_TagLo, + MO_64, MEMTXATTRS_UNSPECIFIED); + break; + case 0b000: /* Index Invalidate */ + case 0b100: /* Hit Invalidate */ + case 0b110: /* Hit Writeback */ + /* no-op */ + break; + default: + qemu_log_mask(LOG_UNIMP, "cache operation:%u (type: %s cache)\n", + cache_operation, type_name[cache_type]); + break; + } +} diff --git a/target/mips/translate.c b/target/mips/translate.c index 8702f9220be..c2e60178d05 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -39,6 +39,19 @@ #include "fpu_helper.h" #include "translate.h" =20 +/* + * Many sysemu-only helpers are not reachable for user-only. + * Define stub generators here, so that we need not either sprinkle + * ifdefs through the translator, nor provide the helper function. + */ +#define STUB_HELPER(NAME, ...) \ + static inline void gen_helper_##NAME(__VA_ARGS__) \ + { qemu_build_not_reached(); } + +#ifdef CONFIG_USER_ONLY +STUB_HELPER(cache, TCGv_env env, TCGv val, TCGv_i32 reg) +#endif + enum { /* indirect opcode tables */ OPC_SPECIAL =3D (0x00 << 26), --=20 2.26.3 From nobody Mon Feb 9 10:44:55 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.47 as permitted sender) client-ip=209.85.221.47; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f47.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.47 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1618786377; cv=none; d=zohomail.com; s=zohoarc; b=lHyLaWYNw3Vncalg+ZMGcf8W66egLr3hSDV6rhok1C9TGjyrhnGAk7Ji2LAOLK/8yKLtZHoWW86nRtA/YrO9DIZ+gwL1pDF3NkZmC+EG1mf3TX5rOR0h8G0eP+Riev1I5XHPzEJzA/89l5yqSgMUKRaco9VM85KxXOBIkJEZG4A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618786377; 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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id v8sm20190429wrt.71.2021.04.18.15.52.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Apr 2021 15:52:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qnR8B5HmcdLNyLimo1G5VCCDH4UQwmKK0/XHBi6b9Tg=; b=e+itL6YHLIPReSvDv624+R//Eced5vPc3FQvpSU6m7VBee+vTCsbOLEaWRIehcaA06 Zf8zDlwYtSLgqRsDzah7rrOrl6cfLYHmvyr2isZD/p+2uj15iJSIbG4Yf0YkTLcnoFX6 Yef22VLLC1X8roukndfvPHCHLnQ9iYyfXZ5EvkRfxW4q86tMl0/s/MUGJYXbm6Ivs/5+ bnIsSqrFUIU7eDx/vjAL53Thz4GOkIUH1kbDwDKb4bqfCaPPzlvAtDQaocSkJIHHcXCZ o8pnozcVS9D1kGVfCCdU+LzEwqJQu9uh6TmH+lRjGWL5w3Ka3kkOElNltak+7v/MQRRb 5JSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=qnR8B5HmcdLNyLimo1G5VCCDH4UQwmKK0/XHBi6b9Tg=; b=lrJ+f6u2HfVGVlCzYOjiel/rPe82AgSL85hpCOCxgLLvHT5bzthgc13UGkryl8zuRA WmRPZLmn59U/nJA5y312WcLKOYtqTq+ayjRv3eXsw6TUG63aQKr8eJl9ulV+wIi7khAS v1bdtYuxwPcxbUKXCb/WhZcg0tVPx2Sfn1dWaY6sK3S1rAoYhHsKXMDx6kNhc/jA2Lll mxOXuXbE15Ibv0Sm48WTMlzIy09TOCSft7jc9STkn25dn5tN4uG76/Sh86+Bu8Zv1kwu cPyX1QCLOKhTyNPYNO7bYd6iB4mlSgsw7tYT5n5DdSkKcts2UaGSzNKzx0U1eahiWKRr CjuQ== X-Gm-Message-State: AOAM533mvpaWdfqp/akKeZrOJPbGtPi1GmL5Gn++BIyZp07wbgZ6zRai eR0aY6pa1DOJ7EwukrqKlw4= X-Google-Smtp-Source: ABdhPJxsJtD+a1OVhnXUzXtXG08bd6VMIdtkob5glY5Aq/7YssHf/Guh3qThYFtVVzMzRe8vl2Rkfg== X-Received: by 2002:a5d:508d:: with SMTP id a13mr10920321wrt.182.1618786375271; Sun, 18 Apr 2021 15:52:55 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen , Jiaxun Yang , Aleksandar Rikalo Subject: [PATCH v2 24/29] target/mips: Move TLB management helpers to tcg/sysemu/tlb_helper.c Date: Mon, 19 Apr 2021 00:50:53 +0200 Message-Id: <20210418225058.1257014-25-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210418225058.1257014-1-f4bug@amsat.org> References: <20210418225058.1257014-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Move TLB management helpers to tcg/sysemu/tlb_helper.c. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/helper.h | 10 - target/mips/internal.h | 7 - target/mips/tcg/sysemu_helper.h.inc | 9 + target/mips/op_helper.c | 333 ---------------------------- target/mips/tcg/sysemu/tlb_helper.c | 331 +++++++++++++++++++++++++++ 5 files changed, 340 insertions(+), 350 deletions(-) diff --git a/target/mips/helper.h b/target/mips/helper.h index d49620f9282..ba301ae160d 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -202,16 +202,6 @@ FOP_PROTO(sune) FOP_PROTO(sne) #undef FOP_PROTO =20 -/* Special functions */ -#ifndef CONFIG_USER_ONLY -DEF_HELPER_1(tlbwi, void, env) -DEF_HELPER_1(tlbwr, void, env) -DEF_HELPER_1(tlbp, void, env) -DEF_HELPER_1(tlbr, void, env) -DEF_HELPER_1(tlbinv, void, env) -DEF_HELPER_1(tlbinvf, void, env) -DEF_HELPER_3(ginvt, void, env, tl, i32) -#endif /* !CONFIG_USER_ONLY */ DEF_HELPER_1(rdhwr_cpunum, tl, env) DEF_HELPER_1(rdhwr_synci_step, tl, env) DEF_HELPER_1(rdhwr_cc, tl, env) diff --git a/target/mips/internal.h b/target/mips/internal.h index a59e2f9007d..88020e22365 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -152,13 +152,6 @@ struct CPUMIPSTLBContext { } mmu; }; =20 -void r4k_helper_tlbwi(CPUMIPSState *env); -void r4k_helper_tlbwr(CPUMIPSState *env); -void r4k_helper_tlbp(CPUMIPSState *env); -void r4k_helper_tlbr(CPUMIPSState *env); -void r4k_helper_tlbinv(CPUMIPSState *env); -void r4k_helper_tlbinvf(CPUMIPSState *env); - void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, diff --git a/target/mips/tcg/sysemu_helper.h.inc b/target/mips/tcg/sysemu_h= elper.h.inc index 1ccbf687237..4353a966f97 100644 --- a/target/mips/tcg/sysemu_helper.h.inc +++ b/target/mips/tcg/sysemu_helper.h.inc @@ -167,6 +167,15 @@ DEF_HELPER_1(evpe, tl, env) DEF_HELPER_1(dvp, tl, env) DEF_HELPER_1(evp, tl, env) =20 +/* TLB */ +DEF_HELPER_1(tlbwi, void, env) +DEF_HELPER_1(tlbwr, void, env) +DEF_HELPER_1(tlbp, void, env) +DEF_HELPER_1(tlbr, void, env) +DEF_HELPER_1(tlbinv, void, env) +DEF_HELPER_1(tlbinvf, void, env) +DEF_HELPER_3(ginvt, void, env, tl, i32) + /* Special */ DEF_HELPER_1(di, tl, env) DEF_HELPER_1(ei, tl, env) diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 659c4d15668..c6373d1de3f 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -325,339 +325,6 @@ target_ulong helper_yield(CPUMIPSState *env, target_u= long arg) return env->CP0_YQMask; } =20 -#ifndef CONFIG_USER_ONLY -/* TLB management */ -static void r4k_mips_tlb_flush_extra(CPUMIPSState *env, int first) -{ - /* Discard entries from env->tlb[first] onwards. */ - while (env->tlb->tlb_in_use > first) { - r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0); - } -} - -static inline uint64_t get_tlb_pfn_from_entrylo(uint64_t entrylo) -{ -#if defined(TARGET_MIPS64) - return extract64(entrylo, 6, 54); -#else - return extract64(entrylo, 6, 24) | /* PFN */ - (extract64(entrylo, 32, 32) << 24); /* PFNX */ -#endif -} - -static void r4k_fill_tlb(CPUMIPSState *env, int idx) -{ - r4k_tlb_t *tlb; - uint64_t mask =3D env->CP0_PageMask >> (TARGET_PAGE_BITS + 1); - - /* XXX: detect conflicting TLBs and raise a MCHECK exception when need= ed */ - tlb =3D &env->tlb->mmu.r4k.tlb[idx]; - if (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) { - tlb->EHINV =3D 1; - return; - } - tlb->EHINV =3D 0; - tlb->VPN =3D env->CP0_EntryHi & (TARGET_PAGE_MASK << 1); -#if defined(TARGET_MIPS64) - tlb->VPN &=3D env->SEGMask; -#endif - tlb->ASID =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; - tlb->MMID =3D env->CP0_MemoryMapID; - tlb->PageMask =3D env->CP0_PageMask; - tlb->G =3D env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1; - tlb->V0 =3D (env->CP0_EntryLo0 & 2) !=3D 0; - tlb->D0 =3D (env->CP0_EntryLo0 & 4) !=3D 0; - tlb->C0 =3D (env->CP0_EntryLo0 >> 3) & 0x7; - tlb->XI0 =3D (env->CP0_EntryLo0 >> CP0EnLo_XI) & 1; - tlb->RI0 =3D (env->CP0_EntryLo0 >> CP0EnLo_RI) & 1; - tlb->PFN[0] =3D (get_tlb_pfn_from_entrylo(env->CP0_EntryLo0) & ~mask) = << 12; - tlb->V1 =3D (env->CP0_EntryLo1 & 2) !=3D 0; - tlb->D1 =3D (env->CP0_EntryLo1 & 4) !=3D 0; - tlb->C1 =3D (env->CP0_EntryLo1 >> 3) & 0x7; - tlb->XI1 =3D (env->CP0_EntryLo1 >> CP0EnLo_XI) & 1; - tlb->RI1 =3D (env->CP0_EntryLo1 >> CP0EnLo_RI) & 1; - tlb->PFN[1] =3D (get_tlb_pfn_from_entrylo(env->CP0_EntryLo1) & ~mask) = << 12; -} - -void r4k_helper_tlbinv(CPUMIPSState *env) -{ - bool mi =3D !!((env->CP0_Config5 >> CP0C5_MI) & 1); - uint16_t ASID =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; - uint32_t MMID =3D env->CP0_MemoryMapID; - uint32_t tlb_mmid; - r4k_tlb_t *tlb; - int idx; - - MMID =3D mi ? MMID : (uint32_t) ASID; - for (idx =3D 0; idx < env->tlb->nb_tlb; idx++) { - tlb =3D &env->tlb->mmu.r4k.tlb[idx]; - tlb_mmid =3D mi ? tlb->MMID : (uint32_t) tlb->ASID; - if (!tlb->G && tlb_mmid =3D=3D MMID) { - tlb->EHINV =3D 1; - } - } - cpu_mips_tlb_flush(env); -} - -void r4k_helper_tlbinvf(CPUMIPSState *env) -{ - int idx; - - for (idx =3D 0; idx < env->tlb->nb_tlb; idx++) { - env->tlb->mmu.r4k.tlb[idx].EHINV =3D 1; - } - cpu_mips_tlb_flush(env); -} - -void r4k_helper_tlbwi(CPUMIPSState *env) -{ - bool mi =3D !!((env->CP0_Config5 >> CP0C5_MI) & 1); - target_ulong VPN; - uint16_t ASID =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; - uint32_t MMID =3D env->CP0_MemoryMapID; - uint32_t tlb_mmid; - bool EHINV, G, V0, D0, V1, D1, XI0, XI1, RI0, RI1; - r4k_tlb_t *tlb; - int idx; - - MMID =3D mi ? MMID : (uint32_t) ASID; - - idx =3D (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb; - tlb =3D &env->tlb->mmu.r4k.tlb[idx]; - VPN =3D env->CP0_EntryHi & (TARGET_PAGE_MASK << 1); -#if defined(TARGET_MIPS64) - VPN &=3D env->SEGMask; -#endif - EHINV =3D (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) !=3D 0; - G =3D env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1; - V0 =3D (env->CP0_EntryLo0 & 2) !=3D 0; - D0 =3D (env->CP0_EntryLo0 & 4) !=3D 0; - XI0 =3D (env->CP0_EntryLo0 >> CP0EnLo_XI) &1; - RI0 =3D (env->CP0_EntryLo0 >> CP0EnLo_RI) &1; - V1 =3D (env->CP0_EntryLo1 & 2) !=3D 0; - D1 =3D (env->CP0_EntryLo1 & 4) !=3D 0; - XI1 =3D (env->CP0_EntryLo1 >> CP0EnLo_XI) &1; - RI1 =3D (env->CP0_EntryLo1 >> CP0EnLo_RI) &1; - - tlb_mmid =3D mi ? tlb->MMID : (uint32_t) tlb->ASID; - /* - * Discard cached TLB entries, unless tlbwi is just upgrading access - * permissions on the current entry. - */ - if (tlb->VPN !=3D VPN || tlb_mmid !=3D MMID || tlb->G !=3D G || - (!tlb->EHINV && EHINV) || - (tlb->V0 && !V0) || (tlb->D0 && !D0) || - (!tlb->XI0 && XI0) || (!tlb->RI0 && RI0) || - (tlb->V1 && !V1) || (tlb->D1 && !D1) || - (!tlb->XI1 && XI1) || (!tlb->RI1 && RI1)) { - r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb); - } - - r4k_invalidate_tlb(env, idx, 0); - r4k_fill_tlb(env, idx); -} - -void r4k_helper_tlbwr(CPUMIPSState *env) -{ - int r =3D cpu_mips_get_random(env); - - r4k_invalidate_tlb(env, r, 1); - r4k_fill_tlb(env, r); -} - -void r4k_helper_tlbp(CPUMIPSState *env) -{ - bool mi =3D !!((env->CP0_Config5 >> CP0C5_MI) & 1); - r4k_tlb_t *tlb; - target_ulong mask; - target_ulong tag; - target_ulong VPN; - uint16_t ASID =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; - uint32_t MMID =3D env->CP0_MemoryMapID; - uint32_t tlb_mmid; - int i; - - MMID =3D mi ? MMID : (uint32_t) ASID; - for (i =3D 0; i < env->tlb->nb_tlb; i++) { - tlb =3D &env->tlb->mmu.r4k.tlb[i]; - /* 1k pages are not supported. */ - mask =3D tlb->PageMask | ~(TARGET_PAGE_MASK << 1); - tag =3D env->CP0_EntryHi & ~mask; - VPN =3D tlb->VPN & ~mask; -#if defined(TARGET_MIPS64) - tag &=3D env->SEGMask; -#endif - tlb_mmid =3D mi ? tlb->MMID : (uint32_t) tlb->ASID; - /* Check ASID/MMID, virtual page number & size */ - if ((tlb->G =3D=3D 1 || tlb_mmid =3D=3D MMID) && VPN =3D=3D tag &&= !tlb->EHINV) { - /* TLB match */ - env->CP0_Index =3D i; - break; - } - } - if (i =3D=3D env->tlb->nb_tlb) { - /* No match. Discard any shadow entries, if any of them match. */ - for (i =3D env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) { - tlb =3D &env->tlb->mmu.r4k.tlb[i]; - /* 1k pages are not supported. */ - mask =3D tlb->PageMask | ~(TARGET_PAGE_MASK << 1); - tag =3D env->CP0_EntryHi & ~mask; - VPN =3D tlb->VPN & ~mask; -#if defined(TARGET_MIPS64) - tag &=3D env->SEGMask; -#endif - tlb_mmid =3D mi ? tlb->MMID : (uint32_t) tlb->ASID; - /* Check ASID/MMID, virtual page number & size */ - if ((tlb->G =3D=3D 1 || tlb_mmid =3D=3D MMID) && VPN =3D=3D ta= g) { - r4k_mips_tlb_flush_extra(env, i); - break; - } - } - - env->CP0_Index |=3D 0x80000000; - } -} - -static inline uint64_t get_entrylo_pfn_from_tlb(uint64_t tlb_pfn) -{ -#if defined(TARGET_MIPS64) - return tlb_pfn << 6; -#else - return (extract64(tlb_pfn, 0, 24) << 6) | /* PFN */ - (extract64(tlb_pfn, 24, 32) << 32); /* PFNX */ -#endif -} - -void r4k_helper_tlbr(CPUMIPSState *env) -{ - bool mi =3D !!((env->CP0_Config5 >> CP0C5_MI) & 1); - uint16_t ASID =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; - uint32_t MMID =3D env->CP0_MemoryMapID; - uint32_t tlb_mmid; - r4k_tlb_t *tlb; - int idx; - - MMID =3D mi ? MMID : (uint32_t) ASID; - idx =3D (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb; - tlb =3D &env->tlb->mmu.r4k.tlb[idx]; - - tlb_mmid =3D mi ? tlb->MMID : (uint32_t) tlb->ASID; - /* If this will change the current ASID/MMID, flush qemu's TLB. */ - if (MMID !=3D tlb_mmid) { - cpu_mips_tlb_flush(env); - } - - r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb); - - if (tlb->EHINV) { - env->CP0_EntryHi =3D 1 << CP0EnHi_EHINV; - env->CP0_PageMask =3D 0; - env->CP0_EntryLo0 =3D 0; - env->CP0_EntryLo1 =3D 0; - } else { - env->CP0_EntryHi =3D mi ? tlb->VPN : tlb->VPN | tlb->ASID; - env->CP0_MemoryMapID =3D tlb->MMID; - env->CP0_PageMask =3D tlb->PageMask; - env->CP0_EntryLo0 =3D tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) | - ((uint64_t)tlb->RI0 << CP0EnLo_RI) | - ((uint64_t)tlb->XI0 << CP0EnLo_XI) | (tlb->C0 << 3= ) | - get_entrylo_pfn_from_tlb(tlb->PFN[0] >> 12); - env->CP0_EntryLo1 =3D tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) | - ((uint64_t)tlb->RI1 << CP0EnLo_RI) | - ((uint64_t)tlb->XI1 << CP0EnLo_XI) | (tlb->C1 << 3= ) | - get_entrylo_pfn_from_tlb(tlb->PFN[1] >> 12); - } -} - -void helper_tlbwi(CPUMIPSState *env) -{ - env->tlb->helper_tlbwi(env); -} - -void helper_tlbwr(CPUMIPSState *env) -{ - env->tlb->helper_tlbwr(env); -} - -void helper_tlbp(CPUMIPSState *env) -{ - env->tlb->helper_tlbp(env); -} - -void helper_tlbr(CPUMIPSState *env) -{ - env->tlb->helper_tlbr(env); -} - -void helper_tlbinv(CPUMIPSState *env) -{ - env->tlb->helper_tlbinv(env); -} - -void helper_tlbinvf(CPUMIPSState *env) -{ - env->tlb->helper_tlbinvf(env); -} - -static void global_invalidate_tlb(CPUMIPSState *env, - uint32_t invMsgVPN2, - uint8_t invMsgR, - uint32_t invMsgMMid, - bool invAll, - bool invVAMMid, - bool invMMid, - bool invVA) -{ - - int idx; - r4k_tlb_t *tlb; - bool VAMatch; - bool MMidMatch; - - for (idx =3D 0; idx < env->tlb->nb_tlb; idx++) { - tlb =3D &env->tlb->mmu.r4k.tlb[idx]; - VAMatch =3D - (((tlb->VPN & ~tlb->PageMask) =3D=3D (invMsgVPN2 & ~tlb->PageM= ask)) -#ifdef TARGET_MIPS64 - && - (extract64(env->CP0_EntryHi, 62, 2) =3D=3D invMsgR) -#endif - ); - MMidMatch =3D tlb->MMID =3D=3D invMsgMMid; - if ((invAll && (idx > env->CP0_Wired)) || - (VAMatch && invVAMMid && (tlb->G || MMidMatch)) || - (VAMatch && invVA) || - (MMidMatch && !(tlb->G) && invMMid)) { - tlb->EHINV =3D 1; - } - } - cpu_mips_tlb_flush(env); -} - -void helper_ginvt(CPUMIPSState *env, target_ulong arg, uint32_t type) -{ - bool invAll =3D type =3D=3D 0; - bool invVA =3D type =3D=3D 1; - bool invMMid =3D type =3D=3D 2; - bool invVAMMid =3D type =3D=3D 3; - uint32_t invMsgVPN2 =3D arg & (TARGET_PAGE_MASK << 1); - uint8_t invMsgR =3D 0; - uint32_t invMsgMMid =3D env->CP0_MemoryMapID; - CPUState *other_cs =3D first_cpu; - -#ifdef TARGET_MIPS64 - invMsgR =3D extract64(arg, 62, 2); -#endif - - CPU_FOREACH(other_cs) { - MIPSCPU *other_cpu =3D MIPS_CPU(other_cs); - global_invalidate_tlb(&other_cpu->env, invMsgVPN2, invMsgR, invMsg= MMid, - invAll, invVAMMid, invMMid, invVA); - } -} - -#endif /* !CONFIG_USER_ONLY */ - static inline void check_hwrena(CPUMIPSState *env, int reg, uintptr_t pc) { if ((env->hflags & MIPS_HFLAG_CP0) || (env->CP0_HWREna & (1 << reg))) { diff --git a/target/mips/tcg/sysemu/tlb_helper.c b/target/mips/tcg/sysemu/t= lb_helper.c index cbb4ccf0dac..b1c706314e7 100644 --- a/target/mips/tcg/sysemu/tlb_helper.c +++ b/target/mips/tcg/sysemu/tlb_helper.c @@ -24,6 +24,337 @@ #include "exec/cpu_ldst.h" #include "exec/log.h" #include "hw/mips/cpudevs.h" +#include "exec/helper-proto.h" + +/* TLB management */ +static void r4k_mips_tlb_flush_extra(CPUMIPSState *env, int first) +{ + /* Discard entries from env->tlb[first] onwards. */ + while (env->tlb->tlb_in_use > first) { + r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0); + } +} + +static inline uint64_t get_tlb_pfn_from_entrylo(uint64_t entrylo) +{ +#if defined(TARGET_MIPS64) + return extract64(entrylo, 6, 54); +#else + return extract64(entrylo, 6, 24) | /* PFN */ + (extract64(entrylo, 32, 32) << 24); /* PFNX */ +#endif +} + +static void r4k_fill_tlb(CPUMIPSState *env, int idx) +{ + r4k_tlb_t *tlb; + uint64_t mask =3D env->CP0_PageMask >> (TARGET_PAGE_BITS + 1); + + /* XXX: detect conflicting TLBs and raise a MCHECK exception when need= ed */ + tlb =3D &env->tlb->mmu.r4k.tlb[idx]; + if (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) { + tlb->EHINV =3D 1; + return; + } + tlb->EHINV =3D 0; + tlb->VPN =3D env->CP0_EntryHi & (TARGET_PAGE_MASK << 1); +#if defined(TARGET_MIPS64) + tlb->VPN &=3D env->SEGMask; +#endif + tlb->ASID =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; + tlb->MMID =3D env->CP0_MemoryMapID; + tlb->PageMask =3D env->CP0_PageMask; + tlb->G =3D env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1; + tlb->V0 =3D (env->CP0_EntryLo0 & 2) !=3D 0; + tlb->D0 =3D (env->CP0_EntryLo0 & 4) !=3D 0; + tlb->C0 =3D (env->CP0_EntryLo0 >> 3) & 0x7; + tlb->XI0 =3D (env->CP0_EntryLo0 >> CP0EnLo_XI) & 1; + tlb->RI0 =3D (env->CP0_EntryLo0 >> CP0EnLo_RI) & 1; + tlb->PFN[0] =3D (get_tlb_pfn_from_entrylo(env->CP0_EntryLo0) & ~mask) = << 12; + tlb->V1 =3D (env->CP0_EntryLo1 & 2) !=3D 0; + tlb->D1 =3D (env->CP0_EntryLo1 & 4) !=3D 0; + tlb->C1 =3D (env->CP0_EntryLo1 >> 3) & 0x7; + tlb->XI1 =3D (env->CP0_EntryLo1 >> CP0EnLo_XI) & 1; + tlb->RI1 =3D (env->CP0_EntryLo1 >> CP0EnLo_RI) & 1; + tlb->PFN[1] =3D (get_tlb_pfn_from_entrylo(env->CP0_EntryLo1) & ~mask) = << 12; +} + +static void r4k_helper_tlbinv(CPUMIPSState *env) +{ + bool mi =3D !!((env->CP0_Config5 >> CP0C5_MI) & 1); + uint16_t ASID =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; + uint32_t MMID =3D env->CP0_MemoryMapID; + uint32_t tlb_mmid; + r4k_tlb_t *tlb; + int idx; + + MMID =3D mi ? MMID : (uint32_t) ASID; + for (idx =3D 0; idx < env->tlb->nb_tlb; idx++) { + tlb =3D &env->tlb->mmu.r4k.tlb[idx]; + tlb_mmid =3D mi ? tlb->MMID : (uint32_t) tlb->ASID; + if (!tlb->G && tlb_mmid =3D=3D MMID) { + tlb->EHINV =3D 1; + } + } + cpu_mips_tlb_flush(env); +} + +static void r4k_helper_tlbinvf(CPUMIPSState *env) +{ + int idx; + + for (idx =3D 0; idx < env->tlb->nb_tlb; idx++) { + env->tlb->mmu.r4k.tlb[idx].EHINV =3D 1; + } + cpu_mips_tlb_flush(env); +} + +static void r4k_helper_tlbwi(CPUMIPSState *env) +{ + bool mi =3D !!((env->CP0_Config5 >> CP0C5_MI) & 1); + target_ulong VPN; + uint16_t ASID =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; + uint32_t MMID =3D env->CP0_MemoryMapID; + uint32_t tlb_mmid; + bool EHINV, G, V0, D0, V1, D1, XI0, XI1, RI0, RI1; + r4k_tlb_t *tlb; + int idx; + + MMID =3D mi ? MMID : (uint32_t) ASID; + + idx =3D (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb; + tlb =3D &env->tlb->mmu.r4k.tlb[idx]; + VPN =3D env->CP0_EntryHi & (TARGET_PAGE_MASK << 1); +#if defined(TARGET_MIPS64) + VPN &=3D env->SEGMask; +#endif + EHINV =3D (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) !=3D 0; + G =3D env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1; + V0 =3D (env->CP0_EntryLo0 & 2) !=3D 0; + D0 =3D (env->CP0_EntryLo0 & 4) !=3D 0; + XI0 =3D (env->CP0_EntryLo0 >> CP0EnLo_XI) &1; + RI0 =3D (env->CP0_EntryLo0 >> CP0EnLo_RI) &1; + V1 =3D (env->CP0_EntryLo1 & 2) !=3D 0; + D1 =3D (env->CP0_EntryLo1 & 4) !=3D 0; + XI1 =3D (env->CP0_EntryLo1 >> CP0EnLo_XI) &1; + RI1 =3D (env->CP0_EntryLo1 >> CP0EnLo_RI) &1; + + tlb_mmid =3D mi ? tlb->MMID : (uint32_t) tlb->ASID; + /* + * Discard cached TLB entries, unless tlbwi is just upgrading access + * permissions on the current entry. + */ + if (tlb->VPN !=3D VPN || tlb_mmid !=3D MMID || tlb->G !=3D G || + (!tlb->EHINV && EHINV) || + (tlb->V0 && !V0) || (tlb->D0 && !D0) || + (!tlb->XI0 && XI0) || (!tlb->RI0 && RI0) || + (tlb->V1 && !V1) || (tlb->D1 && !D1) || + (!tlb->XI1 && XI1) || (!tlb->RI1 && RI1)) { + r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb); + } + + r4k_invalidate_tlb(env, idx, 0); + r4k_fill_tlb(env, idx); +} + +static void r4k_helper_tlbwr(CPUMIPSState *env) +{ + int r =3D cpu_mips_get_random(env); + + r4k_invalidate_tlb(env, r, 1); + r4k_fill_tlb(env, r); +} + +static void r4k_helper_tlbp(CPUMIPSState *env) +{ + bool mi =3D !!((env->CP0_Config5 >> CP0C5_MI) & 1); + r4k_tlb_t *tlb; + target_ulong mask; + target_ulong tag; + target_ulong VPN; + uint16_t ASID =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; + uint32_t MMID =3D env->CP0_MemoryMapID; + uint32_t tlb_mmid; + int i; + + MMID =3D mi ? MMID : (uint32_t) ASID; + for (i =3D 0; i < env->tlb->nb_tlb; i++) { + tlb =3D &env->tlb->mmu.r4k.tlb[i]; + /* 1k pages are not supported. */ + mask =3D tlb->PageMask | ~(TARGET_PAGE_MASK << 1); + tag =3D env->CP0_EntryHi & ~mask; + VPN =3D tlb->VPN & ~mask; +#if defined(TARGET_MIPS64) + tag &=3D env->SEGMask; +#endif + tlb_mmid =3D mi ? tlb->MMID : (uint32_t) tlb->ASID; + /* Check ASID/MMID, virtual page number & size */ + if ((tlb->G =3D=3D 1 || tlb_mmid =3D=3D MMID) && VPN =3D=3D tag &&= !tlb->EHINV) { + /* TLB match */ + env->CP0_Index =3D i; + break; + } + } + if (i =3D=3D env->tlb->nb_tlb) { + /* No match. Discard any shadow entries, if any of them match. */ + for (i =3D env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) { + tlb =3D &env->tlb->mmu.r4k.tlb[i]; + /* 1k pages are not supported. */ + mask =3D tlb->PageMask | ~(TARGET_PAGE_MASK << 1); + tag =3D env->CP0_EntryHi & ~mask; + VPN =3D tlb->VPN & ~mask; +#if defined(TARGET_MIPS64) + tag &=3D env->SEGMask; +#endif + tlb_mmid =3D mi ? tlb->MMID : (uint32_t) tlb->ASID; + /* Check ASID/MMID, virtual page number & size */ + if ((tlb->G =3D=3D 1 || tlb_mmid =3D=3D MMID) && VPN =3D=3D ta= g) { + r4k_mips_tlb_flush_extra(env, i); + break; + } + } + + env->CP0_Index |=3D 0x80000000; + } +} + +static inline uint64_t get_entrylo_pfn_from_tlb(uint64_t tlb_pfn) +{ +#if defined(TARGET_MIPS64) + return tlb_pfn << 6; +#else + return (extract64(tlb_pfn, 0, 24) << 6) | /* PFN */ + (extract64(tlb_pfn, 24, 32) << 32); /* PFNX */ +#endif +} + +static void r4k_helper_tlbr(CPUMIPSState *env) +{ + bool mi =3D !!((env->CP0_Config5 >> CP0C5_MI) & 1); + uint16_t ASID =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; + uint32_t MMID =3D env->CP0_MemoryMapID; + uint32_t tlb_mmid; + r4k_tlb_t *tlb; + int idx; + + MMID =3D mi ? MMID : (uint32_t) ASID; + idx =3D (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb; + tlb =3D &env->tlb->mmu.r4k.tlb[idx]; + + tlb_mmid =3D mi ? tlb->MMID : (uint32_t) tlb->ASID; + /* If this will change the current ASID/MMID, flush qemu's TLB. */ + if (MMID !=3D tlb_mmid) { + cpu_mips_tlb_flush(env); + } + + r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb); + + if (tlb->EHINV) { + env->CP0_EntryHi =3D 1 << CP0EnHi_EHINV; + env->CP0_PageMask =3D 0; + env->CP0_EntryLo0 =3D 0; + env->CP0_EntryLo1 =3D 0; + } else { + env->CP0_EntryHi =3D mi ? tlb->VPN : tlb->VPN | tlb->ASID; + env->CP0_MemoryMapID =3D tlb->MMID; + env->CP0_PageMask =3D tlb->PageMask; + env->CP0_EntryLo0 =3D tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) | + ((uint64_t)tlb->RI0 << CP0EnLo_RI) | + ((uint64_t)tlb->XI0 << CP0EnLo_XI) | (tlb->C0 << 3= ) | + get_entrylo_pfn_from_tlb(tlb->PFN[0] >> 12); + env->CP0_EntryLo1 =3D tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) | + ((uint64_t)tlb->RI1 << CP0EnLo_RI) | + ((uint64_t)tlb->XI1 << CP0EnLo_XI) | (tlb->C1 << 3= ) | + get_entrylo_pfn_from_tlb(tlb->PFN[1] >> 12); + } +} + +void helper_tlbwi(CPUMIPSState *env) +{ + env->tlb->helper_tlbwi(env); +} + +void helper_tlbwr(CPUMIPSState *env) +{ + env->tlb->helper_tlbwr(env); +} + +void helper_tlbp(CPUMIPSState *env) +{ + env->tlb->helper_tlbp(env); +} + +void helper_tlbr(CPUMIPSState *env) +{ + env->tlb->helper_tlbr(env); +} + +void helper_tlbinv(CPUMIPSState *env) +{ + env->tlb->helper_tlbinv(env); +} + +void helper_tlbinvf(CPUMIPSState *env) +{ + env->tlb->helper_tlbinvf(env); +} + +static void global_invalidate_tlb(CPUMIPSState *env, + uint32_t invMsgVPN2, + uint8_t invMsgR, + uint32_t invMsgMMid, + bool invAll, + bool invVAMMid, + bool invMMid, + bool invVA) +{ + + int idx; + r4k_tlb_t *tlb; + bool VAMatch; + bool MMidMatch; + + for (idx =3D 0; idx < env->tlb->nb_tlb; idx++) { + tlb =3D &env->tlb->mmu.r4k.tlb[idx]; + VAMatch =3D + (((tlb->VPN & ~tlb->PageMask) =3D=3D (invMsgVPN2 & ~tlb->PageM= ask)) +#ifdef TARGET_MIPS64 + && + (extract64(env->CP0_EntryHi, 62, 2) =3D=3D invMsgR) +#endif + ); + MMidMatch =3D tlb->MMID =3D=3D invMsgMMid; + if ((invAll && (idx > env->CP0_Wired)) || + (VAMatch && invVAMMid && (tlb->G || MMidMatch)) || + (VAMatch && invVA) || + (MMidMatch && !(tlb->G) && invMMid)) { + tlb->EHINV =3D 1; + } + } + cpu_mips_tlb_flush(env); +} + +void helper_ginvt(CPUMIPSState *env, target_ulong arg, uint32_t type) +{ + bool invAll =3D type =3D=3D 0; + bool invVA =3D type =3D=3D 1; + bool invMMid =3D type =3D=3D 2; + bool invVAMMid =3D type =3D=3D 3; + uint32_t invMsgVPN2 =3D arg & (TARGET_PAGE_MASK << 1); + uint8_t invMsgR =3D 0; + uint32_t invMsgMMid =3D env->CP0_MemoryMapID; + CPUState *other_cs =3D first_cpu; + +#ifdef TARGET_MIPS64 + invMsgR =3D extract64(arg, 62, 2); +#endif + + CPU_FOREACH(other_cs) { + MIPSCPU *other_cpu =3D MIPS_CPU(other_cs); + global_invalidate_tlb(&other_cpu->env, invMsgVPN2, invMsgR, invMsg= MMid, + invAll, invVAMMid, invMMid, invVA); + } +} =20 /* no MMU emulation */ static int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *pr= ot, --=20 2.26.3 From nobody Mon Feb 9 10:44:55 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.51 as permitted sender) client-ip=209.85.221.51; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f51.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.51 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1618786381; cv=none; d=zohomail.com; s=zohoarc; b=h3Y5D1wfzxEdVXmfUHH2VpUa5/+XcKyblBySEwrEqV51Nz6B9XJJjbFBfBN6tauCWU9+E/ouvIoC/hPI1U+9ccihTB3nLiKEhSQvJyH3QbMw6grcJfj2yS8hV9wTLEvI671WVcePJmMKPijABHs1+/dZJ4TUTKnwroLdzCP98H0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618786381; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=6nG8poRcj1wDu49/3j5kVXCk3FjBmpdwDvVGl0DoGNs=; b=JMSPNcqmLgDI3tcijzCTf1tW7rn2B8d9Fg5L3E96NRoixiLfw++wlcx6W/R0tnN9BwkY+y6NtYJCf22LmJXp9QixFsKBlwN505kuLNBHFmI5XvkggwuRsK2ZJkvW5FMn/YN22V/YnVh/NXbjuvl5q3m9KPyOifitK0TLssbDej4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.51 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-wr1-f51.google.com (mail-wr1-f51.google.com [209.85.221.51]) by mx.zohomail.com with SMTPS id 1618786381807695.402017553171; Sun, 18 Apr 2021 15:53:01 -0700 (PDT) Received: by mail-wr1-f51.google.com with SMTP id j5so31086680wrn.4 for ; Sun, 18 Apr 2021 15:53:01 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (39.red-81-40-121.staticip.rima-tde.net. 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/internal.h | 13 --- target/mips/tcg/tcg-internal.h | 14 +++ target/mips/cpu.c | 113 ---------------------- target/mips/exception.c | 169 +++++++++++++++++++++++++++++++++ target/mips/op_helper.c | 37 -------- target/mips/meson.build | 1 + 6 files changed, 184 insertions(+), 163 deletions(-) create mode 100644 target/mips/exception.c diff --git a/target/mips/internal.h b/target/mips/internal.h index 88020e22365..8158078b08b 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -80,7 +80,6 @@ extern const char fregnames[32][4]; extern const struct mips_def_t mips_defs[]; extern const int mips_defs_number; =20 -bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, @@ -411,16 +410,4 @@ void sync_c0_status(CPUMIPSState *env, CPUMIPSState *c= pu, int tc); void cpu_mips_store_status(CPUMIPSState *env, target_ulong val); void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val); =20 -const char *mips_exception_name(int32_t exception); - -void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t exce= ption, - int error_code, uintptr_t pc); - -static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env, - uint32_t exception, - uintptr_t pc) -{ - do_raise_exception_err(env, exception, 0, pc); -} - #endif diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h index e507dd1630f..70f0d5da436 100644 --- a/target/mips/tcg/tcg-internal.h +++ b/target/mips/tcg/tcg-internal.h @@ -14,11 +14,25 @@ #include "hw/core/cpu.h" #include "cpu.h" =20 +void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb= ); void mips_cpu_do_interrupt(CPUState *cpu); +bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); =20 +const char *mips_exception_name(int32_t exception); + +void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t exce= ption, + int error_code, uintptr_t pc); + +static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env, + uint32_t exception, + uintptr_t pc) +{ + do_raise_exception_err(env, exception, 0, pc); +} + #if !defined(CONFIG_USER_ONLY) =20 void mmu_init(CPUMIPSState *env, const mips_def_t *def); diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 949b8ef94ea..61d0dd69751 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -218,112 +218,12 @@ static void mips_cpu_dump_state(CPUState *cs, FILE *= f, int flags) } } =20 -static const char * const excp_names[EXCP_LAST + 1] =3D { - [EXCP_RESET] =3D "reset", - [EXCP_SRESET] =3D "soft reset", - [EXCP_DSS] =3D "debug single step", - [EXCP_DINT] =3D "debug interrupt", - [EXCP_NMI] =3D "non-maskable interrupt", - [EXCP_MCHECK] =3D "machine check", - [EXCP_EXT_INTERRUPT] =3D "interrupt", - [EXCP_DFWATCH] =3D "deferred watchpoint", - [EXCP_DIB] =3D "debug instruction breakpoint", - [EXCP_IWATCH] =3D "instruction fetch watchpoint", - [EXCP_AdEL] =3D "address error load", - [EXCP_AdES] =3D "address error store", - [EXCP_TLBF] =3D "TLB refill", - [EXCP_IBE] =3D "instruction bus error", - [EXCP_DBp] =3D "debug breakpoint", - [EXCP_SYSCALL] =3D "syscall", - [EXCP_BREAK] =3D "break", - [EXCP_CpU] =3D "coprocessor unusable", - [EXCP_RI] =3D "reserved instruction", - [EXCP_OVERFLOW] =3D "arithmetic overflow", - [EXCP_TRAP] =3D "trap", - [EXCP_FPE] =3D "floating point", - [EXCP_DDBS] =3D "debug data break store", - [EXCP_DWATCH] =3D "data watchpoint", - [EXCP_LTLBL] =3D "TLB modify", - [EXCP_TLBL] =3D "TLB load", - [EXCP_TLBS] =3D "TLB store", - [EXCP_DBE] =3D "data bus error", - [EXCP_DDBL] =3D "debug data break load", - [EXCP_THREAD] =3D "thread", - [EXCP_MDMX] =3D "MDMX", - [EXCP_C2E] =3D "precise coprocessor 2", - [EXCP_CACHE] =3D "cache error", - [EXCP_TLBXI] =3D "TLB execute-inhibit", - [EXCP_TLBRI] =3D "TLB read-inhibit", - [EXCP_MSADIS] =3D "MSA disabled", - [EXCP_MSAFPE] =3D "MSA floating point", -}; - -const char *mips_exception_name(int32_t exception) -{ - if (exception < 0 || exception > EXCP_LAST) { - return "unknown"; - } - return excp_names[exception]; -} - void cpu_set_exception_base(int vp_index, target_ulong address) { MIPSCPU *vp =3D MIPS_CPU(qemu_get_cpu(vp_index)); vp->env.exception_base =3D address; } =20 -target_ulong exception_resume_pc(CPUMIPSState *env) -{ - target_ulong bad_pc; - target_ulong isa_mode; - - isa_mode =3D !!(env->hflags & MIPS_HFLAG_M16); - bad_pc =3D env->active_tc.PC | isa_mode; - if (env->hflags & MIPS_HFLAG_BMASK) { - /* - * If the exception was raised from a delay slot, come back to - * the jump. - */ - bad_pc -=3D (env->hflags & MIPS_HFLAG_B16 ? 2 : 4); - } - - return bad_pc; -} - -bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request) -{ - if (interrupt_request & CPU_INTERRUPT_HARD) { - MIPSCPU *cpu =3D MIPS_CPU(cs); - CPUMIPSState *env =3D &cpu->env; - - if (cpu_mips_hw_interrupts_enabled(env) && - cpu_mips_hw_interrupts_pending(env)) { - /* Raise it */ - cs->exception_index =3D EXCP_EXT_INTERRUPT; - env->error_code =3D 0; - mips_cpu_do_interrupt(cs); - return true; - } - } - return false; -} - -void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, - uint32_t exception, - int error_code, - uintptr_t pc) -{ - CPUState *cs =3D env_cpu(env); - - qemu_log_mask(CPU_LOG_INT, "%s: %d (%s) %d\n", - __func__, exception, mips_exception_name(exception), - error_code); - cs->exception_index =3D exception; - env->error_code =3D error_code; - - cpu_loop_exit_restore(cs, pc); -} - static void mips_cpu_set_pc(CPUState *cs, vaddr value) { MIPSCPU *cpu =3D MIPS_CPU(cs); @@ -331,19 +231,6 @@ static void mips_cpu_set_pc(CPUState *cs, vaddr value) mips_cpu_set_error_pc(&cpu->env, value); } =20 -#ifdef CONFIG_TCG -static void mips_cpu_synchronize_from_tb(CPUState *cs, - const TranslationBlock *tb) -{ - MIPSCPU *cpu =3D MIPS_CPU(cs); - CPUMIPSState *env =3D &cpu->env; - - env->active_tc.PC =3D tb->pc; - env->hflags &=3D ~MIPS_HFLAG_BMASK; - env->hflags |=3D tb->flags & MIPS_HFLAG_BMASK; -} -#endif /* CONFIG_TCG */ - static bool mips_cpu_has_work(CPUState *cs) { MIPSCPU *cpu =3D MIPS_CPU(cs); diff --git a/target/mips/exception.c b/target/mips/exception.c new file mode 100644 index 00000000000..ee8319c4e43 --- /dev/null +++ b/target/mips/exception.c @@ -0,0 +1,169 @@ +/* + * MIPS Exceptions processing helpers for QEMU. + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + * + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "internal.h" +#include "exec/helper-proto.h" +#include "exec/exec-all.h" + +target_ulong exception_resume_pc(CPUMIPSState *env) +{ + target_ulong bad_pc; + target_ulong isa_mode; + + isa_mode =3D !!(env->hflags & MIPS_HFLAG_M16); + bad_pc =3D env->active_tc.PC | isa_mode; + if (env->hflags & MIPS_HFLAG_BMASK) { + /* + * If the exception was raised from a delay slot, come back to + * the jump. + */ + bad_pc -=3D (env->hflags & MIPS_HFLAG_B16 ? 2 : 4); + } + + return bad_pc; +} + +void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception, + int error_code) +{ + do_raise_exception_err(env, exception, error_code, 0); +} + +void helper_raise_exception(CPUMIPSState *env, uint32_t exception) +{ + do_raise_exception(env, exception, GETPC()); +} + +void helper_raise_exception_debug(CPUMIPSState *env) +{ + do_raise_exception(env, EXCP_DEBUG, 0); +} + +static void raise_exception(CPUMIPSState *env, uint32_t exception) +{ + do_raise_exception(env, exception, 0); +} + +void helper_wait(CPUMIPSState *env) +{ + CPUState *cs =3D env_cpu(env); + + cs->halted =3D 1; + cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE); + /* + * Last instruction in the block, PC was updated before + * - no need to recover PC and icount. + */ + raise_exception(env, EXCP_HLT); +} + +void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) +{ + MIPSCPU *cpu =3D MIPS_CPU(cs); + CPUMIPSState *env =3D &cpu->env; + + env->active_tc.PC =3D tb->pc; + env->hflags &=3D ~MIPS_HFLAG_BMASK; + env->hflags |=3D tb->flags & MIPS_HFLAG_BMASK; +} + +bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +{ + if (interrupt_request & CPU_INTERRUPT_HARD) { + MIPSCPU *cpu =3D MIPS_CPU(cs); + CPUMIPSState *env =3D &cpu->env; + + if (cpu_mips_hw_interrupts_enabled(env) && + cpu_mips_hw_interrupts_pending(env)) { + /* Raise it */ + cs->exception_index =3D EXCP_EXT_INTERRUPT; + env->error_code =3D 0; + mips_cpu_do_interrupt(cs); + return true; + } + } + return false; +} + +static const char * const excp_names[EXCP_LAST + 1] =3D { + [EXCP_RESET] =3D "reset", + [EXCP_SRESET] =3D "soft reset", + [EXCP_DSS] =3D "debug single step", + [EXCP_DINT] =3D "debug interrupt", + [EXCP_NMI] =3D "non-maskable interrupt", + [EXCP_MCHECK] =3D "machine check", + [EXCP_EXT_INTERRUPT] =3D "interrupt", + [EXCP_DFWATCH] =3D "deferred watchpoint", + [EXCP_DIB] =3D "debug instruction breakpoint", + [EXCP_IWATCH] =3D "instruction fetch watchpoint", + [EXCP_AdEL] =3D "address error load", + [EXCP_AdES] =3D "address error store", + [EXCP_TLBF] =3D "TLB refill", + [EXCP_IBE] =3D "instruction bus error", + [EXCP_DBp] =3D "debug breakpoint", + [EXCP_SYSCALL] =3D "syscall", + [EXCP_BREAK] =3D "break", + [EXCP_CpU] =3D "coprocessor unusable", + [EXCP_RI] =3D "reserved instruction", + [EXCP_OVERFLOW] =3D "arithmetic overflow", + [EXCP_TRAP] =3D "trap", + [EXCP_FPE] =3D "floating point", + [EXCP_DDBS] =3D "debug data break store", + [EXCP_DWATCH] =3D "data watchpoint", + [EXCP_LTLBL] =3D "TLB modify", + [EXCP_TLBL] =3D "TLB load", + [EXCP_TLBS] =3D "TLB store", + [EXCP_DBE] =3D "data bus error", + [EXCP_DDBL] =3D "debug data break load", + [EXCP_THREAD] =3D "thread", + [EXCP_MDMX] =3D "MDMX", + [EXCP_C2E] =3D "precise coprocessor 2", + [EXCP_CACHE] =3D "cache error", + [EXCP_TLBXI] =3D "TLB execute-inhibit", + [EXCP_TLBRI] =3D "TLB read-inhibit", + [EXCP_MSADIS] =3D "MSA disabled", + [EXCP_MSAFPE] =3D "MSA floating point", +}; + +const char *mips_exception_name(int32_t exception) +{ + if (exception < 0 || exception > EXCP_LAST) { + return "unknown"; + } + return excp_names[exception]; +} + +void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, + uint32_t exception, + int error_code, + uintptr_t pc) +{ + CPUState *cs =3D env_cpu(env); + + qemu_log_mask(CPU_LOG_INT, "%s: %d (%s) %d\n", + __func__, exception, mips_exception_name(exception), + error_code); + cs->exception_index =3D exception; + env->error_code =3D error_code; + + cpu_loop_exit_restore(cs, pc); +} diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index c6373d1de3f..94b03be0ea9 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -26,30 +26,6 @@ #include "exec/memop.h" #include "fpu_helper.h" =20 -/*************************************************************************= ****/ -/* Exceptions processing helpers */ - -void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception, - int error_code) -{ - do_raise_exception_err(env, exception, error_code, 0); -} - -void helper_raise_exception(CPUMIPSState *env, uint32_t exception) -{ - do_raise_exception(env, exception, GETPC()); -} - -void helper_raise_exception_debug(CPUMIPSState *env) -{ - do_raise_exception(env, EXCP_DEBUG, 0); -} - -static void raise_exception(CPUMIPSState *env, uint32_t exception) -{ - do_raise_exception(env, exception, 0); -} - /* 64 bits arithmetic for 32 bits hosts */ static inline uint64_t get_HILO(CPUMIPSState *env) { @@ -400,19 +376,6 @@ void helper_pmon(CPUMIPSState *env, int function) } } =20 -void helper_wait(CPUMIPSState *env) -{ - CPUState *cs =3D env_cpu(env); - - cs->halted =3D 1; - cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE); - /* - * Last instruction in the block, PC was updated before - * - no need to recover PC and icount. - */ - raise_exception(env, EXCP_HLT); -} - #if !defined(CONFIG_USER_ONLY) =20 void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr, diff --git a/target/mips/meson.build b/target/mips/meson.build index ff5eb210dfd..e08077bfc18 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -24,6 +24,7 @@ mips_tcg_ss.add(gen) mips_tcg_ss.add(files( 'dsp_helper.c', + 'exception.c', 'fpu_helper.c', 'ldst_helper.c', 'lmmi_helper.c', --=20 2.26.3 From nobody Mon Feb 9 10:44:55 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.44 as permitted sender) client-ip=209.85.128.44; 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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id z14sm21823622wrt.54.2021.04.18.15.53.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Apr 2021 15:53:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=b7B2r8MngKg5MsGtmNycyg6sG5mdHfGJzIr6HUIH8KE=; b=RyrgXoN5CcUf7UiijwMzr8VGdTnaVv7qx/0w1t3wVZoNwsYeKSNXRqH46W5ifFCvRE xBgBt6ybPsiRgV6LyOlzT12AETy6cbMpXA/Z4tuifSQm/Fa/UO/39024EF36PvoT5QTe l/RliCdSV6HkuLTF3dxxjcRoMOQgJck0G4f4mQJjY+8iap8MUj9/zbH0Ahvr/YEG922M aJAV0OuzjVJD4uHv1B6Ny+A98+3Aj1m24yp6z/NFjemEUUIUC8p5b/eRHWL3xx88lu4M jFFqh5Kzx3xiysUMKsg1aSo2cLZ/6EFEGJqyGyeSBwoVopM1PBSzTPl682skINfYH22y 9jEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=b7B2r8MngKg5MsGtmNycyg6sG5mdHfGJzIr6HUIH8KE=; b=NzOviJGgeUs4+kBsMJ4cz8Iaq842t0Nf8aE+gKEAlOfBS8beOqPPXSWU0/Lm+YaT55 /DfbRGNCQSmN1A4TQT0VAB0R26aYxBMHRj1n0L5hd1FDyMkclEode2XgjKAWf1N0YwNC aaEbnxmRV7IR2cHX71+PFQ3ByBmHiKDC8U4NaLBW0b2f+yxo2UTMXiC5QNnsCttBanS0 Eo/DAdlZTJsgiAtzGJqeVMjYF8HTFA65kDw6R+w4vSQ9VnnG6D02DUtvbfHLEbhmUnfj v/cSj0ZB5J0H7EtTU/XMw5vVzXlxJCzLVI/ANY3VExD4vfiDoW7KVGBMdJi7RDqkWwEA Z6Aw== X-Gm-Message-State: AOAM530X6tfTDPe/eFwSYvdQD7tPN1Yk0NnGaJUz2iL3M9E7/Uj8rh43 TpnJIQVBL+h/28PXNIxMYyA= X-Google-Smtp-Source: ABdhPJw3yAZPoFS2mxN/G35cCs6IEtvoc/ZIJkXC1TxXklcctjPms70V4nX601n3c8NsrIJBI9hl0A== X-Received: by 2002:a1c:7311:: with SMTP id d17mr18152032wmb.183.1618786384693; Sun, 18 Apr 2021 15:53:04 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen , Jiaxun Yang , Aleksandar Rikalo Subject: [PATCH v2 26/29] target/mips: Move CP0 helpers to sysemu/cp0.c Date: Mon, 19 Apr 2021 00:50:55 +0200 Message-Id: <20210418225058.1257014-27-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210418225058.1257014-1-f4bug@amsat.org> References: <20210418225058.1257014-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Opcodes accessing Coprocessor 0 are privileged. Move the CP0 helpers to sysemu/ and simplify the #ifdef'ry. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/internal.h | 9 +-- target/mips/cpu.c | 103 --------------------------- target/mips/sysemu/cp0.c | 123 +++++++++++++++++++++++++++++++++ target/mips/sysemu/meson.build | 1 + 4 files changed, 129 insertions(+), 107 deletions(-) create mode 100644 target/mips/sysemu/cp0.c diff --git a/target/mips/internal.h b/target/mips/internal.h index 8158078b08b..588e89cfcda 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -156,6 +156,11 @@ void mips_cpu_do_transaction_failed(CPUState *cs, hwad= dr physaddr, MMUAccessType access_type, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retadd= r); + +void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc); +void cpu_mips_store_status(CPUMIPSState *env, target_ulong val); +void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val); + extern const VMStateDescription vmstate_mips_cpu; =20 #endif /* !CONFIG_USER_ONLY */ @@ -406,8 +411,4 @@ static inline void compute_hflags(CPUMIPSState *env) } } =20 -void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc); -void cpu_mips_store_status(CPUMIPSState *env, target_ulong val); -void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val); - #endif diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 61d0dd69751..9dec912af98 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -42,109 +42,6 @@ const char regnames[32][4] =3D { "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", }; =20 -#if !defined(CONFIG_USER_ONLY) - -/* Called for updates to CP0_Status. */ -void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc) -{ - int32_t tcstatus, *tcst; - uint32_t v =3D cpu->CP0_Status; - uint32_t cu, mx, asid, ksu; - uint32_t mask =3D ((1 << CP0TCSt_TCU3) - | (1 << CP0TCSt_TCU2) - | (1 << CP0TCSt_TCU1) - | (1 << CP0TCSt_TCU0) - | (1 << CP0TCSt_TMX) - | (3 << CP0TCSt_TKSU) - | (0xff << CP0TCSt_TASID)); - - cu =3D (v >> CP0St_CU0) & 0xf; - mx =3D (v >> CP0St_MX) & 0x1; - ksu =3D (v >> CP0St_KSU) & 0x3; - asid =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; - - tcstatus =3D cu << CP0TCSt_TCU0; - tcstatus |=3D mx << CP0TCSt_TMX; - tcstatus |=3D ksu << CP0TCSt_TKSU; - tcstatus |=3D asid; - - if (tc =3D=3D cpu->current_tc) { - tcst =3D &cpu->active_tc.CP0_TCStatus; - } else { - tcst =3D &cpu->tcs[tc].CP0_TCStatus; - } - - *tcst &=3D ~mask; - *tcst |=3D tcstatus; - compute_hflags(cpu); -} - -void cpu_mips_store_status(CPUMIPSState *env, target_ulong val) -{ - uint32_t mask =3D env->CP0_Status_rw_bitmask; - target_ulong old =3D env->CP0_Status; - - if (env->insn_flags & ISA_MIPS_R6) { - bool has_supervisor =3D extract32(mask, CP0St_KSU, 2) =3D=3D 0x3; -#if defined(TARGET_MIPS64) - uint32_t ksux =3D (1 << CP0St_KX) & val; - ksux |=3D (ksux >> 1) & val; /* KX =3D 0 forces SX to be 0 */ - ksux |=3D (ksux >> 1) & val; /* SX =3D 0 forces UX to be 0 */ - val =3D (val & ~(7 << CP0St_UX)) | ksux; -#endif - if (has_supervisor && extract32(val, CP0St_KSU, 2) =3D=3D 0x3) { - mask &=3D ~(3 << CP0St_KSU); - } - mask &=3D ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val); - } - - env->CP0_Status =3D (old & ~mask) | (val & mask); -#if defined(TARGET_MIPS64) - if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) { - /* Access to at least one of the 64-bit segments has been disabled= */ - tlb_flush(env_cpu(env)); - } -#endif - if (ase_mt_available(env)) { - sync_c0_status(env, env, env->current_tc); - } else { - compute_hflags(env); - } -} - -void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val) -{ - uint32_t mask =3D 0x00C00300; - uint32_t old =3D env->CP0_Cause; - int i; - - if (env->insn_flags & ISA_MIPS_R2) { - mask |=3D 1 << CP0Ca_DC; - } - if (env->insn_flags & ISA_MIPS_R6) { - mask &=3D ~((1 << CP0Ca_WP) & val); - } - - env->CP0_Cause =3D (env->CP0_Cause & ~mask) | (val & mask); - - if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) { - if (env->CP0_Cause & (1 << CP0Ca_DC)) { - cpu_mips_stop_count(env); - } else { - cpu_mips_start_count(env); - } - } - - /* Set/reset software interrupts */ - for (i =3D 0 ; i < 2 ; i++) { - if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) { - cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i= ))); - } - } -} - -#endif /* !CONFIG_USER_ONLY */ - static void fpu_dump_fpr(fpr_t *fpr, FILE *f, bool is_fpu64) { if (is_fpu64) { diff --git a/target/mips/sysemu/cp0.c b/target/mips/sysemu/cp0.c new file mode 100644 index 00000000000..bae37f515bf --- /dev/null +++ b/target/mips/sysemu/cp0.c @@ -0,0 +1,123 @@ +/* + * QEMU MIPS CPU + * + * Copyright (c) 2012 SUSE LINUX Products GmbH + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see + * + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "internal.h" +#include "exec/exec-all.h" + +/* Called for updates to CP0_Status. */ +void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc) +{ + int32_t tcstatus, *tcst; + uint32_t v =3D cpu->CP0_Status; + uint32_t cu, mx, asid, ksu; + uint32_t mask =3D ((1 << CP0TCSt_TCU3) + | (1 << CP0TCSt_TCU2) + | (1 << CP0TCSt_TCU1) + | (1 << CP0TCSt_TCU0) + | (1 << CP0TCSt_TMX) + | (3 << CP0TCSt_TKSU) + | (0xff << CP0TCSt_TASID)); + + cu =3D (v >> CP0St_CU0) & 0xf; + mx =3D (v >> CP0St_MX) & 0x1; + ksu =3D (v >> CP0St_KSU) & 0x3; + asid =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; + + tcstatus =3D cu << CP0TCSt_TCU0; + tcstatus |=3D mx << CP0TCSt_TMX; + tcstatus |=3D ksu << CP0TCSt_TKSU; + tcstatus |=3D asid; + + if (tc =3D=3D cpu->current_tc) { + tcst =3D &cpu->active_tc.CP0_TCStatus; + } else { + tcst =3D &cpu->tcs[tc].CP0_TCStatus; + } + + *tcst &=3D ~mask; + *tcst |=3D tcstatus; + compute_hflags(cpu); +} + +void cpu_mips_store_status(CPUMIPSState *env, target_ulong val) +{ + uint32_t mask =3D env->CP0_Status_rw_bitmask; + target_ulong old =3D env->CP0_Status; + + if (env->insn_flags & ISA_MIPS_R6) { + bool has_supervisor =3D extract32(mask, CP0St_KSU, 2) =3D=3D 0x3; +#if defined(TARGET_MIPS64) + uint32_t ksux =3D (1 << CP0St_KX) & val; + ksux |=3D (ksux >> 1) & val; /* KX =3D 0 forces SX to be 0 */ + ksux |=3D (ksux >> 1) & val; /* SX =3D 0 forces UX to be 0 */ + val =3D (val & ~(7 << CP0St_UX)) | ksux; +#endif + if (has_supervisor && extract32(val, CP0St_KSU, 2) =3D=3D 0x3) { + mask &=3D ~(3 << CP0St_KSU); + } + mask &=3D ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val); + } + + env->CP0_Status =3D (old & ~mask) | (val & mask); +#if defined(TARGET_MIPS64) + if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) { + /* Access to at least one of the 64-bit segments has been disabled= */ + tlb_flush(env_cpu(env)); + } +#endif + if (ase_mt_available(env)) { + sync_c0_status(env, env, env->current_tc); + } else { + compute_hflags(env); + } +} + +void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val) +{ + uint32_t mask =3D 0x00C00300; + uint32_t old =3D env->CP0_Cause; + int i; + + if (env->insn_flags & ISA_MIPS_R2) { + mask |=3D 1 << CP0Ca_DC; + } + if (env->insn_flags & ISA_MIPS_R6) { + mask &=3D ~((1 << CP0Ca_WP) & val); + } + + env->CP0_Cause =3D (env->CP0_Cause & ~mask) | (val & mask); + + if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) { + if (env->CP0_Cause & (1 << CP0Ca_DC)) { + cpu_mips_stop_count(env); + } else { + cpu_mips_start_count(env); + } + } + + /* Set/reset software interrupts */ + for (i =3D 0 ; i < 2 ; i++) { + if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) { + cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i= ))); + } + } +} diff --git a/target/mips/sysemu/meson.build b/target/mips/sysemu/meson.build index 925ceeaa449..cefc2275828 100644 --- a/target/mips/sysemu/meson.build +++ b/target/mips/sysemu/meson.build @@ -1,5 +1,6 @@ mips_softmmu_ss.add(files( 'addr.c', + 'cp0.c', 'cp0_timer.c', 'machine.c', 'physaddr.c', --=20 2.26.3 From nobody Mon Feb 9 10:44:55 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.46 as permitted sender) client-ip=209.85.221.46; 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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id l20sm17861921wmg.33.2021.04.18.15.53.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Apr 2021 15:53:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FVrIMG0ikRSFfBCOQgXFDL1QwI5kw8IQhpeNT3H1Bwg=; b=LrL0J3EdjTk1VA0k8jY2ji1Rem1FICxNZa3FeYtQDg3kuzUc+f1x6F2+OBfe+cuetr Jrphm30x7Ud3p0oSf1d9LBSXVvRKxu02MTLIBFjs/is8kGyiWGSe2ZxM8Drw+PKNWcbN S/vxSrjRMc9vnsP7X5hqsRfEjo+RTJ+WU7pML6xiompmSi8xryJT5I0YLPfzlHMQ/S2B S9eF+SaGp/oD7JldVRstnW59DsR/WPTN9Q1D/kWTzc2DrJXCDJN9rX7nYu4qPqggkvfY 75JBaf5IqWs+ZyDAej3P2f8OgoxmLclY2KvUaSQxoxl2sSK3Ben5/q7EXpBvQ/B9vNSP z7TQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=FVrIMG0ikRSFfBCOQgXFDL1QwI5kw8IQhpeNT3H1Bwg=; b=nOdpRWpf58Yu97Kv5goI7HW17psGppMZ7KpA/LWi4UhHOPyl7PckkVs5S2nTpxwvSf Crh1yju41PFzm1Px8ft/78Z4JBSdGC0TaUfdJ0AVneDOxsVZ5myRIFedhIltR+4DPfbV fqQHnhpSDnx5C6bnU0WlWq0qIOeTimLLlH1o2DyXwqkhhN470ocZten8KKOMwWRktfUP ozAPoNQq2pY28nhy7ePvQfcIy0VEJkiZ2Q/StayOQ/FO3nU2NtAdXu5+sxKfABhZG1ak enqh7O5QOwcbd3DKlvDNrOcejOqBOqvwA2jh/wyABFfwD7Bxmgs2BSLB/yeoqewj6m0M JFNA== X-Gm-Message-State: AOAM532sZeDwGT48pqRKKHeGdss448Wb/Vt08TPNh5XmXdCoL2wJxuB7 X0xL16KAUxSNYXSNkYr068A= X-Google-Smtp-Source: ABdhPJx4E1F1iSjvYkwlBYrq1MtAf04HjaLsv8ZmuixOJUaivMwlWUQfw6kNerfPven8NvwfHjMMkw== X-Received: by 2002:adf:fdc7:: with SMTP id i7mr10959979wrs.350.1618786389564; Sun, 18 Apr 2021 15:53:09 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen , Jiaxun Yang , Aleksandar Rikalo Subject: [PATCH v2 27/29] target/mips: Move TCG source files under tcg/ sub directory Date: Mon, 19 Apr 2021 00:50:56 +0200 Message-Id: <20210418225058.1257014-28-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210418225058.1257014-1-f4bug@amsat.org> References: <20210418225058.1257014-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) To ease maintenance, move all TCG specific files under the tcg/ sub-directory. Adapt the Meson machinery. The following prototypes: - mips_tcg_init() - mips_cpu_do_unaligned_access() - mips_cpu_do_transaction_failed() can now be restricted to the "tcg-internal.h" header. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/helper.h | 2 +- target/mips/internal.h | 11 ------- target/mips/tcg/tcg-internal.h | 11 +++++++ target/mips/{ =3D> tcg}/msa_helper.h.inc | 0 target/mips/{ =3D> tcg}/mips32r6.decode | 0 target/mips/{ =3D> tcg}/mips64r6.decode | 0 target/mips/{ =3D> tcg}/msa32.decode | 0 target/mips/{ =3D> tcg}/msa64.decode | 0 target/mips/{ =3D> tcg}/tx79.decode | 0 target/mips/{ =3D> tcg}/dsp_helper.c | 0 target/mips/{ =3D> tcg}/exception.c | 0 target/mips/{ =3D> tcg}/fpu_helper.c | 0 target/mips/{ =3D> tcg}/ldst_helper.c | 0 target/mips/{ =3D> tcg}/lmmi_helper.c | 0 target/mips/{ =3D> tcg}/msa_helper.c | 0 target/mips/{ =3D> tcg}/msa_translate.c | 0 target/mips/{ =3D> tcg}/mxu_translate.c | 0 target/mips/{ =3D> tcg}/op_helper.c | 0 target/mips/{ =3D> tcg}/rel6_translate.c | 0 target/mips/{ =3D> tcg}/translate.c | 0 target/mips/{ =3D> tcg}/translate_addr_const.c | 0 target/mips/{ =3D> tcg}/tx79_translate.c | 0 target/mips/{ =3D> tcg}/txx9_translate.c | 0 target/mips/meson.build | 31 -------------------- target/mips/tcg/meson.build | 29 ++++++++++++++++++ 25 files changed, 41 insertions(+), 43 deletions(-) rename target/mips/{ =3D> tcg}/msa_helper.h.inc (100%) rename target/mips/{ =3D> tcg}/mips32r6.decode (100%) rename target/mips/{ =3D> tcg}/mips64r6.decode (100%) rename target/mips/{ =3D> tcg}/msa32.decode (100%) rename target/mips/{ =3D> tcg}/msa64.decode (100%) rename target/mips/{ =3D> tcg}/tx79.decode (100%) rename target/mips/{ =3D> tcg}/dsp_helper.c (100%) rename target/mips/{ =3D> tcg}/exception.c (100%) rename target/mips/{ =3D> tcg}/fpu_helper.c (100%) rename target/mips/{ =3D> tcg}/ldst_helper.c (100%) rename target/mips/{ =3D> tcg}/lmmi_helper.c (100%) rename target/mips/{ =3D> tcg}/msa_helper.c (100%) rename target/mips/{ =3D> tcg}/msa_translate.c (100%) rename target/mips/{ =3D> tcg}/mxu_translate.c (100%) rename target/mips/{ =3D> tcg}/op_helper.c (100%) rename target/mips/{ =3D> tcg}/rel6_translate.c (100%) rename target/mips/{ =3D> tcg}/translate.c (100%) rename target/mips/{ =3D> tcg}/translate_addr_const.c (100%) rename target/mips/{ =3D> tcg}/tx79_translate.c (100%) rename target/mips/{ =3D> tcg}/txx9_translate.c (100%) diff --git a/target/mips/helper.h b/target/mips/helper.h index ba301ae160d..a9c6c7d1a31 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -608,4 +608,4 @@ DEF_HELPER_FLAGS_2(rddsp, 0, tl, tl, env) #include "tcg/sysemu_helper.h.inc" #endif /* !CONFIG_USER_ONLY */ =20 -#include "msa_helper.h.inc" +#include "tcg/msa_helper.h.inc" diff --git a/target/mips/internal.h b/target/mips/internal.h index 588e89cfcda..c3c8eb0a177 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -82,9 +82,6 @@ extern const int mips_defs_number; =20 int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); -void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr); =20 #define USEG_LIMIT ((target_ulong)(int32_t)0x7FFFFFFFUL) #define KSEG0_BASE ((target_ulong)(int32_t)0x80000000UL) @@ -151,12 +148,6 @@ struct CPUMIPSTLBContext { } mmu; }; =20 -void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, - vaddr addr, unsigned size, - MMUAccessType access_type, - int mmu_idx, MemTxAttrs attrs, - MemTxResult response, uintptr_t retadd= r); - void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc); void cpu_mips_store_status(CPUMIPSState *env, target_ulong val); void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val); @@ -209,8 +200,6 @@ static inline bool cpu_mips_hw_interrupts_pending(CPUMI= PSState *env) return r; } =20 -void mips_tcg_init(void); - void msa_reset(CPUMIPSState *env); =20 /* cp0_timer.c */ diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h index 70f0d5da436..ae9b35ff706 100644 --- a/target/mips/tcg/tcg-internal.h +++ b/target/mips/tcg/tcg-internal.h @@ -11,15 +11,21 @@ #define MIPS_TCG_INTERNAL_H =20 #include "tcg/tcg.h" +#include "exec/memattrs.h" #include "hw/core/cpu.h" #include "cpu.h" =20 +void mips_tcg_init(void); + void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb= ); void mips_cpu_do_interrupt(CPUState *cpu); bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); +void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr); =20 const char *mips_exception_name(int32_t exception); =20 @@ -46,6 +52,11 @@ bool mips_io_recompile_replay_branch(CPUState *cs, const= TranslationBlock *tb); =20 hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, MMUAccessType access_type); +void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, + vaddr addr, unsigned size, + MMUAccessType access_type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, uintptr_t retadd= r); void cpu_mips_tlb_flush(CPUMIPSState *env); =20 #endif /* !CONFIG_USER_ONLY */ diff --git a/target/mips/msa_helper.h.inc b/target/mips/tcg/msa_helper.h.inc similarity index 100% rename from target/mips/msa_helper.h.inc rename to target/mips/tcg/msa_helper.h.inc diff --git a/target/mips/mips32r6.decode b/target/mips/tcg/mips32r6.decode similarity index 100% rename from target/mips/mips32r6.decode rename to target/mips/tcg/mips32r6.decode diff --git a/target/mips/mips64r6.decode b/target/mips/tcg/mips64r6.decode similarity index 100% rename from target/mips/mips64r6.decode rename to target/mips/tcg/mips64r6.decode diff --git a/target/mips/msa32.decode b/target/mips/tcg/msa32.decode similarity index 100% rename from target/mips/msa32.decode rename to target/mips/tcg/msa32.decode diff --git a/target/mips/msa64.decode b/target/mips/tcg/msa64.decode similarity index 100% rename from target/mips/msa64.decode rename to target/mips/tcg/msa64.decode diff --git a/target/mips/tx79.decode b/target/mips/tcg/tx79.decode similarity index 100% rename from target/mips/tx79.decode rename to target/mips/tcg/tx79.decode diff --git a/target/mips/dsp_helper.c b/target/mips/tcg/dsp_helper.c similarity index 100% rename from target/mips/dsp_helper.c rename to target/mips/tcg/dsp_helper.c diff --git a/target/mips/exception.c b/target/mips/tcg/exception.c similarity index 100% rename from target/mips/exception.c rename to target/mips/tcg/exception.c diff --git a/target/mips/fpu_helper.c b/target/mips/tcg/fpu_helper.c similarity index 100% rename from target/mips/fpu_helper.c rename to target/mips/tcg/fpu_helper.c diff --git a/target/mips/ldst_helper.c b/target/mips/tcg/ldst_helper.c similarity index 100% rename from target/mips/ldst_helper.c rename to target/mips/tcg/ldst_helper.c diff --git a/target/mips/lmmi_helper.c b/target/mips/tcg/lmmi_helper.c similarity index 100% rename from target/mips/lmmi_helper.c rename to target/mips/tcg/lmmi_helper.c diff --git a/target/mips/msa_helper.c b/target/mips/tcg/msa_helper.c similarity index 100% rename from target/mips/msa_helper.c rename to target/mips/tcg/msa_helper.c diff --git a/target/mips/msa_translate.c b/target/mips/tcg/msa_translate.c similarity index 100% rename from target/mips/msa_translate.c rename to target/mips/tcg/msa_translate.c diff --git a/target/mips/mxu_translate.c b/target/mips/tcg/mxu_translate.c similarity index 100% rename from target/mips/mxu_translate.c rename to target/mips/tcg/mxu_translate.c diff --git a/target/mips/op_helper.c b/target/mips/tcg/op_helper.c similarity index 100% rename from target/mips/op_helper.c rename to target/mips/tcg/op_helper.c diff --git a/target/mips/rel6_translate.c b/target/mips/tcg/rel6_translate.c similarity index 100% rename from target/mips/rel6_translate.c rename to target/mips/tcg/rel6_translate.c diff --git a/target/mips/translate.c b/target/mips/tcg/translate.c similarity index 100% rename from target/mips/translate.c rename to target/mips/tcg/translate.c diff --git a/target/mips/translate_addr_const.c b/target/mips/tcg/translate= _addr_const.c similarity index 100% rename from target/mips/translate_addr_const.c rename to target/mips/tcg/translate_addr_const.c diff --git a/target/mips/tx79_translate.c b/target/mips/tcg/tx79_translate.c similarity index 100% rename from target/mips/tx79_translate.c rename to target/mips/tcg/tx79_translate.c diff --git a/target/mips/txx9_translate.c b/target/mips/tcg/txx9_translate.c similarity index 100% rename from target/mips/txx9_translate.c rename to target/mips/tcg/txx9_translate.c diff --git a/target/mips/meson.build b/target/mips/meson.build index e08077bfc18..2407a05d4c0 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -1,11 +1,3 @@ -gen =3D [ - decodetree.process('mips32r6.decode', extra_args: '--static-decode=3Ddec= ode_mips32r6'), - decodetree.process('mips64r6.decode', extra_args: '--static-decode=3Ddec= ode_mips64r6'), - decodetree.process('msa32.decode', extra_args: '--static-decode=3Ddecode= _msa32'), - decodetree.process('msa64.decode', extra_args: '--static-decode=3Ddecode= _msa64'), - decodetree.process('tx79.decode', extra_args: '--static-decode=3Ddecode_= tx79'), -] - mips_user_ss =3D ss.source_set() mips_softmmu_ss =3D ss.source_set() mips_ss =3D ss.source_set() @@ -20,35 +12,12 @@ subdir('sysemu') endif =20 -mips_tcg_ss =3D ss.source_set() -mips_tcg_ss.add(gen) -mips_tcg_ss.add(files( - 'dsp_helper.c', - 'exception.c', - 'fpu_helper.c', - 'ldst_helper.c', - 'lmmi_helper.c', - 'msa_helper.c', - 'msa_translate.c', - 'op_helper.c', - 'rel6_translate.c', - 'translate.c', - 'translate_addr_const.c', - 'txx9_translate.c', -)) -mips_tcg_ss.add(when: 'TARGET_MIPS64', if_true: files( - 'tx79_translate.c', -), if_false: files( - 'mxu_translate.c', -)) if 'CONFIG_TCG' in config_all subdir('tcg') endif =20 mips_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) =20 -mips_ss.add_all(when: 'CONFIG_TCG', if_true: [mips_tcg_ss]) - target_arch +=3D {'mips': mips_ss} target_softmmu_arch +=3D {'mips': mips_softmmu_ss} target_user_arch +=3D {'mips': mips_user_ss} diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build index 2cffc5a5ac6..5d8acbaf0d3 100644 --- a/target/mips/tcg/meson.build +++ b/target/mips/tcg/meson.build @@ -1,3 +1,32 @@ +gen =3D [ + decodetree.process('mips32r6.decode', extra_args: '--static-decode=3Ddec= ode_mips32r6'), + decodetree.process('mips64r6.decode', extra_args: '--static-decode=3Ddec= ode_mips64r6'), + decodetree.process('msa32.decode', extra_args: '--static-decode=3Ddecode= _msa32'), + decodetree.process('msa64.decode', extra_args: '--static-decode=3Ddecode= _msa64'), + decodetree.process('tx79.decode', extra_args: '--static-decode=3Ddecode_= tx79'), +] + +mips_ss.add(gen) +mips_ss.add(files( + 'dsp_helper.c', + 'exception.c', + 'fpu_helper.c', + 'ldst_helper.c', + 'lmmi_helper.c', + 'msa_helper.c', + 'msa_translate.c', + 'op_helper.c', + 'rel6_translate.c', + 'translate.c', + 'translate_addr_const.c', + 'txx9_translate.c', +)) +mips_ss.add(when: 'TARGET_MIPS64', if_true: files( + 'tx79_translate.c', +), if_false: files( + 'mxu_translate.c', +)) + if have_user subdir('user') endif --=20 2.26.3 From nobody Mon Feb 9 10:44:55 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.41 as permitted sender) client-ip=209.85.221.41; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f41.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.41 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1618786396; cv=none; d=zohomail.com; s=zohoarc; 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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id e10sm2913045wrw.20.2021.04.18.15.53.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Apr 2021 15:53:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=oEwKjogwzqew9LHnVJfSpLxM+9Yj6ci2FrJpneJ2XN0=; b=FUCGQgPAzx7EBNV7Cv9or+sgjH69Cp32GVtsD6mBlb1UkLz9s+SwNx85fjc+ET8nBU +7qOYGiq34cYy5Jg9hGJ0OpsARDt9mwo1PUsiB0+MtVazcnIaeq4rx9Er3ndkKxLqmr5 JtpVwQ1EHagAGptfxet91iSl1NbAALDeZ4Uvtj9GADeMptQyBAnH2Sg5ga9CejMy/ruL YT8mcSX2n7/DMyK5duP5JBBLXcAKN+xNhmUuVA8WIcTFkUB0zEsRY4fR6XBEjzsa93Ht C54BRAvEYcf948Lu8O/rRPb3lGNc1/emLbgyJ/19X6w5mTsNyZudowYm2m02mlcAdhLY NIjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=oEwKjogwzqew9LHnVJfSpLxM+9Yj6ci2FrJpneJ2XN0=; b=Kn7j4zQUHLloU2bT/5Cby9F+puj0u2wCBdzShtqWLiSkGd91hwj3nxpOvu8krIDmts Wav3ypSPzPEu/RjbFZHXy5Q1slakGBlRpYksaUVceE4CoqVeYxn/drHtRFdyPRYCCaPk Ph5CRgpoYdysg0zrv3Wu4x2MI5XHaWnB4EtOLkT/U7oefqR5A2ij1umN8bMajCZtO8hn W/FdtMB8RKilDBqv3qkP816ByflcRNSqJ2xRhkzxDU2EajJks+fkwMh7co12PO1Fxnyd NC1TN4byPYG5DKB+ugoY3PN18tOHVPdzi9RlYYZSE6zyy0CMiP+1VlkjGAegkOisvffq OYPA== X-Gm-Message-State: AOAM531OrMkoaI6L7CkO2HThKN8AhdFLetB+Q4STsw0qmqoZNSQ0DrM/ n0GO+MHn2NjEBujlb83fVVI= X-Google-Smtp-Source: ABdhPJxj3mbCKVtixNWtCN/J5ea7YiCLr+94dbSkq3ZHFJG08yyJRbAupL1ZQVMmD8XoxSEX1wlmcw== X-Received: by 2002:adf:f80b:: with SMTP id s11mr10714459wrp.231.1618786394470; Sun, 18 Apr 2021 15:53:14 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen , Jiaxun Yang , Aleksandar Rikalo Subject: [PATCH v2 28/29] hw/mips: Restrict non-virtualized machines to TCG Date: Mon, 19 Apr 2021 00:50:57 +0200 Message-Id: <20210418225058.1257014-29-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210418225058.1257014-1-f4bug@amsat.org> References: <20210418225058.1257014-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Only the malta and loongson3-virt machines support KVM. Restrict the other machines to TCG: - mipssim - magnum - pica61 - fuloong2e - boston Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/mips/meson.build | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/hw/mips/meson.build b/hw/mips/meson.build index 1195716dc73..dd0101ad4d8 100644 --- a/hw/mips/meson.build +++ b/hw/mips/meson.build @@ -1,12 +1,15 @@ mips_ss =3D ss.source_set() mips_ss.add(files('bootloader.c', 'mips_int.c')) mips_ss.add(when: 'CONFIG_FW_CFG_MIPS', if_true: files('fw_cfg.c')) -mips_ss.add(when: 'CONFIG_FULOONG', if_true: files('fuloong2e.c')) mips_ss.add(when: 'CONFIG_LOONGSON3V', if_true: files('loongson3_bootp.c',= 'loongson3_virt.c')) -mips_ss.add(when: 'CONFIG_JAZZ', if_true: files('jazz.c')) mips_ss.add(when: 'CONFIG_MALTA', if_true: files('gt64xxx_pci.c', 'malta.c= ')) -mips_ss.add(when: 'CONFIG_MIPSSIM', if_true: files('mipssim.c')) -mips_ss.add(when: 'CONFIG_MIPS_BOSTON', if_true: [files('boston.c'), fdt]) mips_ss.add(when: 'CONFIG_MIPS_CPS', if_true: files('cps.c')) =20 +if 'CONFIG_TCG' in config_all +mips_ss.add(when: 'CONFIG_JAZZ', if_true: files('jazz.c')) +mips_ss.add(when: 'CONFIG_MIPSSIM', if_true: files('mipssim.c')) +mips_ss.add(when: 'CONFIG_FULOONG', if_true: files('fuloong2e.c')) +mips_ss.add(when: 'CONFIG_MIPS_BOSTON', if_true: [files('boston.c'), fdt]) +endif + hw_arch +=3D {'mips': mips_ss} --=20 2.26.3 From nobody Mon Feb 9 10:44:55 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.46 as permitted sender) client-ip=209.85.221.46; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f46.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.46 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1618786400; cv=none; d=zohomail.com; s=zohoarc; b=NB9Kdzk+glcr/UZ433S9sq1k6gS6YpDAEGqzavh+VwEPtrRh7a5q+9gdYskMMa4T+5Rt41dtVe1ZFut//Eu9P89QYqqDhE2jpZqa+uN8CG8bz4U8hHvE7aswweKbZVg+S/P8wQ0HfGeAuM7y5UVf+hHG5bOfzVxcseyEb1jWa8U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618786400; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=evwnaA8cIdCjxIuHS6DqhR3yWKvMOcmCdSzq2jJjUOM=; b=G1Nkca+7oiQzf2fV3X9QCeST7Dh8dtKsejpiTfdLdDl5fqpacnwlV8vv4yZwvwBD8HsSCHpCXWGJ7rTKSQYLwYiILBJl0lrU7WWPb2VNvHYE8fUoirTfNw96l8p69blIIrMmRd2mJQsWf0uYF3VtY/GQwnVM4NVpYYT4J2eOZ/Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.46 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f46.google.com (mail-wr1-f46.google.com [209.85.221.46]) by mx.zohomail.com with SMTPS id 1618786400896829.200893328714; Sun, 18 Apr 2021 15:53:20 -0700 (PDT) Received: by mail-wr1-f46.google.com with SMTP id w4so28313604wrt.5 for ; Sun, 18 Apr 2021 15:53:20 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id q17sm20376364wro.33.2021.04.18.15.53.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Apr 2021 15:53:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=evwnaA8cIdCjxIuHS6DqhR3yWKvMOcmCdSzq2jJjUOM=; b=sNFJmPvZMVxZbRCedtM0rQLK9kJK5303YCzhVLKK9Hy4RLRkXEUFYNu+Z11S03FEa3 vye5q9n3LMX5eRHbzJjKTMN9ApiIayg7Yu4KOTrfrClA508IMnhvkOU1zpmX+Wmj6hTF zk/z3TlanL4Fxek6aIk+vQP6ZEczfGVrd0psxbu8D99rAsRRVCOOzm3UHQM/xARwSN46 BKoXh1Gh8w1mDmFerHoivd+ZzWt+mK4w1TuF/cwooT7i2wNh58JzUIiPicHpvrasijnu 9BRifIrFdPo64heb/K2/TBP9pr2TP+buSQtaE4K5SG9pTNsJ/1XBBwIfD0+DRetxFvxb xmhw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=evwnaA8cIdCjxIuHS6DqhR3yWKvMOcmCdSzq2jJjUOM=; b=ucuMOQ9/hBR8Tyv2O7sCeC6Y3qwUS7BbTcncij4KA7WSN4ROC3FnB1SrRrq1qLVjPt jyn7QbxtsSesrzEuU2yV6vlgwFu8EBbplKvlPWuCZl7QGW44Fdy+O86MbZkLOwljYTos nmfmNh6aY0RoBpDo7zGt8ATb+WYxxx0JyUVnlqCwIieS/guu++2D5r27BwQ+tS9qlyGj 2JCU3zq1BGWXdVPcLXKpGmtbckglbOX6gUoW17PCs48ezDbs0PGpdneMAirror1R+zTd pjcrbVhFSxOmc07xpI0YxAPauJeHygpKH6/dvYYp3Pr/k8EnL6MAP3MJnTrf2rc5AlTM BjQw== X-Gm-Message-State: AOAM530r68GkImYrRpi5HP17E0iDnwupQ0mKHYIushQC8T+mV7C90r1G JH2zjVx98bwCsu/uYicJRLQ= X-Google-Smtp-Source: ABdhPJzQZO3IkyXBFCVqdWhAK9OTFGIkwN7lUpb02ZKoOR6iHNAApW7EXsh1Betl2wU+eE0eE22IMw== X-Received: by 2002:adf:e790:: with SMTP id n16mr10721262wrm.278.1618786399178; Sun, 18 Apr 2021 15:53:19 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen , Jiaxun Yang , Aleksandar Rikalo , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Thomas Huth , Wainer dos Santos Moschetta , Willian Rampazzo Subject: [PATCH v2 29/29] gitlab-ci: Add KVM mips64el cross-build jobs Date: Mon, 19 Apr 2021 00:50:58 +0200 Message-Id: <20210418225058.1257014-30-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210418225058.1257014-1-f4bug@amsat.org> References: <20210418225058.1257014-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Add a new job to cross-build the mips64el target without the TCG accelerator (IOW: only KVM accelerator enabled). Only build the mips64el target which is known to work and has users. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Thomas Huth --- .gitlab-ci.d/crossbuilds.yml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/.gitlab-ci.d/crossbuilds.yml b/.gitlab-ci.d/crossbuilds.yml index 2d95784ed51..e44e4b49a25 100644 --- a/.gitlab-ci.d/crossbuilds.yml +++ b/.gitlab-ci.d/crossbuilds.yml @@ -176,6 +176,14 @@ cross-s390x-kvm-only: IMAGE: debian-s390x-cross ACCEL_CONFIGURE_OPTS: --disable-tcg =20 +cross-mips64el-kvm-only: + extends: .cross_accel_build_job + needs: + job: mips64el-debian-cross-container + variables: + IMAGE: debian-mips64el-cross + ACCEL_CONFIGURE_OPTS: --disable-tcg --target-list=3Dmips64el-softmmu + cross-win32-system: extends: .cross_system_build_job needs: --=20 2.26.3