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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id p14sm19488676wrn.49.2021.04.18.09.33.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Apr 2021 09:33:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9aVDjscrzB3ow8BOCfGrETyqSXdEWr7eXbOjIPWKjdA=; b=b4zOcCQRrtkeLGa0bIT8BNcXq783RM20kWG6KvBZP1OFRzP+ldT/g53Dnp0H3hEp0m YAx3cAJLG+EeCt1KLDziKR44YUZB5AezTsA8QqwGwsmLhaUmUijz9dh8nbhqoOafL5/H TWXZs5ASnaB0xdeCtwyey3a5duykf4Km7plkHKpMRsYt/apgHEhVTfROjJwpAXv2YGdG IFuyz9Y1VZyw8z7wff6sm2erJOiJqhLBDQ9cGM4SS8ZoPHMPj5R/7mo/uOblSbRjkC04 o9QTwhl1+VleM+TwQEAlPGzJCa1RWIIP8plp2TA/czbL6YusEUAi/s14j6tEBv7uufje MKYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=9aVDjscrzB3ow8BOCfGrETyqSXdEWr7eXbOjIPWKjdA=; b=d3lZfE1wlTptMz8gOGlRD42SnXJB6A5wVKEr7JIpOgv5XZB2ykm88kiICHli219Tj+ qFxBHAogWolHTvSiPfujVZGLov0rOMlAKGkZ1adJqhcIqyNQcHkN1Ha6suxLu2FergcN Zoq+QUwZ7lwgdrjB9JKN5e3aQu1y9CcCSA81TnYzfw0297IoT5vfOB6CWuN5cxQzWGld totAwX4G82iq+cj6rS2TRiDPWqUm32BlxUlYVtGe+eI/zoAGaDHM9zo1zIZJmM2028iP pMkGq6X22oifaSRfkkoTYuzFXit6wcyNGAoTNNFc3eRIrn6kMplRHFXyfnGA27JiuPJl EMkw== X-Gm-Message-State: AOAM5324u7yBR6HQnwOqqyvaoh4cv8WzYTGniBQ/z22i96qVDgvFKGCn o6GFyywZcvhPhnru1Ex5cWg= X-Google-Smtp-Source: ABdhPJyUd4C1QhxwMB3eYvSsZ0o+0OeNh7MslYDzHCDIuz60cpViLmyrwIe73d+G9e9xHEkja3lRvw== X-Received: by 2002:a1c:2541:: with SMTP id l62mr17655746wml.188.1618763602001; Sun, 18 Apr 2021 09:33:22 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Huacai Chen , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang , Richard Henderson , Aurelien Jarno Subject: [PATCH 22/26] target/mips: Move CP0 helpers to sysemu/cp0.c Date: Sun, 18 Apr 2021 18:31:30 +0200 Message-Id: <20210418163134.1133100-23-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210418163134.1133100-1-f4bug@amsat.org> References: <20210418163134.1133100-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Opcodes accessing Coprocessor 0 are privileged. Move the CP0 helpers to sysemu/ and simplify the #ifdef'ry. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/internal.h | 9 +-- target/mips/cpu.c | 103 --------------------------- target/mips/sysemu/cp0.c | 123 +++++++++++++++++++++++++++++++++ target/mips/sysemu/meson.build | 1 + 4 files changed, 129 insertions(+), 107 deletions(-) create mode 100644 target/mips/sysemu/cp0.c diff --git a/target/mips/internal.h b/target/mips/internal.h index 1e085b0625c..57eec83384a 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -156,6 +156,11 @@ void mips_cpu_do_transaction_failed(CPUState *cs, hwad= dr physaddr, MMUAccessType access_type, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retadd= r); + +void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc); +void cpu_mips_store_status(CPUMIPSState *env, target_ulong val); +void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val); + extern const VMStateDescription vmstate_mips_cpu; =20 #endif /* !CONFIG_USER_ONLY */ @@ -395,8 +400,4 @@ static inline void compute_hflags(CPUMIPSState *env) } } =20 -void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc); -void cpu_mips_store_status(CPUMIPSState *env, target_ulong val); -void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val); - #endif diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 38328ba0927..aa42f1e5647 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -42,109 +42,6 @@ const char * const regnames[32] =3D { "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", }; =20 -#if !defined(CONFIG_USER_ONLY) - -/* Called for updates to CP0_Status. */ -void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc) -{ - int32_t tcstatus, *tcst; - uint32_t v =3D cpu->CP0_Status; - uint32_t cu, mx, asid, ksu; - uint32_t mask =3D ((1 << CP0TCSt_TCU3) - | (1 << CP0TCSt_TCU2) - | (1 << CP0TCSt_TCU1) - | (1 << CP0TCSt_TCU0) - | (1 << CP0TCSt_TMX) - | (3 << CP0TCSt_TKSU) - | (0xff << CP0TCSt_TASID)); - - cu =3D (v >> CP0St_CU0) & 0xf; - mx =3D (v >> CP0St_MX) & 0x1; - ksu =3D (v >> CP0St_KSU) & 0x3; - asid =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; - - tcstatus =3D cu << CP0TCSt_TCU0; - tcstatus |=3D mx << CP0TCSt_TMX; - tcstatus |=3D ksu << CP0TCSt_TKSU; - tcstatus |=3D asid; - - if (tc =3D=3D cpu->current_tc) { - tcst =3D &cpu->active_tc.CP0_TCStatus; - } else { - tcst =3D &cpu->tcs[tc].CP0_TCStatus; - } - - *tcst &=3D ~mask; - *tcst |=3D tcstatus; - compute_hflags(cpu); -} - -void cpu_mips_store_status(CPUMIPSState *env, target_ulong val) -{ - uint32_t mask =3D env->CP0_Status_rw_bitmask; - target_ulong old =3D env->CP0_Status; - - if (env->insn_flags & ISA_MIPS_R6) { - bool has_supervisor =3D extract32(mask, CP0St_KSU, 2) =3D=3D 0x3; -#if defined(TARGET_MIPS64) - uint32_t ksux =3D (1 << CP0St_KX) & val; - ksux |=3D (ksux >> 1) & val; /* KX =3D 0 forces SX to be 0 */ - ksux |=3D (ksux >> 1) & val; /* SX =3D 0 forces UX to be 0 */ - val =3D (val & ~(7 << CP0St_UX)) | ksux; -#endif - if (has_supervisor && extract32(val, CP0St_KSU, 2) =3D=3D 0x3) { - mask &=3D ~(3 << CP0St_KSU); - } - mask &=3D ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val); - } - - env->CP0_Status =3D (old & ~mask) | (val & mask); -#if defined(TARGET_MIPS64) - if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) { - /* Access to at least one of the 64-bit segments has been disabled= */ - tlb_flush(env_cpu(env)); - } -#endif - if (ase_mt_available(env)) { - sync_c0_status(env, env, env->current_tc); - } else { - compute_hflags(env); - } -} - -void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val) -{ - uint32_t mask =3D 0x00C00300; - uint32_t old =3D env->CP0_Cause; - int i; - - if (env->insn_flags & ISA_MIPS_R2) { - mask |=3D 1 << CP0Ca_DC; - } - if (env->insn_flags & ISA_MIPS_R6) { - mask &=3D ~((1 << CP0Ca_WP) & val); - } - - env->CP0_Cause =3D (env->CP0_Cause & ~mask) | (val & mask); - - if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) { - if (env->CP0_Cause & (1 << CP0Ca_DC)) { - cpu_mips_stop_count(env); - } else { - cpu_mips_start_count(env); - } - } - - /* Set/reset software interrupts */ - for (i =3D 0 ; i < 2 ; i++) { - if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) { - cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i= ))); - } - } -} - -#endif /* !CONFIG_USER_ONLY */ - static void fpu_dump_state(CPUMIPSState *env, FILE * f, int flags) { int i; diff --git a/target/mips/sysemu/cp0.c b/target/mips/sysemu/cp0.c new file mode 100644 index 00000000000..bae37f515bf --- /dev/null +++ b/target/mips/sysemu/cp0.c @@ -0,0 +1,123 @@ +/* + * QEMU MIPS CPU + * + * Copyright (c) 2012 SUSE LINUX Products GmbH + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see + * + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "internal.h" +#include "exec/exec-all.h" + +/* Called for updates to CP0_Status. */ +void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc) +{ + int32_t tcstatus, *tcst; + uint32_t v =3D cpu->CP0_Status; + uint32_t cu, mx, asid, ksu; + uint32_t mask =3D ((1 << CP0TCSt_TCU3) + | (1 << CP0TCSt_TCU2) + | (1 << CP0TCSt_TCU1) + | (1 << CP0TCSt_TCU0) + | (1 << CP0TCSt_TMX) + | (3 << CP0TCSt_TKSU) + | (0xff << CP0TCSt_TASID)); + + cu =3D (v >> CP0St_CU0) & 0xf; + mx =3D (v >> CP0St_MX) & 0x1; + ksu =3D (v >> CP0St_KSU) & 0x3; + asid =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; + + tcstatus =3D cu << CP0TCSt_TCU0; + tcstatus |=3D mx << CP0TCSt_TMX; + tcstatus |=3D ksu << CP0TCSt_TKSU; + tcstatus |=3D asid; + + if (tc =3D=3D cpu->current_tc) { + tcst =3D &cpu->active_tc.CP0_TCStatus; + } else { + tcst =3D &cpu->tcs[tc].CP0_TCStatus; + } + + *tcst &=3D ~mask; + *tcst |=3D tcstatus; + compute_hflags(cpu); +} + +void cpu_mips_store_status(CPUMIPSState *env, target_ulong val) +{ + uint32_t mask =3D env->CP0_Status_rw_bitmask; + target_ulong old =3D env->CP0_Status; + + if (env->insn_flags & ISA_MIPS_R6) { + bool has_supervisor =3D extract32(mask, CP0St_KSU, 2) =3D=3D 0x3; +#if defined(TARGET_MIPS64) + uint32_t ksux =3D (1 << CP0St_KX) & val; + ksux |=3D (ksux >> 1) & val; /* KX =3D 0 forces SX to be 0 */ + ksux |=3D (ksux >> 1) & val; /* SX =3D 0 forces UX to be 0 */ + val =3D (val & ~(7 << CP0St_UX)) | ksux; +#endif + if (has_supervisor && extract32(val, CP0St_KSU, 2) =3D=3D 0x3) { + mask &=3D ~(3 << CP0St_KSU); + } + mask &=3D ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val); + } + + env->CP0_Status =3D (old & ~mask) | (val & mask); +#if defined(TARGET_MIPS64) + if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) { + /* Access to at least one of the 64-bit segments has been disabled= */ + tlb_flush(env_cpu(env)); + } +#endif + if (ase_mt_available(env)) { + sync_c0_status(env, env, env->current_tc); + } else { + compute_hflags(env); + } +} + +void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val) +{ + uint32_t mask =3D 0x00C00300; + uint32_t old =3D env->CP0_Cause; + int i; + + if (env->insn_flags & ISA_MIPS_R2) { + mask |=3D 1 << CP0Ca_DC; + } + if (env->insn_flags & ISA_MIPS_R6) { + mask &=3D ~((1 << CP0Ca_WP) & val); + } + + env->CP0_Cause =3D (env->CP0_Cause & ~mask) | (val & mask); + + if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) { + if (env->CP0_Cause & (1 << CP0Ca_DC)) { + cpu_mips_stop_count(env); + } else { + cpu_mips_start_count(env); + } + } + + /* Set/reset software interrupts */ + for (i =3D 0 ; i < 2 ; i++) { + if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) { + cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i= ))); + } + } +} diff --git a/target/mips/sysemu/meson.build b/target/mips/sysemu/meson.build index 925ceeaa449..cefc2275828 100644 --- a/target/mips/sysemu/meson.build +++ b/target/mips/sysemu/meson.build @@ -1,5 +1,6 @@ mips_softmmu_ss.add(files( 'addr.c', + 'cp0.c', 'cp0_timer.c', 'machine.c', 'physaddr.c', --=20 2.26.3