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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id z66sm17464700wmc.4.2021.04.18.09.32.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Apr 2021 09:32:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JUUEmf5SlbaTemzMWy5ADTcmG/EE1+NtSG+aWRZw2E0=; b=IrR5Ar+OhqWIkUc7vvqHloLE62Tyc9VlOBma5scdROewW5t2Ss/T7nXdzkmv2QRRYp XKSAx1wdmxnmjUl0knuUGjStUAsUNWb90z8LyE5JqAsF0ZquwPk8PMU4ze6u2yjbd/Cg paAAqot7iZm6WeyiMJC2XJtK9UEV6gJ713nXb/3Y7+GbvWweGmtKOANuec2vvj3+Y1sh FclAvFsetqsOTdbuR1kqgGFCokGIa/K7SSbstjx6HPoAV+2kH56QuLocjdWc1O1vq6yS HiaRkiDKzT1SwzWhcsLNS0KOrUpxzdg69lzfmIEFBEBro5VljuvnYCkTzDES+B2yxMdm CIAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=JUUEmf5SlbaTemzMWy5ADTcmG/EE1+NtSG+aWRZw2E0=; b=PNlngcLA1v/kNWN011uuwa6QLnVMjJzXMkaujSORDNDHBoOW9leRGJzwWe9X31ECIl uJH/G5RSMCFb7Ty8+zu4robO0CT1U5M4rm8GdV+hs2v/7ucHeaC0VrYiIEP0eYvlMDi7 vEqEzyJeh54isPqwBGkJP++j5Bvo9L2d+Unj5cikwrYSklWpm3yYJNPMPLHH2C9pmKKr 7tLFebiZPkcubzyRvvwaRZtAAdjaNkDN1xD/Eb7yacgCg1cDIZnLh9EOynukSTDpjIyX ETa5bWlcOVNp2HkIPVDL5PSgik/FNkBMZFttxbgHMGt6wvxHBEWACatO0ychdPq4qroz knDw== X-Gm-Message-State: AOAM533Hsg7RgS2NjbOz2KeB3ahjoTUGgO8qKaLfw5YkD5QN6rICzf92 HkD7j55J/sYsOenPVoxmamk= X-Google-Smtp-Source: ABdhPJxAo5dkox6ArdkNMvW7IstmIsdCOVZXvzoxwez2XJh+V9CMR/ar9YqMEZ/0kYKVSvd+LxGJ2A== X-Received: by 2002:a1c:f402:: with SMTP id z2mr13099959wma.21.1618763544518; Sun, 18 Apr 2021 09:32:24 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Huacai Chen , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang , Richard Henderson , Aurelien Jarno Subject: [PATCH 10/26] target/mips: Add simple user-mode mips_cpu_tlb_fill() Date: Sun, 18 Apr 2021 18:31:18 +0200 Message-Id: <20210418163134.1133100-11-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210418163134.1133100-1-f4bug@amsat.org> References: <20210418163134.1133100-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) tlb_helper.c's #ifdef'ry hides a quite simple user-mode implementation of mips_cpu_tlb_fill(). Copy the user-mode implementation (without #ifdef'ry) to tcg/user/helper.c and simplify tlb_helper.c's #ifdef'ry. This will allow us to restrict tlb_helper.c to sysemu. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/tcg/user/helper.c | 36 +++++++++++++++++++++++++++++++++++ target/mips/tlb_helper.c | 10 ---------- 2 files changed, 36 insertions(+), 10 deletions(-) diff --git a/target/mips/tcg/user/helper.c b/target/mips/tcg/user/helper.c index 453b9e9b930..b835144b820 100644 --- a/target/mips/tcg/user/helper.c +++ b/target/mips/tcg/user/helper.c @@ -22,6 +22,42 @@ #include "exec/exec-all.h" #include "internal.h" =20 +static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, + MMUAccessType access_type) +{ + CPUState *cs =3D env_cpu(env); + + env->error_code =3D 0; + if (access_type =3D=3D MMU_INST_FETCH) { + env->error_code |=3D EXCP_INST_NOTAVAIL; + } + + /* Reference to kernel address from user mode or supervisor mode */ + /* Reference to supervisor address from user mode */ + if (access_type =3D=3D MMU_DATA_STORE) { + cs->exception_index =3D EXCP_AdES; + } else { + cs->exception_index =3D EXCP_AdEL; + } + + /* Raise exception */ + if (!(env->hflags & MIPS_HFLAG_DM)) { + env->CP0_BadVAddr =3D address; + } +} + +bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) +{ + MIPSCPU *cpu =3D MIPS_CPU(cs); + CPUMIPSState *env =3D &cpu->env; + + /* data access */ + raise_mmu_exception(env, address, access_type); + do_raise_exception_err(env, cs->exception_index, env->error_code, reta= ddr); +} + void mips_cpu_do_interrupt(CPUState *cs) { cs->exception_index =3D EXCP_NONE; diff --git a/target/mips/tlb_helper.c b/target/mips/tlb_helper.c index 46e9555c9ab..bb4b503ff72 100644 --- a/target/mips/tlb_helper.c +++ b/target/mips/tlb_helper.c @@ -403,8 +403,6 @@ void cpu_mips_tlb_flush(CPUMIPSState *env) env->tlb->tlb_in_use =3D env->tlb->nb_tlb; } =20 -#endif /* !CONFIG_USER_ONLY */ - static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, MMUAccessType access_type, int tlb_error) { @@ -484,8 +482,6 @@ static void raise_mmu_exception(CPUMIPSState *env, targ= et_ulong address, env->error_code =3D error_code; } =20 -#if !defined(CONFIG_USER_ONLY) - hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { MIPSCPU *cpu =3D MIPS_CPU(cs); @@ -833,7 +829,6 @@ refill: return true; } #endif -#endif /* !CONFIG_USER_ONLY */ =20 bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, @@ -841,14 +836,11 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, { MIPSCPU *cpu =3D MIPS_CPU(cs); CPUMIPSState *env =3D &cpu->env; -#if !defined(CONFIG_USER_ONLY) hwaddr physical; int prot; -#endif int ret =3D TLBRET_BADADDR; =20 /* data access */ -#if !defined(CONFIG_USER_ONLY) /* XXX: put correct access by using cpu_restore_state() correctly */ ret =3D get_physical_address(env, &physical, &prot, address, access_type, mmu_idx); @@ -896,13 +888,11 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, if (probe) { return false; } -#endif =20 raise_mmu_exception(env, address, access_type, ret); do_raise_exception_err(env, cs->exception_index, env->error_code, reta= ddr); } =20 -#ifndef CONFIG_USER_ONLY hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, MMUAccessType access_type) { --=20 2.26.3