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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id n9sm11795815wmo.27.2021.04.17.03.31.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Apr 2021 03:31:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=L5A08oqJfnwHuu4IIvHVyo2CuhBx8oIfeNWXxwFL7uE=; b=QvJcVwgjwo/yqaRENhIL6JYzDNYm0QfGCfHXA36JgYq698gGRG+bGZ98BrpmcbPNen 9odV19fsxLa5woaotQsV3fOExc/BH1OAuBeBFw9QzsTmvda50Sf/6FDp3vQzzY7y6LRP R+0eFzWsDEyJT6Ytd17YwAgDxYM4TIwtYVSZT5wiQIwi8rB6a/YJSHvaDwWMDF4XPzUx Fe91kag1X1/M4+sm2NrLWGTohS82XGvrTulAE/E1/kdlpcliBPm61JzWF/iHOqcIa5qr qGE2TeEUWovktEIt4IFjuc09jrlBFV+13jHwPApoB5Kc3jVyx6gycNo91+Ma5UKvm3wj H03A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=L5A08oqJfnwHuu4IIvHVyo2CuhBx8oIfeNWXxwFL7uE=; b=Qe5aCnZZkY6Twa0I7qgXu2Il1dlV0AJBJKuhNtePycgg/gRV+E090AJu42ZPLQ9g/G juytde/CGDgB8KPBAey3NoLjMH4GiMKa6LnecufMqrUb99K/Wt/Ux5ur6hIIJztwAgNV f8qiKho8z6eMYw2XLmbrPMd/0QzeBT+TFT7LQQiI68U2YTrTXK533ixRDlVzQSgNzoGx VzYaBb4+WQ1oxsOlEFVmfYWMaQ9Mi9r/0SMtCIObiGFF8csbUA/oioJobFOi74vrflAQ AU5s6f8V8su0TKASvVqG/SHHZuTralEo92INz3NwwT5KthssyBXRh+mYGJlCGsF8pf7S 8deQ== X-Gm-Message-State: AOAM532bHeFDgPWUWKrz4BIIKXLG0eO8i/bThnhI3UQl2wkR7Nen0yF8 taQCYRGRyx1pATRjmpQeW7k= X-Google-Smtp-Source: ABdhPJzvD0QAKxHmespnrW3MzoXZhd7Of64fnGKfU8KE/1YYIcN2qgkVDpZqmJeEsJ42UFwUfxZzJQ== X-Received: by 2002:adf:dc8d:: with SMTP id r13mr3655698wrj.339.1618655466854; Sat, 17 Apr 2021 03:31:06 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, Peter Maydell , Peter Xu , David Gibson , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Greg Kurz Subject: [PATCH v2 07/11] hw/pci-host/raven: Use MR alias for AS root, not sysbus mapped MR Date: Sat, 17 Apr 2021 12:30:24 +0200 Message-Id: <20210417103028.601124-8-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210417103028.601124-1-f4bug@amsat.org> References: <20210417103028.601124-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) The PCI I/O region is exposed as AddressSpace. AddressSpaces must not be sysbus-mapped (to be zero-based), therefore map the region using an alias. As the new AdressSpace root memory region is now zero-based, we do not need anymore to add the PCI I/O base address to the MemoryRegionOps handlers. Update the temporary assertion and its comment. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/pci-host/raven.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/hw/pci-host/raven.c b/hw/pci-host/raven.c index 36652122424..7bbb7ef0a29 100644 --- a/hw/pci-host/raven.c +++ b/hw/pci-host/raven.c @@ -67,6 +67,7 @@ struct PRePPCIState { PCIBus pci_bus; AddressSpace pci_io_as; MemoryRegion pci_io; + MemoryRegion pci_io_alias; MemoryRegion pci_io_non_contiguous; MemoryRegion pci_memory; MemoryRegion pci_intack; @@ -143,14 +144,13 @@ static inline hwaddr raven_io_address(PREPPCIState *s, { /* * We shouldn't access AddressSpace internals. However this assert - * is temporarily introduced to prove a subtle inconsistency from - * commit 1ae1dc5ba24 ("raven: Set a correct PCI I/O memory region"): - * AddressSpace root region must be zero-based, but the Raven use is n= ot. + * is temporarily used to prove a subtle inconsistency from commit + * 1ae1dc5ba24 ("raven: Set a correct PCI I/O memory region") which + * expected the PCI I/O root region base address to be 0x80000000. * - * Assert the root region is based on physical address 0x80000000 - * until the issue is fixed. + * We now use an alias memory region as root, which is zero-based. */ - assert(s->pci_io_as.root->addr =3D=3D PCI_IO_BASE_ADDR); + assert(s->pci_io_as.root->addr =3D=3D 0); =20 if (s->contiguous_map =3D=3D 0) { /* 64 KB contiguous space for IOs */ @@ -172,8 +172,7 @@ static uint64_t raven_io_read(void *opaque, hwaddr addr, uint8_t buf[4]; =20 addr =3D raven_io_address(s, addr); - address_space_read(&s->pci_io_as, addr + PCI_IO_BASE_ADDR, - MEMTXATTRS_UNSPECIFIED, buf, size); + address_space_read(&s->pci_io_as, addr, MEMTXATTRS_UNSPECIFIED, buf, s= ize); =20 if (size =3D=3D 1) { return buf[0]; @@ -204,8 +203,7 @@ static void raven_io_write(void *opaque, hwaddr addr, g_assert_not_reached(); } =20 - address_space_write(&s->pci_io_as, addr + PCI_IO_BASE_ADDR, - MEMTXATTRS_UNSPECIFIED, buf, size); + address_space_write(&s->pci_io_as, addr, MEMTXATTRS_UNSPECIFIED, buf, = size); } =20 static const MemoryRegionOps raven_io_ops =3D { @@ -301,6 +299,8 @@ static void raven_pcihost_initfn(Object *obj) DeviceState *pci_dev; =20 memory_region_init(&s->pci_io, obj, "pci-io", 0x3f800000); + memory_region_init_alias(&s->pci_io_alias, obj, "pci-io", + &s->pci_io, 0, memory_region_size(&s->pci_io)= ); memory_region_init_io(&s->pci_io_non_contiguous, obj, &raven_io_ops, s, "pci-io-non-contiguous", 0x00800000); memory_region_init(&s->pci_memory, obj, "pci-memory", 0x3f000000); @@ -308,7 +308,7 @@ static void raven_pcihost_initfn(Object *obj) =20 /* CPU address space */ memory_region_add_subregion(address_space_mem, PCI_IO_BASE_ADDR, - &s->pci_io); + &s->pci_io_alias); memory_region_add_subregion_overlap(address_space_mem, PCI_IO_BASE_ADD= R, &s->pci_io_non_contiguous, 1); memory_region_add_subregion(address_space_mem, 0xc0000000, &s->pci_mem= ory); --=20 2.26.3