From nobody Tue Feb 10 06:08:31 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1618591483; cv=none; d=zohomail.com; s=zohoarc; b=SPoLHyEhH9TJwHJXNZjyQoWUyIh9k+fr1Vv74raxbe5rBDzjoPFS5mZeFMsX35B7kuGqN/WEJgM3Crf6f3rDsBCQe0EBaTlqHzl+rE1Yw5DXEW08HK+5JuLp5OF/evo15SwaGzo9rq/ECw1vb9XRaA9kCqVPAnXkewYXrzC9J5w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618591483; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=IIVvSmSian+b+tzpo3Ltao60xYc1PjEmfv46ny5l8sw=; b=b8ZlC/Xcr8l8lC/+Xm4RQO5wlLI83UUlBZ1hp1808tsxCq1H9udErrR/OV/zM7Ob+8cF1fZSofhXy9LXTKe0TpoQAA4J4Uvv06dEDG0PJSBMEC2K9mzuy46ETlRI+DyBwnHh62Q/yXRz8Hphq5+zmS3E3frysx/fSi+7dQqMgYg= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 161859148310997.84591520947697; Fri, 16 Apr 2021 09:44:43 -0700 (PDT) Received: from localhost ([::1]:47532 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lXRaE-0002PV-0x for importer@patchew.org; Fri, 16 Apr 2021 12:44:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46130) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lXRKf-0003HL-9z for qemu-devel@nongnu.org; Fri, 16 Apr 2021 12:28:37 -0400 Received: from mx2.suse.de ([195.135.220.15]:42674) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lXRKb-0001Ix-E3 for qemu-devel@nongnu.org; Fri, 16 Apr 2021 12:28:37 -0400 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 70E24B10B; Fri, 16 Apr 2021 16:28:29 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [RFC v14 07/80] target/arm: tcg: split tlb_helper user-only and sysemu-only parts Date: Fri, 16 Apr 2021 18:27:11 +0200 Message-Id: <20210416162824.25131-8-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210416162824.25131-1-cfontana@suse.de> References: <20210416162824.25131-1-cfontana@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Roman Bolshakov , Claudio Fontana , Eduardo Habkost , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- target/arm/tcg/tlb_helper.h | 17 ++++++ target/arm/tcg/sysemu/tlb_helper.c | 83 +++++++++++++++++++++++++ target/arm/tcg/tlb_helper.c | 97 ++---------------------------- target/arm/tcg/user/tlb_helper.c | 32 ++++++++++ target/arm/tcg/sysemu/meson.build | 1 + target/arm/tcg/user/meson.build | 1 + 6 files changed, 138 insertions(+), 93 deletions(-) create mode 100644 target/arm/tcg/tlb_helper.h create mode 100644 target/arm/tcg/sysemu/tlb_helper.c create mode 100644 target/arm/tcg/user/tlb_helper.c diff --git a/target/arm/tcg/tlb_helper.h b/target/arm/tcg/tlb_helper.h new file mode 100644 index 0000000000..6ce3d315cf --- /dev/null +++ b/target/arm/tcg/tlb_helper.h @@ -0,0 +1,17 @@ +/* + * ARM TLB (Translation lookaside buffer) helpers. + * + * This code is licensed under the GNU GPL v2 or later. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef TLB_HELPER_H +#define TLB_HELPER_H + +#include "cpu.h" + +void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, vaddr addr, + MMUAccessType access_type, + int mmu_idx, ARMMMUFaultInfo *fi); + +#endif /* TLB_HELPER_H */ diff --git a/target/arm/tcg/sysemu/tlb_helper.c b/target/arm/tcg/sysemu/tlb= _helper.c new file mode 100644 index 0000000000..586f602989 --- /dev/null +++ b/target/arm/tcg/sysemu/tlb_helper.c @@ -0,0 +1,83 @@ +/* + * ARM TLB (Translation lookaside buffer) helpers. + * + * This code is licensed under the GNU GPL v2 or later. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#include "qemu/osdep.h" +#include "cpu.h" +#include "internals.h" +#include "exec/exec-all.h" +#include "tcg/tlb_helper.h" + +/* + * arm_cpu_do_transaction_failed: handle a memory system error response + * (eg "no device/memory present at address") by raising an external abort + * exception + */ +void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, + vaddr addr, unsigned size, + MMUAccessType access_type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, uintptr_t retaddr) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + ARMMMUFaultInfo fi =3D {}; + + /* now we have a real cpu fault */ + cpu_restore_state(cs, retaddr, true); + + fi.ea =3D arm_extabort_type(response); + fi.type =3D ARMFault_SyncExternal; + arm_deliver_fault(cpu, addr, access_type, mmu_idx, &fi); +} + +bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + ARMMMUFaultInfo fi =3D {}; + hwaddr phys_addr; + target_ulong page_size; + int prot, ret; + MemTxAttrs attrs =3D {}; + ARMCacheAttrs cacheattrs =3D {}; + + /* + * Walk the page table and (if the mapping exists) add the page + * to the TLB. On success, return true. Otherwise, if probing, + * return false. Otherwise populate fsr with ARM DFSR/IFSR fault + * register format, and signal the fault. + */ + ret =3D get_phys_addr(&cpu->env, address, access_type, + core_to_arm_mmu_idx(&cpu->env, mmu_idx), + &phys_addr, &attrs, &prot, &page_size, + &fi, &cacheattrs); + if (likely(!ret)) { + /* + * Map a single [sub]page. Regions smaller than our declared + * target page size are handled specially, so for those we + * pass in the exact addresses. + */ + if (page_size >=3D TARGET_PAGE_SIZE) { + phys_addr &=3D TARGET_PAGE_MASK; + address &=3D TARGET_PAGE_MASK; + } + /* Notice and record tagged memory. */ + if (cpu_isar_feature(aa64_mte, cpu) && cacheattrs.attrs =3D=3D 0xf= 0) { + arm_tlb_mte_tagged(&attrs) =3D true; + } + + tlb_set_page_with_attrs(cs, address, phys_addr, attrs, + prot, mmu_idx, page_size); + return true; + } else if (probe) { + return false; + } else { + /* now we have a real cpu fault */ + cpu_restore_state(cs, retaddr, true); + arm_deliver_fault(cpu, address, access_type, mmu_idx, &fi); + } +} diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c index 3107f9823e..77aefc274d 100644 --- a/target/arm/tcg/tlb_helper.c +++ b/target/arm/tcg/tlb_helper.c @@ -9,6 +9,7 @@ #include "cpu.h" #include "internals.h" #include "exec/exec-all.h" +#include "tcg/tlb_helper.h" =20 static inline uint32_t merge_syn_data_abort(uint32_t template_syn, unsigned int target_el, @@ -49,9 +50,9 @@ static inline uint32_t merge_syn_data_abort(uint32_t temp= late_syn, return syn; } =20 -static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, vaddr addr, - MMUAccessType access_type, - int mmu_idx, ARMMMUFaultInfo *= fi) +void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, vaddr addr, + MMUAccessType access_type, + int mmu_idx, ARMMMUFaultInfo *fi) { CPUARMState *env =3D &cpu->env; int target_el; @@ -122,93 +123,3 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr v= addr, fi.type =3D ARMFault_Alignment; arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi); } - -#if !defined(CONFIG_USER_ONLY) - -/* - * arm_cpu_do_transaction_failed: handle a memory system error response - * (eg "no device/memory present at address") by raising an external abort - * exception - */ -void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, - vaddr addr, unsigned size, - MMUAccessType access_type, - int mmu_idx, MemTxAttrs attrs, - MemTxResult response, uintptr_t retaddr) -{ - ARMCPU *cpu =3D ARM_CPU(cs); - ARMMMUFaultInfo fi =3D {}; - - /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr, true); - - fi.ea =3D arm_extabort_type(response); - fi.type =3D ARMFault_SyncExternal; - arm_deliver_fault(cpu, addr, access_type, mmu_idx, &fi); -} - -#endif /* !defined(CONFIG_USER_ONLY) */ - -bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) -{ - ARMCPU *cpu =3D ARM_CPU(cs); - ARMMMUFaultInfo fi =3D {}; - -#ifdef CONFIG_USER_ONLY - int flags =3D page_get_flags(useronly_clean_ptr(address)); - if (flags & PAGE_VALID) { - fi.type =3D ARMFault_Permission; - } else { - fi.type =3D ARMFault_Translation; - } - fi.level =3D 3; - - /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr, true); - arm_deliver_fault(cpu, address, access_type, mmu_idx, &fi); -#else - hwaddr phys_addr; - target_ulong page_size; - int prot, ret; - MemTxAttrs attrs =3D {}; - ARMCacheAttrs cacheattrs =3D {}; - - /* - * Walk the page table and (if the mapping exists) add the page - * to the TLB. On success, return true. Otherwise, if probing, - * return false. Otherwise populate fsr with ARM DFSR/IFSR fault - * register format, and signal the fault. - */ - ret =3D get_phys_addr(&cpu->env, address, access_type, - core_to_arm_mmu_idx(&cpu->env, mmu_idx), - &phys_addr, &attrs, &prot, &page_size, - &fi, &cacheattrs); - if (likely(!ret)) { - /* - * Map a single [sub]page. Regions smaller than our declared - * target page size are handled specially, so for those we - * pass in the exact addresses. - */ - if (page_size >=3D TARGET_PAGE_SIZE) { - phys_addr &=3D TARGET_PAGE_MASK; - address &=3D TARGET_PAGE_MASK; - } - /* Notice and record tagged memory. */ - if (cpu_isar_feature(aa64_mte, cpu) && cacheattrs.attrs =3D=3D 0xf= 0) { - arm_tlb_mte_tagged(&attrs) =3D true; - } - - tlb_set_page_with_attrs(cs, address, phys_addr, attrs, - prot, mmu_idx, page_size); - return true; - } else if (probe) { - return false; - } else { - /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr, true); - arm_deliver_fault(cpu, address, access_type, mmu_idx, &fi); - } -#endif -} diff --git a/target/arm/tcg/user/tlb_helper.c b/target/arm/tcg/user/tlb_hel= per.c new file mode 100644 index 0000000000..9f24c96ba0 --- /dev/null +++ b/target/arm/tcg/user/tlb_helper.c @@ -0,0 +1,32 @@ +/* + * ARM TLB (Translation lookaside buffer) helpers. + * + * This code is licensed under the GNU GPL v2 or later. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#include "qemu/osdep.h" +#include "cpu.h" +#include "internals.h" +#include "exec/exec-all.h" +#include "tcg/tlb_helper.h" + +bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + ARMMMUFaultInfo fi =3D {}; + + int flags =3D page_get_flags(useronly_clean_ptr(address)); + if (flags & PAGE_VALID) { + fi.type =3D ARMFault_Permission; + } else { + fi.type =3D ARMFault_Translation; + } + fi.level =3D 3; + + /* now we have a real cpu fault */ + cpu_restore_state(cs, retaddr, true); + arm_deliver_fault(cpu, address, access_type, mmu_idx, &fi); +} diff --git a/target/arm/tcg/sysemu/meson.build b/target/arm/tcg/sysemu/meso= n.build index 1a4d7a0940..8f5e955cbd 100644 --- a/target/arm/tcg/sysemu/meson.build +++ b/target/arm/tcg/sysemu/meson.build @@ -1,4 +1,5 @@ arm_softmmu_ss.add(when: 'CONFIG_TCG', if_true: files( 'debug_helper.c', 'mte_helper.c', + 'tlb_helper.c', )) diff --git a/target/arm/tcg/user/meson.build b/target/arm/tcg/user/meson.bu= ild index e681e5f5a1..cdca5d970c 100644 --- a/target/arm/tcg/user/meson.build +++ b/target/arm/tcg/user/meson.build @@ -1,3 +1,4 @@ arm_user_ss.add(when: 'CONFIG_TCG', if_true: files( 'mte_helper.c', + 'tlb_helper.c', )) --=20 2.26.2