From nobody Mon Feb 9 17:24:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1618402988; cv=none; d=zohomail.com; s=zohoarc; b=SdGEY/FREgazHGBXq9eWBv4GDVm6ymSNvoptFrZTpTtzDAcCWo2g8wo15oSgT3dYP4QMnBRVw0zgT342Qgr/8STEjxp8xn79WrUtU5DDYhg7s73kiceJGwtlhs+Y3sU5d2mGK5FzscKJTtCc/pbxaTKcMhseF9xayF9ae3B+oG4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618402988; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=GBS5SuSYELpYTEpeWSEE1h6/c+N1JyDpWfR4Nr0tptw=; b=ifPmXlc7KebbdICiHHSWjHBH1w/tx0FIJ+LRODfnIjL1JcZjgu+SxbK6Ls0QdxWq6PONcgbO8XoaBbIR8GBu0ZydPArvI21JIOuOUnABskWPxGtEkDy/MEcJ3JTCKKoHyf37xmqJg2pm/3pW/vaixvXg5v7sy6k4ro0x2250OPo= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1618402988242547.9042106921784; Wed, 14 Apr 2021 05:23:08 -0700 (PDT) Received: from localhost ([::1]:45802 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lWeXz-0002Rz-5I for importer@patchew.org; Wed, 14 Apr 2021 08:23:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42796) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lWdh9-0007OV-Ar for qemu-devel@nongnu.org; Wed, 14 Apr 2021 07:28:31 -0400 Received: from mx2.suse.de ([195.135.220.15]:45958) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lWdgu-0005qW-0O for qemu-devel@nongnu.org; Wed, 14 Apr 2021 07:28:31 -0400 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id A3CF2B1BC; Wed, 14 Apr 2021 11:27:25 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [RFC v13 71/80] cpu-sve: rename sve_zcr_len_for_el to cpu_sve_get_zcr_len_for_el Date: Wed, 14 Apr 2021 13:26:41 +0200 Message-Id: <20210414112650.18003-72-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210414112650.18003-1-cfontana@suse.de> References: <20210414112650.18003-1-cfontana@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Roman Bolshakov , Claudio Fontana , Eduardo Habkost , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" use a canonical module prefix followed by the get_zcr_len_for_el() method name. Also rename the static internal auxiliary function, where the module prefix is not necessary. Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson --- target/arm/cpu-sve.h | 2 +- target/arm/arch_dump.c | 2 +- target/arm/cpu-sve.c | 6 +++--- target/arm/cpu64.c | 2 +- target/arm/tcg/cpregs.c | 4 ++-- target/arm/tcg/helper.c | 4 ++-- target/arm/tcg/tcg-sve.c | 4 ++-- 7 files changed, 12 insertions(+), 12 deletions(-) diff --git a/target/arm/cpu-sve.h b/target/arm/cpu-sve.h index 1512c56a6b..c83508ea0a 100644 --- a/target/arm/cpu-sve.h +++ b/target/arm/cpu-sve.h @@ -35,6 +35,6 @@ void cpu_sve_add_props(Object *obj); void cpu_sve_add_props_max(Object *obj); =20 /* return the vector length for EL */ -uint32_t sve_zcr_len_for_el(CPUARMState *env, int el); +uint32_t cpu_sve_get_zcr_len_for_el(CPUARMState *env, int el); =20 #endif /* CPU_SVE_H */ diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c index 9b2e76f5a7..f192c8df97 100644 --- a/target/arm/arch_dump.c +++ b/target/arm/arch_dump.c @@ -168,7 +168,7 @@ static off_t sve_fpcr_offset(uint32_t vq) =20 static uint32_t sve_current_vq(CPUARMState *env) { - return sve_zcr_len_for_el(env, arm_current_el(env)) + 1; + return cpu_sve_get_zcr_len_for_el(env, arm_current_el(env)) + 1; } =20 static size_t sve_size_vq(uint32_t vq) diff --git a/target/arm/cpu-sve.c b/target/arm/cpu-sve.c index e8e817e110..1bc8c0bdb0 100644 --- a/target/arm/cpu-sve.c +++ b/target/arm/cpu-sve.c @@ -289,7 +289,7 @@ void cpu_sve_add_props_max(Object *obj) object_property_add(obj, "sve-max-vq", "uint32", get_prop_max_vq, set_= prop_max_vq, NULL, NULL); } =20 -static uint32_t sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len) +static uint32_t get_valid_len(ARMCPU *cpu, uint32_t start_len) { uint32_t end_len; =20 @@ -304,7 +304,7 @@ static uint32_t sve_zcr_get_valid_len(ARMCPU *cpu, uint= 32_t start_len) /* * Given that SVE is enabled, return the vector length for EL. */ -uint32_t sve_zcr_len_for_el(CPUARMState *env, int el) +uint32_t cpu_sve_get_zcr_len_for_el(CPUARMState *env, int el) { ARMCPU *cpu =3D env_archcpu(env); uint32_t zcr_len =3D cpu->sve_max_vq - 1; @@ -319,5 +319,5 @@ uint32_t sve_zcr_len_for_el(CPUARMState *env, int el) zcr_len =3D MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[3]); } =20 - return sve_zcr_get_valid_len(cpu, zcr_len); + return get_valid_len(cpu, zcr_len); } diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 8c96a108fc..b1b5cf5cc9 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -535,7 +535,7 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *= f, int flags) vfp_get_fpcr(env), vfp_get_fpsr(env)); =20 if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) =3D= =3D 0) { - int j, zcr_len =3D sve_zcr_len_for_el(env, el); + int j, zcr_len =3D cpu_sve_get_zcr_len_for_el(env, el); =20 for (i =3D 0; i <=3D FFR_PRED_NUM; i++) { bool eol; diff --git a/target/arm/tcg/cpregs.c b/target/arm/tcg/cpregs.c index 0f4460e28a..c4117b68f5 100644 --- a/target/arm/tcg/cpregs.c +++ b/target/arm/tcg/cpregs.c @@ -5802,7 +5802,7 @@ static void zcr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) { int cur_el =3D arm_current_el(env); - int old_len =3D sve_zcr_len_for_el(env, cur_el); + int old_len =3D cpu_sve_get_zcr_len_for_el(env, cur_el); int new_len; =20 /* Bits other than [3:0] are RAZ/WI. */ @@ -5813,7 +5813,7 @@ static void zcr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, * Because we arrived here, we know both FP and SVE are enabled; * otherwise we would have trapped access to the ZCR_ELn register. */ - new_len =3D sve_zcr_len_for_el(env, cur_el); + new_len =3D cpu_sve_get_zcr_len_for_el(env, cur_el); if (new_len < old_len) { tcg_sve_narrow_vq(env, new_len + 1); } diff --git a/target/arm/tcg/helper.c b/target/arm/tcg/helper.c index 04ea37e101..a10b8a62dc 100644 --- a/target/arm/tcg/helper.c +++ b/target/arm/tcg/helper.c @@ -186,7 +186,7 @@ static int arm_gdb_get_svereg(CPUARMState *env, GByteAr= ray *buf, int reg) * We report in Vector Granules (VG) which is 64bit in a Z reg * while the ZCR works in Vector Quads (VQ) which is 128bit chunks. */ - int vq =3D sve_zcr_len_for_el(env, arm_current_el(env)) + 1; + int vq =3D cpu_sve_get_zcr_len_for_el(env, arm_current_el(env)) + = 1; return gdb_get_reg64(buf, vq * 2); } default: @@ -1023,7 +1023,7 @@ static uint32_t rebuild_hflags_a64(CPUARMState *env, = int el, int fp_el, if (sve_el !=3D 0 && fp_el =3D=3D 0) { zcr_len =3D 0; } else { - zcr_len =3D sve_zcr_len_for_el(env, el); + zcr_len =3D cpu_sve_get_zcr_len_for_el(env, el); } flags =3D FIELD_DP32(flags, TBFLAG_A64, SVEEXC_EL, sve_el); flags =3D FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len); diff --git a/target/arm/tcg/tcg-sve.c b/target/arm/tcg/tcg-sve.c index 25d5a5867c..80a37caf6e 100644 --- a/target/arm/tcg/tcg-sve.c +++ b/target/arm/tcg/tcg-sve.c @@ -155,10 +155,10 @@ void tcg_sve_change_el(CPUARMState *env, int old_el, */ old_a64 =3D old_el ? arm_el_is_aa64(env, old_el) : el0_a64; old_len =3D (old_a64 && !sve_exception_el(env, old_el) - ? sve_zcr_len_for_el(env, old_el) : 0); + ? cpu_sve_get_zcr_len_for_el(env, old_el) : 0); new_a64 =3D new_el ? arm_el_is_aa64(env, new_el) : el0_a64; new_len =3D (new_a64 && !sve_exception_el(env, new_el) - ? sve_zcr_len_for_el(env, new_el) : 0); + ? cpu_sve_get_zcr_len_for_el(env, new_el) : 0); =20 /* When changing vector length, clear inaccessible state. */ if (new_len < old_len) { --=20 2.26.2