From nobody Tue Feb 10 14:49:15 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1618403072; cv=none; d=zohomail.com; s=zohoarc; b=MAnHVFEcBCxADHTCZzo5gzza4JCxJh94LFcF45QOXEBW84E4I4vyqnwG/hS0TFCUcIaQ5qHUA6fMCbsmQf05Z1S2Q9RXJmz+iad00ckSq3yaqLsn+/Jc5ZtDA8ufwJNv406/2Uo6twizHr8XzHOnYM3pP/BsPq7A1cE4MQ2wT60= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618403072; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=R3L0BvwUTwI9Us7ZTmPtAeAEqP0MZJ6AwJmcIZUcW2Y=; b=Ax/nHto5h0DPGkIZ/92AcL5jg2sTAJY+VFz6nsUCcVvigVN/i/zROlHAkkWB5EcBhbCddCkn3MSIt1IK5WCXnbl0rm53tIfeHkvJU7ZHSY73pAbNm/IDbjH1D0z8nmKAl7OWfMT5ug4e1yyEBLWvfPo/JfoDajuThrhmwsSFp14= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1618403072013531.8857573905476; Wed, 14 Apr 2021 05:24:32 -0700 (PDT) Received: from localhost ([::1]:50736 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lWeZK-0004Ox-G3 for importer@patchew.org; Wed, 14 Apr 2021 08:24:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42482) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lWdgu-00070r-7r for qemu-devel@nongnu.org; Wed, 14 Apr 2021 07:28:16 -0400 Received: from mx2.suse.de ([195.135.220.15]:45908) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lWdgi-0005mc-7f for qemu-devel@nongnu.org; Wed, 14 Apr 2021 07:28:15 -0400 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id DE44EB139; Wed, 14 Apr 2021 11:27:19 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [RFC v13 58/80] target/arm: move TCG gt timer creation code in tcg/ Date: Wed, 14 Apr 2021 13:26:28 +0200 Message-Id: <20210414112650.18003-59-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210414112650.18003-1-cfontana@suse.de> References: <20210414112650.18003-1-cfontana@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Roman Bolshakov , Claudio Fontana , Eduardo Habkost , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" we need to be careful not to use if (tcg_enabled()) here, because of the VMSTATE definitions in machine.c, which are only protected by CONFIG_TCG, and thus it would break the --enable-tcg --enable-kvm build. Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson --- target/arm/tcg/tcg-cpu.h | 1 + target/arm/cpu.c | 30 ++++--------------------- target/arm/tcg/sysemu/tcg-cpu.c | 40 +++++++++++++++++++++++++++++++++ 3 files changed, 45 insertions(+), 26 deletions(-) diff --git a/target/arm/tcg/tcg-cpu.h b/target/arm/tcg/tcg-cpu.h index dd08587949..3e4ce2c355 100644 --- a/target/arm/tcg/tcg-cpu.h +++ b/target/arm/tcg/tcg-cpu.h @@ -33,6 +33,7 @@ void tcg_arm_init_accel_cpu(AccelCPUClass *accel_cpu, CPU= Class *cc); /* Do semihosting call and set the appropriate return value. */ void tcg_handle_semihosting(CPUState *cs); bool tcg_cpu_realizefn(CPUState *cs, Error **errp); +bool tcg_cpu_realize_gt_timers(CPUState *cs, Error **errp); =20 #endif /* !CONFIG_USER_ONLY */ =20 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 0b708238d4..4344a0d64d 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -859,32 +859,10 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) bool no_aa32 =3D false; =20 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) - { - uint64_t scale; - - if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { - if (!cpu->gt_cntfrq_hz) { - error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz", - cpu->gt_cntfrq_hz); - return; - } - scale =3D gt_cntfrq_period_ns(cpu); - } else { - scale =3D GTIMER_SCALE; - } - - cpu->gt_timer[GTIMER_PHYS] =3D timer_new(QEMU_CLOCK_VIRTUAL, scale, - arm_gt_ptimer_cb, cpu); - cpu->gt_timer[GTIMER_VIRT] =3D timer_new(QEMU_CLOCK_VIRTUAL, scale, - arm_gt_vtimer_cb, cpu); - cpu->gt_timer[GTIMER_HYP] =3D timer_new(QEMU_CLOCK_VIRTUAL, scale, - arm_gt_htimer_cb, cpu); - cpu->gt_timer[GTIMER_SEC] =3D timer_new(QEMU_CLOCK_VIRTUAL, scale, - arm_gt_stimer_cb, cpu); - cpu->gt_timer[GTIMER_HYPVIRT] =3D timer_new(QEMU_CLOCK_VIRTUAL, sc= ale, - arm_gt_hvtimer_cb, cpu); - } -#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ + if (!tcg_cpu_realize_gt_timers(cs, errp)) { + return; + } +#endif =20 cpu_exec_realizefn(cs, &local_err); if (local_err !=3D NULL) { diff --git a/target/arm/tcg/sysemu/tcg-cpu.c b/target/arm/tcg/sysemu/tcg-cp= u.c index 115ac523dc..1c6df15092 100644 --- a/target/arm/tcg/sysemu/tcg-cpu.c +++ b/target/arm/tcg/sysemu/tcg-cpu.c @@ -54,6 +54,46 @@ void tcg_handle_semihosting(CPUState *cs) } } =20 +/* + * we cannot use tcg_enabled() to condition the call to this function, + * due to the fields VMSTATE definitions in machine.c : it would break + * the --enable-tcg --enable-kvm build. We need to run this code whenever + * CONFIG_TCG is true, regardless of the chosen accelerator. + * + * So we cannot call this from tcg_cpu_realizefn, as this needs to + * be called whenever TCG is built-in, regardless of whether it is + * enabled or not. + */ +bool tcg_cpu_realize_gt_timers(CPUState *cs, Error **errp) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + uint64_t scale; + + if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { + if (!cpu->gt_cntfrq_hz) { + error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz", + cpu->gt_cntfrq_hz); + return false; + } + scale =3D gt_cntfrq_period_ns(cpu); + } else { + scale =3D GTIMER_SCALE; + } + + cpu->gt_timer[GTIMER_PHYS] =3D timer_new(QEMU_CLOCK_VIRTUAL, scale, + arm_gt_ptimer_cb, cpu); + cpu->gt_timer[GTIMER_VIRT] =3D timer_new(QEMU_CLOCK_VIRTUAL, scale, + arm_gt_vtimer_cb, cpu); + cpu->gt_timer[GTIMER_HYP] =3D timer_new(QEMU_CLOCK_VIRTUAL, scale, + arm_gt_htimer_cb, cpu); + cpu->gt_timer[GTIMER_SEC] =3D timer_new(QEMU_CLOCK_VIRTUAL, scale, + arm_gt_stimer_cb, cpu); + cpu->gt_timer[GTIMER_HYPVIRT] =3D timer_new(QEMU_CLOCK_VIRTUAL, scale, + arm_gt_hvtimer_cb, cpu); + return true; +} + bool tcg_cpu_realizefn(CPUState *cs, Error **errp) { ARMCPU *cpu =3D ARM_CPU(cs); --=20 2.26.2