From nobody Mon Feb 9 23:02:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1618402116; cv=none; d=zohomail.com; s=zohoarc; b=MmtWBQOW01OAkgXYUHxgsB9o6A3aboNP43p1YDxoyOzDDldNELzlSkM9+Wa/wB440kWL1/SZwvV1zMVh54g6dy9yLBgv68ZPCNr2qNfsSqinBGPUjc1VyBm2Kr9NkZcJ86TsRCAiAhTbwI0T0/AKycVKKMjiWwEuE5g+jx2zRgU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618402116; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=24+x26DHhV7H++Ekp/MyckQ9+LGIqSpUWlX9I1Rpfos=; b=foEOXtdAoiThP9RoeMn4ZcKzlnRQCznoWtEMcKZtK8CQRmRKvqvOJa//VoCR2Dah6eXQrLDb5uQzAwPdEiD5iF97CEU3lFZtQ/ejM2T7tF6wIe0m1Pb+fXACQq03rWtdqPeWHxBMNmptGVvsBnntKsYEftIsWUI0C5cQUSJwm0c= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1618402116485403.11751754115437; Wed, 14 Apr 2021 05:08:36 -0700 (PDT) Received: from localhost ([::1]:41846 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lWeJv-00041O-Dr for importer@patchew.org; Wed, 14 Apr 2021 08:08:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42238) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lWdgk-0006eP-EL for qemu-devel@nongnu.org; Wed, 14 Apr 2021 07:28:06 -0400 Received: from mx2.suse.de ([195.135.220.15]:45718) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lWdgW-0005gF-CN for qemu-devel@nongnu.org; Wed, 14 Apr 2021 07:28:06 -0400 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id D6306B11A; Wed, 14 Apr 2021 11:27:09 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [RFC v13 36/80] target/arm: fix style of arm_cpu_do_interrupt functions before move Date: Wed, 14 Apr 2021 13:26:06 +0200 Message-Id: <20210414112650.18003-37-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210414112650.18003-1-cfontana@suse.de> References: <20210414112650.18003-1-cfontana@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Roman Bolshakov , Claudio Fontana , Eduardo Habkost , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" before refactoring the exception code, fix the style of the functions being moved. Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson --- target/arm/tcg/helper.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/target/arm/tcg/helper.c b/target/arm/tcg/helper.c index f2407f0af5..9f16af8a68 100644 --- a/target/arm/tcg/helper.c +++ b/target/arm/tcg/helper.c @@ -896,10 +896,11 @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs) new_mode =3D ARM_CPU_MODE_UND; addr =3D 0x04; mask =3D CPSR_I; - if (env->thumb) + if (env->thumb) { offset =3D 2; - else + } else { offset =3D 4; + } break; case EXCP_SWI: new_mode =3D ARM_CPU_MODE_SVC; @@ -985,7 +986,8 @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs) /* High vectors. When enabled, base address cannot be remapped. */ addr +=3D 0xffff0000; } else { - /* ARM v7 architectures provide a vector base address register to = remap + /* + * ARM v7 architectures provide a vector base address register to = remap * the interrupt vector table. * This register is only followed in non-monitor mode, and is bank= ed. * Note: only bits 31:5 are valid. @@ -1094,7 +1096,8 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) aarch64_sve_change_el(env, cur_el, new_el, is_a64(env)); =20 if (cur_el < new_el) { - /* Entry vector offset depends on whether the implemented EL + /* + * Entry vector offset depends on whether the implemented EL * immediately lower than the target level is using AArch32 or AAr= ch64 */ bool is_aa64; @@ -1285,7 +1288,8 @@ static void handle_semihosting(CPUState *cs) } #endif =20 -/* Handle a CPU exception for A and R profile CPUs. +/* + * Handle a CPU exception for A and R profile CPUs. * Do any appropriate logging, handle PSCI calls, and then hand off * to the AArch64-entry or AArch32-entry function depending on the * target exception level's register width. @@ -1330,7 +1334,8 @@ void arm_cpu_do_interrupt(CPUState *cs) } #endif =20 - /* Hooks may change global state so BQL should be held, also the + /* + * Hooks may change global state so BQL should be held, also the * BQL needs to be held for any modification of * cs->interrupt_request. */ --=20 2.26.2