From nobody Mon Feb 9 22:38:53 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1618401714; cv=none; d=zohomail.com; s=zohoarc; b=S0glCahRpajS/keF2FBADUa4IzZ+Lc6VMBzYDgn/zMVPoy30vjzGy5614abYkPvbt8I/5GgsoxY4sQs8l8ZImxr5f2uExTFT7JAYsMRbYgXQJ+RvahItswoOYchTALWFIjWG5RbtcwUaRlylwrhfNxIHDnSnV7+bE/41NCFW/xo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618401714; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=feb1iKHg3lLErG9wpA2dfIOfX4RFvyqd8k/zJxcA1vE=; b=cacb79uvG/w3H8umiVVfvP+NUYwb8flkV0UXYd7rQnq69a8Wiaa3vQo4NM4K/xI4g/h7s0RxhB9ZJ1J0KPGZRRbKnf5ozjZh9V8Ns6gPLs64EX9JnVyUwwEC91JaiEn+Gv+93QZQBSxVjHxEX3hGCenFYnjT7fS9ymDM/mVbIFE= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16184017139849.845300136944275; Wed, 14 Apr 2021 05:01:53 -0700 (PDT) Received: from localhost ([::1]:56040 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lWeDO-0006Xx-3b for importer@patchew.org; Wed, 14 Apr 2021 08:01:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42182) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lWdgh-0006bJ-Lk for qemu-devel@nongnu.org; Wed, 14 Apr 2021 07:28:05 -0400 Received: from mx2.suse.de ([195.135.220.15]:45672) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lWdgT-0005fa-0n for qemu-devel@nongnu.org; Wed, 14 Apr 2021 07:28:03 -0400 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id A1990B0BE; Wed, 14 Apr 2021 11:27:07 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [RFC v13 31/80] target/arm: move sve_exception_el out of TCG helpers Date: Wed, 14 Apr 2021 13:26:01 +0200 Message-Id: <20210414112650.18003-32-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210414112650.18003-1-cfontana@suse.de> References: <20210414112650.18003-1-cfontana@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Roman Bolshakov , Claudio Fontana , Eduardo Habkost , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" we need this for KVM too. Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson --- target/arm/cpu-sysemu.c | 62 +++++++++++++++++++++++++++++++++++++++ target/arm/cpu-user.c | 5 ++++ target/arm/tcg/helper.c | 64 ----------------------------------------- 3 files changed, 67 insertions(+), 64 deletions(-) diff --git a/target/arm/cpu-sysemu.c b/target/arm/cpu-sysemu.c index 7a314bf805..7cc721fe68 100644 --- a/target/arm/cpu-sysemu.c +++ b/target/arm/cpu-sysemu.c @@ -348,3 +348,65 @@ void aarch64_sync_64_to_32(CPUARMState *env) =20 env->regs[15] =3D env->pc; } + +/* + * Return the exception level to which exceptions should be taken + * via SVEAccessTrap. If an exception should be routed through + * AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should + * take care of raising that exception. + * C.f. the ARM pseudocode function CheckSVEEnabled. + */ +int sve_exception_el(CPUARMState *env, int el) +{ + uint64_t hcr_el2 =3D arm_hcr_el2_eff(env); + + if (el <=3D 1 && (hcr_el2 & (HCR_E2H | HCR_TGE)) !=3D (HCR_E2H | HCR_T= GE)) { + bool disabled =3D false; + + /* + * The CPACR.ZEN controls traps to EL1: + * 0, 2 : trap EL0 and EL1 accesses + * 1 : trap only EL0 accesses + * 3 : trap no accesses + */ + if (!extract32(env->cp15.cpacr_el1, 16, 1)) { + disabled =3D true; + } else if (!extract32(env->cp15.cpacr_el1, 17, 1)) { + disabled =3D el =3D=3D 0; + } + if (disabled) { + /* route_to_el2 */ + return hcr_el2 & HCR_TGE ? 2 : 1; + } + + /* Check CPACR.FPEN. */ + if (!extract32(env->cp15.cpacr_el1, 20, 1)) { + disabled =3D true; + } else if (!extract32(env->cp15.cpacr_el1, 21, 1)) { + disabled =3D el =3D=3D 0; + } + if (disabled) { + return 0; + } + } + + /* + * CPTR_EL2. Since TZ and TFP are positive, + * they will be zero when EL2 is not present. + */ + if (el <=3D 2 && arm_is_el2_enabled(env)) { + if (env->cp15.cptr_el[2] & CPTR_TZ) { + return 2; + } + if (env->cp15.cptr_el[2] & CPTR_TFP) { + return 0; + } + } + + /* CPTR_EL3. Since EZ is negative we must check for EL3. */ + if (arm_feature(env, ARM_FEATURE_EL3) + && !(env->cp15.cptr_el[3] & CPTR_EZ)) { + return 3; + } + return 0; +} diff --git a/target/arm/cpu-user.c b/target/arm/cpu-user.c index 0225089e46..39093ade76 100644 --- a/target/arm/cpu-user.c +++ b/target/arm/cpu-user.c @@ -33,3 +33,8 @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t e= xcp_idx, { return 1; } + +int sve_exception_el(CPUARMState *env, int el) +{ + return 0; +} diff --git a/target/arm/tcg/helper.c b/target/arm/tcg/helper.c index e4f18bcaa7..aaa307daca 100644 --- a/target/arm/tcg/helper.c +++ b/target/arm/tcg/helper.c @@ -261,70 +261,6 @@ static int arm_gdb_set_svereg(CPUARMState *env, uint8_= t *buf, int reg) } #endif /* TARGET_AARCH64 */ =20 -/* - * Return the exception level to which exceptions should be taken - * via SVEAccessTrap. If an exception should be routed through - * AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should - * take care of raising that exception. - * C.f. the ARM pseudocode function CheckSVEEnabled. - */ -int sve_exception_el(CPUARMState *env, int el) -{ -#ifndef CONFIG_USER_ONLY - uint64_t hcr_el2 =3D arm_hcr_el2_eff(env); - - if (el <=3D 1 && (hcr_el2 & (HCR_E2H | HCR_TGE)) !=3D (HCR_E2H | HCR_T= GE)) { - bool disabled =3D false; - - /* - * The CPACR.ZEN controls traps to EL1: - * 0, 2 : trap EL0 and EL1 accesses - * 1 : trap only EL0 accesses - * 3 : trap no accesses - */ - if (!extract32(env->cp15.cpacr_el1, 16, 1)) { - disabled =3D true; - } else if (!extract32(env->cp15.cpacr_el1, 17, 1)) { - disabled =3D el =3D=3D 0; - } - if (disabled) { - /* route_to_el2 */ - return hcr_el2 & HCR_TGE ? 2 : 1; - } - - /* Check CPACR.FPEN. */ - if (!extract32(env->cp15.cpacr_el1, 20, 1)) { - disabled =3D true; - } else if (!extract32(env->cp15.cpacr_el1, 21, 1)) { - disabled =3D el =3D=3D 0; - } - if (disabled) { - return 0; - } - } - - /* - * CPTR_EL2. Since TZ and TFP are positive, - * they will be zero when EL2 is not present. - */ - if (el <=3D 2 && arm_is_el2_enabled(env)) { - if (env->cp15.cptr_el[2] & CPTR_TZ) { - return 2; - } - if (env->cp15.cptr_el[2] & CPTR_TFP) { - return 0; - } - } - - /* CPTR_EL3. Since EZ is negative we must check for EL3. */ - if (arm_feature(env, ARM_FEATURE_EL3) - && !(env->cp15.cptr_el[3] & CPTR_EZ)) { - return 3; - } -#endif - return 0; -} - void hw_watchpoint_update(ARMCPU *cpu, int n) { CPUARMState *env =3D &cpu->env; --=20 2.26.2