From nobody Mon Feb 9 21:12:04 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1618401909; cv=none; d=zohomail.com; s=zohoarc; b=m0eXILEc3kJsbFU9+cad6emFP85T8p6k/QcUKzLj4IpnTG+Hy1di7JtzqoEx3OD8ckLuyrMyno4R7XSkVL/JrkuHwhb2SuBTaJwUB2qBncsRP2RnEU4tBwpaugOxrjs22L+Tz6FjxNvVoFcVI60X2JUntRj5TNEbkyZq8l9GWFE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618401909; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Kwv9+h3MbUqnf3GG3szbhh4bj4k67wlmVT+EIXTQ0N4=; b=hRgw2FJWVtYMT8wlvnqiabahA1bZFtFOQME8E+0xgel3jWm7mq2ZoXATNV9o49VJh0VeyetvVrKgyJUE5ZNALloZ4m1oXnBPt6UppwvxbhFmb6w6MNC7qZeS9C+PhZpvewSdzsyaNs5vszjXbff0U5M1cUOGAC52KCQ5LjorIWo= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1618401909619108.23294608949516; Wed, 14 Apr 2021 05:05:09 -0700 (PDT) Received: from localhost ([::1]:36018 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lWeGa-0001WF-0r for importer@patchew.org; Wed, 14 Apr 2021 08:05:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42180) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lWdgh-0006bH-Ky for qemu-devel@nongnu.org; Wed, 14 Apr 2021 07:28:05 -0400 Received: from mx2.suse.de ([195.135.220.15]:45622) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lWdgQ-0005dN-4K for qemu-devel@nongnu.org; Wed, 14 Apr 2021 07:28:01 -0400 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id C18BCAF0F; Wed, 14 Apr 2021 11:27:06 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [RFC v13 29/80] target/arm: move a15 cpu model away from the TCG-only models Date: Wed, 14 Apr 2021 13:25:59 +0200 Message-Id: <20210414112650.18003-30-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210414112650.18003-1-cfontana@suse.de> References: <20210414112650.18003-1-cfontana@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Roman Bolshakov , Claudio Fontana , Eduardo Habkost , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Cortex-A15 is the only ARM cpu class we need in KVM too. We will be able to move it to tcg/ once the board code and configurations are fixed. Signed-off-by: Claudio Fontana --- target/arm/cpu32.h | 4 +++ target/arm/cpu32.c | 73 ++++++++++++++++++++++++++++++++++++++++++++ target/arm/cpu_tcg.c | 67 ---------------------------------------- 3 files changed, 77 insertions(+), 67 deletions(-) diff --git a/target/arm/cpu32.h b/target/arm/cpu32.h index 128d0c9247..abd575d47d 100644 --- a/target/arm/cpu32.h +++ b/target/arm/cpu32.h @@ -21,8 +21,12 @@ #ifndef ARM_CPU32_H #define ARM_CPU32_H =20 +#include "cpregs.h" + void arm32_cpu_dump_state(CPUState *cs, FILE *f, int flags); void arm32_cpu_class_init(ObjectClass *oc, void *data); void arm32_cpu_register(const ARMCPUInfo *info); +void cortex_a15_initfn(Object *obj); +extern const ARMCPRegInfo cortexa15_cp_reginfo[]; =20 #endif /* ARM_CPU32_H */ diff --git a/target/arm/cpu32.c b/target/arm/cpu32.c index c03f420ba2..a6ba91ae08 100644 --- a/target/arm/cpu32.c +++ b/target/arm/cpu32.c @@ -43,8 +43,81 @@ #include "cpu-mmu.h" #include "cpu32.h" =20 +#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) + +#ifndef CONFIG_USER_ONLY +static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + MachineState *ms =3D MACHINE(qdev_get_machine()); + + /* + * Linux wants the number of processors from here. + * Might as well set the interrupt-controller bit too. + */ + return ((ms->smp.cpus - 1) << 24) | (1 << 23); +} +#endif + +const ARMCPRegInfo cortexa15_cp_reginfo[] =3D { +#ifndef CONFIG_USER_ONLY + { .name =3D "L2CTLR", .cp =3D 15, .crn =3D 9, .crm =3D 0, .opc1 =3D 1,= .opc2 =3D 2, + .access =3D PL1_RW, .resetvalue =3D 0, .readfn =3D a15_l2ctlr_read, + .writefn =3D arm_cp_write_ignore, }, +#endif + { .name =3D "L2ECTLR", .cp =3D 15, .crn =3D 9, .crm =3D 0, .opc1 =3D 1= , .opc2 =3D 3, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + REGINFO_SENTINEL +}; + +void cortex_a15_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,cortex-a15"; + set_feature(&cpu->env, ARM_FEATURE_V7VE); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + cpu->kvm_target =3D QEMU_KVM_ARM_TARGET_CORTEX_A15; + cpu->midr =3D 0x412fc0f1; + cpu->reset_fpsid =3D 0x410430f0; + cpu->isar.mvfr0 =3D 0x10110222; + cpu->isar.mvfr1 =3D 0x11111111; + cpu->ctr =3D 0x8444c004; + cpu->reset_sctlr =3D 0x00c50078; + cpu->isar.id_pfr0 =3D 0x00001131; + cpu->isar.id_pfr1 =3D 0x00011011; + cpu->isar.id_dfr0 =3D 0x02010555; + cpu->id_afr0 =3D 0x00000000; + cpu->isar.id_mmfr0 =3D 0x10201105; + cpu->isar.id_mmfr1 =3D 0x20000000; + cpu->isar.id_mmfr2 =3D 0x01240000; + cpu->isar.id_mmfr3 =3D 0x02102211; + cpu->isar.id_isar0 =3D 0x02101110; + cpu->isar.id_isar1 =3D 0x13112111; + cpu->isar.id_isar2 =3D 0x21232041; + cpu->isar.id_isar3 =3D 0x11112131; + cpu->isar.id_isar4 =3D 0x10011142; + cpu->isar.dbgdidr =3D 0x3515f021; + cpu->clidr =3D 0x0a200023; + cpu->ccsidr[0] =3D 0x701fe00a; /* 32K L1 dcache */ + cpu->ccsidr[1] =3D 0x201fe00a; /* 32K L1 icache */ + cpu->ccsidr[2] =3D 0x711fe07a; /* 4096K L2 unified cache */ + define_arm_cp_regs(cpu, cortexa15_cp_reginfo); +} + +#endif /* !CONFIG_USER_ONLY || !TARGET_AARCH64 */ + /* we can move this to tcg/ after the cleanup of ARM boards configurations= */ static const ARMCPUInfo arm32_cpus[] =3D { +#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) + { .name =3D "cortex-a15", .initfn =3D cortex_a15_initfn }, +#endif /* !CONFIG_USER_ONLY || !TARGET_AARCH64 */ }; =20 static gchar *arm_gdb_arch_name(CPUState *cs) diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 0d5c8340b7..d120250b18 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -378,30 +378,6 @@ static void cortex_a9_initfn(Object *obj) define_arm_cp_regs(cpu, cortexa9_cp_reginfo); } =20 -#ifndef CONFIG_USER_ONLY -static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - MachineState *ms =3D MACHINE(qdev_get_machine()); - - /* - * Linux wants the number of processors from here. - * Might as well set the interrupt-controller bit too. - */ - return ((ms->smp.cpus - 1) << 24) | (1 << 23); -} -#endif - -static const ARMCPRegInfo cortexa15_cp_reginfo[] =3D { -#ifndef CONFIG_USER_ONLY - { .name =3D "L2CTLR", .cp =3D 15, .crn =3D 9, .crm =3D 0, .opc1 =3D 1,= .opc2 =3D 2, - .access =3D PL1_RW, .resetvalue =3D 0, .readfn =3D a15_l2ctlr_read, - .writefn =3D arm_cp_write_ignore, }, -#endif - { .name =3D "L2ECTLR", .cp =3D 15, .crn =3D 9, .crm =3D 0, .opc1 =3D 1= , .opc2 =3D 3, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - REGINFO_SENTINEL -}; - static void cortex_a7_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); @@ -448,48 +424,6 @@ static void cortex_a7_initfn(Object *obj) define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ } =20 -static void cortex_a15_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "arm,cortex-a15"; - set_feature(&cpu->env, ARM_FEATURE_V7VE); - set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); - set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); - set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); - set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); - set_feature(&cpu->env, ARM_FEATURE_EL2); - set_feature(&cpu->env, ARM_FEATURE_EL3); - set_feature(&cpu->env, ARM_FEATURE_PMU); - cpu->kvm_target =3D QEMU_KVM_ARM_TARGET_CORTEX_A15; - cpu->midr =3D 0x412fc0f1; - cpu->reset_fpsid =3D 0x410430f0; - cpu->isar.mvfr0 =3D 0x10110222; - cpu->isar.mvfr1 =3D 0x11111111; - cpu->ctr =3D 0x8444c004; - cpu->reset_sctlr =3D 0x00c50078; - cpu->isar.id_pfr0 =3D 0x00001131; - cpu->isar.id_pfr1 =3D 0x00011011; - cpu->isar.id_dfr0 =3D 0x02010555; - cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x10201105; - cpu->isar.id_mmfr1 =3D 0x20000000; - cpu->isar.id_mmfr2 =3D 0x01240000; - cpu->isar.id_mmfr3 =3D 0x02102211; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232041; - cpu->isar.id_isar3 =3D 0x11112131; - cpu->isar.id_isar4 =3D 0x10011142; - cpu->isar.dbgdidr =3D 0x3515f021; - cpu->clidr =3D 0x0a200023; - cpu->ccsidr[0] =3D 0x701fe00a; /* 32K L1 dcache */ - cpu->ccsidr[1] =3D 0x201fe00a; /* 32K L1 icache */ - cpu->ccsidr[2] =3D 0x711fe07a; /* 4096K L2 unified cache */ - define_arm_cp_regs(cpu, cortexa15_cp_reginfo); -} - static void cortex_m0_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); @@ -1021,7 +955,6 @@ static const ARMCPUInfo arm_tcg_cpus[] =3D { { .name =3D "cortex-a7", .initfn =3D cortex_a7_initfn }, { .name =3D "cortex-a8", .initfn =3D cortex_a8_initfn }, { .name =3D "cortex-a9", .initfn =3D cortex_a9_initfn }, - { .name =3D "cortex-a15", .initfn =3D cortex_a15_initfn }, { .name =3D "cortex-m0", .initfn =3D cortex_m0_initfn, .class_init =3D arm_v7m_class_init }, { .name =3D "cortex-m3", .initfn =3D cortex_m3_initfn, --=20 2.26.2