From nobody Mon Feb 9 20:31:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1618401421; cv=none; d=zohomail.com; s=zohoarc; b=l/nB1JmjYmvSDX8GNl/JZec6ewctQhvx9bwxzV6YPHG3OSTWtFNnt7fXNVyqA4LqxP8oNYLjTr8nzb19G7O9404lGcA1ikv3rGUmWMQCaqVynr/yXfuik3GArQ1Qs9fjxthkHNCRKZbRBLoChhVPZHKCnncjY0oBjfVj6JnTDkU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618401421; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Gg/QWpaq7KdhqKdUMbwXzm8+ITpunuCEU2JxOiQX12A=; b=nKTwlyollwWJVV5jxek06XpdFExRQZfiZtM9t+heRWVIz4bkBdelEBXEXthja5hTZK4Re+0CLuWCdxX2YDl9EaCRH5WZeru0Wgyc/O+V78Eu2e+MhreueW4y9y6sYfll6Ui+cxyKJFlhGVi/lP1pew95m3M6mHK6owl6pL0N8Jo= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1618401421796138.537027573567; Wed, 14 Apr 2021 04:57:01 -0700 (PDT) Received: from localhost ([::1]:44322 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lWe8i-0001jw-Kq for importer@patchew.org; Wed, 14 Apr 2021 07:57:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41924) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lWdgO-0006Pg-Sz for qemu-devel@nongnu.org; Wed, 14 Apr 2021 07:27:45 -0400 Received: from mx2.suse.de ([195.135.220.15]:44982) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lWdg9-0005Vz-MQ for qemu-devel@nongnu.org; Wed, 14 Apr 2021 07:27:44 -0400 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id C0D27B07B; Wed, 14 Apr 2021 11:27:02 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [RFC v13 20/80] target/arm: move arm_hcr_el2_eff from tcg/ to common_cpu Date: Wed, 14 Apr 2021 13:25:50 +0200 Message-Id: <20210414112650.18003-21-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210414112650.18003-1-cfontana@suse.de> References: <20210414112650.18003-1-cfontana@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Roman Bolshakov , Claudio Fontana , Eduardo Habkost , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" we will need this for KVM too, especially for Nested support. Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson --- target/arm/cpu-common.c | 68 +++++++++++++++++++++++++++++++++++++++++ target/arm/tcg/helper.c | 68 ----------------------------------------- 2 files changed, 68 insertions(+), 68 deletions(-) diff --git a/target/arm/cpu-common.c b/target/arm/cpu-common.c index 694e5d73f3..040e06392a 100644 --- a/target/arm/cpu-common.c +++ b/target/arm/cpu-common.c @@ -231,3 +231,71 @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32= _t mask, mask &=3D ~CACHED_CPSR_BITS; env->uncached_cpsr =3D (env->uncached_cpsr & ~mask) | (val & mask); } + +/* + * Return the effective value of HCR_EL2. + * Bits that are not included here: + * RW (read from SCR_EL3.RW as needed) + */ +uint64_t arm_hcr_el2_eff(CPUARMState *env) +{ + uint64_t ret =3D env->cp15.hcr_el2; + + if (!arm_is_el2_enabled(env)) { + /* + * "This register has no effect if EL2 is not enabled in the + * current Security state". This is ARMv8.4-SecEL2 speak for + * !(SCR_EL3.NS=3D=3D1 || SCR_EL3.EEL2=3D=3D1). + * + * Prior to that, the language was "In an implementation that + * includes EL3, when the value of SCR_EL3.NS is 0 the PE behaves + * as if this field is 0 for all purposes other than a direct + * read or write access of HCR_EL2". With lots of enumeration + * on a per-field basis. In current QEMU, this is condition + * is arm_is_secure_below_el3. + * + * Since the v8.4 language applies to the entire register, and + * appears to be backward compatible, use that. + */ + return 0; + } + + /* + * For a cpu that supports both aarch64 and aarch32, we can set bits + * in HCR_EL2 (e.g. via EL3) that are RES0 when we enter EL2 as aa32. + * Ignore all of the bits in HCR+HCR2 that are not valid for aarch32. + */ + if (!arm_el_is_aa64(env, 2)) { + uint64_t aa32_valid; + + /* + * These bits are up-to-date as of ARMv8.6. + * For HCR, it's easiest to list just the 2 bits that are invalid. + * For HCR2, list those that are valid. + */ + aa32_valid =3D MAKE_64BIT_MASK(0, 32) & ~(HCR_RW | HCR_TDZ); + aa32_valid |=3D (HCR_CD | HCR_ID | HCR_TERR | HCR_TEA | HCR_MIOCNC= E | + HCR_TID4 | HCR_TICAB | HCR_TOCU | HCR_TTLBIS); + ret &=3D aa32_valid; + } + + if (ret & HCR_TGE) { + /* These bits are up-to-date as of ARMv8.6. */ + if (ret & HCR_E2H) { + ret &=3D ~(HCR_VM | HCR_FMO | HCR_IMO | HCR_AMO | + HCR_BSU_MASK | HCR_DC | HCR_TWI | HCR_TWE | + HCR_TID0 | HCR_TID2 | HCR_TPCP | HCR_TPU | + HCR_TDZ | HCR_CD | HCR_ID | HCR_MIOCNCE | + HCR_TID4 | HCR_TICAB | HCR_TOCU | HCR_ENSCXT | + HCR_TTLBIS | HCR_TTLBOS | HCR_TID5); + } else { + ret |=3D HCR_FMO | HCR_IMO | HCR_AMO; + } + ret &=3D ~(HCR_SWIO | HCR_PTW | HCR_VF | HCR_VI | HCR_VSE | + HCR_FB | HCR_TID1 | HCR_TID3 | HCR_TSC | HCR_TACR | + HCR_TSW | HCR_TTLB | HCR_TVM | HCR_HCD | HCR_TRVM | + HCR_TLOR); + } + + return ret; +} diff --git a/target/arm/tcg/helper.c b/target/arm/tcg/helper.c index f35d2969b0..15f53d57b0 100644 --- a/target/arm/tcg/helper.c +++ b/target/arm/tcg/helper.c @@ -261,74 +261,6 @@ static int arm_gdb_set_svereg(CPUARMState *env, uint8_= t *buf, int reg) } #endif /* TARGET_AARCH64 */ =20 -/* - * Return the effective value of HCR_EL2. - * Bits that are not included here: - * RW (read from SCR_EL3.RW as needed) - */ -uint64_t arm_hcr_el2_eff(CPUARMState *env) -{ - uint64_t ret =3D env->cp15.hcr_el2; - - if (!arm_is_el2_enabled(env)) { - /* - * "This register has no effect if EL2 is not enabled in the - * current Security state". This is ARMv8.4-SecEL2 speak for - * !(SCR_EL3.NS=3D=3D1 || SCR_EL3.EEL2=3D=3D1). - * - * Prior to that, the language was "In an implementation that - * includes EL3, when the value of SCR_EL3.NS is 0 the PE behaves - * as if this field is 0 for all purposes other than a direct - * read or write access of HCR_EL2". With lots of enumeration - * on a per-field basis. In current QEMU, this is condition - * is arm_is_secure_below_el3. - * - * Since the v8.4 language applies to the entire register, and - * appears to be backward compatible, use that. - */ - return 0; - } - - /* - * For a cpu that supports both aarch64 and aarch32, we can set bits - * in HCR_EL2 (e.g. via EL3) that are RES0 when we enter EL2 as aa32. - * Ignore all of the bits in HCR+HCR2 that are not valid for aarch32. - */ - if (!arm_el_is_aa64(env, 2)) { - uint64_t aa32_valid; - - /* - * These bits are up-to-date as of ARMv8.6. - * For HCR, it's easiest to list just the 2 bits that are invalid. - * For HCR2, list those that are valid. - */ - aa32_valid =3D MAKE_64BIT_MASK(0, 32) & ~(HCR_RW | HCR_TDZ); - aa32_valid |=3D (HCR_CD | HCR_ID | HCR_TERR | HCR_TEA | HCR_MIOCNC= E | - HCR_TID4 | HCR_TICAB | HCR_TOCU | HCR_TTLBIS); - ret &=3D aa32_valid; - } - - if (ret & HCR_TGE) { - /* These bits are up-to-date as of ARMv8.6. */ - if (ret & HCR_E2H) { - ret &=3D ~(HCR_VM | HCR_FMO | HCR_IMO | HCR_AMO | - HCR_BSU_MASK | HCR_DC | HCR_TWI | HCR_TWE | - HCR_TID0 | HCR_TID2 | HCR_TPCP | HCR_TPU | - HCR_TDZ | HCR_CD | HCR_ID | HCR_MIOCNCE | - HCR_TID4 | HCR_TICAB | HCR_TOCU | HCR_ENSCXT | - HCR_TTLBIS | HCR_TTLBOS | HCR_TID5); - } else { - ret |=3D HCR_FMO | HCR_IMO | HCR_AMO; - } - ret &=3D ~(HCR_SWIO | HCR_PTW | HCR_VF | HCR_VI | HCR_VSE | - HCR_FB | HCR_TID1 | HCR_TID3 | HCR_TSC | HCR_TACR | - HCR_TSW | HCR_TTLB | HCR_TVM | HCR_HCD | HCR_TRVM | - HCR_TLOR); - } - - return ret; -} - /* Return the exception level to which exceptions should be taken * via SVEAccessTrap. If an exception should be routed through * AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should --=20 2.26.2