From nobody Sun May 19 05:50:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1618370808; cv=none; d=zohomail.com; s=zohoarc; b=XFmvfepxYRMHKz4xHMqQZrffrxrvhPUdAeQQHYPqS1p+gwV6aUkWAGfKnkFEEUwzahahBh9V7P2mg5uMO9WbYjJ49wMAw7CjZRdJG5BfJhyiXuipHrMeE5VumJBVNBe/B+76R+pNA3SqN1z0TC1RVxXCnB69FWJMjoiJPXw9s74= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618370808; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=tUfpiQ1JIdUEP6e/PV+PX1/SVxIZMN/m+9EssQMGzpk=; b=WSIk9fBAy8Uqcb1m8yS7eCpJOlJjZsBJ/q8RrPeuEcTXt8SX90OJs9p97Db3gA8MIJDNC5S4O2JfLPGqm0DDhZA49aGRL+stQVCncqtOInkHA8wbItyohsQHGbTCGfj6nxeCRN99Q8bZsqrTVPwLazSdUmyfdsaZdcG8YT8Q7cE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1618370808940331.5331975924395; Tue, 13 Apr 2021 20:26:48 -0700 (PDT) Received: from localhost ([::1]:50880 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lWWAx-0000UB-Sv for importer@patchew.org; Tue, 13 Apr 2021 23:26:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52030) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lWW8D-0006nM-Fb; Tue, 13 Apr 2021 23:23:57 -0400 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]:42763) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lWW8B-0003am-9q; Tue, 13 Apr 2021 23:23:57 -0400 Received: by mail-pj1-x1029.google.com with SMTP id j6-20020a17090adc86b02900cbfe6f2c96so10079182pjv.1; Tue, 13 Apr 2021 20:23:54 -0700 (PDT) Received: from bobo.ibm.com (193-116-90-211.tpgi.com.au. [193.116.90.211]) by smtp.gmail.com with ESMTPSA id fa6sm3407435pjb.2.2021.04.13.20.23.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Apr 2021 20:23:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tUfpiQ1JIdUEP6e/PV+PX1/SVxIZMN/m+9EssQMGzpk=; b=T33NNyqgtuCxptE168yvhMI6OTxRUFrHGXvW54xzbUAcqqXbYREYmFG/Q90ESpbhPw 2GP08xZNXOTaPJz7ZzbA+Fy/pPXapoEJ2zOCt6E2Xz9iXZiDJaGc6nthekVTfDUlFMBC 6ous3xe/F3kIih+2dX//s9Yz4KZRBTq8EaYfA0h4yOPR9gI5FzMlzzk7oHoPIQvHg+aH Y4OrdebTIQnOA5iJr33GW/Wz65jVigp4emYhE3H0fCV+3JOOfOLW2/eMQnAYI5a4LlA7 mvCOI24UchLguL08NbBmCuz6A6lcLx3cagW06DiO87aaVdsUarFfA5z6nuPlyQ1I4o/j 8BPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tUfpiQ1JIdUEP6e/PV+PX1/SVxIZMN/m+9EssQMGzpk=; b=iIE3LHhi5L0LqZjcNgJ5BmdjMxpzQSqCW0NVbsCqJ5GqHIehCQbLifQDolfIkRGXU6 BvH85IhqwNsH/koEUqo04DxYagw+kIcrMRBoeLnI7CgxkYniHxL2Nf39vdpZzIBx8K3i +RR6wShTaIafc90Fyw2Zcptapz2Yg/4qKIT558IOZW+KASjSleyRafDG28fxWC3/1D1u trAbntW2/pPj3+1APCgZ7j8XZnZYMffflHbDNe1GTT9X3dDzvBUgSJI5p7DRiQskzaq1 1Jh1R8zaJa3Up3HgqACdqFHBPV/E7RJVH7+0H+V23WOIjoXO7FAOMsV4VJ51N1fFHWCR 0bWw== X-Gm-Message-State: AOAM530jNf+H/UfdDeJ64Z3a7aj7wR95PcGPXVuMYe7J53rtPfaXTwQn u1mDYq5+yoQOpR33Pxhp7pHFqoVrJTw= X-Google-Smtp-Source: ABdhPJxi7qBQzUgy2AWEDkNMm1Xf8LJiHY/JxsN70edUIw/hC97Lk4nb0iWgqOAJv1Usqm3b6TQnbQ== X-Received: by 2002:a17:902:e84a:b029:e8:c4ca:1164 with SMTP id t10-20020a170902e84ab02900e8c4ca1164mr35034255plg.26.1618370633275; Tue, 13 Apr 2021 20:23:53 -0700 (PDT) From: Nicholas Piggin To: qemu-ppc@nongnu.org Subject: [RFC PATCH 1/2] target/ppc: rework AIL logic in interrupt delivery Date: Wed, 14 Apr 2021 13:23:42 +1000 Message-Id: <20210414032343.1720010-2-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20210414032343.1720010-1-npiggin@gmail.com> References: <20210414032343.1720010-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=npiggin@gmail.com; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fabiano Rosas , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-devel@nongnu.org, Nicholas Piggin , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The AIL logic is becoming unmanageable spread all over powerpc_excp(), and it is slated to get even worse with POWER10 support. Move it all to a new helper function. Signed-off-by: Nicholas Piggin Reviewed-by: C=C3=A9dric Le Goater Tested-by: C=C3=A9dric Le Goater --- hw/ppc/spapr_hcall.c | 3 +- target/ppc/cpu.h | 8 -- target/ppc/excp_helper.c | 161 ++++++++++++++++++++------------ target/ppc/translate_init.c.inc | 2 +- 4 files changed, 104 insertions(+), 70 deletions(-) diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index 7b5cd3553c..2fbe04a689 100644 --- a/hw/ppc/spapr_hcall.c +++ b/hw/ppc/spapr_hcall.c @@ -1395,7 +1395,8 @@ static target_ulong h_set_mode_resource_addr_trans_mo= de(PowerPCCPU *cpu, return H_P4; } =20 - if (mflags =3D=3D AIL_RESERVED) { + if (mflags =3D=3D 1) { + /* AIL=3D1 is reserved */ return H_UNSUPPORTED_FLAG; } =20 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index e73416da68..5200a16d23 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2375,14 +2375,6 @@ enum { HMER_XSCOM_STATUS_MASK =3D PPC_BITMASK(21, 23), }; =20 -/* Alternate Interrupt Location (AIL) */ -enum { - AIL_NONE =3D 0, - AIL_RESERVED =3D 1, - AIL_0001_8000 =3D 2, - AIL_C000_0000_0000_4000 =3D 3, -}; - /*************************************************************************= ****/ =20 #define is_isa300(ctx) (!!(ctx->insns_flags2 & PPC2_ISA300)) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index b8881c0f85..9ff316767c 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -136,25 +136,107 @@ static int powerpc_reset_wakeup(CPUState *cs, CPUPPC= State *env, int excp, return POWERPC_EXCP_RESET; } =20 -static uint64_t ppc_excp_vector_offset(CPUState *cs, int ail) +/* + * AIL - Alternate Interrupt Location, a mode that allows interrupts to be + * taken with the MMU on, and which uses an alternate location (e.g., so t= he + * kernel/hv can map the vectors there with an effective address). + * + * An interrupt is considered to be taken "with AIL" or "AIL applies" if t= hey + * are delivered in this way. AIL requires the LPCR to be set to enable th= is + * mode, and a number of conditions have to be true for AIL to apply. + * + * First of all, SRESET, MCE, and HMI are always delivered without AIL, + * because they are specifically want to be in real mode (e.g., MCE might + * be signaling a SLB multi-hit which requires SLB flush before the MMU can + * be enabled). + * + * After that, behaviour depends on the current MSR[IR], MSR[DR], MSR[HV],= and + * whether or not the interrupt changes MSR[HV] from 0 to 1, and the curre= nt + * radix mode (LPCR[HR]). + * + * POWER8, POWER9 with LPCR[HR]=3D0 + * | LPCR[AIL] | MSR[IR||DR] | MSR[HV] | new MSR[HV] | AIL | + * +-----------+-------------+---------+-------------+-----+ + * | a | 00/01/10 | x | x | 0 | + * | a | 11 | 0 | 1 | 0 | + * | a | 11 | 1 | 1 | a | + * | a | 11 | 0 | 0 | a | + * +-------------------------------------------------------+ + * + * POWER9 with LPCR[HR]=3D1 + * | LPCR[AIL] | MSR[IR||DR] | MSR[HV] | new MSR[HV] | AIL | + * +-----------+-------------+---------+-------------+-----+ + * | a | 00/01/10 | x | x | 0 | + * | a | 11 | x | x | a | + * +-------------------------------------------------------+ + * + * The difference with POWER9 being that MSR[HV] 0->1 interrupts can be + * sent to the hypervisor in AIL mode if the guest is radix (LPCR[HR]=3D1). + */ +static inline void ppc_excp_apply_ail(PowerPCCPU *cpu, int excp_model, int= excp, + target_ulong msr, + target_ulong *new_msr, + target_ulong *vector) { - uint64_t offset =3D 0; +#if defined(TARGET_PPC64) + CPUPPCState *env =3D &cpu->env; + bool mmu_all_on =3D ((msr >> MSR_IR) & 1) && ((msr >> MSR_DR) & 1); + bool hv_escalation =3D !(msr & MSR_HVB) && (*new_msr & MSR_HVB); + int ail =3D 0; + + if (excp =3D=3D POWERPC_EXCP_MCHECK || + excp =3D=3D POWERPC_EXCP_RESET || + excp =3D=3D POWERPC_EXCP_HV_MAINT) { + /* SRESET, MCE, HMI never apply AIL */ + return; + } =20 - switch (ail) { - case AIL_NONE: - break; - case AIL_0001_8000: - offset =3D 0x18000; - break; - case AIL_C000_0000_0000_4000: - offset =3D 0xc000000000004000ull; - break; - default: - cpu_abort(cs, "Invalid AIL combination %d\n", ail); - break; + if (excp_model =3D=3D POWERPC_EXCP_POWER8 || + excp_model =3D=3D POWERPC_EXCP_POWER9) { + if (!mmu_all_on) { + /* AIL only works if MSR[IR] and MSR[DR] are both enabled. */ + return; + } + if (hv_escalation && !(env->spr[SPR_LPCR] & LPCR_HR)) { + /* + * AIL does not work if there is a MSR[HV] 0->1 transition and= the + * partition is in HPT mode. For radix guests, such interrupts= are + * allowed to be delivered to the hypervisor in ail mode. + */ + return; + } + + ail =3D (env->spr[SPR_LPCR] & LPCR_AIL) >> LPCR_AIL_SHIFT; + if (ail !=3D 2 && ail !=3D 3) { + /* AIL=3D1 is reserved */ + return; + } + } else { + /* Other processors do not support AIL */ + return; } =20 - return offset; + /* + * AIL applies, so the new MSR gets IR and DR set, and an offset appli= ed + * to the new IP. + */ + *new_msr |=3D (1 << MSR_IR) | (1 << MSR_DR); + + if (excp !=3D POWERPC_EXCP_SYSCALL_VECTORED) { + if (ail =3D=3D 2) { + *vector |=3D 0x0000000000018000ull; + } else if (ail =3D=3D 3) { + *vector |=3D 0xc000000000004000ull; + } + } else { + /* scv AIL is a little different */ + if (ail =3D=3D 3) { + /* Un-apply the base offset */ + *vector &=3D ~0x0000000000017000ull; + *vector |=3D 0xc000000000003000ull; + } + } +#endif } =20 static inline void powerpc_set_excp_state(PowerPCCPU *cpu, @@ -197,7 +279,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int ex= cp_model, int excp) CPUState *cs =3D CPU(cpu); CPUPPCState *env =3D &cpu->env; target_ulong msr, new_msr, vector; - int srr0, srr1, asrr0, asrr1, lev =3D -1, ail; + int srr0, srr1, asrr0, asrr1, lev =3D -1; bool lpes0; =20 qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx @@ -238,25 +320,16 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int = excp_model, int excp) * * On anything else, we behave as if LPES0 is 1 * (externals don't alter MSR:HV) - * - * AIL is initialized here but can be cleared by - * selected exceptions */ #if defined(TARGET_PPC64) if (excp_model =3D=3D POWERPC_EXCP_POWER7 || excp_model =3D=3D POWERPC_EXCP_POWER8 || excp_model =3D=3D POWERPC_EXCP_POWER9) { lpes0 =3D !!(env->spr[SPR_LPCR] & LPCR_LPES0); - if (excp_model !=3D POWERPC_EXCP_POWER7) { - ail =3D (env->spr[SPR_LPCR] & LPCR_AIL) >> LPCR_AIL_SHIFT; - } else { - ail =3D 0; - } } else #endif /* defined(TARGET_PPC64) */ { lpes0 =3D true; - ail =3D 0; } =20 /* @@ -315,7 +388,6 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int ex= cp_model, int excp) */ new_msr |=3D (target_ulong)MSR_HVB; } - ail =3D 0; =20 /* machine check exceptions don't have ME set */ new_msr &=3D ~((target_ulong)1 << MSR_ME); @@ -519,7 +591,6 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int ex= cp_model, int excp) "exception %d with no HV support\n", excp); } } - ail =3D 0; break; case POWERPC_EXCP_DSEG: /* Data segment exception = */ case POWERPC_EXCP_ISEG: /* Instruction segment exception = */ @@ -790,24 +861,6 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int e= xcp_model, int excp) } #endif =20 - /* - * AIL only works if MSR[IR] and MSR[DR] are both enabled. - */ - if (!((msr >> MSR_IR) & 1) || !((msr >> MSR_DR) & 1)) { - ail =3D 0; - } - - /* - * AIL does not work if there is a MSR[HV] 0->1 transition and the - * partition is in HPT mode. For radix guests, such interrupts are - * allowed to be delivered to the hypervisor in ail mode. - */ - if ((new_msr & MSR_HVB) && !(msr & MSR_HVB)) { - if (!(env->spr[SPR_LPCR] & LPCR_HR)) { - ail =3D 0; - } - } - vector =3D env->excp_vectors[excp]; if (vector =3D=3D (target_ulong)-1ULL) { cpu_abort(cs, "Raised an exception without defined vector %d\n", @@ -848,23 +901,8 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int e= xcp_model, int excp) /* Save MSR */ env->spr[srr1] =3D msr; =20 - /* Handle AIL */ - if (ail) { - new_msr |=3D (1 << MSR_IR) | (1 << MSR_DR); - vector |=3D ppc_excp_vector_offset(cs, ail); - } - #if defined(TARGET_PPC64) } else { - /* scv AIL is a little different */ - if (ail) { - new_msr |=3D (1 << MSR_IR) | (1 << MSR_DR); - } - if (ail =3D=3D AIL_C000_0000_0000_4000) { - vector |=3D 0xc000000000003000ull; - } else { - vector |=3D 0x0000000000017000ull; - } vector +=3D lev * 0x20; =20 env->lr =3D env->nip; @@ -872,6 +910,9 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int ex= cp_model, int excp) #endif } =20 + /* This can update new_msr and vector if AIL applies */ + ppc_excp_apply_ail(cpu, excp_model, excp, msr, &new_msr, &vector); + powerpc_set_excp_state(cpu, vector, new_msr); } =20 diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.= inc index 70f9b9b150..a82d9ed647 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -3457,7 +3457,7 @@ static void init_excp_POWER9(CPUPPCState *env) =20 #if !defined(CONFIG_USER_ONLY) env->excp_vectors[POWERPC_EXCP_HVIRT] =3D 0x00000EA0; - env->excp_vectors[POWERPC_EXCP_SYSCALL_VECTORED] =3D 0x00000000; + env->excp_vectors[POWERPC_EXCP_SYSCALL_VECTORED] =3D 0x00017000; #endif } =20 --=20 2.23.0 From nobody Sun May 19 05:50:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1618370900; cv=none; d=zohomail.com; s=zohoarc; b=S3Cy/dJycq71qT6eVEJjU1l+fJuvl1/Hwgs+rEhWV0FVxMf71LGFLm8cxCygDxHW4XGnL0QWFNFZ1/s89+lW7eNFenHx0+fSsj6VxNokLqezG0qR7/cuCWJ+nOBY/qJ+a8B3AWLD+j/iLrjJa45Pk9qMbH5GYfW5hLxidLme6mk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618370900; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ISqCfvePphae68szf7yjOoOBLEqDPA6tRjmQMiXccUg=; b=bLdPklwv5rTPmXrLt/XiPlzIYOUycoH2gogbDSbt9TTz1AU67WcMfT+VkTvgvakKJbcmQpcgrF0FihtfMOzmMGkbBhFzTIRljxOzGKYmC7FcrI5nvgo8hffIEg4JBHTuKPWU3McZqLh+elA6xWFCPButHCU4Rm5/0Mr7coGgk7w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1618370900572331.24464755739143; Tue, 13 Apr 2021 20:28:20 -0700 (PDT) Received: from localhost ([::1]:55928 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lWWCR-0002bU-EV for importer@patchew.org; Tue, 13 Apr 2021 23:28:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52042) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lWW8G-0006qN-KQ; Tue, 13 Apr 2021 23:24:02 -0400 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]:51198) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lWW8D-0003ce-Vp; Tue, 13 Apr 2021 23:24:00 -0400 Received: by mail-pj1-x102d.google.com with SMTP id u11so5880000pjr.0; Tue, 13 Apr 2021 20:23:57 -0700 (PDT) Received: from bobo.ibm.com (193-116-90-211.tpgi.com.au. [193.116.90.211]) by smtp.gmail.com with ESMTPSA id fa6sm3407435pjb.2.2021.04.13.20.23.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Apr 2021 20:23:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ISqCfvePphae68szf7yjOoOBLEqDPA6tRjmQMiXccUg=; b=dEjuH7Kv1vX/INPFkZ6OOvaqS2ojy7pcr9D91bozaijHJs0DWUo7GvXZqiWROa0aU9 IMcPz9PWrLN9H3/rCciIRnApADBzwJUDB44V26fY55Cj2b0xxLJfSLUZ197mKF1WwEGC ipxTlJ1RE/MwqNHDERh3bF0rprkNeEk8b58N461lbb4QkLgUyCGVf8EWotEsVhdGqeh3 jN1fiD36sEXBKVHi9JMi05KVGt/ck7NRtwvk68K4S8pcuwqZ4ueyKVotvr02fnvgcfBU wUV5ds2dBjv3Y8pWOyIOS/Gli7va1rDcIja3RnYAk8XmEhV9fAcS2/O5oX+GzFAfnXev Wgow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ISqCfvePphae68szf7yjOoOBLEqDPA6tRjmQMiXccUg=; b=A1a3Nkhhq4PPqQTmrDl6CCer0mD3Hlc6aou/NtAzeDN1JzCnAGFgZ3UsHK7rMbH7Vd ks2Qgkwq6b7PvVPdakJwm91Mg7aM+leu4/swFnrLquAmzS/d+E8nTRRhG9poVgKQurap i67i1cMCN14lhvbIjN0P7qLLRcH6bVkIN0JqQunB0qV0IknAlweGipJt5wOnCv6mAZhr MvhZMYN61QXn8x1CR8esoHd2IRJnSyP5+Bodc0x8KnznnGGhKpsqnWSGt0TXpkIHQLls y8LmQ1jbVg9czZiacUwwFRYe+U8Ph9l4PBzGM1QitmnYUG9ZoZdkQ3wPhH1DgCJpTeo0 jtmw== X-Gm-Message-State: AOAM532gWgEEZR3cXLYU4OPEcA6+x/lMAJMKVAn1Qa/UwFbdZMea8MD7 45Js1waE+CWE6Z9nSM59gHYKwJiiK2k= X-Google-Smtp-Source: ABdhPJwk16TZH/scE1KWuofz/i6eKL9Hnfb9edIBTafhejQlXExRtfLdjDqVC1ldqA8meKYQyn84Jw== X-Received: by 2002:a17:90b:4a50:: with SMTP id lb16mr1078518pjb.229.1618370636315; Tue, 13 Apr 2021 20:23:56 -0700 (PDT) From: Nicholas Piggin To: qemu-ppc@nongnu.org Subject: [RFC PATCH 2/2] target/ppc: Add POWER10 exception model Date: Wed, 14 Apr 2021 13:23:43 +1000 Message-Id: <20210414032343.1720010-3-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20210414032343.1720010-1-npiggin@gmail.com> References: <20210414032343.1720010-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=npiggin@gmail.com; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fabiano Rosas , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-devel@nongnu.org, Nicholas Piggin , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" POWER10 adds a new bit that modifies interrupt behaviour, LPCR[HAIL], and it removes support for the LPCR[AIL]=3D0b10 mode. Signed-off-by: Nicholas Piggin Reviewed-by: C=C3=A9dric Le Goater Tested-by: C=C3=A9dric Le Goater --- hw/ppc/spapr_hcall.c | 7 +++++- target/ppc/cpu-qom.h | 2 ++ target/ppc/cpu.h | 5 ++-- target/ppc/excp_helper.c | 43 +++++++++++++++++++++++++++++++++ target/ppc/translate.c | 3 ++- target/ppc/translate_init.c.inc | 2 +- 6 files changed, 57 insertions(+), 5 deletions(-) diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index 2fbe04a689..6802cd4dc8 100644 --- a/hw/ppc/spapr_hcall.c +++ b/hw/ppc/spapr_hcall.c @@ -1396,7 +1396,12 @@ static target_ulong h_set_mode_resource_addr_trans_m= ode(PowerPCCPU *cpu, } =20 if (mflags =3D=3D 1) { - /* AIL=3D1 is reserved */ + /* AIL=3D1 is reserved in POWER8/POWER9 */ + return H_UNSUPPORTED_FLAG; + } + + if (mflags =3D=3D 2 && (pcc->insns_flags2 & PPC2_ISA310)) { + /* AIL=3D2 is also reserved in POWER10 (ISA v3.1) */ return H_UNSUPPORTED_FLAG; } =20 diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index 118baf8d41..06b6571bc9 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -116,6 +116,8 @@ enum powerpc_excp_t { POWERPC_EXCP_POWER8, /* POWER9 exception model */ POWERPC_EXCP_POWER9, + /* POWER10 exception model */ + POWERPC_EXCP_POWER10, }; =20 /*************************************************************************= ****/ diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 5200a16d23..9d35cdfa92 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -354,10 +354,11 @@ typedef struct ppc_v3_pate_t { #define LPCR_PECE_U_SHIFT (63 - 19) #define LPCR_PECE_U_MASK (0x7ull << LPCR_PECE_U_SHIFT) #define LPCR_HVEE PPC_BIT(17) /* Hypervisor Virt Exit Enable */ -#define LPCR_RMLS_SHIFT (63 - 37) +#define LPCR_RMLS_SHIFT (63 - 37) /* RMLS (removed in ISA v3.0) */ #define LPCR_RMLS (0xfull << LPCR_RMLS_SHIFT) +#define LPCR_HAIL PPC_BIT(37) /* ISA v3.1 HV AIL=3D3 equivalent */ #define LPCR_ILE PPC_BIT(38) -#define LPCR_AIL_SHIFT (63 - 40) /* Alternate interrupt location */ +#define LPCR_AIL_SHIFT (63 - 40) /* Alternate interrupt location */ #define LPCR_AIL (3ull << LPCR_AIL_SHIFT) #define LPCR_UPRT PPC_BIT(41) /* Use Process Table */ #define LPCR_EVIRT PPC_BIT(42) /* Enhanced Virtualisation */ diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 9ff316767c..19931361a0 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -172,6 +172,26 @@ static int powerpc_reset_wakeup(CPUState *cs, CPUPPCSt= ate *env, int excp, * * The difference with POWER9 being that MSR[HV] 0->1 interrupts can be * sent to the hypervisor in AIL mode if the guest is radix (LPCR[HR]=3D1). + * This is good for performance but allows the guest to influence the + * AIL of hypervisor interrupts using its MSR, and also the hypervisor + * must disallow guest interrupts (MSR[HV] 0->0) from using AIL if the + * hypervisor does not want to use AIL for its MSR[HV] 0->1 interrupts. + * + * POWER10 addresses those issues with a new LPCR[HAIL] bit that is + * applied to interrupt that begin execution with MSR[HV]=3D1 (so both + * MSR[HV] 0->1 and 1->1). + * + * HAIL=3D1 is equivalent to AIL=3D3, for interrupts delivered with MSR[HV= ]=3D1. + * + * POWER10 behaviour is + * | LPCR[AIL] | LPCR[HAIL] | MSR[IR||DR] | MSR[HV] | new MSR[HV] | AIL | + * +-----------+------------+-------------+---------+-------------+-----+ + * | a | h | 00/01/10 | 0 | 0 | 0 | + * | a | h | 11 | 0 | 0 | a | + * | a | h | x | 0 | 1 | h | + * | a | h | 00/01/10 | 1 | 1 | 0 | + * | a | h | 11 | 1 | 1 | h | + * +--------------------------------------------------------------------+ */ static inline void ppc_excp_apply_ail(PowerPCCPU *cpu, int excp_model, int= excp, target_ulong msr, @@ -211,6 +231,29 @@ static inline void ppc_excp_apply_ail(PowerPCCPU *cpu,= int excp_model, int excp, /* AIL=3D1 is reserved */ return; } + + } else if (excp_model =3D=3D POWERPC_EXCP_POWER10) { + if (!mmu_all_on && !hv_escalation) { + /* + * AIL works for HV interrupts even with guest MSR[IR/DR] disa= bled. + * Guest->guest and HV->HV interrupts do require MMU on. + */ + return; + } + + if (*new_msr & MSR_HVB) { + if (!(env->spr[SPR_LPCR] & LPCR_HAIL)) { + /* HV interrupts depend on LPCR[HAIL] */ + return; + } + ail =3D 3; /* HAIL=3D1 gives AIL=3D3 behaviour for HV interrup= ts */ + } else { + ail =3D (env->spr[SPR_LPCR] & LPCR_AIL) >> LPCR_AIL_SHIFT; + } + if (ail !=3D 3) { + /* AIL=3D1 and AIL=3D2 are reserved */ + return; + } } else { /* Other processors do not support AIL */ return; diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 0984ce637b..e9ed001229 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7731,7 +7731,8 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, int fl= ags) #if defined(TARGET_PPC64) if (env->excp_model =3D=3D POWERPC_EXCP_POWER7 || env->excp_model =3D=3D POWERPC_EXCP_POWER8 || - env->excp_model =3D=3D POWERPC_EXCP_POWER9) { + env->excp_model =3D=3D POWERPC_EXCP_POWER9 || + env->excp_model =3D=3D POWERPC_EXCP_POWER10) { qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n= ", env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); } diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.= inc index a82d9ed647..76d82cc2f6 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -9317,7 +9317,7 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) pcc->radix_page_info =3D &POWER10_radix_page_info; pcc->lrg_decr_bits =3D 56; #endif - pcc->excp_model =3D POWERPC_EXCP_POWER9; + pcc->excp_model =3D POWERPC_EXCP_POWER10; pcc->bus_model =3D PPC_FLAGS_INPUT_POWER9; pcc->bfd_mach =3D bfd_mach_ppc64; pcc->flags =3D POWERPC_FLAG_VRE | POWERPC_FLAG_SE | --=20 2.23.0