From nobody Tue Feb 10 03:39:54 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=huawei.com ARC-Seal: i=1; a=rsa-sha256; t=1618210677; cv=none; d=zohomail.com; s=zohoarc; b=Czg6SdzVapURsOaXOCRXF7hnvAbVWg3FFj1ALbn08UsUzx+qxDfGZIv+LtzJg7T53z4UhutMs2l3A5lmJ2zkfULznXXsAR1Y9+mAh7WP7oazFZFcK7O2uYc5JQCOdfV2rhEJisFmQeBaKYHRo/KAdXrhXM664Pk6iL3hBcQ9YfE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618210677; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=vBB17VcQcn5F9WUCieE+fqHhEWl2K9nz6v95NOWz0Eo=; b=elrFTpKT7xnUf6jlAPHZtOY73BxtZKQIpyXtkAVnjstyGWX+GCZZ0Z9ZfidhQ9uTz+8O4dc1DB2YIYbgBKYoesJR8LjSexQs64h0TfAZRwFA5fEbpezpOfLruu1TPGJW0XYTQSHUOLDTEGPKDW8INgCosUzxrDFeWuRZ3pKuSx0= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 161821067714225.453035329309955; Sun, 11 Apr 2021 23:57:57 -0700 (PDT) Received: from localhost ([::1]:57510 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lVqWB-0004OZ-35 for importer@patchew.org; Mon, 12 Apr 2021 02:57:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40654) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lVqS6-0007gH-NM; Mon, 12 Apr 2021 02:53:42 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:5026) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lVqS3-0004Wt-Mb; Mon, 12 Apr 2021 02:53:42 -0400 Received: from DGGEMS412-HUB.china.huawei.com (unknown [172.30.72.59]) by szxga06-in.huawei.com (SkyGuard) with ESMTP id 4FJfXx6zC5zjYsL; Mon, 12 Apr 2021 14:51:45 +0800 (CST) Received: from huawei.com (10.174.186.236) by DGGEMS412-HUB.china.huawei.com (10.3.19.212) with Microsoft SMTP Server id 14.3.498.0; Mon, 12 Apr 2021 14:53:27 +0800 From: Yifei Jiang To: , Subject: [PATCH RFC v5 05/12] target/riscv: Implement kvm_arch_put_registers Date: Mon, 12 Apr 2021 14:52:39 +0800 Message-ID: <20210412065246.1853-6-jiangyifei@huawei.com> X-Mailer: git-send-email 2.26.2.windows.1 In-Reply-To: <20210412065246.1853-1-jiangyifei@huawei.com> References: <20210412065246.1853-1-jiangyifei@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.174.186.236] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.32; envelope-from=jiangyifei@huawei.com; helo=szxga06-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bin.meng@windriver.com, sagark@eecs.berkeley.edu, kvm@vger.kernel.org, libvir-list@redhat.com, kbastian@mail.uni-paderborn.de, anup.patel@wdc.com, yinyipeng1@huawei.com, Alistair.Francis@wdc.com, Yifei Jiang , kvm-riscv@lists.infradead.org, palmer@dabbelt.com, fanliang@huawei.com, wu.wubin@huawei.com, zhang.zhanghailiang@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Put GPR CSR and FP registers to kvm by KVM_SET_ONE_REG ioctl Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin Reviewed-by: Alistair Francis --- target/riscv/kvm.c | 142 ++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 141 insertions(+), 1 deletion(-) diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index 63485d7b65..9d1441952a 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -85,6 +85,31 @@ static int kvm_riscv_get_regs_core(CPUState *cs) return ret; } =20 +static int kvm_riscv_put_regs_core(CPUState *cs) +{ + int ret =3D 0; + int i; + target_ulong reg; + CPURISCVState *env =3D &RISCV_CPU(cs)->env; + + reg =3D env->pc; + ret =3D kvm_set_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®); + if (ret) { + return ret; + } + + for (i =3D 1; i < 32; i++) { + __u64 id =3D kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, i); + reg =3D env->gpr[i]; + ret =3D kvm_set_one_reg(cs, id, ®); + if (ret) { + return ret; + } + } + + return ret; +} + static int kvm_riscv_get_regs_csr(CPUState *cs) { int ret =3D 0; @@ -148,6 +173,70 @@ static int kvm_riscv_get_regs_csr(CPUState *cs) return ret; } =20 +static int kvm_riscv_put_regs_csr(CPUState *cs) +{ + int ret =3D 0; + target_ulong reg; + CPURISCVState *env =3D &RISCV_CPU(cs)->env; + + reg =3D env->mstatus; + ret =3D kvm_set_one_reg(cs, RISCV_CSR_REG(env, sstatus), ®); + if (ret) { + return ret; + } + + reg =3D env->mie; + ret =3D kvm_set_one_reg(cs, RISCV_CSR_REG(env, sie), ®); + if (ret) { + return ret; + } + + reg =3D env->stvec; + ret =3D kvm_set_one_reg(cs, RISCV_CSR_REG(env, stvec), ®); + if (ret) { + return ret; + } + + reg =3D env->sscratch; + ret =3D kvm_set_one_reg(cs, RISCV_CSR_REG(env, sscratch), ®); + if (ret) { + return ret; + } + + reg =3D env->sepc; + ret =3D kvm_set_one_reg(cs, RISCV_CSR_REG(env, sepc), ®); + if (ret) { + return ret; + } + + reg =3D env->scause; + ret =3D kvm_set_one_reg(cs, RISCV_CSR_REG(env, scause), ®); + if (ret) { + return ret; + } + + reg =3D env->sbadaddr; + ret =3D kvm_set_one_reg(cs, RISCV_CSR_REG(env, stval), ®); + if (ret) { + return ret; + } + + reg =3D env->mip; + ret =3D kvm_set_one_reg(cs, RISCV_CSR_REG(env, sip), ®); + if (ret) { + return ret; + } + + reg =3D env->satp; + ret =3D kvm_set_one_reg(cs, RISCV_CSR_REG(env, satp), ®); + if (ret) { + return ret; + } + + return ret; +} + + static int kvm_riscv_get_regs_fp(CPUState *cs) { int ret =3D 0; @@ -181,6 +270,40 @@ static int kvm_riscv_get_regs_fp(CPUState *cs) return ret; } =20 +static int kvm_riscv_put_regs_fp(CPUState *cs) +{ + int ret =3D 0; + int i; + CPURISCVState *env =3D &RISCV_CPU(cs)->env; + + if (riscv_has_ext(env, RVD)) { + uint64_t reg; + for (i =3D 0; i < 32; i++) { + reg =3D env->fpr[i]; + ret =3D kvm_set_one_reg(cs, RISCV_FP_D_REG(env, i), ®); + if (ret) { + return ret; + } + } + return ret; + } + + if (riscv_has_ext(env, RVF)) { + uint32_t reg; + for (i =3D 0; i < 32; i++) { + reg =3D env->fpr[i]; + ret =3D kvm_set_one_reg(cs, RISCV_FP_F_REG(env, i), ®); + if (ret) { + return ret; + } + } + return ret; + } + + return ret; +} + + const KVMCapabilityInfo kvm_arch_required_capabilities[] =3D { KVM_CAP_LAST_INFO }; @@ -209,7 +332,24 @@ int kvm_arch_get_registers(CPUState *cs) =20 int kvm_arch_put_registers(CPUState *cs, int level) { - return 0; + int ret =3D 0; + + ret =3D kvm_riscv_put_regs_core(cs); + if (ret) { + return ret; + } + + ret =3D kvm_riscv_put_regs_csr(cs); + if (ret) { + return ret; + } + + ret =3D kvm_riscv_put_regs_fp(cs); + if (ret) { + return ret; + } + + return ret; } =20 int kvm_arch_release_virq_post(int virq) --=20 2.19.1