From nobody Mon Apr 29 02:48:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1617954842; cv=none; d=zohomail.com; s=zohoarc; b=QoMLC3YhAtwwvCwqe40e3CbOjKxWGjdK+nxrEVoSOeP0T+og8twI4VTzFSLYSbYEIophcbM7dEEFg8Kq0OF1a6JON1HK/fvjxEmvvyAF6GFD3AoMmOppuoidXWwHmre+uR2vAefpxzMvgfbWXkNbGay/g1Jb7Az6FU2qWCK36r0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1617954842; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=0Vj5CWsSu/W8FSTMegXTyUHo/P3KRyVPhnktNdN7TYI=; b=DSgSjVGjzMrUG05qVAWTRTqaNlQC2YQnp017PW10f51Eia/DJxpkszeIS9kzarxviAJCqe+wFvZEZxBz5a2G0UbBkGozdV1rKebYEcI76Vt5SU9wjis9QdFOOJXLDsbTBeSw8x4WQiIeRwyHTrLAAyJA9u/EJbrrHQfBryumU1Q= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1617954842563964.3110948444162; Fri, 9 Apr 2021 00:54:02 -0700 (PDT) Received: from localhost ([::1]:42356 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lUlxp-0007RZ-Ja for importer@patchew.org; Fri, 09 Apr 2021 03:54:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37552) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lUlte-0002H1-Ij; Fri, 09 Apr 2021 03:49:42 -0400 Received: from mail142-31.mail.alibaba.com ([198.11.142.31]:13317) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lUlta-0003hc-Ms; Fri, 09 Apr 2021 03:49:42 -0400 Received: from localhost.localdomain(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.JxL3BOG_1617954563) by smtp.aliyun-inc.com(10.147.40.7); Fri, 09 Apr 2021 15:49:24 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07439654|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_regular_dialog|0.14363-0.000421398-0.855948; FP=8842789452891429954|1|1|1|0|-1|-1|-1; HT=ay29a033018047190; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=6; RT=6; SR=0; TI=SMTPD_---.JxL3BOG_1617954563; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC PATCH 01/11] target/riscv: Add CLIC CSR mintstatus Date: Fri, 9 Apr 2021 15:48:47 +0800 Message-Id: <20210409074857.166082-2-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210409074857.166082-1-zhiwei_liu@c-sky.com> References: <20210409074857.166082-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=198.11.142.31; envelope-from=zhiwei_liu@c-sky.com; helo=mail142-31.mail.alibaba.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, Alistair.Francis@wdc.com, LIU Zhiwei , wxy194768@alibaba-inc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" CSR mintstatus holds the active interrupt level for each supported privilege mode. sintstatus, and user, uintstatus, provide restricted views of mintstatus. Signed-off-by: LIU Zhiwei --- target/riscv/cpu.h | 2 ++ target/riscv/cpu_bits.h | 11 +++++++++++ target/riscv/csr.c | 26 ++++++++++++++++++++++++++ 3 files changed, 39 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0a33d387ba..1a44ca62c7 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -159,6 +159,7 @@ struct CPURISCVState { target_ulong mip; =20 uint32_t miclaim; + uint32_t mintstatus; /* clic-spec */ =20 target_ulong mie; target_ulong mideleg; @@ -243,6 +244,7 @@ struct CPURISCVState { =20 /* Fields from here on are preserved across CPU reset. */ QEMUTimer *timer; /* Internal timer */ + void *clic; /* clic interrupt controller */ }; =20 OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass, diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index caf4599207..c4ce6ec3d9 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -165,6 +165,7 @@ #define CSR_MCAUSE 0x342 #define CSR_MTVAL 0x343 #define CSR_MIP 0x344 +#define CSR_MINTSTATUS 0x346 /* clic-spec-draft */ =20 /* Legacy Machine Trap Handling (priv v1.9.1) */ #define CSR_MBADADDR 0x343 @@ -183,6 +184,7 @@ #define CSR_SCAUSE 0x142 #define CSR_STVAL 0x143 #define CSR_SIP 0x144 +#define CSR_SINTSTATUS 0x146 /* clic-spec-draft */ =20 /* Legacy Supervisor Trap Handling (priv v1.9.1) */ #define CSR_SBADADDR 0x143 @@ -585,6 +587,15 @@ #define SIP_STIP MIP_STIP #define SIP_SEIP MIP_SEIP =20 +/* mintstatus */ +#define MINTSTATUS_MIL 0xff000000 /* mil[7:0] */ +#define MINTSTATUS_SIL 0x0000ff00 /* sil[7:0] */ +#define MINTSTATUS_UIL 0x000000ff /* uil[7:0] */ + +/* sintstatus */ +#define SINTSTATUS_SIL 0x0000ff00 /* sil[7:0] */ +#define SINTSTATUS_UIL 0x000000ff /* uil[7:0] */ + /* MIE masks */ #define MIE_SEIE (1 << IRQ_S_EXT) #define MIE_UEIE (1 << IRQ_U_EXT) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d2585395bf..320b18ab60 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -188,6 +188,12 @@ static int pmp(CPURISCVState *env, int csrno) { return -!riscv_feature(env, RISCV_FEATURE_PMP); } + +static int clic(CPURISCVState *env, int csrno) +{ + return !!env->clic; +} + #endif =20 /* User Floating-Point CSRs */ @@ -734,6 +740,12 @@ static int rmw_mip(CPURISCVState *env, int csrno, targ= et_ulong *ret_value, return 0; } =20 +static int read_mintstatus(CPURISCVState *env, int csrno, target_ulong *va= l) +{ + *val =3D env->mintstatus; + return 0; +} + /* Supervisor Trap Setup */ static int read_sstatus(CPURISCVState *env, int csrno, target_ulong *val) { @@ -893,6 +905,13 @@ static int rmw_sip(CPURISCVState *env, int csrno, targ= et_ulong *ret_value, return ret; } =20 +static int read_sintstatus(CPURISCVState *env, int csrno, target_ulong *va= l) +{ + target_ulong mask =3D SINTSTATUS_SIL | SINTSTATUS_UIL; + *val =3D env->mintstatus & mask; + return 0; +} + /* Supervisor Protection and Translation */ static int read_satp(CPURISCVState *env, int csrno, target_ulong *val) { @@ -1644,5 +1663,12 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_MHPMCOUNTER29H] =3D { "mhpmcounter29h", any32, read_zero }, [CSR_MHPMCOUNTER30H] =3D { "mhpmcounter30h", any32, read_zero }, [CSR_MHPMCOUNTER31H] =3D { "mhpmcounter31h", any32, read_zero }, + + /* Machine Mode Core Level Interrupt Controller */ + [CSR_MINTSTATUS] =3D { "mintstatus", clic, read_mintstatus }, + + /* Supervisor Mode Core Level Interrupt Controller */ + [CSR_SINTSTATUS] =3D { "sintstatus", clic, read_sintstatus }, + #endif /* !CONFIG_USER_ONLY */ }; --=20 2.25.1 From nobody Mon Apr 29 02:48:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1617954939; cv=none; d=zohomail.com; s=zohoarc; b=TuaEIpnvcEOv4A3v3sOSDu0eU47f9Qfo1o2atlch4QioSJEDscCDCWhGkg5cLMkg80MVEmEUaRogBYkhbiCelASIqFo18l5E+VBW9oKZRyKI02JezGQwA/wVEgU02KliJzkn7OjV2rguuveJz8otNabdQu/eFBwE8OxthWm7np4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1617954939; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=bwsBqT8xuZf8yUCA0vcCas+/xhiSWeRaotyPh8haIPA=; b=CX6MJ6mLjcN8E7utiLIXPe+7G1lXaVEgAofxy3Tr1Yg112+xglc0DfnritQ+Z0EoFl8NN4y/9FRgHFca5UeEAeDPLLFSzmUDoEGqMoYuFrAsh+pv62NDH7EXAHlmimLrvUg2zhtJkyYJEg8P6LQT5I1i2Cqe9qXQgeNhqKTuZ8c= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1617954939670342.2421657011123; Fri, 9 Apr 2021 00:55:39 -0700 (PDT) Received: from localhost ([::1]:49804 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lUlzO-00022j-L9 for importer@patchew.org; Fri, 09 Apr 2021 03:55:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37642) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lUlti-0002Pk-PU; Fri, 09 Apr 2021 03:49:46 -0400 Received: from mail142-22.mail.alibaba.com ([198.11.142.22]:31561) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lUltb-0003hJ-2R; Fri, 09 Apr 2021 03:49:46 -0400 Received: from localhost.localdomain(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.JxL3BOG_1617954563) by smtp.aliyun-inc.com(10.147.40.7); Fri, 09 Apr 2021 15:49:24 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07452568|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.246224-0.00021039-0.753566; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047187; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=6; RT=6; SR=0; TI=SMTPD_---.JxL3BOG_1617954563; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC PATCH 02/11] target/riscv: Update CSR xintthresh in CLIC mode Date: Fri, 9 Apr 2021 15:48:48 +0800 Message-Id: <20210409074857.166082-3-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210409074857.166082-1-zhiwei_liu@c-sky.com> References: <20210409074857.166082-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=198.11.142.22; envelope-from=zhiwei_liu@c-sky.com; helo=mail142-22.mail.alibaba.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, Alistair.Francis@wdc.com, LIU Zhiwei , wxy194768@alibaba-inc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The interrupt-level threshold (xintthresh) CSR holds an 8-bit field for the threshold level of the associated privilege mode. For horizontal interrupts, only the ones with higher interrupt levels than the threshold level are allowed to preempt. Signed-off-by: LIU Zhiwei Reviewed-by: Frank Chang --- target/riscv/cpu.h | 2 ++ target/riscv/cpu_bits.h | 2 ++ target/riscv/csr.c | 28 ++++++++++++++++++++++++++++ 3 files changed, 32 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 1a44ca62c7..a5eab26a69 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -160,6 +160,7 @@ struct CPURISCVState { =20 uint32_t miclaim; uint32_t mintstatus; /* clic-spec */ + target_ulong mintthresh; /* clic-spec */ =20 target_ulong mie; target_ulong mideleg; @@ -173,6 +174,7 @@ struct CPURISCVState { target_ulong stvec; target_ulong sepc; target_ulong scause; + target_ulong sintthresh; /* clic-spec */ =20 target_ulong mtvec; target_ulong mepc; diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index c4ce6ec3d9..9447801d22 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -166,6 +166,7 @@ #define CSR_MTVAL 0x343 #define CSR_MIP 0x344 #define CSR_MINTSTATUS 0x346 /* clic-spec-draft */ +#define CSR_MINTTHRESH 0x347 /* clic-spec-draft */ =20 /* Legacy Machine Trap Handling (priv v1.9.1) */ #define CSR_MBADADDR 0x343 @@ -185,6 +186,7 @@ #define CSR_STVAL 0x143 #define CSR_SIP 0x144 #define CSR_SINTSTATUS 0x146 /* clic-spec-draft */ +#define CSR_SINTTHRESH 0x147 /* clic-spec-draft */ =20 /* Legacy Supervisor Trap Handling (priv v1.9.1) */ #define CSR_SBADADDR 0x143 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 320b18ab60..4c31364967 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -746,6 +746,18 @@ static int read_mintstatus(CPURISCVState *env, int csr= no, target_ulong *val) return 0; } =20 +static int read_mintthresh(CPURISCVState *env, int csrno, target_ulong *va= l) +{ + *val =3D env->mintthresh; + return 0; +} + +static int write_mintthresh(CPURISCVState *env, int csrno, target_ulong va= l) +{ + env->mintthresh =3D val; + return 0; +} + /* Supervisor Trap Setup */ static int read_sstatus(CPURISCVState *env, int csrno, target_ulong *val) { @@ -912,6 +924,18 @@ static int read_sintstatus(CPURISCVState *env, int csr= no, target_ulong *val) return 0; } =20 +static int read_sintthresh(CPURISCVState *env, int csrno, target_ulong *va= l) +{ + *val =3D env->sintthresh; + return 0; +} + +static int write_sintthresh(CPURISCVState *env, int csrno, target_ulong va= l) +{ + env->sintthresh =3D val; + return 0; +} + /* Supervisor Protection and Translation */ static int read_satp(CPURISCVState *env, int csrno, target_ulong *val) { @@ -1666,9 +1690,13 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { =20 /* Machine Mode Core Level Interrupt Controller */ [CSR_MINTSTATUS] =3D { "mintstatus", clic, read_mintstatus }, + [CSR_MINTTHRESH] =3D { "mintthresh", clic, read_mintthresh, + write_mintthresh }, =20 /* Supervisor Mode Core Level Interrupt Controller */ [CSR_SINTSTATUS] =3D { "sintstatus", clic, read_sintstatus }, + [CSR_SINTTHRESH] =3D { "sintthresh", clic, read_sintthresh, + write_sintthresh }, =20 #endif /* !CONFIG_USER_ONLY */ }; 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mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 161795508105128.747741239566494; Fri, 9 Apr 2021 00:58:01 -0700 (PDT) Received: from localhost ([::1]:55696 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lUm1f-0004Vi-Pm for importer@patchew.org; Fri, 09 Apr 2021 03:57:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37666) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lUltl-0002WA-5x; Fri, 09 Apr 2021 03:49:49 -0400 Received: from mail142-21.mail.alibaba.com ([198.11.142.21]:28054) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lUlta-0003hV-UY; Fri, 09 Apr 2021 03:49:48 -0400 Received: from localhost.localdomain(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.JxL3BOG_1617954563) by smtp.aliyun-inc.com(10.147.40.7); Fri, 09 Apr 2021 15:49:24 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07436282|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.0260835-0.000735125-0.973181; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047198; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=6; RT=6; SR=0; TI=SMTPD_---.JxL3BOG_1617954563; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC PATCH 03/11] hw/intc: Add CLIC device Date: Fri, 9 Apr 2021 15:48:49 +0800 Message-Id: <20210409074857.166082-4-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210409074857.166082-1-zhiwei_liu@c-sky.com> References: <20210409074857.166082-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=198.11.142.21; envelope-from=zhiwei_liu@c-sky.com; helo=mail142-21.mail.alibaba.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, Alistair.Francis@wdc.com, LIU Zhiwei , wxy194768@alibaba-inc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" The Core-Local Interrupt Controller (CLIC) provides low-latency, vectored, pre-emptive interrupts for RISC-V systems. The CLIC also supports a new Selective Hardware Vectoring feature that allow users to optimize each interrupt for either faster response or smaller code size. Signed-off-by: LIU Zhiwei --- default-configs/devices/riscv32-softmmu.mak | 1 + default-configs/devices/riscv64-softmmu.mak | 1 + hw/intc/Kconfig | 3 + hw/intc/meson.build | 1 + hw/intc/riscv_clic.c | 835 ++++++++++++++++++++ include/hw/intc/riscv_clic.h | 103 +++ target/riscv/cpu.h | 2 + 7 files changed, 946 insertions(+) create mode 100644 hw/intc/riscv_clic.c create mode 100644 include/hw/intc/riscv_clic.h diff --git a/default-configs/devices/riscv32-softmmu.mak b/default-configs/= devices/riscv32-softmmu.mak index d847bd5692..1430c30588 100644 --- a/default-configs/devices/riscv32-softmmu.mak +++ b/default-configs/devices/riscv32-softmmu.mak @@ -5,6 +5,7 @@ #CONFIG_PCI_DEVICES=3Dn CONFIG_SEMIHOSTING=3Dy CONFIG_ARM_COMPATIBLE_SEMIHOSTING=3Dy +CONFIG_RISCV_CLIC=3Dy =20 # Boards: # diff --git a/default-configs/devices/riscv64-softmmu.mak b/default-configs/= devices/riscv64-softmmu.mak index d5eec75f05..396800bbbd 100644 --- a/default-configs/devices/riscv64-softmmu.mak +++ b/default-configs/devices/riscv64-softmmu.mak @@ -5,6 +5,7 @@ #CONFIG_PCI_DEVICES=3Dn CONFIG_SEMIHOSTING=3Dy CONFIG_ARM_COMPATIBLE_SEMIHOSTING=3Dy +CONFIG_RISCV_CLIC=3Dy =20 # Boards: # diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig index f4694088a4..5bf492b48f 100644 --- a/hw/intc/Kconfig +++ b/hw/intc/Kconfig @@ -68,6 +68,9 @@ config SIFIVE_CLINT config SIFIVE_PLIC bool =20 +config RISCV_CLIC + bool + config GOLDFISH_PIC bool =20 diff --git a/hw/intc/meson.build b/hw/intc/meson.build index 1c299039f6..2aa71b6738 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -50,6 +50,7 @@ specific_ss.add(when: 'CONFIG_S390_FLIC_KVM', if_true: fi= les('s390_flic_kvm.c')) specific_ss.add(when: 'CONFIG_SH_INTC', if_true: files('sh_intc.c')) specific_ss.add(when: 'CONFIG_SIFIVE_CLINT', if_true: files('sifive_clint.= c')) specific_ss.add(when: 'CONFIG_SIFIVE_PLIC', if_true: files('sifive_plic.c'= )) +specific_ss.add(when: 'CONFIG_RISCV_CLIC', if_true: files('riscv_clic.c')) specific_ss.add(when: 'CONFIG_XICS', if_true: files('xics.c')) specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_XICS'], if_true: files('xics_kvm.c')) diff --git a/hw/intc/riscv_clic.c b/hw/intc/riscv_clic.c new file mode 100644 index 0000000000..8ad534c506 --- /dev/null +++ b/hw/intc/riscv_clic.c @@ -0,0 +1,835 @@ +/* + * RISC-V CLIC(Core Local Interrupt Controller) for QEMU. + * + * Copyright (c) 2021 T-Head Semiconductor Co., Ltd. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu/log.h" +#include "hw/sysbus.h" +#include "sysemu/qtest.h" +#include "target/riscv/cpu.h" +#include "hw/qdev-properties.h" +#include "hw/intc/riscv_clic.h" + +/* + * The 2-bit trig WARL field specifies the trigger type and polarity for e= ach + * interrupt input. Bit 1, trig[0], is defined as "edge-triggered" + * (0: level-triggered, 1: edge-triggered); while bit 2, trig[1], is defin= ed as + * "negative-edge" (0: positive-edge, 1: negative-edge). (Section 3.6) + */ + +static inline TRIG_TYPE +riscv_clic_get_trigger_type(RISCVCLICState *clic, size_t irq_offset) +{ + return (clic->clicintattr[irq_offset] >> 1) & 0x3; +} + +static inline bool +riscv_clic_is_edge_triggered(RISCVCLICState *clic, size_t irq_offset) +{ + return (clic->clicintattr[irq_offset] >> 1) & 0x1; +} + +static inline bool +riscv_clic_is_shv_interrupt(RISCVCLICState *clic, size_t irq_offset) +{ + return (clic->clicintattr[irq_offset] & 0x1) && clic->nvbits; +} + +static uint8_t +riscv_clic_get_interrupt_level(RISCVCLICState *clic, uint8_t intctl) +{ + int nlbits =3D clic->nlbits; + + uint8_t mask_il =3D ((1 << nlbits) - 1) << (8 - nlbits); + uint8_t mask_padding =3D (1 << (8 - nlbits)) - 1; + /* unused level bits are set to 1 */ + return (intctl & mask_il) | mask_padding; +} + +static uint8_t +riscv_clic_get_interrupt_priority(RISCVCLICState *clic, uint8_t intctl) +{ + int npbits =3D clic->clicintctlbits - clic->nlbits; + uint8_t mask_priority =3D ((1 << npbits) - 1) << (8 - npbits); + uint8_t mask_padding =3D (1 << (8 - npbits)) - 1; + + if (npbits < 0) { + return UINT8_MAX; + } + /* unused priority bits are set to 1 */ + return (intctl & mask_priority) | mask_padding; +} + +static void +riscv_clic_intcfg_decode(RISCVCLICState *clic, uint16_t intcfg, + uint8_t *mode, uint8_t *level, + uint8_t *priority) +{ + *mode =3D intcfg >> 8; + *level =3D riscv_clic_get_interrupt_level(clic, intcfg & 0xff); + *priority =3D riscv_clic_get_interrupt_priority(clic, intcfg & 0xff); +} + +/* + * In a system with multiple harts, the M-mode CLIC regions for all the ha= rts + * are placed contiguously in the memory space, followed by the S-mode CLIC + * regions for all harts. (Section 3.11) + */ +static size_t +riscv_clic_get_irq_offset(RISCVCLICState *clic, int mode, int hartid, int = irq) +{ + size_t mode_offset =3D 0; + size_t unit =3D clic->num_harts * clic->num_sources; + + switch (mode) { + case PRV_M: + mode_offset =3D 0; + break; + case PRV_S: + mode_offset =3D unit; + break; + case PRV_U: + mode_offset =3D clic->prv_s ? 2 * unit : unit; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "clic: invalid mode %d\n", mode); + exit(1); + } + return mode_offset + hartid * clic->num_sources + irq; +} + +static void riscv_clic_next_interrupt(void *opaque, int hartid) +{ + /* + * Scan active list for highest priority pending interrupts + * comparing against this harts mintstatus register and interrupt + * the core if we have a higher priority interrupt to deliver + */ + RISCVCPU *cpu =3D RISCV_CPU(qemu_get_cpu(hartid)); + CPURISCVState *env =3D &cpu->env; + RISCVCLICState *clic =3D (RISCVCLICState *)opaque; + + int il[4] =3D { + MAX(get_field(env->mintstatus, MINTSTATUS_UIL), + clic->mintthresh), /* PRV_U */ + MAX(get_field(env->mintstatus, MINTSTATUS_SIL), + clic->sintthresh), /* PRV_S */ + 0, /* reserverd */ + MAX(get_field(env->mintstatus, MINTSTATUS_MIL), + clic->uintthresh) /* PRV_M */ + }; + + /* Get sorted list of enabled interrupts for this hart */ + size_t hart_offset =3D hartid * clic->num_sources; + CLICActiveInterrupt *active =3D &clic->active_list[hart_offset]; + size_t active_count =3D clic->active_count[hartid]; + uint8_t mode, level, priority; + + /* Loop through the enabled interrupts sorted by mode+priority+level */ + while (active_count) { + size_t irq_offset; + riscv_clic_intcfg_decode(clic, active->intcfg, &mode, &level, + &priority); + if (mode < env->priv || (mode =3D=3D env->priv && level <=3D il[mo= de])) { + /* + * No pending interrupts with high enough mode+priority+level + * break and clear pending interrupt for this hart + */ + break; + } + irq_offset =3D riscv_clic_get_irq_offset(clic, mode, hartid, activ= e->irq); + /* Check pending interrupt with high enough mode+priority+level */ + if (clic->clicintip[irq_offset]) { + /* Clean vector edge-triggered pending */ + if (riscv_clic_is_edge_triggered(clic, irq_offset) && + riscv_clic_is_shv_interrupt(clic, irq_offset)) { + clic->clicintip[irq_offset] =3D 0; + } + /* Post pending interrupt for this hart */ + clic->exccode[hartid] =3D active->irq | mode << 12 | level << = 14; + qemu_set_irq(clic->cpu_irqs[hartid], 1); + return; + } + /* Check next enabled interrupt */ + active_count--; + active++; + } +} + +/* + * Any interrupt i that is not accessible to S-mode or U-Mode + * appears as hard-wired zeros in clicintip[i], clicintie[i], + * clicintattr[i], and clicintctl[i].(Section 3.9)(Section 3.10) + */ +static bool +riscv_clic_check_visible(RISCVCLICState *clic, int mode, int hartid, int i= rq) +{ + size_t irq_offset =3D riscv_clic_get_irq_offset(clic, mode, hartid, ir= q); + if (!clic->prv_s && !clic->prv_u) { /* M */ + return mode =3D=3D PRV_M; + } else if (!clic->prv_s) { /* M/U */ + switch (clic->nmbits) { + case 0: + return mode =3D=3D PRV_M; + case 1: + return clic->clicintattr[irq_offset] & 0x80 ? (mode =3D=3D PRV= _M) : + (mode =3D=3D PRV= _U); + default: + qemu_log_mask(LOG_GUEST_ERROR, + "clic: nmbits can only be 0 or 1 for M/U hart"); + exit(1); + } + } else { /* M/S/U */ + switch (clic->nmbits) { + case 0: + return mode =3D=3D PRV_M; + case 1: + return clic->clicintattr[irq_offset] & 0x80 ? (mode =3D=3D PRV= _M) : + (mode =3D=3D PRV= _S); + case 2: + return mode =3D=3D clic->clicintattr[irq_offset]; + case 3: + qemu_log_mask(LOG_GUEST_ERROR, + "clic: nmbits can only be 0 or 1 or 2 for M/S/U hart"); + exit(1); + } + } + return false; +} + +/* + * For level-triggered interrupts, software writes to pending bits are + * ignored completely. (Section 3.4) + */ +static bool +riscv_clic_validate_intip(RISCVCLICState *clic, int mode, int hartid, int = irq) +{ + size_t irq_offset =3D riscv_clic_get_irq_offset(clic, mode, hartid, ir= q); + return riscv_clic_is_edge_triggered(clic, irq_offset); +} + +static void +riscv_clic_update_intip(RISCVCLICState *clic, int mode, int hartid, + int irq, uint64_t value) +{ + size_t irq_offset =3D riscv_clic_get_irq_offset(clic, mode, hartid, ir= q); + clic->clicintip[irq_offset] =3D !!value; + riscv_clic_next_interrupt(clic, hartid); +} + +/* + * For security purpose, the field can only be set to a privilege + * level that is equal mode to or lower than the currently running + * privilege level.(Section 3.6) + */ + +static bool riscv_clic_validate_intattr(RISCVCLICState *clic, uint64_t val= ue) +{ + int mode =3D extract64(value, 6, 2); + + if (!qtest_enabled()) { + CPURISCVState *env =3D current_cpu->env_ptr; + if (env->priv < mode) { + return false; + } + } + return true; +} + +static inline int riscv_clic_encode_priority(const CLICActiveInterrupt *i) +{ + return ((i->intcfg & 0x3ff) << 12) | /* Highest mode+level+priority */ + (i->irq & 0xfff); /* Highest irq number */ +} + +static int riscv_clic_active_compare(const void *a, const void *b) +{ + return riscv_clic_encode_priority(b) - riscv_clic_encode_priority(a); +} + +static void +riscv_clic_update_intie(RISCVCLICState *clic, int mode, int hartid, + int irq, uint64_t new_intie) +{ + size_t hart_offset =3D hartid * clic->num_sources; + size_t irq_offset =3D riscv_clic_get_irq_offset(clic, mode, hartid, ir= q); + CLICActiveInterrupt *active_list =3D &clic->active_list[hart_offset]; + size_t *active_count =3D &clic->active_count[hartid]; + + uint8_t old_intie =3D clic->clicintie[irq_offset]; + clic->clicintie[irq_offset] =3D !!new_intie; + + /* Add to or remove from list of active interrupts */ + if (new_intie && !old_intie) { + active_list[*active_count].intcfg =3D (mode << 8) | + clic->clicintctl[irq_offset]; + active_list[*active_count].irq =3D irq; + (*active_count)++; + } else if (!new_intie && old_intie) { + CLICActiveInterrupt key =3D { + (mode << 8) | clic->clicintctl[irq_offset], irq + }; + CLICActiveInterrupt *result =3D bsearch(&key, + active_list, *active_count, + sizeof(CLICActiveInterrupt), + riscv_clic_active_compare); + size_t elem =3D (result - active_list) / sizeof(CLICActiveInterrup= t); + size_t sz =3D (--(*active_count) - elem) * sizeof(CLICActiveInterr= upt); + assert(result); + memmove(&result[0], &result[1], sz); + } + + /* Sort list of active interrupts */ + qsort(active_list, *active_count, + sizeof(CLICActiveInterrupt), + riscv_clic_active_compare); + + riscv_clic_next_interrupt(clic, hartid); +} + +static void +riscv_clic_hart_write(RISCVCLICState *clic, hwaddr addr, + uint64_t value, unsigned size, + int mode, int hartid, int irq) +{ + int req =3D extract32(addr, 0, 2); + size_t irq_offset =3D riscv_clic_get_irq_offset(clic, mode, hartid, ir= q); + + if (hartid >=3D clic->num_harts) { + qemu_log_mask(LOG_GUEST_ERROR, + "clic: invalid hartid %u: 0x%" HWADDR_PRIx "\n", + hartid, addr); + return; + } + + if (irq >=3D clic->num_sources) { + qemu_log_mask(LOG_GUEST_ERROR, + "clic: invalid irq %u: 0x%" HWADDR_PRIx "\n", irq, a= ddr); + return; + } + + switch (req) { + case 0: /* clicintip[i] */ + if (riscv_clic_validate_intip(clic, mode, hartid, irq)) { + /* + * The actual pending bit is located at bit 0 (i.e., the + * leastsignificant bit). In case future extensions expand the= bit + * field, from FW perspective clicintip[i]=3Dzero means no int= errupt + * pending, and clicintip[i]!=3D0 (not just 1) indicates an + * interrupt is pending. (Section 3.4) + */ + if (value !=3D clic->clicintip[irq_offset]) { + riscv_clic_update_intip(clic, mode, hartid, irq, value); + } + } + break; + case 1: /* clicintie[i] */ + if (clic->clicintie[irq_offset] !=3D value) { + riscv_clic_update_intie(clic, mode, hartid, irq, value); + } + break; + case 2: /* clicintattr[i] */ + if (riscv_clic_validate_intattr(clic, value)) { + if (clic->clicintattr[irq_offset] !=3D value) { + /* When nmbits=3D2, check WARL */ + bool invalid =3D (clic->nmbits =3D=3D 2) && + (extract64(value, 6, 2) =3D=3D 0b10); + if (invalid) { + uint8_t old_mode =3D extract32(clic->clicintattr[irq_o= ffset], + 6, 2); + value =3D deposit32(value, 6, 2, old_mode); + } + clic->clicintattr[irq_offset] =3D value; + riscv_clic_next_interrupt(clic, hartid); + } + } + break; + case 3: /* clicintctl[i] */ + if (value !=3D clic->clicintctl[irq_offset]) { + clic->clicintctl[irq_offset] =3D value; + riscv_clic_next_interrupt(clic, hartid); + } + break; + } +} + +static uint64_t +riscv_clic_hart_read(RISCVCLICState *clic, hwaddr addr, int mode, + int hartid, int irq) +{ + int req =3D extract32(addr, 0, 2); + size_t irq_offset =3D riscv_clic_get_irq_offset(clic, mode, hartid, ir= q); + + if (hartid >=3D clic->num_harts) { + qemu_log_mask(LOG_GUEST_ERROR, + "clic: invalid hartid %u: 0x%" HWADDR_PRIx "\n", + hartid, addr); + return 0; + } + + if (irq >=3D clic->num_sources) { + qemu_log_mask(LOG_GUEST_ERROR, + "clic: invalid irq %u: 0x%" HWADDR_PRIx "\n", irq, a= ddr); + return 0; + } + + switch (req) { + case 0: /* clicintip[i] */ + return clic->clicintip[irq_offset]; + case 1: /* clicintie[i] */ + return clic->clicintie[irq_offset]; + case 2: /* clicintattr[i] */ + /* + * clicintattr register layout + * Bits Field + * 7:6 mode + * 5:3 reserved (WPRI 0) + * 2:1 trig + * 0 shv + */ + return clic->clicintattr[irq_offset] & ~0x38; + case 3: /* clicintctrl */ + /* + * The implemented bits are kept left-justified in the most-signif= icant + * bits of each 8-bit clicintctl[i] register, with the lower + * unimplemented bits treated as hardwired to 1.(Section 3.7) + */ + return clic->clicintctl[irq_offset] | + ((1 << (8 - clic->clicintctlbits)) - 1); + } + + return 0; +} + +/* Return target interrupt mode */ +static int riscv_clic_get_mode(RISCVCLICState *clic, hwaddr addr) +{ + int mode =3D addr / (4 * clic->num_harts * clic->num_sources); + switch (mode) { + case 0: + return PRV_M; + case 1: + assert(clic->prv_s || clic->prv_u); + return clic->prv_s ? PRV_S : PRV_U; + case 2: + assert(clic->prv_s && clic->prv_u); + return PRV_U; + default: + g_assert_not_reached(); + break; + } +} + +/* Return target hart id */ +static int riscv_clic_get_hartid(RISCVCLICState *clic, hwaddr addr) +{ + int mode_unit =3D 4 * clic->num_harts * clic->num_sources; + int hart_unit =3D 4 * clic->num_sources; + + return (addr % mode_unit) / hart_unit; +} + +/* Return target interrupt number */ +static int riscv_clic_get_irq(RISCVCLICState *clic, hwaddr addr) +{ + int hart_unit =3D 4 * clic->num_sources; + return (addr % hart_unit) / 4; +} + +static void +riscv_clic_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) +{ + RISCVCLICState *clic =3D opaque; + hwaddr clic_size =3D clic->clic_size; + int hartid, mode, irq; + + if (addr < clic_size) { + if (addr < 0x1000) { + assert(addr % 4 =3D=3D 0); + int index =3D addr / 4; + switch (index) { + case 0: /* cliccfg */ + { + uint8_t nlbits =3D extract32(value, 1, 4); + uint8_t nmbits =3D extract32(value, 5, 2); + + /* + * The 4-bit cliccfg.nlbits WARL field. + * Valid values are 0=E2=80=948. + */ + if (nlbits <=3D 8) { + clic->nlbits =3D nlbits; + } + /* Valid values are given by implemented priviledges */ + if (clic->prv_s && clic->prv_u) { + if (nmbits <=3D 2) { + clic->nmbits =3D nmbits; + } + } else if (clic->prv_u) { + if (nmbits <=3D 1) { + clic->nmbits =3D nmbits; + } + } else { + assert(!clic->prv_s); + if (nmbits =3D=3D 0) { + clic->nmbits =3D 0; + } + } + clic->nvbits =3D extract32(value, 0, 1); + break; + } + case 1: /* clicinfo, read-only register */ + qemu_log_mask(LOG_GUEST_ERROR, + "clic: write read-only clicinfo.\n"); + break; + case 0x10 ... 0x2F: /* clicinttrig */ + { + uint32_t interrupt_number =3D value & MAKE_64BIT_MASK(= 0, 13); + if (interrupt_number <=3D clic->num_sources) { + value &=3D ~MAKE_64BIT_MASK(13, 18); + clic->clicinttrig[index - 0x10] =3D value; + } + break; + } + case 2: /* mintthresh */ + if (!strcmp(clic->version, "v0.8")) { + clic->mintthresh =3D value; + break; + } + qemu_log_mask(LOG_GUEST_ERROR, + "clic: invalid write addr: 0x%" HWADDR_PRIx = "\n", + addr); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "clic: invalid write addr: 0x%" HWADDR_PRIx = "\n", + addr); + return; + } + } else { + addr -=3D 0x1000; + hartid =3D riscv_clic_get_hartid(clic, addr); + mode =3D riscv_clic_get_mode(clic, addr); + irq =3D riscv_clic_get_irq(clic, addr); + + if (riscv_clic_check_visible(clic, mode, hartid, irq)) { + riscv_clic_hart_write(clic, addr, value, size, mode, + hartid, irq); + } + } + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "clic: invalid write: 0x%" HWADDR_PRIx "\n", addr); + } +} + +static uint64_t riscv_clic_read(void *opaque, hwaddr addr, unsigned size) +{ + RISCVCLICState *clic =3D opaque; + hwaddr clic_size =3D clic->clic_size; + int hartid, mode, irq; + + if (addr < clic_size) { + if (addr < 0x1000) { + assert(addr % 4 =3D=3D 0); + int index =3D addr / 4; + switch (index) { + case 0: /* cliccfg */ + return clic->nvbits | + (clic->nlbits << 1) | + (clic->nmbits << 5); + case 1: /* clicinfo */ + /* + * clicinfo register layout + * + * Bits Field + * 31 reserved (WARL 0) + * 30:25 num_trigger + * 24:21 CLICINTCTLBITS + * 20:13 version (for version control) + * 12:0 num_interrupt + */ + return clic->clicinfo & ~INT32_MAX; + case 0x10 ... 0x2F: /* clicinttrig */ + /* + * clicinttrig register layout + * + * Bits Field + * 31 enable + * 30:13 reserved (WARL 0) + * 12:0 interrupt_number + */ + return clic->clicinttrig[index - 0x10] & + ~MAKE_64BIT_MASK(13, 18); + case 2: /* mintthresh */ + if (!strcmp(clic->version, "v0.8")) { + return clic->mintthresh; + break; + } + qemu_log_mask(LOG_GUEST_ERROR, + "clic: invalid read : 0x%" HWADDR_PRIx "\n", + addr); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "clic: invalid read : 0x%" HWADDR_PRIx "\n", + addr); + break; + } + } else { + addr -=3D 0x1000; + hartid =3D riscv_clic_get_hartid(clic, addr); + mode =3D riscv_clic_get_mode(clic, addr); + irq =3D riscv_clic_get_irq(clic, addr); + + if (riscv_clic_check_visible(clic, mode, hartid, irq)) { + return riscv_clic_hart_read(clic, addr, mode, hartid, irq); + } + } + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "clic: invalid read: 0x%" HWADDR_PRIx "\n", addr); + } + return 0; +} + +static void riscv_clic_set_irq(void *opaque, int id, int level) +{ + RISCVCLICState *clic =3D opaque; + int irq, hartid, mode; + hwaddr addr =3D 4 * id; + TRIG_TYPE type; + + hartid =3D riscv_clic_get_hartid(clic, addr); + mode =3D riscv_clic_get_mode(clic, addr); + irq =3D riscv_clic_get_irq(clic, addr); + type =3D riscv_clic_get_trigger_type(clic, id); + + /* + * In general, the edge-triggered interrupt state should be kept in pe= nding + * bit, while the level-triggered interrupt should be kept in the level + * state of the incoming wire. + * + * For CLIC, model the level-triggered interrupt by read-only pending = bit. + */ + if (level) { + switch (type) { + case POSITIVE_LEVEL: + case POSITIVE_EDGE: + riscv_clic_update_intip(clic, mode, hartid, irq, level); + break; + case NEG_LEVEL: + riscv_clic_update_intip(clic, mode, hartid, irq, !level); + break; + case NEG_EDGE: + break; + } + } else { + switch (type) { + case POSITIVE_LEVEL: + riscv_clic_update_intip(clic, mode, hartid, irq, level); + break; + case POSITIVE_EDGE: + break; + case NEG_LEVEL: + case NEG_EDGE: + riscv_clic_update_intip(clic, mode, hartid, irq, !level); + break; + } + } +} + +static void riscv_clic_cpu_irq_handler(void *opaque, int irq, int level) +{ + CPURISCVState *env =3D (CPURISCVState *)opaque; + RISCVCLICState *clic =3D env->clic; + CPUState *cpu =3D env_cpu(env); + + if (level) { + env->exccode =3D clic->exccode[cpu->cpu_index]; + cpu_interrupt(env_cpu(env), CPU_INTERRUPT_CLIC); + } +} + +static const MemoryRegionOps riscv_clic_ops =3D { + .read =3D riscv_clic_read, + .write =3D riscv_clic_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 8 + } +}; + +static void riscv_clic_realize(DeviceState *dev, Error **errp) +{ + RISCVCLICState *clic =3D RISCV_CLIC(dev); + size_t harts_x_sources =3D clic->num_harts * clic->num_sources; + int irqs, i; + + if (clic->prv_s && clic->prv_u) { + irqs =3D 3 * harts_x_sources; + } else if (clic->prv_s || clic->prv_u) { + irqs =3D 2 * harts_x_sources; + } else { + irqs =3D harts_x_sources; + } + + clic->clic_size =3D irqs * 4 + 0x1000; + memory_region_init_io(&clic->mmio, OBJECT(dev), &riscv_clic_ops, clic, + TYPE_RISCV_CLIC, clic->clic_size); + + clic->clicintip =3D g_new0(uint8_t, irqs); + clic->clicintie =3D g_new0(uint8_t, irqs); + clic->clicintattr =3D g_new0(uint8_t, irqs); + clic->clicintctl =3D g_new0(uint8_t, irqs); + clic->active_list =3D g_new0(CLICActiveInterrupt, irqs); + clic->active_count =3D g_new0(size_t, clic->num_harts); + clic->exccode =3D g_new0(uint32_t, clic->num_harts); + clic->cpu_irqs =3D g_new0(qemu_irq, clic->num_harts); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &clic->mmio); + + /* Allocate irq through gpio, so that we can use qtest */ + qdev_init_gpio_in(dev, riscv_clic_set_irq, irqs); + qdev_init_gpio_out(dev, clic->cpu_irqs, clic->num_harts); + + for (i =3D 0; i < clic->num_harts; i++) { + RISCVCPU *cpu =3D RISCV_CPU(qemu_get_cpu(i)); + qemu_irq irq =3D qemu_allocate_irq(riscv_clic_cpu_irq_handler, + &cpu->env, 1); + qdev_connect_gpio_out(dev, i, irq); + cpu->env.clic =3D clic; + } +} + +static Property riscv_clic_properties[] =3D { + DEFINE_PROP_BOOL("prv-s", RISCVCLICState, prv_s, false), + DEFINE_PROP_BOOL("prv-u", RISCVCLICState, prv_u, false), + DEFINE_PROP_UINT32("num-harts", RISCVCLICState, num_harts, 0), + DEFINE_PROP_UINT32("num-sources", RISCVCLICState, num_sources, 0), + DEFINE_PROP_UINT32("clicintctlbits", RISCVCLICState, clicintctlbits, 0= ), + DEFINE_PROP_UINT64("mclicbase", RISCVCLICState, mclicbase, 0), + DEFINE_PROP_STRING("version", RISCVCLICState, version), + DEFINE_PROP_END_OF_LIST(), +}; + +static void riscv_clic_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D riscv_clic_realize; + device_class_set_props(dc, riscv_clic_properties); +} + +static const TypeInfo riscv_clic_info =3D { + .name =3D TYPE_RISCV_CLIC, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(RISCVCLICState), + .class_init =3D riscv_clic_class_init, +}; + +static void riscv_clic_register_types(void) +{ + type_register_static(&riscv_clic_info); +} + +type_init(riscv_clic_register_types) + +/* + * riscv_clic_create: + * + * @addr: base address of M-Mode CLIC memory-mapped registers + * @prv_s: have smode region + * @prv_u: have umode region + * @num_harts: number of CPU harts + * @num_sources: number of interrupts supporting by each aperture + * @clicintctlbits: bits are actually implemented in the clicintctl regist= ers + * @version: clic version, such as "v0.9" + * + * Returns: the device object + */ +DeviceState *riscv_clic_create(hwaddr addr, bool prv_s, bool prv_u, + uint32_t num_harts, uint32_t num_sources, + uint8_t clicintctlbits, + const char *version) +{ + DeviceState *dev =3D qdev_new(TYPE_RISCV_CLIC); + + assert(num_sources <=3D 4096); + assert(num_harts <=3D 1024); + assert(clicintctlbits <=3D 8); + assert(!strcmp(version, "v0.8") || !strcmp(version, "v0.9")); + + qdev_prop_set_bit(dev, "prv-s", prv_s); + qdev_prop_set_bit(dev, "prv-u", prv_u); + qdev_prop_set_uint32(dev, "num-harts", num_harts); + qdev_prop_set_uint32(dev, "num-sources", num_sources); + qdev_prop_set_uint32(dev, "clicintctlbits", clicintctlbits); + qdev_prop_set_uint64(dev, "mclicbase", addr); + qdev_prop_set_string(dev, "version", version); + + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); + return dev; +} + +void riscv_clic_get_next_interrupt(void *opaque, int hartid) +{ + RISCVCLICState *clic =3D opaque; + riscv_clic_next_interrupt(clic, hartid); +} + +bool riscv_clic_shv_interrupt(void *opaque, int mode, int hartid, int irq) +{ + RISCVCLICState *clic =3D opaque; + size_t irq_offset =3D riscv_clic_get_irq_offset(clic, mode, hartid, ir= q); + return riscv_clic_is_shv_interrupt(clic, irq_offset); +} + +bool riscv_clic_edge_triggered(void *opaque, int mode, int hartid, int irq) +{ + RISCVCLICState *clic =3D opaque; + size_t irq_offset =3D riscv_clic_get_irq_offset(clic, mode, hartid, ir= q); + return riscv_clic_is_edge_triggered(clic, irq_offset); +} + +void riscv_clic_clean_pending(void *opaque, int mode, int hartid, int irq) +{ + RISCVCLICState *clic =3D opaque; + size_t irq_offset =3D riscv_clic_get_irq_offset(clic, mode, hartid, ir= q); + clic->clicintip[irq_offset] =3D 0; +} + +/* + * The new CLIC interrupt-handling mode is encoded as a new state in + * the existing WARL xtvec register, where the low two bits of are 11. + */ +bool riscv_clic_is_clic_mode(CPURISCVState *env) +{ + target_ulong xtvec =3D (env->priv =3D=3D PRV_M) ? env->mtvec : env->st= vec; + return env->clic && ((xtvec & 0x3) =3D=3D 3); +} + +void riscv_clic_decode_exccode(uint32_t exccode, int *mode, + int *il, int *irq) +{ + *irq =3D extract32(exccode, 0, 12); + *mode =3D extract32(exccode, 12, 2); + *il =3D extract32(exccode, 14, 8); +} diff --git a/include/hw/intc/riscv_clic.h b/include/hw/intc/riscv_clic.h new file mode 100644 index 0000000000..e5f89672a6 --- /dev/null +++ b/include/hw/intc/riscv_clic.h @@ -0,0 +1,103 @@ +/* + * RISC-V CLIC(Core Local Interrupt Controller) interface. + * + * Copyright (c) 2021 T-Head Semiconductor Co., Ltd. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#ifndef RISCV_CLIC_H +#define RISCV_CLIC_H + +#include "hw/irq.h" +#include "hw/sysbus.h" + +#define TYPE_RISCV_CLIC "riscv_clic" +#define RISCV_CLIC(obj) \ + OBJECT_CHECK(RISCVCLICState, (obj), TYPE_RISCV_CLIC) + +/* + * CLIC per hart active interrupts + * + * We maintain per hart lists of enabled interrupts sorted by + * mode+level+priority. The sorting is done on the configuration path + * so that the interrupt delivery fastpath can linear scan enabled + * interrupts in priority order. + */ +typedef struct CLICActiveInterrupt { + uint16_t intcfg; + uint16_t irq; +} CLICActiveInterrupt; + +typedef enum TRIG_TYPE { + POSITIVE_LEVEL, + POSITIVE_EDGE, + NEG_LEVEL, + NEG_EDGE, +} TRIG_TYPE; + +typedef struct RISCVCLICState { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + + /* Implementaion parameters */ + bool prv_s; + bool prv_u; + uint32_t num_harts; + uint32_t num_sources; + uint32_t clic_size; + uint32_t clic_mmode_base; + uint32_t clicintctlbits; + uint64_t mclicbase; + char *version; + + /* Global configuration */ + uint8_t nmbits; + uint8_t nlbits; + uint8_t nvbits; + uint32_t clicinfo; + uint32_t clicinttrig[32]; + + /* Aperture configuration */ + uint8_t *clicintip; + uint8_t *clicintie; + uint8_t *clicintattr; + uint8_t *clicintctl; + + /* Complatible with v0.8 */ + uint32_t mintthresh; + uint32_t sintthresh; + uint32_t uintthresh; + + /* QEMU implementaion related fields */ + uint32_t *exccode; + CLICActiveInterrupt *active_list; + size_t *active_count; + MemoryRegion mmio; + qemu_irq *cpu_irqs; +} RISCVCLICState; + +DeviceState *riscv_clic_create(hwaddr addr, bool prv_s, bool prv_u, + uint32_t num_harts, uint32_t num_sources, + uint8_t clicintctlbits, + const char *version); + +void riscv_clic_decode_exccode(uint32_t exccode, int *mode, int *il, int *= irq); +void riscv_clic_clean_pending(void *opaque, int mode, int hartid, int irq); +bool riscv_clic_edge_triggered(void *opaque, int mode, int hartid, int irq= ); +bool riscv_clic_shv_interrupt(void *opaque, int mode, int hartid, int irq); +void riscv_clic_get_next_interrupt(void *opaque, int hartid); +bool riscv_clic_is_clic_mode(CPURISCVState *env); +#endif diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index a5eab26a69..9e389d7bbf 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -33,6 +33,7 @@ #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU +#define CPU_INTERRUPT_CLIC CPU_INTERRUPT_TGT_EXT_0 =20 #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") @@ -247,6 +248,7 @@ struct CPURISCVState { /* Fields from here on are preserved across CPU reset. */ QEMUTimer *timer; /* Internal timer */ void *clic; /* clic interrupt controller */ + uint32_t exccode; /* clic irq encode */ }; =20 OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass, --=20 2.25.1 From nobody Mon Apr 29 02:48:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1617954674; cv=none; d=zohomail.com; s=zohoarc; b=XSvntpeATejNl7wYWvmJACWdECr5+dmjvqqWC808Jteyemc+5lXXmCI+6RihrneNJV9wgcWZ8/gQ5pzzNBxZsd9rj7LKN3F/sDPihOanBKf83/5sHLCbfuEuwshADLJPeFUXcPZBAJLrlTS4GiuJXmWKHniq+0U1US41E1FXtTk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1617954674; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=BXJ3Ffe78ntH/0EKfnegAmcC9WUujUcGTr+I3QlwZ70=; b=AdLTDLf4sRNtylE3tlUGGmKKkvUGcT4voPu6CG9FfJwAZeHFN2imYLAlKdNp5XQSjalHdOs0dGoQ472qZEn+o9zVyRfe1YOXmwhfR/gdXPh2XedGuKXt/97y0tdribodrAnE843hmNHkEVw7/gOU97xFtdQmVtvlNouJNmAvVOU= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1617954674578135.96171173948892; Fri, 9 Apr 2021 00:51:14 -0700 (PDT) Received: from localhost ([::1]:33910 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lUlv6-0003wi-S6 for importer@patchew.org; Fri, 09 Apr 2021 03:51:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37514) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lUltd-0002Gp-83; Fri, 09 Apr 2021 03:49:41 -0400 Received: from mail142-32.mail.alibaba.com ([198.11.142.32]:13004) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lUlta-0003iN-OR; Fri, 09 Apr 2021 03:49:41 -0400 Received: from localhost.localdomain(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.JxL3BOG_1617954563) by smtp.aliyun-inc.com(10.147.40.7); Fri, 09 Apr 2021 15:49:25 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07535652|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_regular_dialog|0.100308-0.000891546-0.8988; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047205; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=6; RT=6; SR=0; TI=SMTPD_---.JxL3BOG_1617954563; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC PATCH 04/11] target/riscv: Update CSR xie in CLIC mode Date: Fri, 9 Apr 2021 15:48:50 +0800 Message-Id: <20210409074857.166082-5-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210409074857.166082-1-zhiwei_liu@c-sky.com> References: <20210409074857.166082-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=198.11.142.32; envelope-from=zhiwei_liu@c-sky.com; helo=mail142-32.mail.alibaba.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, Alistair.Francis@wdc.com, LIU Zhiwei , wxy194768@alibaba-inc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The xie CSR appears hardwired to zero in CLIC mode, replaced by separate memory-mapped interrupt enables (clicintie[i]). Writes to xie will be ignored and will not trap (i.e., no access faults). Signed-off-by: LIU Zhiwei Reviewed-by: Frank Chang --- target/riscv/csr.c | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 4c31364967..74bc7a08aa 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -23,6 +23,10 @@ #include "qemu/main-loop.h" #include "exec/exec-all.h" =20 +#if !defined(CONFIG_USER_ONLY) +#include "hw/intc/riscv_clic.h" +#endif + /* CSR function table public API */ void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops) { @@ -611,13 +615,17 @@ static int write_mideleg(CPURISCVState *env, int csrn= o, target_ulong val) =20 static int read_mie(CPURISCVState *env, int csrno, target_ulong *val) { - *val =3D env->mie; + /* The xie CSR appears hardwired to zero in CLIC mode, (Section 4.3) */ + *val =3D riscv_clic_is_clic_mode(env) ? 0 : env->mie; return 0; } =20 static int write_mie(CPURISCVState *env, int csrno, target_ulong val) { - env->mie =3D (env->mie & ~all_ints) | (val & all_ints); + /* Writes to xie will be ignored and will not trap. (Section 4.3) */ + if (!riscv_clic_is_clic_mode(env)) { + env->mie =3D (env->mie & ~all_ints) | (val & all_ints); + } return 0; } =20 @@ -785,7 +793,8 @@ static int read_sie(CPURISCVState *env, int csrno, targ= et_ulong *val) if (riscv_cpu_virt_enabled(env)) { read_vsie(env, CSR_VSIE, val); } else { - *val =3D env->mie & env->mideleg; + /* The xie CSR appears hardwired to zero in CLIC mode. (Section 4.= 3) */ + *val =3D riscv_clic_is_clic_mode(env) ? 0 : env->mie & env->midele= g; } return 0; } @@ -805,6 +814,10 @@ static int write_sie(CPURISCVState *env, int csrno, ta= rget_ulong val) } else { target_ulong newval =3D (env->mie & ~S_MODE_INTERRUPTS) | (val & S_MODE_INTERRUPTS); + /* Writes to xie will be ignored and will not trap. (Section 4.3) = */ + if (riscv_clic_is_clic_mode(env)) { + return 0; + } write_mie(env, CSR_MIE, newval); } =20 --=20 2.25.1 From nobody Mon Apr 29 02:48:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1617954677; cv=none; d=zohomail.com; s=zohoarc; b=KPdhOmv/jlVsB1AWuVfP6/lRAQQZWyRu7VNK/iOuvcO7txvzeVvICj/Z43z81fR+l7ZUr5keRXqoLjpYaz/tcoRUvJlLIcWUInitDl+zSWfWMiarJsQK99gSS/ZNpehayORCM7SfO1r6RbaAjrlsXBoctpv3jKFm6WXqahAN4xo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1617954677; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=wmBBN36DmwhC21uLXWPdOfrCqjYxoNzhpxDUREoL394=; b=J8cRBgsZwKYqt9tg7E1Qv45bB5JKO8vEq5aQeX6iT5Q1VQLGOfhtLSw/Cg/5zr6Her93qUFSJhf/OCnDrIUBL+FfUbsjvfH3hVqVwSrIEve7oXLLVE6QWixXemDZ+HM4ypyVQ0qQV9DQtQqGY+Ezw11QuNFHbMjj8IyL2VKaXWc= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1617954677891861.0896004500075; Fri, 9 Apr 2021 00:51:17 -0700 (PDT) Received: from localhost ([::1]:34372 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lUlvA-000482-SM for importer@patchew.org; Fri, 09 Apr 2021 03:51:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37558) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lUlte-0002H7-QM; Fri, 09 Apr 2021 03:49:42 -0400 Received: from mail142-34.mail.alibaba.com ([198.11.142.34]:65454) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lUlta-0003hh-UU; Fri, 09 Apr 2021 03:49:42 -0400 Received: from localhost.localdomain(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.JxL3BOG_1617954563) by smtp.aliyun-inc.com(10.147.40.7); Fri, 09 Apr 2021 15:49:25 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.08305461|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.082169-0.00153044-0.916301; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047211; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=6; RT=6; SR=0; TI=SMTPD_---.JxL3BOG_1617954563; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC PATCH 05/11] target/riscv: Update CSR xip in CLIC mode Date: Fri, 9 Apr 2021 15:48:51 +0800 Message-Id: <20210409074857.166082-6-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210409074857.166082-1-zhiwei_liu@c-sky.com> References: <20210409074857.166082-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=198.11.142.34; envelope-from=zhiwei_liu@c-sky.com; helo=mail142-34.mail.alibaba.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, Alistair.Francis@wdc.com, LIU Zhiwei , wxy194768@alibaba-inc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The xip CSR appears hardwired to zero in CLIC mode, replaced by separate memory-mapped interrupt pendings (clicintip[i]). Writes to xip will be ignored and will not trap (i.e., no access faults). Signed-off-by: LIU Zhiwei Reviewed-by: Frank Chang --- target/riscv/csr.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 74bc7a08aa..f6c84b9fe4 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -735,6 +735,11 @@ static int rmw_mip(CPURISCVState *env, int csrno, targ= et_ulong *ret_value, target_ulong mask =3D write_mask & delegable_ints & ~env->miclaim; uint32_t old_mip; =20 + /* The xip CSR appears hardwired to zero in CLIC mode. (Section 4.3) = */ + if (riscv_clic_is_clic_mode(env)) { + *ret_value =3D 0; + return 0; + } if (mask) { old_mip =3D riscv_cpu_update_mip(cpu, mask, (new_value & mask)); } else { @@ -922,6 +927,11 @@ static int rmw_sip(CPURISCVState *env, int csrno, targ= et_ulong *ret_value, if (riscv_cpu_virt_enabled(env)) { ret =3D rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask); } else { + /* The xip CSR appears hardwired to zero in CLIC mode. (Section 4.= 3) */ + if (riscv_clic_is_clic_mode(env)) { + *ret_value =3D 0; + return 0; + } ret =3D rmw_mip(env, CSR_MSTATUS, ret_value, new_value, write_mask & env->mideleg & sip_writable_mask); } --=20 2.25.1 From nobody Mon Apr 29 02:48:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1617954678; cv=none; d=zohomail.com; s=zohoarc; b=mpKYtaas3i1aSdtlmto+WuYiXYMpVQw7ZRIso7rHT4VE+wvdrixa8UuAbblGMBKekWMQjZYpxOfcZJjdKvs/UNNt8TruQ0KvQJwwFgpX2ACYhj+IIbA7HO6rOToEkKAtoWz5eX5JcTilR7s4/TOFwpU0s35/h1BVW/no0puz5bY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1617954678; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=YP3j3b3oyJokda/Py4kqScSPvSzBYffX8zRplAEXhA8=; b=RE59DfBfH4AEAzotFRtFowy1DFvMUOq/qeFfTupM2iTreidvTh82KW2e8vbJADeJ6KeCdK791IFnwk9fBWUNCqDZa0g+Z2vmGabPnHZIIfZVYwm/G6DKilE3Of53UG+lD50pAowj2iK49K76b8H3fp6OyoBaIs/OpWd1vm8i/p8= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1617954678004772.7119560846996; Fri, 9 Apr 2021 00:51:18 -0700 (PDT) Received: from localhost ([::1]:34340 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lUlvA-00047C-Re for importer@patchew.org; Fri, 09 Apr 2021 03:51:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37588) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lUltg-0002I8-1l; Fri, 09 Apr 2021 03:49:44 -0400 Received: from mail142-33.mail.alibaba.com ([198.11.142.33]:4122) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lUlta-0003iE-Uq; Fri, 09 Apr 2021 03:49:43 -0400 Received: from localhost.localdomain(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.JxL3BOG_1617954563) by smtp.aliyun-inc.com(10.147.40.7); Fri, 09 Apr 2021 15:49:25 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.1349344|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.0245098-0.000202005-0.975288; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047192; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=6; RT=6; SR=0; TI=SMTPD_---.JxL3BOG_1617954563; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC PATCH 06/11] target/riscv: Update CSR xtvec in CLIC mode Date: Fri, 9 Apr 2021 15:48:52 +0800 Message-Id: <20210409074857.166082-7-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210409074857.166082-1-zhiwei_liu@c-sky.com> References: <20210409074857.166082-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=198.11.142.33; envelope-from=zhiwei_liu@c-sky.com; helo=mail142-33.mail.alibaba.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, Alistair.Francis@wdc.com, LIU Zhiwei , wxy194768@alibaba-inc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The new CLIC interrupt-handling mode is encoded as a new state in the existing WARL xtvec register, where the low two bits of are 11. Signed-off-by: LIU Zhiwei --- target/riscv/csr.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index f6c84b9fe4..39ff72041a 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -637,9 +637,18 @@ static int read_mtvec(CPURISCVState *env, int csrno, t= arget_ulong *val) =20 static int write_mtvec(CPURISCVState *env, int csrno, target_ulong val) { - /* bits [1:0] encode mode; 0 =3D direct, 1 =3D vectored, 2 >=3D reserv= ed */ + /* + * bits [1:0] encode mode; 0 =3D direct, 1 =3D vectored, 3 =3D CLIC, + * others reserved + */ if ((val & 3) < 2) { env->mtvec =3D val; + } else if ((val & 1) && env->clic) { + /* + * If only CLIC mode is supported, writes to bit 1 are also ignore= d and + * it is always set to one. CLIC mode hardwires xtvec bits 2-5 to = zero. + */ + env->mtvec =3D ((val & ~0x3f) << 6) | (0b000011); } else { qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n= "); } @@ -837,9 +846,18 @@ static int read_stvec(CPURISCVState *env, int csrno, t= arget_ulong *val) =20 static int write_stvec(CPURISCVState *env, int csrno, target_ulong val) { - /* bits [1:0] encode mode; 0 =3D direct, 1 =3D vectored, 2 >=3D reserv= ed */ + /* + * bits [1:0] encode mode; 0 =3D direct, 1 =3D vectored, 3 =3D CLIC, + * others reserved + */ if ((val & 3) < 2) { env->stvec =3D val; + } else if ((val & 1) && env->clic) { + /* + * If only CLIC mode is supported, writes to bit 1 are also ignore= d and + * it is always set to one. CLIC mode hardwires xtvec bits 2-5 to = zero. + */ + env->stvec =3D ((val & ~0x3f) << 6) | (0b000011); } else { qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n= "); } --=20 2.25.1 From nobody Mon Apr 29 02:48:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1617954852; cv=none; d=zohomail.com; s=zohoarc; b=KIJlojGFx5/ieg1R/YG+ImJCX3OHtqg6IPnA9OZQaSV+boaFFC++DvknAV0ZYHdwzXn3TLkKAEI09AIcpzrRsmiskGctuTkYGN9WRy9SXS3O9+LN6bNnCCbAlxeXdnsIRNzxo255w/yPDrXoJVGmcVmVdoLIUyjBLgZvT08gBkQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1617954852; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=YavTiidB3fJS0iCwsYrluZraR6+EnbiTDyLt/KlDhdg=; b=ixLPsMlRAmrLyS16Onbckb9Cp4Nvq3E6m5UaXoPWgMrR10Q/y4FTrt58dx1p8ll43fdcDSE6nsZWq8Rt+fcy+aVV3C20HPlJoMM/QywaTJRogj3biZK88sRYf4tBSiZsAeOzZvUqitNP6f0gdKUCvQGdMD/5sNKxADbHkHT/yVc= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1617954852283445.86014147101366; Fri, 9 Apr 2021 00:54:12 -0700 (PDT) Received: from localhost ([::1]:43002 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lUlxz-0007iO-70 for importer@patchew.org; Fri, 09 Apr 2021 03:54:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37590) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lUltg-0002Iz-B4; Fri, 09 Apr 2021 03:49:44 -0400 Received: from mail142-32.mail.alibaba.com ([198.11.142.32]:2846) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lUlta-0003ih-W8; Fri, 09 Apr 2021 03:49:43 -0400 Received: from localhost.localdomain(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.JxL3BOG_1617954563) by smtp.aliyun-inc.com(10.147.40.7); Fri, 09 Apr 2021 15:49:25 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.0745143|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.170168-0.000410475-0.829421; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047199; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=6; RT=6; SR=0; TI=SMTPD_---.JxL3BOG_1617954563; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC PATCH 07/11] target/riscv: Update CSR xtvt in CLIC mode Date: Fri, 9 Apr 2021 15:48:53 +0800 Message-Id: <20210409074857.166082-8-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210409074857.166082-1-zhiwei_liu@c-sky.com> References: <20210409074857.166082-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=198.11.142.32; envelope-from=zhiwei_liu@c-sky.com; helo=mail142-32.mail.alibaba.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, Alistair.Francis@wdc.com, LIU Zhiwei , wxy194768@alibaba-inc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The xtvt WARL XLEN-bit CSR holds the base address of the trap vector table, aligned on a 64-byte or greater power-of-two boundary. Signed-off-by: LIU Zhiwei --- target/riscv/cpu.h | 2 ++ target/riscv/cpu_bits.h | 2 ++ target/riscv/csr.c | 28 ++++++++++++++++++++++++++++ 3 files changed, 32 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 9e389d7bbf..b5fd796f98 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -173,11 +173,13 @@ struct CPURISCVState { target_ulong medeleg; =20 target_ulong stvec; + target_ulong stvt; /* clic-spec */ target_ulong sepc; target_ulong scause; target_ulong sintthresh; /* clic-spec */ =20 target_ulong mtvec; + target_ulong mtvt; /* clic-spec */ target_ulong mepc; target_ulong mcause; target_ulong mtval; /* since: priv-1.10.0 */ diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 9447801d22..7922097776 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -149,6 +149,7 @@ #define CSR_MIE 0x304 #define CSR_MTVEC 0x305 #define CSR_MCOUNTEREN 0x306 +#define CSR_MTVT 0x307 /* clic-spec-draft */ =20 /* 32-bit only */ #define CSR_MSTATUSH 0x310 @@ -178,6 +179,7 @@ #define CSR_SIE 0x104 #define CSR_STVEC 0x105 #define CSR_SCOUNTEREN 0x106 +#define CSR_STVT 0x107 /* clic-spec-draft */ =20 /* Supervisor Trap Handling */ #define CSR_SSCRATCH 0x140 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 39ff72041a..e12222b77f 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -667,6 +667,18 @@ static int write_mcounteren(CPURISCVState *env, int cs= rno, target_ulong val) return 0; } =20 +static int read_mtvt(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->mtvt; + return 0; +} + +static int write_mtvt(CPURISCVState *env, int csrno, target_ulong val) +{ + env->mtvt =3D val & ~((1ULL << 6) - 1); + return 0; +} + /* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */ static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *v= al) { @@ -876,6 +888,18 @@ static int write_scounteren(CPURISCVState *env, int cs= rno, target_ulong val) return 0; } =20 +static int read_stvt(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->stvt; + return 0; +} + +static int write_stvt(CPURISCVState *env, int csrno, target_ulong val) +{ + env->stvt =3D val & ~((1ULL << 6) - 1); + return 0; +} + /* Supervisor Trap Handling */ static int read_sscratch(CPURISCVState *env, int csrno, target_ulong *val) { @@ -1730,6 +1754,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_MHPMCOUNTER31H] =3D { "mhpmcounter31h", any32, read_zero }, =20 /* Machine Mode Core Level Interrupt Controller */ + [CSR_MTVT] =3D { "mtvt", clic, read_mtvt, write_mtvt }, [CSR_MINTSTATUS] =3D { "mintstatus", clic, read_mintstatus }, [CSR_MINTTHRESH] =3D { "mintthresh", clic, read_mintthresh, write_mintthresh }, @@ -1739,5 +1764,8 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_SINTTHRESH] =3D { "sintthresh", clic, read_sintthresh, write_sintthresh }, =20 + /* Supervisor Mode Core Level Interrupt Controller */ + [CSR_STVT] =3D { "stvt", clic, read_stvt, write_stvt }, + #endif /* !CONFIG_USER_ONLY */ }; --=20 2.25.1 From nobody Mon Apr 29 02:48:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1617954674; cv=none; d=zohomail.com; s=zohoarc; b=cjzIjc+bnLa2THaBbfiIsQv5kd9n+YPmGba4m3eDH4r01MqLQwyoCMH9VzXIXW3j7z1eqhxeUVZ1tebx3MW21jk55i5Jsq3JoL5KfBsnyjhFfLmKRx8fXfmYfyXNJz8pZeXtOpSiboPvKe2N4WOBx+VUNO8sHDIwAEgSWXbKbkk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1617954674; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=GmbZCzlnSYfl6+gzk6xYKEfw39JyFa7br4MyhA/z+I4=; b=b8pyO97rm54gX5JNvEqHut/IxBcdWK4EmEGB3Qmgho2zvBUPRCJ9gCafMnhvCtpZCZkNlXYpQLGVwexsSwq659iLvEEK4k6+pRfrQyHA/eiB1HhiXCRng5w+D3kZoY+h9fbTVI8JosevAD7yGAuVw82YrFjaJsgMIHHDLRWTWoE= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1617954674670675.5078574294338; Fri, 9 Apr 2021 00:51:14 -0700 (PDT) Received: from localhost ([::1]:33948 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lUlv7-0003xX-Ab for importer@patchew.org; Fri, 09 Apr 2021 03:51:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37562) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lUltf-0002HG-35; Fri, 09 Apr 2021 03:49:43 -0400 Received: from mail142-5.mail.alibaba.com ([198.11.142.5]:56791) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lUlta-0003ip-TZ; Fri, 09 Apr 2021 03:49:42 -0400 Received: from localhost.localdomain(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.JxL3BOG_1617954563) by smtp.aliyun-inc.com(10.147.40.7); Fri, 09 Apr 2021 15:49:26 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07436284|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.0509276-0.000424076-0.948648; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047201; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=6; RT=6; SR=0; TI=SMTPD_---.JxL3BOG_1617954563; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC PATCH 08/11] target/riscv: Update CSR xnxti in CLIC mode Date: Fri, 9 Apr 2021 15:48:54 +0800 Message-Id: <20210409074857.166082-9-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210409074857.166082-1-zhiwei_liu@c-sky.com> References: <20210409074857.166082-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=198.11.142.5; envelope-from=zhiwei_liu@c-sky.com; helo=mail142-5.mail.alibaba.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, Alistair.Francis@wdc.com, LIU Zhiwei , wxy194768@alibaba-inc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The CSR can be used by software to service the next horizontal interrupt when it has greater level than the saved interrupt context (held in xcause`.pil`) and greater level than the interrupt threshold of the corresponding privilege mode, Signed-off-by: LIU Zhiwei --- target/riscv/cpu_bits.h | 16 ++++++ target/riscv/csr.c | 114 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 130 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 7922097776..494e41edc9 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -166,6 +166,7 @@ #define CSR_MCAUSE 0x342 #define CSR_MTVAL 0x343 #define CSR_MIP 0x344 +#define CSR_MNXTI 0x345 /* clic-spec-draft */ #define CSR_MINTSTATUS 0x346 /* clic-spec-draft */ #define CSR_MINTTHRESH 0x347 /* clic-spec-draft */ =20 @@ -187,6 +188,7 @@ #define CSR_SCAUSE 0x142 #define CSR_STVAL 0x143 #define CSR_SIP 0x144 +#define CSR_SNXTI 0x145 /* clic-spec-draft */ #define CSR_SINTSTATUS 0x146 /* clic-spec-draft */ #define CSR_SINTTHRESH 0x147 /* clic-spec-draft */ =20 @@ -596,10 +598,24 @@ #define MINTSTATUS_SIL 0x0000ff00 /* sil[7:0] */ #define MINTSTATUS_UIL 0x000000ff /* uil[7:0] */ =20 +/* mcause */ +#define MCAUSE_MINHV 0x40000000 /* minhv */ +#define MCAUSE_MPP 0x30000000 /* mpp[1:0] */ +#define MCAUSE_MPIE 0x08000000 /* mpie */ +#define MCAUSE_MPIL 0x00ff0000 /* mpil[7:0] */ +#define MCAUSE_EXCCODE 0x00000fff /* exccode[11:0] */ + /* sintstatus */ #define SINTSTATUS_SIL 0x0000ff00 /* sil[7:0] */ #define SINTSTATUS_UIL 0x000000ff /* uil[7:0] */ =20 +/* scause */ +#define SCAUSE_SINHV 0x40000000 /* sinhv */ +#define SCAUSE_SPP 0x10000000 /* spp */ +#define SCAUSE_SPIE 0x08000000 /* spie */ +#define SCAUSE_SPIL 0x00ff0000 /* spil[7:0] */ +#define SCAUSE_EXCCODE 0x00000fff /* exccode[11:0] */ + /* MIE masks */ #define MIE_SEIE (1 << IRQ_S_EXT) #define MIE_UEIE (1 << IRQ_U_EXT) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index e12222b77f..72cba080bf 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -774,6 +774,80 @@ static int rmw_mip(CPURISCVState *env, int csrno, targ= et_ulong *ret_value, return 0; } =20 +static bool get_xnxti_status(CPURISCVState *env) +{ + CPUState *cs =3D env_cpu(env); + int clic_irq, clic_priv, clic_il, pil; + + if (!env->exccode) { /* No interrupt */ + return false; + } + /* The system is not in a CLIC mode */ + if (!riscv_clic_is_clic_mode(env)) { + return false; + } else { + riscv_clic_decode_exccode(env->exccode, &clic_priv, &clic_il, + &clic_irq); + + if (env->priv =3D=3D PRV_M) { + pil =3D MAX(get_field(env->mcause, MCAUSE_MPIL), env->mintthre= sh); + } else if (env->priv =3D=3D PRV_S) { + pil =3D MAX(get_field(env->scause, SCAUSE_SPIL), env->sintthre= sh); + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "CSR: rmw xnxti with unsupported mode\n"); + exit(1); + } + + if ((clic_priv !=3D env->priv) || /* No horizontal interrupt */ + (clic_il <=3D pil) || /* No higher level interrupt */ + (riscv_clic_shv_interrupt(env->clic, clic_priv, cs->cpu_index, + clic_irq))) { /* CLIC vector mode */ + return false; + } else { + return true; + } + } +} + +static int rmw_mnxti(CPURISCVState *env, int csrno, target_ulong *ret_valu= e, + target_ulong new_value, target_ulong write_mask) +{ + int clic_priv, clic_il, clic_irq; + bool ready; + CPUState *cs =3D env_cpu(env); + if (write_mask) { + env->mstatus |=3D new_value & (write_mask & 0b11111); + } + + qemu_mutex_lock_iothread(); + ready =3D get_xnxti_status(env); + if (ready) { + riscv_clic_decode_exccode(env->exccode, &clic_priv, &clic_il, + &clic_irq); + if (write_mask) { + bool edge =3D riscv_clic_edge_triggered(env->clic, clic_priv, + cs->cpu_index, clic_irq); + if (edge) { + riscv_clic_clean_pending(env->clic, clic_priv, + cs->cpu_index, clic_irq); + } + env->mintstatus =3D set_field(env->mintstatus, + MINTSTATUS_MIL, clic_il); + env->mcause =3D set_field(env->mcause, MCAUSE_EXCCODE, clic_ir= q); + } + if (ret_value) { + *ret_value =3D (env->mtvt & ~0x3f) + sizeof(target_ulong) * cl= ic_irq; + } + } else { + if (ret_value) { + *ret_value =3D 0; + } + } + qemu_mutex_unlock_iothread(); + return 0; +} + static int read_mintstatus(CPURISCVState *env, int csrno, target_ulong *va= l) { *val =3D env->mintstatus; @@ -982,6 +1056,44 @@ static int rmw_sip(CPURISCVState *env, int csrno, tar= get_ulong *ret_value, return ret; } =20 +static int rmw_snxti(CPURISCVState *env, int csrno, target_ulong *ret_valu= e, + target_ulong new_value, target_ulong write_mask) +{ + int clic_priv, clic_il, clic_irq; + bool ready; + CPUState *cs =3D env_cpu(env); + if (write_mask) { + env->mstatus |=3D new_value & (write_mask & 0b11111); + } + + qemu_mutex_lock_iothread(); + ready =3D get_xnxti_status(env); + if (ready) { + riscv_clic_decode_exccode(env->exccode, &clic_priv, &clic_il, + &clic_irq); + if (write_mask) { + bool edge =3D riscv_clic_edge_triggered(env->clic, clic_priv, + cs->cpu_index, clic_irq); + if (edge) { + riscv_clic_clean_pending(env->clic, clic_priv, + cs->cpu_index, clic_irq); + } + env->mintstatus =3D set_field(env->mintstatus, + MINTSTATUS_SIL, clic_il); + env->scause =3D set_field(env->scause, SCAUSE_EXCCODE, clic_ir= q); + } + if (ret_value) { + *ret_value =3D (env->stvt & ~0x3f) + sizeof(target_ulong) * cl= ic_irq; + } + } else { + if (ret_value) { + *ret_value =3D 0; + } + } + qemu_mutex_unlock_iothread(); + return 0; +} + static int read_sintstatus(CPURISCVState *env, int csrno, target_ulong *va= l) { target_ulong mask =3D SINTSTATUS_SIL | SINTSTATUS_UIL; @@ -1755,6 +1867,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { =20 /* Machine Mode Core Level Interrupt Controller */ [CSR_MTVT] =3D { "mtvt", clic, read_mtvt, write_mtvt }, + [CSR_MNXTI] =3D { "mnxti", clic, NULL, NULL, rmw_mnxti }, [CSR_MINTSTATUS] =3D { "mintstatus", clic, read_mintstatus }, [CSR_MINTTHRESH] =3D { "mintthresh", clic, read_mintthresh, write_mintthresh }, @@ -1766,6 +1879,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { =20 /* Supervisor Mode Core Level Interrupt Controller */ [CSR_STVT] =3D { "stvt", clic, read_stvt, write_stvt }, + [CSR_SNXTI] =3D { "snxti", clic, NULL, NULL, rmw_snxti }, =20 #endif /* !CONFIG_USER_ONLY */ }; --=20 2.25.1 From nobody Mon Apr 29 02:48:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=6; RT=6; SR=0; TI=SMTPD_---.JxL3BOG_1617954563; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC PATCH 09/11] target/riscv: Update CSR mclicbase in CLIC mode Date: Fri, 9 Apr 2021 15:48:55 +0800 Message-Id: <20210409074857.166082-10-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210409074857.166082-1-zhiwei_liu@c-sky.com> References: <20210409074857.166082-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=198.11.142.4; envelope-from=zhiwei_liu@c-sky.com; helo=mail142-4.mail.alibaba.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, Alistair.Francis@wdc.com, LIU Zhiwei , wxy194768@alibaba-inc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The machine mode mclicbase CSR is an XLEN-bit read-only register providing the base address of CLIC memory mapped registers. Signed-off-by: LIU Zhiwei Reviewed-by: Frank Chang --- hw/intc/riscv_clic.c | 1 + target/riscv/cpu.h | 1 + 2 files changed, 2 insertions(+) diff --git a/hw/intc/riscv_clic.c b/hw/intc/riscv_clic.c index 8ad534c506..e902dd4062 100644 --- a/hw/intc/riscv_clic.c +++ b/hw/intc/riscv_clic.c @@ -715,6 +715,7 @@ static void riscv_clic_realize(DeviceState *dev, Error = **errp) &cpu->env, 1); qdev_connect_gpio_out(dev, i, irq); cpu->env.clic =3D clic; + cpu->env.mclicbase =3D clic->mclicbase; } } =20 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index b5fd796f98..b0b8565649 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -162,6 +162,7 @@ struct CPURISCVState { uint32_t miclaim; uint32_t mintstatus; /* clic-spec */ target_ulong mintthresh; /* clic-spec */ + target_ulong mclicbase; /* clic-spec */ =20 target_ulong mie; target_ulong mideleg; --=20 2.25.1 From nobody Mon Apr 29 02:48:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1617954842; cv=none; d=zohomail.com; s=zohoarc; b=ff7J7nulL7sbX6Cfdk1vYsklZrlItPizwuKF3ewnLixgVMCH5SmZEhI+fBge8wFtpmtyvhvU+cVArOs6GUnKTEE5Yigt6SmMnsZS3acfc0hEK7nKVANjCmHfI6Z/vsJs+QnJRd/dvI+5MdqqaWdFvfcFd6cTMYSF2t8uq4tj4Vk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1617954842; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=W8SNtx0JRE1nQbQlarkp9NwVoadNer4FSqtKx4YZfn4=; b=bJTutgG0hEaHAaAuNzJMHaXNgiJTdb3UKSmNxrPIlemRl6DP/BARrTHqhweAOuUhGL7WW35TtVlCvzaXKSjKcnHVdXUV0IZxDvxkpVDycB7D0nDwYEXunHb1Ef6O4kqCj4Mu6J6tq0F5yoBi1+Kd/k4ABkLV0YGUomwVPW5SrSs= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 161795484236177.30443297071861; Fri, 9 Apr 2021 00:54:02 -0700 (PDT) Received: from localhost ([::1]:42378 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lUlxp-0007S2-D4 for importer@patchew.org; Fri, 09 Apr 2021 03:54:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37614) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lUlth-0002M9-Ja; Fri, 09 Apr 2021 03:49:45 -0400 Received: from mail142-23.mail.alibaba.com ([198.11.142.23]:30036) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lUltb-0003iu-0J; Fri, 09 Apr 2021 03:49:45 -0400 Received: from localhost.localdomain(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.JxL3BOG_1617954563) by smtp.aliyun-inc.com(10.147.40.7); Fri, 09 Apr 2021 15:49:26 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07436282|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.35297-0.00215807-0.644872; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047203; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=6; RT=6; SR=0; TI=SMTPD_---.JxL3BOG_1617954563; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC PATCH 10/11] target/riscv: Update interrupt handling in CLIC mode Date: Fri, 9 Apr 2021 15:48:56 +0800 Message-Id: <20210409074857.166082-11-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210409074857.166082-1-zhiwei_liu@c-sky.com> References: <20210409074857.166082-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=198.11.142.23; envelope-from=zhiwei_liu@c-sky.com; helo=mail142-23.mail.alibaba.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, Alistair.Francis@wdc.com, LIU Zhiwei , wxy194768@alibaba-inc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Decode CLIC interrupt information from exccode, includes interrupt priviledge mode, interrupt level, and irq number. Then update CSRs xcause, xstatus, xepc, xintstatus and jump to correct PC according to the CLIC specification. Signed-off-by: LIU Zhiwei --- target/riscv/cpu_bits.h | 1 + target/riscv/cpu_helper.c | 117 +++++++++++++++++++++++++++++++++++--- 2 files changed, 111 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 494e41edc9..d8378d2384 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -557,6 +557,7 @@ #define RISCV_EXCP_VIRT_INSTRUCTION_FAULT 0x16 #define RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT 0x17 =20 +#define RISCV_EXCP_INT_CLIC 0x40000000 #define RISCV_EXCP_INT_FLAG 0x80000000 #define RISCV_EXCP_INT_MASK 0x7fffffff =20 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 21c54ef561..998d1a2742 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -26,6 +26,10 @@ #include "trace.h" #include "semihosting/common-semi.h" =20 +#if !defined(CONFIG_USER_ONLY) +#include "hw/intc/riscv_clic.h" +#endif + int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) { #ifdef CONFIG_USER_ONLY @@ -36,6 +40,20 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) } =20 #ifndef CONFIG_USER_ONLY +static int riscv_cpu_local_irq_mode_enabled(CPURISCVState *env, int mode) +{ + switch (mode) { + case PRV_M: + return env->priv < PRV_M || + (env->priv =3D=3D PRV_M && get_field(env->mstatus, MSTATUS_= MIE)); + case PRV_S: + return env->priv < PRV_S || + (env->priv =3D=3D PRV_S && get_field(env->mstatus, MSTATUS_= SIE)); + default: + return false; + } +} + static int riscv_cpu_local_irq_pending(CPURISCVState *env) { target_ulong irqs; @@ -90,6 +108,18 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int interru= pt_request) return true; } } + if (interrupt_request & CPU_INTERRUPT_CLIC) { + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + int mode =3D (env->exccode >> 12) & 0b11; + int enabled =3D riscv_cpu_local_irq_mode_enabled(env, mode); + if (enabled) { + cs->exception_index =3D RISCV_EXCP_INT_CLIC | env->exccode; + cs->interrupt_request =3D cs->interrupt_request & ~CPU_INTERRU= PT_CLIC; + riscv_cpu_do_interrupt(cs); + return true; + } + } #endif return false; } @@ -884,6 +914,55 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, #endif } =20 + +#if !defined(CONFIG_USER_ONLY) +static target_ulong riscv_intr_pc(CPURISCVState *env, target_ulong tvec, + target_ulong tvt, bool async, bool clic, + int cause, int mode) +{ + int mode1 =3D tvec & 0b11, mode2 =3D tvec & 0b111111; + CPUState *cs =3D env_cpu(env); + + if (!(async || clic)) { + return tvec & ~0b11; + } + /* bits [1:0] encode mode; 0 =3D direct, 1 =3D vectored, 2 >=3D reserv= ed */ + switch (mode1) { + case 0b00: + return tvec & ~0b11; + case 0b01: + return (tvec & ~0b11) + cause * 4; + default: + if (env->clic && (mode2 =3D=3D 0b000011)) { + /* Non-vectored, clicintattr[i].shv =3D 0 || cliccfg.nvbits = =3D 0 */ + if (!riscv_clic_shv_interrupt(env->clic, mode, cs->cpu_index, + cause)) { + /* NBASE =3D mtvec[XLEN-1:6]<<6 */ + return tvec & ~0b111111; + } else { + /* + * pc :=3D M[TBASE + XLEN/8 * exccode)] & ~1, + * TBASE =3D mtvt[XLEN-1:6]<<6 + */ + int size =3D TARGET_LONG_BITS / 8; + target_ulong tbase =3D (tvt & ~0b111111) + size * cause; + void *host =3D tlb_vaddr_to_host(env, tbase, MMU_DATA_LOAD= , mode); + if (host !=3D NULL) { + target_ulong new_pc =3D ldn_p(host, size); + if (tlb_vaddr_to_host(env, new_pc, MMU_INST_FETCH, mod= e)) { + return new_pc; + } + } + qemu_log_mask(LOG_GUEST_ERROR, + "CLIC: load trap handler error!\n"); + exit(1); + } + } + g_assert_not_reached(); + } +} +#endif + /* * Handle Traps * @@ -898,11 +977,13 @@ void riscv_cpu_do_interrupt(CPUState *cs) CPURISCVState *env =3D &cpu->env; bool force_hs_execp =3D riscv_cpu_force_hs_excep_enabled(env); uint64_t s; + int mode, level; =20 /* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide * so we mask off the MSB and separate into trap type and cause. */ bool async =3D !!(cs->exception_index & RISCV_EXCP_INT_FLAG); + bool clic =3D !!(cs->exception_index & RISCV_EXCP_INT_CLIC); target_ulong cause =3D cs->exception_index & RISCV_EXCP_INT_MASK; target_ulong deleg =3D async ? env->mideleg : env->medeleg; bool write_tval =3D false; @@ -958,6 +1039,28 @@ void riscv_cpu_do_interrupt(CPUState *cs) } } =20 + if (clic) { + mode =3D (cause >> 12) & 3; + level =3D (cause >> 14) & 0xff; + cause &=3D 0xfff; + cause |=3D get_field(env->mstatus, MSTATUS_MPP) << 28; + switch (mode) { + case PRV_M: + cause |=3D get_field(env->mintstatus, MINTSTATUS_MIL) << 16; + cause |=3D get_field(env->mstatus, MSTATUS_MIE) << 27; + env->mintstatus =3D set_field(env->mintstatus, MINTSTATUS_MIL,= level); + break; + case PRV_S: + cause |=3D get_field(env->mintstatus, MINTSTATUS_SIL) << 16; + cause |=3D get_field(env->mstatus, MSTATUS_SPIE) << 27; + env->mintstatus =3D set_field(env->mintstatus, MINTSTATUS_SIL,= level); + break; + } + } else { + mode =3D env->priv <=3D PRV_S && + cause < TARGET_LONG_BITS && ((deleg >> cause) & 1) ? PRV_S : P= RV_M; + } + trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, riscv_cpu_get_trap_name(cause, async)); =20 @@ -967,8 +1070,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) __func__, env->mhartid, async, cause, env->pc, tval, riscv_cpu_get_trap_name(cause, async)); =20 - if (env->priv <=3D PRV_S && - cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) { + if (mode =3D=3D PRV_S) { /* handle the trap in S-mode */ if (riscv_has_ext(env, RVH)) { target_ulong hdeleg =3D async ? env->hideleg : env->hedeleg; @@ -1021,12 +1123,13 @@ void riscv_cpu_do_interrupt(CPUState *cs) s =3D set_field(s, MSTATUS_SPP, env->priv); s =3D set_field(s, MSTATUS_SIE, 0); env->mstatus =3D s; - env->scause =3D cause | ((target_ulong)async << (TARGET_LONG_BITS = - 1)); + env->scause =3D cause | ((target_ulong)(async | clic) << + (TARGET_LONG_BITS - 1)); env->sepc =3D env->pc; env->sbadaddr =3D tval; env->htval =3D htval; - env->pc =3D (env->stvec >> 2 << 2) + - ((async && (env->stvec & 3) =3D=3D 1) ? cause * 4 : 0); + env->pc =3D riscv_intr_pc(env, env->stvec, env->stvt, async, + clic & 0xfff, cause, PRV_S); riscv_cpu_set_mode(env, PRV_S); } else { /* handle the trap in M-mode */ @@ -1056,8 +1159,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) env->mepc =3D env->pc; env->mbadaddr =3D tval; env->mtval2 =3D mtval2; - env->pc =3D (env->mtvec >> 2 << 2) + - ((async && (env->mtvec & 3) =3D=3D 1) ? cause * 4 : 0); + env->pc =3D riscv_intr_pc(env, env->mtvec, env->mtvt, async, + clic, cause & 0xfff, PRV_M); riscv_cpu_set_mode(env, PRV_M); } =20 --=20 2.25.1 From nobody Mon Apr 29 02:48:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1617954927; cv=none; d=zohomail.com; s=zohoarc; b=dYJyI3dllR4f+QFwxOlLLaAFGrFXjmdfrlZ8ObJbUM8X3C+4x6/NCcP8SutpSFRDfIwvcuxdIxDn9GLibPEJb87bkEpeBsoHcM0QgfTBaWS4gV5dO9l/D2A++c7fYvKaNo8xj6GJppa0L5PyzxHA/j7PProsEPQwPDfH5AMHI6E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1617954927; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ue3aMX7Eep3/qKYXkhM0p8T6kFlgJLE19k3C0KtQEHI=; b=HER7cUE0q5c4cYP6CquIx8cZxgL2zOG7ytaxRPaQurEo/oQOI6FWhYL6v5BQhLt+i7ZHWNKALfyrGR1TLxdYirslo41NMyVaeSrvOx4aMMjWNzK4RqZVkkeVhTesMpl6pV9iXwG6e/sxbTx7T75Fp89vNLN9Ml5DHDb3PII2DZc= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1617954927511823.4135552037359; Fri, 9 Apr 2021 00:55:27 -0700 (PDT) Received: from localhost ([::1]:48866 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lUlzC-0001dD-Fu for importer@patchew.org; Fri, 09 Apr 2021 03:55:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37648) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lUltj-0002RY-Bj; Fri, 09 Apr 2021 03:49:47 -0400 Received: from mail142-25.mail.alibaba.com ([198.11.142.25]:27055) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lUltb-0003jh-Gv; Fri, 09 Apr 2021 03:49:47 -0400 Received: from localhost.localdomain(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.JxL3BOG_1617954563) by smtp.aliyun-inc.com(10.147.40.7); Fri, 09 Apr 2021 15:49:26 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07700841|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.15412-0.00058156-0.845299; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047204; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=6; RT=6; SR=0; TI=SMTPD_---.JxL3BOG_1617954563; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC PATCH 11/11] target/riscv: Update interrupt return in CLIC mode Date: Fri, 9 Apr 2021 15:48:57 +0800 Message-Id: <20210409074857.166082-12-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210409074857.166082-1-zhiwei_liu@c-sky.com> References: <20210409074857.166082-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=198.11.142.25; envelope-from=zhiwei_liu@c-sky.com; helo=mail142-25.mail.alibaba.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, Alistair.Francis@wdc.com, LIU Zhiwei , wxy194768@alibaba-inc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" When a vectored interrupt is selected and serviced, the hardware will automatically clear the corresponding pending bit in edge-triggered mode. This may lead to a lower priviledge interrupt pending forever. Therefore when interrupts return, pull a pending interrupt to service. Signed-off-by: LIU Zhiwei --- target/riscv/op_helper.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 1eddcb94de..42563b22ba 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -24,6 +24,10 @@ #include "exec/exec-all.h" #include "exec/helper-proto.h" =20 +#if !defined(CONFIG_USER_ONLY) +#include "hw/intc/riscv_clic.h" +#endif + /* Exceptions processing helpers */ void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env, uint32_t exception, uintptr_t pc) @@ -130,6 +134,17 @@ target_ulong helper_sret(CPURISCVState *env, target_ul= ong cpu_pc_deb) mstatus =3D set_field(mstatus, MSTATUS_SPIE, 1); mstatus =3D set_field(mstatus, MSTATUS_SPP, PRV_U); env->mstatus =3D mstatus; + + if (riscv_clic_is_clic_mode(env)) { + CPUState *cs =3D env_cpu(env); + target_ulong spil =3D get_field(env->scause, SCAUSE_SPIL); + env->mintstatus =3D set_field(env->mintstatus, MINTSTATUS_SIL,= spil); + env->scause =3D set_field(env->scause, SCAUSE_SPIE, 0); + env->scause =3D set_field(env->scause, SCAUSE_SPP, PRV_U); + qemu_mutex_lock_iothread(); + riscv_clic_get_next_interrupt(env->clic, cs->cpu_index); + qemu_mutex_unlock_iothread(); + } } =20 riscv_cpu_set_mode(env, prev_priv); @@ -172,6 +187,16 @@ target_ulong helper_mret(CPURISCVState *env, target_ul= ong cpu_pc_deb) riscv_cpu_set_virt_enabled(env, prev_virt); } =20 + if (riscv_clic_is_clic_mode(env)) { + CPUState *cs =3D env_cpu(env); + target_ulong mpil =3D get_field(env->mcause, MCAUSE_MPIL); + env->mintstatus =3D set_field(env->mintstatus, MINTSTATUS_MIL, mpi= l); + env->mcause =3D set_field(env->mcause, MCAUSE_MPIE, 0); + env->mcause =3D set_field(env->mcause, MCAUSE_MPP, PRV_U); + qemu_mutex_lock_iothread(); + riscv_clic_get_next_interrupt(env->clic, cs->cpu_index); + qemu_mutex_unlock_iothread(); + } return retpc; } =20 --=20 2.25.1