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[174.52.16.57]) by smtp.gmail.com with ESMTPSA id 11sm1818393ilg.53.2021.04.07.17.20.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Apr 2021 17:20:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zwZq+t97SgnMqyfF6b0pI8SyhVaDvItExYxxm1cmwZM=; b=UkXf6WMZ/8gbFj6jsxmC5nVJkvNhIOCWNpXSjU5hNx+g0DkBrSfDFg45hZGRnbkRdi unGCBUSWHDgRObSLaMUrYquob1XPTNLVfD5aSaGggbh1qX1RAZO+Mwg/p72EAAn8dP3r dPbIOJVV1esvByWBc2iJO5QL+OZ2mgMU0/+UIQikOmhW/6B0ZiIIlEpXJ7U0MKBE6QLT +Qlq5j3ohxd/bntYCmOr/Bw7MQfFk3UicZFLcveNj08638tyX/1i1VE4c/KuPyZdrvYe u6VNrrzCkFo+HhA2VpPW2QCSHc2+Ag2VaQoum574qrZDgEOeAsdkflLtaA+1/KFXNO61 fAjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zwZq+t97SgnMqyfF6b0pI8SyhVaDvItExYxxm1cmwZM=; b=HUk7O7EkF8X8Xaq47hrbuBmcHfvXyUvp3EZgjhTJ4Nj3KG0+b9B+/JszwWsauFQjlY O8Tt0RLZWVNvQH1DVYZ51HS5WrKpsgCJ9Doy+D6MK48uMBCFG7wi45Nx/K6U3x1u8l3V wXtCfUDNp/vao3CN/ODFloAATi06/ZFTUCl/TltWcMI5TcC2yOtpfOYmyfFaaSVHrwzr 70Zop5CbL8OG7s/GKZKmn+N3gtH8wF5Xs5mYvUB6/ozEZoRgy9Cu3IGXYsr/1fYuq4+J pU8e6EJ1rcbWDjTYpRmUFL0ICv0wO5ny9H5JNalWPMLprvtqXG6eBg4va3GSIJq8p1RC l6dQ== X-Gm-Message-State: AOAM531Q3MbgGz/cieFlbQwg3ZLcL6Rpj0j137r6+DPeBIl1rMLN36zf W2+guQlDAQLzGeVpZ5lV0vCgPQ== X-Google-Smtp-Source: ABdhPJyTbw/z3g/tJrCstfT/0GsRiua5ykB4l8KuilMzq4xkLeKRPW6N8MYJ0d4ZGPzrWyEs0HbA3A== X-Received: by 2002:a05:6e02:13e2:: with SMTP id w2mr4633285ilj.233.1617841252617; Wed, 07 Apr 2021 17:20:52 -0700 (PDT) From: Rebecca Cran To: peter.maydell@linaro.org, richard.henderson@linaro.org Subject: [PATCH v6 1/4] accel/tcg: Add TLB invalidation support for ranges of addresses Date: Wed, 7 Apr 2021 18:20:36 -0600 Message-Id: <20210408002039.18027-2-rebecca@nuviainc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210408002039.18027-1-rebecca@nuviainc.com> References: <20210408002039.18027-1-rebecca@nuviainc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::12c; envelope-from=rebecca@nuviainc.com; helo=mail-il1-x12c.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rebecca Cran , qemu-devel@nongnu.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Add functions to support the FEAT_TLBIRANGE ARMv8.4 feature that adds TLB invalidation instructions to invalidate ranges of addresses. Signed-off-by: Rebecca Cran --- accel/tcg/cputlb.c | 130 +++++++++++++++++++- include/exec/exec-all.h | 46 +++++++ 2 files changed, 173 insertions(+), 3 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 8a7b779270a4..dc44967dcf8e 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -709,7 +709,7 @@ void tlb_flush_page_all_cpus_synced(CPUState *src, targ= et_ulong addr) tlb_flush_page_by_mmuidx_all_cpus_synced(src, addr, ALL_MMUIDX_BITS); } =20 -static void tlb_flush_page_bits_locked(CPUArchState *env, int midx, +static bool tlb_flush_page_bits_locked(CPUArchState *env, int midx, target_ulong page, unsigned bits) { CPUTLBDesc *d =3D &env_tlb(env)->d[midx]; @@ -729,7 +729,7 @@ static void tlb_flush_page_bits_locked(CPUArchState *en= v, int midx, TARGET_FMT_lx "/" TARGET_FMT_lx ")\n", midx, page, mask); tlb_flush_one_mmuidx_locked(env, midx, get_clock_realtime()); - return; + return true; } =20 /* Check if we need to flush due to large pages. */ @@ -738,13 +738,14 @@ static void tlb_flush_page_bits_locked(CPUArchState *= env, int midx, TARGET_FMT_lx "/" TARGET_FMT_lx ")\n", midx, d->large_page_addr, d->large_page_mask); tlb_flush_one_mmuidx_locked(env, midx, get_clock_realtime()); - return; + return true; } =20 if (tlb_flush_entry_mask_locked(tlb_entry(env, midx, page), page, mask= )) { tlb_n_used_entries_dec(env, midx); } tlb_flush_vtlb_page_mask_locked(env, midx, page, mask); + return false; } =20 typedef struct { @@ -943,6 +944,129 @@ void tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CP= UState *src_cpu, } } =20 +typedef struct { + target_ulong addr; + target_ulong length; + uint16_t idxmap; + uint16_t bits; +} TLBFlushPageRangeBitsByMMUIdxData; + +static void +tlb_flush_page_range_bits_by_mmuidx_async_0(CPUState *cpu, + target_ulong addr, + target_ulong length, + uint16_t idxmap, + unsigned bits) +{ + CPUArchState *env =3D cpu->env_ptr; + int mmu_idx; + target_ulong l; + target_ulong page =3D addr; + bool full_flush; + + assert_cpu_is_self(cpu); + + tlb_debug("page addr:" TARGET_FMT_lx "/%u len: " TARGET_FMT_lx + " mmu_map:0x%x\n", + addr, bits, length, idxmap); + + qemu_spin_lock(&env_tlb(env)->c.lock); + for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { + if ((idxmap >> mmu_idx) & 1) { + for (l =3D 0; l < length; l +=3D TARGET_PAGE_SIZE) { + page =3D addr + l; + full_flush =3D tlb_flush_page_bits_locked(env, mmu_idx, + page, bits); + if (full_flush) { + break; + } + } + } + } + qemu_spin_unlock(&env_tlb(env)->c.lock); + + for (l =3D 0; l < length; l +=3D TARGET_PAGE_SIZE) { + tb_flush_jmp_cache(cpu, page); + } +} + +static void +tlb_flush_page_range_bits_by_mmuidx_async_1(CPUState *cpu, + run_on_cpu_data data) +{ + TLBFlushPageRangeBitsByMMUIdxData *d =3D data.host_ptr; + + tlb_flush_page_range_bits_by_mmuidx_async_0(cpu, d->addr, d->length, + d->idxmap, d->bits); + + g_free(d); +} + +void tlb_flush_page_range_bits_by_mmuidx(CPUState *cpu, + target_ulong addr, + target_ulong length, + uint16_t idxmap, + unsigned bits) +{ + TLBFlushPageRangeBitsByMMUIdxData d; + TLBFlushPageRangeBitsByMMUIdxData *p; + + /* This should already be page aligned */ + addr &=3D TARGET_PAGE_BITS; + + d.addr =3D addr & TARGET_PAGE_MASK; + d.idxmap =3D idxmap; + d.bits =3D bits; + d.length =3D length; + + if (qemu_cpu_is_self(cpu)) { + tlb_flush_page_range_bits_by_mmuidx_async_0(cpu, addr, length, + idxmap, bits); + } else { + p =3D g_new(TLBFlushPageRangeBitsByMMUIdxData, 1); + + /* Allocate a structure, freed by the worker. */ + *p =3D d; + async_run_on_cpu(cpu, tlb_flush_page_range_bits_by_mmuidx_async_1, + RUN_ON_CPU_HOST_PTR(p)); + } +} + +void tlb_flush_page_range_bits_by_mmuidx_all_cpus_synced(CPUState *src_cpu, + target_ulong addr, + target_ulong leng= th, + uint16_t idxmap, + unsigned bits) +{ + TLBFlushPageRangeBitsByMMUIdxData d; + TLBFlushPageRangeBitsByMMUIdxData *p; + CPUState *dst_cpu; + + /* This should already be page aligned */ + addr &=3D TARGET_PAGE_BITS; + + d.addr =3D addr; + d.idxmap =3D idxmap; + d.bits =3D bits; + d.length =3D length; + + /* Allocate a separate data block for each destination cpu. */ + CPU_FOREACH(dst_cpu) { + if (dst_cpu !=3D src_cpu) { + p =3D g_new(TLBFlushPageRangeBitsByMMUIdxData, 1); + *p =3D d; + async_run_on_cpu(dst_cpu, + tlb_flush_page_range_bits_by_mmuidx_async_1, + RUN_ON_CPU_HOST_PTR(p)); + } + } + + p =3D g_new(TLBFlushPageRangeBitsByMMUIdxData, 1); + *p =3D d; + async_safe_run_on_cpu(src_cpu, tlb_flush_page_range_bits_by_mmuidx_asy= nc_1, + RUN_ON_CPU_HOST_PTR(p)); +} + /* update the TLBs so that writes to code in the virtual page 'addr' can be detected */ void tlb_protect_code(ram_addr_t ram_addr) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 6b036cae8f65..a7ff35efb865 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -212,6 +212,37 @@ void tlb_flush_page_by_mmuidx_all_cpus(CPUState *cpu, = target_ulong addr, */ void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, target_ulong = addr, uint16_t idxmap); +/** + * tlb_flush_page_range_by_mmuidx: + * @cpu: CPU whose TLB should be flushed + * @addr: virtual address of start of page range to be flushed + * @length: the number of bytes to be flushed + * @idxmap: bitmap of MMU indexes to flush + * + * Flush a range of pages from the TLB of the specified CPU, for the speci= fied + * MMU indexes. + */ +void tlb_flush_page_range_bits_by_mmuidx(CPUState *cpu, target_ulong addr, + target_ulong length, uint16_t idx= map, + unsigned bits); +/** + * tlb_flush_page_range_by_mmuidx_all_cpus_synced: + * @cpu: Originating CPU of the flush + * @addr: virtual address of start of page range to be flushed + * @length: the number of bytes to be flushed + * @idxmap: bitmap of MMU indexes to flush + * + * Flush a range of pages from the TLB of all CPUs, for the specified MMU + * indexes like tlb_flush_page_by_mmuidx_all_cpus except the source + * vCPUs work is scheduled as safe work meaning all flushes will be + * complete once the source vCPUs safe work is complete. This will + * depend on when the guests translation ends the TB. + */ +void tlb_flush_page_range_bits_by_mmuidx_all_cpus_synced(CPUState *cpu, + target_ulong addr, + target_ulong leng= th, + uint16_t idxmap, + unsigned bits); /** * tlb_flush_by_mmuidx: * @cpu: CPU whose TLB should be flushed @@ -313,6 +344,21 @@ static inline void tlb_flush_page_all_cpus_synced(CPUS= tate *src, target_ulong addr) { } +static inline void tlb_flush_page_range_bits_by_mmuidx(CPUState *cpu, + target_ulong addr, + target_ulong length, + uint16_t idxmap, + unsigned bits) +{ +} +static inline void +tlb_flush_page_range_bits_by_mmuidx_all_cpus_synced(CPUState *src_cpu, + target_ulong addr, + target_ulong length, + uint16_t idxmap, + unsigned bits) +{ +} static inline void tlb_flush(CPUState *cpu) { } --=20 2.26.2 From nobody Thu Apr 18 16:14:40 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1617841388; cv=none; d=zohomail.com; s=zohoarc; b=QC62WJUIzdBJoPVnxEkwVfxAtlxU1+YUN8z5lFVejsOZ42lwIaXOUZFd9ntstZRfXA04JYigLUW949rmloey5OQvy1/XhGsBGY9dyz0VvH9xXTXI3IDUcMuGH0GT+OvTozlzkvwDjITm0ri11IQr9XZ9+HEEDgLRqJW7CTez1vE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1617841388; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=S00jNqe5qwvG10WP/V0cTf/NyHRWwWBdToA8oYUTOt4=; b=MnSRqiumPgF4Xu4cUy9HUru9nNwNwoUEXfo64xaf59F+RP3Ep+Nj1pRFqRa7FeMHb0B/booi8WcG6fUuzpF9/3LIHT/rIglglW9Opo0ovlbIq0zxF1LxW1QoUARC0wvgRXTSGbuwdgtC0z8inDzhV7SWtChNtdUfzGH0E2ov0LI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1617841388739735.3544432569508; Wed, 7 Apr 2021 17:23:08 -0700 (PDT) Received: from localhost ([::1]:50016 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lUIRv-0006sl-LM for importer@patchew.org; Wed, 07 Apr 2021 20:23:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46832) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lUIPw-0005Ec-J9 for qemu-devel@nongnu.org; Wed, 07 Apr 2021 20:21:04 -0400 Received: from mail-il1-x135.google.com ([2607:f8b0:4864:20::135]:40763) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lUIPm-0002du-N3 for qemu-devel@nongnu.org; Wed, 07 Apr 2021 20:21:02 -0400 Received: by mail-il1-x135.google.com with SMTP id c18so278500iln.7 for ; Wed, 07 Apr 2021 17:20:54 -0700 (PDT) Received: from cube.nuviainc.com (c-174-52-16-57.hsd1.ut.comcast.net. [174.52.16.57]) by smtp.gmail.com with ESMTPSA id 11sm1818393ilg.53.2021.04.07.17.20.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Apr 2021 17:20:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=S00jNqe5qwvG10WP/V0cTf/NyHRWwWBdToA8oYUTOt4=; b=pNbgwKXvwPL2R8V9r6Q4m0hNcx/euIxIeLWt6ba1TBI+5gM28mcNU5jwGJ4HRKWoAg 4UavdPjecWWEsCOPjVDVtFm852CvPM3uiO0VZcurXyaR5a3sjwttsqNcozZ8Omw4q+Q0 EXMWSaA2yg1nmTiYnMJy8CtK/bVEx0rGwLsPJ1OOSfWgVhqvCIyX5FGzrq49u838rebM 5ASM6/fcAxoca9zAV052WPiyc8cWSS8haAutd+crZ9/z2P9KhQOAIhneQd7DFo574yXh BhXQlUzfV1y8iPD3KOUdu75VjurgKl5ITyknOvh5LhJ58sZUN89LSXBLd46oWbNUstW/ ba6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=S00jNqe5qwvG10WP/V0cTf/NyHRWwWBdToA8oYUTOt4=; b=UxmRLOpoJaRX3LG7nknYxAvYLMtTRzTHDxf856bNVS9ARDz5v1rFZzpicIM/W/Yr9y olFL4j4JkQ/u5Jq/8w/l3zkhsTChBMhGlK4s8Q9WmFkHtjDGAMY1A+0odjXLtekvMf1q +miJE3yMnDXxEcOAGgflKb8qvFmKTp2pF0JyW4yVFJUaqDVWgjeJF/BVBw8zyyXi9SOJ Ko1s1rTsWYfkm0hni5YDEAwWUSvA1LkRYDZ+AI3c5qeLt6J8zQf6e0K/CG1HAtSwx8TQ LF7tgI8xtOhKFYDIRHzr61k5S13UK5pMqhaMJKvwslhWabO6Lrs2x5jnj7OuZFWA7F7t FZUA== X-Gm-Message-State: AOAM533FQFKtd0pme0UC9LHkY4tYHQrVNs9FOnTDPmQjX/xibRvXEELj Swgzu/z3BTSXu6hti2HcBD8ktA== X-Google-Smtp-Source: ABdhPJyBaTEGZWJI2ONWqN2OUsF3IZu6NR88fGolTA+42XdnsLtGBglsyDojfqJhJud4GZYSwgJsuA== X-Received: by 2002:a05:6e02:1a68:: with SMTP id w8mr5028288ilv.129.1617841253635; Wed, 07 Apr 2021 17:20:53 -0700 (PDT) From: Rebecca Cran To: peter.maydell@linaro.org, richard.henderson@linaro.org Subject: [PATCH v6 2/4] target/arm: Add support for FEAT_TLBIRANGE Date: Wed, 7 Apr 2021 18:20:37 -0600 Message-Id: <20210408002039.18027-3-rebecca@nuviainc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210408002039.18027-1-rebecca@nuviainc.com> References: <20210408002039.18027-1-rebecca@nuviainc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::135; envelope-from=rebecca@nuviainc.com; helo=mail-il1-x135.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rebecca Cran , qemu-devel@nongnu.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" ARMv8.4 adds the mandatory FEAT_TLBIRANGE. It provides TLBI maintenance instructions that apply to a range of input addresses. Signed-off-by: Rebecca Cran --- target/arm/cpu.h | 5 + target/arm/helper.c | 294 ++++++++++++++++++++ 2 files changed, 299 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 193a49ec7fac..32b78a4ef587 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -4038,6 +4038,11 @@ static inline bool isar_feature_aa64_pauth_arch(cons= t ARMISARegisters *id) return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) !=3D 0; } =20 +static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) =3D=3D 2; +} + static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) !=3D 0; diff --git a/target/arm/helper.c b/target/arm/helper.c index d9220be7c5a0..ce913deff490 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4759,6 +4759,217 @@ static void tlbi_aa64_vae3is_write(CPUARMState *env= , const ARMCPRegInfo *ri, ARMMMUIdxBit_SE3, bits); } =20 +#ifdef TARGET_AARCH64 +static uint64_t tlbi_aa64_range_get_length(CPUARMState *env, + uint64_t value) +{ + unsigned int page_shift; + unsigned int page_size_granule; + uint64_t num; + uint64_t scale; + uint64_t exponent; + uint64_t length; + + num =3D extract64(value, 39, 4); + scale =3D extract64(value, 44, 2); + page_size_granule =3D extract64(value, 46, 2); + + page_shift =3D page_size_granule * 2 + 10; + + if (page_size_granule =3D=3D 0) { + qemu_log_mask(LOG_GUEST_ERROR, "Invalid page size granule %d\n", + page_size_granule); + return 0; + } + + exponent =3D (5 * scale) + 1; + length =3D (num + 1) << (exponent + page_shift); + + return length; +} + +static void tlbi_aa64_rvae1_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* + * Invalidate by VA range, EL1&0. + * Currently handles all of RVAE1, RVAAE1, RVAALE1 and RVALE1, + * since we don't support flush-for-specific-ASID-only or + * flush-last-level-only. + */ + ARMMMUIdx mask; + int bits; + uint64_t pageaddr; + uint64_t length; + + CPUState *cs =3D env_cpu(env); + mask =3D vae1_tlbmask(env); + if (regime_has_2_ranges(ctz32(mask))) { + pageaddr =3D sextract64(value, 0, 37) << TARGET_PAGE_BITS; + } else { + pageaddr =3D extract64(value, 0, 37) << TARGET_PAGE_BITS; + } + length =3D tlbi_aa64_range_get_length(env, value); + bits =3D tlbbits_for_regime(env, mask, pageaddr); + + if (tlb_force_broadcast(env)) { + tlb_flush_page_range_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, + length, mask, + bits); + } else { + tlb_flush_page_range_bits_by_mmuidx(cs, pageaddr, length, mask, + bits); + } +} + +static void tlbi_aa64_rvae1is_write(CPUARMState *env, const ARMCPRegInfo *= ri, + uint64_t value) +{ + /* + * Invalidate by VA range, Inner/Outer Shareable EL1&0. + * Currently handles all of RVAE1IS, RVAE1OS, RVAAE1IS, RVAAE1OS, + * RVAALE1IS, RVAALE1OS, RVALE1IS and RVALE1OS, since we don't support + * flush-for-specific-ASID-only, flush-last-level-only or inner/outer + * shareable specific flushes. + */ + ARMMMUIdx mask; + int bits; + uint64_t pageaddr; + uint64_t length; + + CPUState *cs =3D env_cpu(env); + mask =3D vae1_tlbmask(env); + if (regime_has_2_ranges(ctz32(mask))) { + pageaddr =3D sextract64(value, 0, 37) << TARGET_PAGE_BITS; + } else { + pageaddr =3D extract64(value, 0, 37) << TARGET_PAGE_BITS; + } + length =3D tlbi_aa64_range_get_length(env, value); + bits =3D tlbbits_for_regime(env, mask, pageaddr); + + tlb_flush_page_range_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, + length, mask, + bits); +} + +static void tlbi_aa64_rvae2_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* + * Invalidate by VA range, EL2. + * Currently handles all of RVAE2, RVAAE2, RVAALE2 and RVALE2, + * since we don't support flush-for-specific-ASID-only or + * flush-last-level-only. + */ + ARMMMUIdx mask; + bool secure; + int bits; + uint64_t pageaddr; + uint64_t length; + + CPUState *cs =3D env_cpu(env); + secure =3D arm_is_secure_below_el3(env); + pageaddr =3D extract64(value, 0, 37) << TARGET_PAGE_BITS; + length =3D tlbi_aa64_range_get_length(env, value); + mask =3D secure ? ARMMMUIdxBit_SE2 : ARMMMUIdxBit_E2; + bits =3D tlbbits_for_regime(env, secure ? ARMMMUIdx_SE2 : ARMMMUIdx_E2, + pageaddr); + + if (tlb_force_broadcast(env)) { + tlb_flush_page_range_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, + length, mask, + bits); + } else { + tlb_flush_page_range_bits_by_mmuidx(cs, pageaddr, length, mask, + bits); + } +} + +static void tlbi_aa64_rvae2is_write(CPUARMState *env, const ARMCPRegInfo *= ri, + uint64_t value) +{ + /* + * Invalidate by VA range, Inner/Outer Shareable, EL2. + * Currently handles all of RVAE2IS, RVAE2OS, RVAAE2IS, RVAAE2OS, + * RVAALE2IS, RVAALE2OS, RVALE2IS and RVALE2OS, since we don't support + * flush-for-specific-ASID-only, flush-last-level-only or inner/outer + * shareable specific flushes. + */ + ARMMMUIdx mask; + bool secure; + int bits; + uint64_t pageaddr; + uint64_t length; + + CPUState *cs =3D env_cpu(env); + secure =3D arm_is_secure_below_el3(env); + pageaddr =3D extract64(value, 0, 37) << TARGET_PAGE_BITS; + length =3D tlbi_aa64_range_get_length(env, value); + mask =3D secure ? ARMMMUIdxBit_SE2 : ARMMMUIdxBit_E2; + bits =3D tlbbits_for_regime(env, secure ? ARMMMUIdx_SE2 : ARMMMUIdx_E2, + pageaddr); + + tlb_flush_page_range_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, + length, mask, + bits); +} + +static void tlbi_aa64_rvae3_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* + * Invalidate by VA range, EL3. + * Currently handles all of RVAE3, RVAAE3, RVAALE3 and RVALE3, + * since we don't support flush-for-specific-ASID-only or + * flush-last-level-only. + */ + int bits; + uint64_t pageaddr; + uint64_t length; + + CPUState *cs =3D env_cpu(env); + pageaddr =3D extract64(value, 0, 37) << TARGET_PAGE_BITS; + length =3D tlbi_aa64_range_get_length(env, value); + bits =3D tlbbits_for_regime(env, ARMMMUIdx_SE3, pageaddr); + + if (tlb_force_broadcast(env)) { + tlb_flush_page_range_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, + length, + ARMMMUIdxBit_S= E3, + bits); + } else { + tlb_flush_page_range_bits_by_mmuidx(cs, pageaddr, length, + ARMMMUIdxBit_SE3, + bits); + } +} + +static void tlbi_aa64_rvae3is_write(CPUARMState *env, const ARMCPRegInfo *= ri, + uint64_t value) +{ + /* + * Invalidate by VA range, EL3, Inner/Outer Shareable. + * Currently handles all of RVAE3IS, RVAE3OS, RVAAE3IS, RVAAE3OS, + * RVAALE3IS, RVAALE3OS, RVALE3IS, and RVALE3OS, since we don't support + * flush-for-specific-ASID-only, flush-last-level-only or inner/outer + * specific flushes. + */ + int bits; + uint64_t pageaddr; + uint64_t length; + + CPUState *cs =3D env_cpu(env); + pageaddr =3D extract64(value, 0, 37) << TARGET_PAGE_BITS; + length =3D tlbi_aa64_range_get_length(env, value); + bits =3D tlbbits_for_regime(env, ARMMMUIdx_SE3, pageaddr); + + tlb_flush_page_range_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, + length, + ARMMMUIdxBit_SE3, + bits); +} +#endif + static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo= *ri, bool isread) { @@ -6920,6 +7131,86 @@ static const ARMCPRegInfo pauth_reginfo[] =3D { REGINFO_SENTINEL }; =20 +static const ARMCPRegInfo tlbirange_reginfo[] =3D { + { .name =3D "TLBI_RVAE1IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 2, .opc2 =3D 1, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1is_write }, + { .name =3D "TLBI_RVAAE1IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 2, .opc2 =3D 3, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1is_write }, + { .name =3D "TLBI_RVALE1IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 2, .opc2 =3D 5, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1is_write }, + { .name =3D "TLBI_RVAALE1IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 2, .opc2 =3D 7, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1is_write }, + { .name =3D "TLBI_RVAE1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 1, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1_write }, + { .name =3D "TLBI_RVAAE1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 3, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1_write }, + { .name =3D "TLBI_RVALE1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 5, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1_write }, + { .name =3D "TLBI_RVAALE1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 7, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1_write }, + { .name =3D "TLBI_RIPAS2E1IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 2, + .access =3D PL2_W, .type =3D ARM_CP_NOP }, + { .name =3D "TLBI_RIPAS2LE1IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 6, + .access =3D PL2_W, .type =3D ARM_CP_NOP }, + { .name =3D "TLBI_RVAE2IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 2, .opc2 =3D 1, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae2is_write }, + { .name =3D "TLBI_RVALE2IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 2, .opc2 =3D 5, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae2is_write }, + { .name =3D "TLBI_RIPAS2E1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 2, + .access =3D PL2_W, .type =3D ARM_CP_NOP }, + { .name =3D "TLBI_RIPAS2LE1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 6, + .access =3D PL2_W, .type =3D ARM_CP_NOP }, + { .name =3D "TLBI_RVAE2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 6, .opc2 =3D 1, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae2_write }, + { .name =3D "TLBI_RVALE2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 6, .opc2 =3D 5, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae2_write }, + { .name =3D "TLBI_RVAE3IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 2, .opc2 =3D 1, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae3is_write }, + { .name =3D "TLBI_RVALE3IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 2, .opc2 =3D 5, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae3is_write }, + { .name =3D "TLBI_RVAE3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 6, .opc2 =3D 1, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae3_write }, + { .name =3D "TLBI_RVALE3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 6, .opc2 =3D 5, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae3_write }, + REGINFO_SENTINEL +}; + static uint64_t rndr_readfn(CPUARMState *env, const ARMCPRegInfo *ri) { Error *err =3D NULL; @@ -8289,6 +8580,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_rndr, cpu)) { define_arm_cp_regs(cpu, rndr_reginfo); } + if (cpu_isar_feature(aa64_tlbirange, cpu)) { + define_arm_cp_regs(cpu, tlbirange_reginfo); + } #ifndef CONFIG_USER_ONLY /* Data Cache clean instructions up to PoP */ if (cpu_isar_feature(aa64_dcpop, cpu)) { --=20 2.26.2 From nobody Thu Apr 18 16:14:40 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1617841597; cv=none; d=zohomail.com; s=zohoarc; b=js+MxJSKYQMZMdV51nHSkQwqOyBpBzIyTfbokP19IwnM6eRl2/cQ2dPLCAWjfybQVN13/eCavAKRYOdtJu/xbmR5U++i1YDYPEG0SnxcR/YvZdOaI0gZI5aH60u94fnRtzeZbNWcBWWm1IeltCsMM0hfEJKiWBXrzHo5IyIY4Vs= ARC-Message-Signature: i=1; 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[174.52.16.57]) by smtp.gmail.com with ESMTPSA id 11sm1818393ilg.53.2021.04.07.17.20.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Apr 2021 17:20:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=isLK5SgCVgmU05FBFa6ZughRqyflJB/ni8lS60DTSH8=; b=ErYS/cxlKRt/7iRrNpkSwufmqqtVory0JbMx7VVfIXduiU6oSVQPQVLNASfCYQ6MX0 c1nRrXtx6AYfaCluHZTXnOUrBZCMT1QISnSt/ct2KWcJG2Z1pwHkWs35xXPV/g40uWBC NWgsABeRL0EYKY1DcGVWhm13hNEe8Hk9IfxA9NkMBFNh9+Bfe0/0x1AZp7xUINLaqHuh rX0+p/vKuyKPpIvM7Pom3/0c6KHHUQOKMLKaqUIjYsVFtteWLaZIWrQmhhlIGJl4AXyQ vzKxgADMCvcHO6EQ/17IeWimX/7Z1Ixy1nrAvrfpmo9jtN5PDwv1BIQecmDaLlAOKbM2 bjww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=isLK5SgCVgmU05FBFa6ZughRqyflJB/ni8lS60DTSH8=; b=r/1COHkrDKCP7MMvSxCDgWW0QPqmYSpF3jn1Do6IM9bARzWpHGUu8KHNdjvEi971z6 x/GYZkYEbe4v7oJ8LCjhmCtaOczfOZyROx1JNixTUR/Rjq5xbC7Z8Q1QzgnD6xUeRkn5 I+fN/GAw0iOI5mKeWJiiIl4wOl9q+Inj8EIIqOuaXc+7IH/WLrwtsQaDBlFGvYh5yck3 FaRv57jK7+FJnaGVYGyMEtQdK9EY36PTTv6M1+T7XDvUcS1BSUY9TvvgLk5tKwBxXmwv aQacJeTjI98vuB948l8MORuAnRo/HYK1FUiCgUmNRMM77qh0nROWFRyqF19ycvOz7Psq hOFA== X-Gm-Message-State: AOAM531CiIk95yctQTzP+jqXaKYJ1E6oCvA3+CkSEpmGrBvtKWtpe0Ed oguYS/Yjk6aIvWGvWjM8zIErxQ== X-Google-Smtp-Source: ABdhPJzDvnrel9x6C25+FjBV4AyO6rR9rgtguv7IIvIxhzdTEDKZv4UWABP0TBbLYOPbxV1L722EiQ== X-Received: by 2002:a05:6e02:1584:: with SMTP id m4mr4884385ilu.108.1617841254645; Wed, 07 Apr 2021 17:20:54 -0700 (PDT) From: Rebecca Cran To: peter.maydell@linaro.org, richard.henderson@linaro.org Subject: [PATCH v6 3/4] target/arm: Add support for FEAT_TLBIOS Date: Wed, 7 Apr 2021 18:20:38 -0600 Message-Id: <20210408002039.18027-4-rebecca@nuviainc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210408002039.18027-1-rebecca@nuviainc.com> References: <20210408002039.18027-1-rebecca@nuviainc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::132; envelope-from=rebecca@nuviainc.com; helo=mail-il1-x132.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rebecca Cran , qemu-devel@nongnu.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" ARMv8.4 adds the mandatory FEAT_TLBIOS. It provides TLBI maintenance instructions that extend to the Outer Shareable domain. Signed-off-by: Rebecca Cran --- target/arm/cpu.h | 5 ++ target/arm/helper.c | 75 ++++++++++++++++++++ 2 files changed, 80 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 32b78a4ef587..272fde83ca4e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -4043,6 +4043,11 @@ static inline bool isar_feature_aa64_tlbirange(const= ARMISARegisters *id) return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) =3D=3D 2; } =20 +static inline bool isar_feature_aa64_tlbios(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) !=3D 0; +} + static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) !=3D 0; diff --git a/target/arm/helper.c b/target/arm/helper.c index ce913deff490..5b10f179b761 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7211,6 +7211,78 @@ static const ARMCPRegInfo tlbirange_reginfo[] =3D { REGINFO_SENTINEL }; =20 +static const ARMCPRegInfo tlbios_reginfo[] =3D { + { .name =3D "TLBI_VMALLE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 0, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_vmalle1is_write }, + { .name =3D "TLBI_ASIDE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 2, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_vmalle1is_write }, + { .name =3D "TLBI_RVAE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 5, .opc2 =3D 1, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1is_write }, + { .name =3D "TLBI_RVAAE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 5, .opc2 =3D 3, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1is_write }, + { .name =3D "TLBI_RVALE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 5, .opc2 =3D 5, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1is_write }, + { .name =3D "TLBI_RVAALE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 5, .opc2 =3D 7, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1is_write }, + { .name =3D "TLBI_ALLE2OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 0, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_alle2is_write }, + { .name =3D "TLBI_ALLE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 4, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_alle1is_write }, + { .name =3D "TLBI_VMALLS12E1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 6, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_alle1is_write }, + { .name =3D "TLBI_IPAS2E1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 0, + .access =3D PL2_W, .type =3D ARM_CP_NOP }, + { .name =3D "TLBI_RIPAS2E1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 3, + .access =3D PL2_W, .type =3D ARM_CP_NOP }, + { .name =3D "TLBI_IPAS2LE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 4, + .access =3D PL2_W, .type =3D ARM_CP_NOP }, + { .name =3D "TLBI_RIPAS2LE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 7, + .access =3D PL2_W, .type =3D ARM_CP_NOP }, + { .name =3D "TLBI_RVAE2OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 5, .opc2 =3D 1, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae2is_write }, + { .name =3D "TLBI_RVALE2OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 5, .opc2 =3D 5, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae2is_write }, + { .name =3D "TLBI_ALLE3OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 1, .opc2 =3D 0, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_alle3is_write }, + { .name =3D "TLBI_RVAE3OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 5, .opc2 =3D 1, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae3is_write }, + { .name =3D "TLBI_RVALE3OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 5, .opc2 =3D 5, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae3is_write }, + REGINFO_SENTINEL +}; + static uint64_t rndr_readfn(CPUARMState *env, const ARMCPRegInfo *ri) { Error *err =3D NULL; @@ -8583,6 +8655,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_tlbirange, cpu)) { define_arm_cp_regs(cpu, tlbirange_reginfo); } + if (cpu_isar_feature(aa64_tlbios, cpu)) { + define_arm_cp_regs(cpu, tlbios_reginfo); + } #ifndef CONFIG_USER_ONLY /* Data Cache clean instructions up to PoP */ if (cpu_isar_feature(aa64_dcpop, cpu)) { --=20 2.26.2 From nobody Thu Apr 18 16:14:40 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1617841645; cv=none; d=zohomail.com; s=zohoarc; b=IjKucg+UwCF/yuhTJe7VmyKHR7Q8C3XULSKhGyIYWBRsMH1RpauXiTfyWqqURpkjrgzzjEzzHca2Dn1jn7DvHFAdr1ShDCOlsKv7hGTSjviGPpbTH9bnq/NnZLYBGyq+es/tRyMt86v6AAwmXnM2F5XLw1lq7azIfTFhHbUD5dM= ARC-Message-Signature: i=1; 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[174.52.16.57]) by smtp.gmail.com with ESMTPSA id 11sm1818393ilg.53.2021.04.07.17.20.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Apr 2021 17:20:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uNizM5dd+njefSGglfwPGotA4yVew4h3gSREpFzckEs=; b=T8F2BdCg9Xwz9klXJ1oZB/EAyOBoP6h8WFUg2AK40+MoKYlYCSNpYPvPzsJTVNUJRX G6Uc/DT0T9L+iH+bA0FHmsHYop8NnqOqVIfjPq5qU1TaJz1ztndoPBjrDIoSPA4hlYkq 1E8csSufo+DGxISqXyxJXbC0wZ94bXO9wPHf+SYCYhI3pJ7Jpf6m3bMgUay02X4DP15z IvkpnQgcu1ix629Jzazh9xSpypiA7mtgHqjBtHjQrItjs8qkNRrI50kqMaOjpWG4X8+a T83DvSscClF9es8Ikuw0rVglOC+c6wjac7Sghttubs6LkCuk05w/b35gWv8L/er+7svM /zkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uNizM5dd+njefSGglfwPGotA4yVew4h3gSREpFzckEs=; b=Jl3UWkNr48wcMGA1tmCLK8njllXLNyumLsXN7dllriMUArW8UfN6A77VMn/gLmd0kb 9aNIc2KKFCQtI5+6US1nSSrHPs07wzYjH+vIwQDzUeB+3VdtW46sxZJPmdcbRPM4xy71 Ea8QVxPdjF7FYno89yV2omlmbOaC+ASFcS/8DXXR5Vvg0zPeV42kpM3ypt3PCwg0yAax p4bwHcdaW7VClazbQ/LNEcm3i2kzIMhfadoE/sb+HzGHjdlECTjTKUvLTwmv5I1pNWja 8+DaLYXiwF+11Nqr56xEMisO2l1qLMHx2BMdut6Z82V4s4rdrcCHrQQBp4nYnCZkIwlz pbUg== X-Gm-Message-State: AOAM533sc+fSNszdZmPDRq+I5IxLkOf4Xg88SZdDJrWEgDYICaKDczsw WGmNPAcfcnFG4irGeuhWmyN+7ZCsnzUUgg== X-Google-Smtp-Source: ABdhPJz9TdC/iTWtMMGsXcmSkTEERYbvTs+tAQf2WVvplICrDDnTdK6Abr9myX5GTaSwKjXjep12LQ== X-Received: by 2002:a05:6e02:6cf:: with SMTP id p15mr4855650ils.237.1617841256915; Wed, 07 Apr 2021 17:20:56 -0700 (PDT) From: Rebecca Cran To: peter.maydell@linaro.org, richard.henderson@linaro.org Subject: [PATCH v6 4/4] target/arm: set ID_AA64ISAR0.TLB to 2 for max AARCH64 CPU type Date: Wed, 7 Apr 2021 18:20:39 -0600 Message-Id: <20210408002039.18027-5-rebecca@nuviainc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210408002039.18027-1-rebecca@nuviainc.com> References: <20210408002039.18027-1-rebecca@nuviainc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::141; envelope-from=rebecca@nuviainc.com; helo=mail-il1-x141.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rebecca Cran , qemu-devel@nongnu.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Indicate support for FEAT_TLBIOS and FEAT_TLBIRANGE by setting ID_AA64ISAR0.TLB to 2 for the max AARCH64 CPU type. Signed-off-by: Rebecca Cran Reviewed-by: Richard Henderson --- target/arm/cpu64.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index f0a9e968c9c1..f42803ecaf1d 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -651,6 +651,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ISAR0, DP, 1); t =3D FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); t =3D FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */ t =3D FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); cpu->isar.id_aa64isar0 =3D t; =20 --=20 2.26.2