From nobody Sat May 18 23:23:43 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=vijai@behindbytes.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=fail (Bad Signature) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1617301311152528.5447080947293; Thu, 1 Apr 2021 11:21:51 -0700 (PDT) Received: from localhost ([::1]:41236 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lS1x0-0006TF-33 for importer@patchew.org; Thu, 01 Apr 2021 14:21:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60284) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lS1qc-0003LA-KJ; Thu, 01 Apr 2021 14:15:16 -0400 Received: from sender-of-o51.zoho.in ([103.117.158.51]:2303) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lS1qX-0003YL-Tj; Thu, 01 Apr 2021 14:15:14 -0400 Received: from localhost.localdomain (49.207.218.164 [49.207.218.164]) by mx.zoho.in with SMTPS id 1617300900611717.8044221259788; Thu, 1 Apr 2021 23:45:00 +0530 (IST) ARC-Seal: i=1; a=rsa-sha256; t=1617300902; cv=none; d=zohomail.in; s=zohoarc; b=RhsO1CNVkJ6yIvEmxIQXnKxGxdjiMwgoxh6SApan552XyWoWNwofj5+q0hFLr1KTOuOj+d0aIXez9kIpDf7e641u2AXzAmznWY+sCXMQER2AgdHcSQ6BG6gjOg9OmFiT6SBkm1gb1RnUCksrQs78+KlXHJZiUuChQTPNmEbKv0c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.in; s=zohoarc; t=1617300902; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=evHDLWBYxQMqqDMawDnxpTEbO7c4T6GucCah48FP61Q=; b=aoS3Nl6wYDvHq7HeGI/ynSSxvu4gr3eKXW2y01l+MxYtW+T2M6yve6PmWNLgPV7p77qRz8SjWu9W3yRwss1GZXydcMmS14t9gZsrmkxZPsQ05IfnZk9sO1T9pjktfKk+JPs4b2oGd4SVLtPt3y9yumFcc2cVsc6VYkbRS9s8eO0= ARC-Authentication-Results: i=1; mx.zohomail.in; dkim=pass header.i=behindbytes.com; spf=pass smtp.mailfrom=vijai@behindbytes.com; dmarc=pass header.from= header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1617300902; s=yrk; d=behindbytes.com; i=vijai@behindbytes.com; h=From:To:Cc:Message-ID:Subject:Date:In-Reply-To:References:MIME-Version:Content-Transfer-Encoding:Content-Type; bh=evHDLWBYxQMqqDMawDnxpTEbO7c4T6GucCah48FP61Q=; b=JLV+eDfksiP3zKO/PeHxL9HFZ4A2tkk7FYevFr1qIju75XalD/uIq0+/fZ/WBw6U BMWpt6eVWW5VORD5A8yzzdCiVqOvzC65X2/mEdebOORcbzv0fvGwHpfeUFLwt8YmexR 4bG9yqBGge2Mowq4h/P+pgUFj9eBlLweQakZIR5E= From: Vijai Kumar K To: qemu-riscv@nongnu.org, alistair23@gmail.com Message-ID: <20210401181457.73039-2-vijai@behindbytes.com> Subject: [PATCH v3 1/4] target/riscv: Add Shakti C class CPU Date: Thu, 1 Apr 2021 23:44:54 +0530 X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210401181457.73039-1-vijai@behindbytes.com> References: <20210401181457.73039-1-vijai@behindbytes.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMailClient: External Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=103.117.158.51; envelope-from=vijai@behindbytes.com; helo=sender-of-o51.zoho.in X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Vijai Kumar K , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" C-Class is a member of the SHAKTI family of processors from IIT-M. It is an extremely configurable and commercial-grade 5-stage in-order core supporting the standard RV64GCSUN ISA extensions. Signed-off-by: Vijai Kumar K Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 1 + 2 files changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 2a990f6253..140094fd52 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -707,6 +707,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), #endif }; =20 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0edb2826a2..ebbf15fb1c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -38,6 +38,7 @@ #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") +#define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") --=20 2.25.1 From nobody Sat May 18 23:23:43 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=vijai@behindbytes.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=fail (Bad Signature) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1617301482704303.2091864032577; Thu, 1 Apr 2021 11:24:42 -0700 (PDT) Received: from localhost ([::1]:47756 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lS1zl-0000pu-I8 for importer@patchew.org; Thu, 01 Apr 2021 14:24:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60322) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lS1qk-0003My-Bl; Thu, 01 Apr 2021 14:15:26 -0400 Received: from sender-of-o51.zoho.in ([103.117.158.51]:2304) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lS1qZ-0003aG-Hl; Thu, 01 Apr 2021 14:15:22 -0400 Received: from localhost.localdomain (49.207.218.164 [49.207.218.164]) by mx.zoho.in with SMTPS id 1617300901032973.9261640028456; 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i=vijai@behindbytes.com; h=From:To:Cc:Message-ID:Subject:Date:In-Reply-To:References:MIME-Version:Content-Transfer-Encoding:Content-Type; bh=xva6Q3VZKfSIpao0nZm3UY6sJquZiyKFcSF2sWUmYrU=; b=J9MCxCrhC968yLdRDCoBOFirYqvVRFQvISGBYKqpK1hkScS29+99AxgmPYxo0BtI 7BsbnndOpE6lrVGERmE1cQe34RdWlEe/hu0n6C6aHI8J1tQnl7j/FeTDFZ3XPkk4k/E 7JFCkQGVMRGv2wt3MPcIlG17Nj8qbKVrdVRDYN/Y= From: Vijai Kumar K To: qemu-riscv@nongnu.org, alistair23@gmail.com Message-ID: <20210401181457.73039-3-vijai@behindbytes.com> Subject: [PATCH v3 2/4] riscv: Add initial support for Shakti C machine Date: Thu, 1 Apr 2021 23:44:55 +0530 X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210401181457.73039-1-vijai@behindbytes.com> References: <20210401181457.73039-1-vijai@behindbytes.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMailClient: External Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=103.117.158.51; envelope-from=vijai@behindbytes.com; helo=sender-of-o51.zoho.in X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Vijai Kumar K , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Add support for emulating Shakti reference platform based on C-class running on arty-100T board. https://gitlab.com/shaktiproject/cores/shakti-soc/-/blob/master/README.rst Signed-off-by: Vijai Kumar K Reviewed-by: Alistair Francis --- MAINTAINERS | 7 + default-configs/devices/riscv64-softmmu.mak | 1 + hw/riscv/Kconfig | 10 ++ hw/riscv/meson.build | 1 + hw/riscv/shakti_c.c | 170 ++++++++++++++++++++ include/hw/riscv/shakti_c.h | 73 +++++++++ 6 files changed, 262 insertions(+) create mode 100644 hw/riscv/shakti_c.c create mode 100644 include/hw/riscv/shakti_c.h diff --git a/MAINTAINERS b/MAINTAINERS index 8e9f0d591e..9f71c4cc3f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1380,6 +1380,13 @@ F: include/hw/misc/mchp_pfsoc_dmc.h F: include/hw/misc/mchp_pfsoc_ioscb.h F: include/hw/misc/mchp_pfsoc_sysreg.h =20 +Shakti C class SoC +M: Vijai Kumar K +L: qemu-riscv@nongnu.org +S: Supported +F: hw/riscv/shakti_c.c +F: include/hw/riscv/shakti_c.h + SiFive Machines M: Alistair Francis M: Bin Meng diff --git a/default-configs/devices/riscv64-softmmu.mak b/default-configs/= devices/riscv64-softmmu.mak index d5eec75f05..bc69301fa4 100644 --- a/default-configs/devices/riscv64-softmmu.mak +++ b/default-configs/devices/riscv64-softmmu.mak @@ -13,3 +13,4 @@ CONFIG_SIFIVE_E=3Dy CONFIG_SIFIVE_U=3Dy CONFIG_RISCV_VIRT=3Dy CONFIG_MICROCHIP_PFSOC=3Dy +CONFIG_SHAKTI_C=3Dy diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index d139074b02..92a62b5ce9 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -19,6 +19,16 @@ config OPENTITAN select IBEX select UNIMP =20 +config SHAKTI + bool + +config SHAKTI_C + bool + select UNIMP + select SHAKTI + select SIFIVE_CLINT + select SIFIVE_PLIC + config RISCV_VIRT bool imply PCI_DEVICES diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build index 275c0f7eb7..a97454661c 100644 --- a/hw/riscv/meson.build +++ b/hw/riscv/meson.build @@ -4,6 +4,7 @@ riscv_ss.add(files('numa.c')) riscv_ss.add(files('riscv_hart.c')) riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c')) riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c')) +riscv_ss.add(when: 'CONFIG_SHAKTI_C', if_true: files('shakti_c.c')) riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c')) riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c')) riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c')) diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c new file mode 100644 index 0000000000..c8205d3f22 --- /dev/null +++ b/hw/riscv/shakti_c.c @@ -0,0 +1,170 @@ +/* + * Shakti C-class SoC emulation + * + * Copyright (c) 2021 Vijai Kumar K + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "hw/boards.h" +#include "hw/riscv/shakti_c.h" +#include "qapi/error.h" +#include "hw/intc/sifive_plic.h" +#include "hw/intc/sifive_clint.h" +#include "sysemu/sysemu.h" +#include "hw/qdev-properties.h" +#include "exec/address-spaces.h" +#include "hw/riscv/boot.h" + + +static const struct MemmapEntry { + hwaddr base; + hwaddr size; +} shakti_c_memmap[] =3D { + [SHAKTI_C_ROM] =3D { 0x00001000, 0x2000 }, + [SHAKTI_C_RAM] =3D { 0x80000000, 0x0 }, + [SHAKTI_C_UART] =3D { 0x00011300, 0x00040 }, + [SHAKTI_C_GPIO] =3D { 0x020d0000, 0x00100 }, + [SHAKTI_C_PLIC] =3D { 0x0c000000, 0x20000 }, + [SHAKTI_C_CLINT] =3D { 0x02000000, 0xc0000 }, + [SHAKTI_C_I2C] =3D { 0x20c00000, 0x00100 }, +}; + +static void shakti_c_machine_state_init(MachineState *mstate) +{ + ShaktiCMachineState *sms =3D RISCV_SHAKTI_MACHINE(mstate); + MemoryRegion *system_memory =3D get_system_memory(); + MemoryRegion *main_mem =3D g_new(MemoryRegion, 1); + + /* Allow only Shakti C CPU for this platform */ + if (strcmp(mstate->cpu_type, TYPE_RISCV_CPU_SHAKTI_C) !=3D 0) { + error_report("This board can only be used with Shakti C CPU"); + exit(1); + } + + /* Initialize SoC */ + object_initialize_child(OBJECT(mstate), "soc", &sms->soc, + TYPE_RISCV_SHAKTI_SOC); + qdev_realize(DEVICE(&sms->soc), NULL, &error_abort); + + /* register RAM */ + memory_region_init_ram(main_mem, NULL, "riscv.shakti.c.ram", + mstate->ram_size, &error_fatal); + memory_region_add_subregion(system_memory, + shakti_c_memmap[SHAKTI_C_RAM].base, + main_mem); + + /* ROM reset vector */ + riscv_setup_rom_reset_vec(mstate, &sms->soc.cpus, + shakti_c_memmap[SHAKTI_C_RAM].base, + shakti_c_memmap[SHAKTI_C_ROM].base, + shakti_c_memmap[SHAKTI_C_ROM].size, 0, 0, + NULL); + riscv_load_firmware(mstate->firmware, shakti_c_memmap[SHAKTI_C_RAM].ba= se, + NULL); +} + +static void shakti_c_machine_instance_init(Object *obj) +{ +} + +static void shakti_c_machine_class_init(ObjectClass *klass, void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(klass); + mc->desc =3D "RISC-V Board compatible with Shakti SDK"; + mc->init =3D shakti_c_machine_state_init; + mc->default_cpu_type =3D TYPE_RISCV_CPU_SHAKTI_C; +} + +static const TypeInfo shakti_c_machine_type_info =3D { + .name =3D TYPE_RISCV_SHAKTI_MACHINE, + .parent =3D TYPE_MACHINE, + .class_init =3D shakti_c_machine_class_init, + .instance_init =3D shakti_c_machine_instance_init, + .instance_size =3D sizeof(ShaktiCMachineState), +}; + +static void shakti_c_machine_type_info_register(void) +{ + type_register_static(&shakti_c_machine_type_info); +} +type_init(shakti_c_machine_type_info_register) + +static void shakti_c_soc_state_realize(DeviceState *dev, Error **errp) +{ + ShaktiCSoCState *sss =3D RISCV_SHAKTI_SOC(dev); + MemoryRegion *system_memory =3D get_system_memory(); + + sysbus_realize(SYS_BUS_DEVICE(&sss->cpus), &error_abort); + + sss->plic =3D sifive_plic_create(shakti_c_memmap[SHAKTI_C_PLIC].base, + (char *)SHAKTI_C_PLIC_HART_CONFIG, 0, + SHAKTI_C_PLIC_NUM_SOURCES, + SHAKTI_C_PLIC_NUM_PRIORITIES, + SHAKTI_C_PLIC_PRIORITY_BASE, + SHAKTI_C_PLIC_PENDING_BASE, + SHAKTI_C_PLIC_ENABLE_BASE, + SHAKTI_C_PLIC_ENABLE_STRIDE, + SHAKTI_C_PLIC_CONTEXT_BASE, + SHAKTI_C_PLIC_CONTEXT_STRIDE, + shakti_c_memmap[SHAKTI_C_PLIC].size); + + sifive_clint_create(shakti_c_memmap[SHAKTI_C_CLINT].base, + shakti_c_memmap[SHAKTI_C_CLINT].size, 0, 1, + SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, + SIFIVE_CLINT_TIMEBASE_FREQ, false); + + /* ROM */ + memory_region_init_rom(&sss->rom, OBJECT(dev), "riscv.shakti.c.rom", + shakti_c_memmap[SHAKTI_C_ROM].size, &error_fata= l); + memory_region_add_subregion(system_memory, + shakti_c_memmap[SHAKTI_C_ROM].base, &sss->rom); +} + +static void shakti_c_soc_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + dc->realize =3D shakti_c_soc_state_realize; +} + +static void shakti_c_soc_instance_init(Object *obj) +{ + ShaktiCSoCState *sss =3D RISCV_SHAKTI_SOC(obj); + + object_initialize_child(obj, "cpus", &sss->cpus, TYPE_RISCV_HART_ARRAY= ); + + /* + * CPU type is fixed and we are not supporting passing from commandlin= e yet. + * So let it be in instance_init. When supported should use ms->cpu_ty= pe + * instead of TYPE_RISCV_CPU_SHAKTI_C + */ + object_property_set_str(OBJECT(&sss->cpus), "cpu-type", + TYPE_RISCV_CPU_SHAKTI_C, &error_abort); + object_property_set_int(OBJECT(&sss->cpus), "num-harts", 1, + &error_abort); +} + +static const TypeInfo shakti_c_type_info =3D { + .name =3D TYPE_RISCV_SHAKTI_SOC, + .parent =3D TYPE_DEVICE, + .class_init =3D shakti_c_soc_class_init, + .instance_init =3D shakti_c_soc_instance_init, + .instance_size =3D sizeof(ShaktiCSoCState), +}; + +static void shakti_c_type_info_register(void) +{ + type_register_static(&shakti_c_type_info); +} +type_init(shakti_c_type_info_register) diff --git a/include/hw/riscv/shakti_c.h b/include/hw/riscv/shakti_c.h new file mode 100644 index 0000000000..8ffc2b0213 --- /dev/null +++ b/include/hw/riscv/shakti_c.h @@ -0,0 +1,73 @@ +/* + * Shakti C-class SoC emulation + * + * Copyright (c) 2021 Vijai Kumar K + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#ifndef HW_SHAKTI_H +#define HW_SHAKTI_H + +#include "hw/riscv/riscv_hart.h" +#include "hw/boards.h" + +#define TYPE_RISCV_SHAKTI_SOC "riscv.shakti.cclass.soc" +#define RISCV_SHAKTI_SOC(obj) \ + OBJECT_CHECK(ShaktiCSoCState, (obj), TYPE_RISCV_SHAKTI_SOC) + +typedef struct ShaktiCSoCState { + /*< private >*/ + DeviceState parent_obj; + + /*< public >*/ + RISCVHartArrayState cpus; + DeviceState *plic; + MemoryRegion rom; + +} ShaktiCSoCState; + +#define TYPE_RISCV_SHAKTI_MACHINE MACHINE_TYPE_NAME("shakti_c") +#define RISCV_SHAKTI_MACHINE(obj) \ + OBJECT_CHECK(ShaktiCMachineState, (obj), TYPE_RISCV_SHAKTI_MACHINE) +typedef struct ShaktiCMachineState { + /*< private >*/ + MachineState parent_obj; + + /*< public >*/ + ShaktiCSoCState soc; +} ShaktiCMachineState; + +enum { + SHAKTI_C_ROM, + SHAKTI_C_RAM, + SHAKTI_C_UART, + SHAKTI_C_GPIO, + SHAKTI_C_PLIC, + SHAKTI_C_CLINT, + SHAKTI_C_I2C, +}; + +#define SHAKTI_C_PLIC_HART_CONFIG "MS" +/* Including Interrupt ID 0 (no interrupt)*/ +#define SHAKTI_C_PLIC_NUM_SOURCES 28 +/* Excluding Priority 0 */ +#define SHAKTI_C_PLIC_NUM_PRIORITIES 2 +#define SHAKTI_C_PLIC_PRIORITY_BASE 0x04 +#define SHAKTI_C_PLIC_PENDING_BASE 0x1000 +#define SHAKTI_C_PLIC_ENABLE_BASE 0x2000 +#define SHAKTI_C_PLIC_ENABLE_STRIDE 0x80 +#define SHAKTI_C_PLIC_CONTEXT_BASE 0x200000 +#define SHAKTI_C_PLIC_CONTEXT_STRIDE 0x1000 + +#endif --=20 2.25.1 From nobody Sat May 18 23:23:43 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=vijai@behindbytes.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=fail (Bad Signature) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1617301649814668.3713025117571; Thu, 1 Apr 2021 11:27:29 -0700 (PDT) Received: from localhost ([::1]:52828 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lS22Q-00033F-1O for importer@patchew.org; Thu, 01 Apr 2021 14:27:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60352) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lS1qo-0003NF-AY; Thu, 01 Apr 2021 14:15:28 -0400 Received: from sender-of-o51.zoho.in ([103.117.158.51]:2305) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lS1qZ-0003aK-HY; Thu, 01 Apr 2021 14:15:24 -0400 Received: from localhost.localdomain (49.207.218.164 [49.207.218.164]) by mx.zoho.in with SMTPS id 1617300901432556.8555773449766; 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i=vijai@behindbytes.com; h=From:To:Cc:Message-ID:Subject:Date:In-Reply-To:References:MIME-Version:Content-Transfer-Encoding:Content-Type; bh=xFo9r9JEtBqpLxIEtXqPr/jj7ZNiZVgywVbyzxMJVCU=; b=OsSQGxDIoCkKUXkBsLywOQ+w3G/QYyHlbOQnovlkbbQnGGWGAhJuwRaEfdjP4t2u whHqlTPLNm6DpUyVZhI03OnzAzFmPniiR7UVROLUd+JPt2ZC+zcyrk+HZkXZa/AcOdr ZnbHxow/Ke4npOfNi+UldmRjmZpvwvrMZZ1Ij2k8= From: Vijai Kumar K To: qemu-riscv@nongnu.org, alistair23@gmail.com Message-ID: <20210401181457.73039-4-vijai@behindbytes.com> Subject: [PATCH v3 3/4] hw/char: Add Shakti UART emulation Date: Thu, 1 Apr 2021 23:44:56 +0530 X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210401181457.73039-1-vijai@behindbytes.com> References: <20210401181457.73039-1-vijai@behindbytes.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMailClient: External Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=103.117.158.51; envelope-from=vijai@behindbytes.com; helo=sender-of-o51.zoho.in X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Vijai Kumar K , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" This is the initial implementation of Shakti UART. Signed-off-by: Vijai Kumar K Reviewed-by: Alistair Francis --- MAINTAINERS | 2 + hw/char/meson.build | 1 + hw/char/shakti_uart.c | 185 ++++++++++++++++++++++++++++++++++ hw/char/trace-events | 4 + include/hw/char/shakti_uart.h | 74 ++++++++++++++ 5 files changed, 266 insertions(+) create mode 100644 hw/char/shakti_uart.c create mode 100644 include/hw/char/shakti_uart.h diff --git a/MAINTAINERS b/MAINTAINERS index 9f71c4cc3f..be084865db 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1385,7 +1385,9 @@ M: Vijai Kumar K L: qemu-riscv@nongnu.org S: Supported F: hw/riscv/shakti_c.c +F: hw/char/shakti_uart.c F: include/hw/riscv/shakti_c.h +F: include/hw/char/shakti_uart.h =20 SiFive Machines M: Alistair Francis diff --git a/hw/char/meson.build b/hw/char/meson.build index 7ba38dbd96..61c43d4b51 100644 --- a/hw/char/meson.build +++ b/hw/char/meson.build @@ -19,6 +19,7 @@ softmmu_ss.add(when: 'CONFIG_SERIAL', if_true: files('ser= ial.c')) softmmu_ss.add(when: 'CONFIG_SERIAL_ISA', if_true: files('serial-isa.c')) softmmu_ss.add(when: 'CONFIG_SERIAL_PCI', if_true: files('serial-pci.c')) softmmu_ss.add(when: 'CONFIG_SERIAL_PCI_MULTI', if_true: files('serial-pci= -multi.c')) +softmmu_ss.add(when: 'CONFIG_SHAKTI', if_true: files('shakti_uart.c')) softmmu_ss.add(when: 'CONFIG_VIRTIO_SERIAL', if_true: files('virtio-consol= e.c')) softmmu_ss.add(when: 'CONFIG_XEN', if_true: files('xen_console.c')) softmmu_ss.add(when: 'CONFIG_XILINX', if_true: files('xilinx_uartlite.c')) diff --git a/hw/char/shakti_uart.c b/hw/char/shakti_uart.c new file mode 100644 index 0000000000..6870821325 --- /dev/null +++ b/hw/char/shakti_uart.c @@ -0,0 +1,185 @@ +/* + * SHAKTI UART + * + * Copyright (c) 2021 Vijai Kumar K + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "hw/char/shakti_uart.h" +#include "hw/qdev-properties.h" +#include "hw/qdev-properties-system.h" +#include "qemu/log.h" + +static uint64_t shakti_uart_read(void *opaque, hwaddr addr, unsigned size) +{ + ShaktiUartState *s =3D opaque; + + switch (addr) { + case SHAKTI_UART_BAUD: + return s->uart_baud; + case SHAKTI_UART_RX: + qemu_chr_fe_accept_input(&s->chr); + s->uart_status &=3D ~SHAKTI_UART_STATUS_RX_NOT_EMPTY; + return s->uart_rx; + case SHAKTI_UART_STATUS: + return s->uart_status; + case SHAKTI_UART_DELAY: + return s->uart_delay; + case SHAKTI_UART_CONTROL: + return s->uart_control; + case SHAKTI_UART_INT_EN: + return s->uart_interrupt; + case SHAKTI_UART_IQ_CYCLES: + return s->uart_iq_cycles; + case SHAKTI_UART_RX_THRES: + return s->uart_rx_threshold; + default: + /* Also handles TX REG which is write only */ + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); + } + + return 0; +} + +static void shakti_uart_write(void *opaque, hwaddr addr, + uint64_t data, unsigned size) +{ + ShaktiUartState *s =3D opaque; + uint32_t value =3D data; + uint8_t ch; + + switch (addr) { + case SHAKTI_UART_BAUD: + s->uart_baud =3D value; + break; + case SHAKTI_UART_TX: + ch =3D value; + qemu_chr_fe_write_all(&s->chr, &ch, 1); + s->uart_status &=3D ~SHAKTI_UART_STATUS_TX_FULL; + break; + case SHAKTI_UART_STATUS: + s->uart_status =3D value; + break; + case SHAKTI_UART_DELAY: + s->uart_delay =3D value; + break; + case SHAKTI_UART_CONTROL: + s->uart_control =3D value; + break; + case SHAKTI_UART_INT_EN: + s->uart_interrupt =3D value; + break; + case SHAKTI_UART_IQ_CYCLES: + s->uart_iq_cycles =3D value; + break; + case SHAKTI_UART_RX_THRES: + s->uart_rx_threshold =3D value; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); + } +} + +static const MemoryRegionOps shakti_uart_ops =3D { + .read =3D shakti_uart_read, + .write =3D shakti_uart_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .impl =3D {.min_access_size =3D 1, .max_access_size =3D 4}, + .valid =3D {.min_access_size =3D 1, .max_access_size =3D 4}, +}; + +static void shakti_uart_reset(DeviceState *dev) +{ + ShaktiUartState *s =3D SHAKTI_UART(dev); + + s->uart_baud =3D SHAKTI_UART_BAUD_DEFAULT; + s->uart_tx =3D 0x0; + s->uart_rx =3D 0x0; + s->uart_status =3D 0x0000; + s->uart_delay =3D 0x0000; + s->uart_control =3D SHAKTI_UART_CONTROL_DEFAULT; + s->uart_interrupt =3D 0x0000; + s->uart_iq_cycles =3D 0x00; + s->uart_rx_threshold =3D 0x00; +} + +static int shakti_uart_can_receive(void *opaque) +{ + ShaktiUartState *s =3D opaque; + + return !(s->uart_status & SHAKTI_UART_STATUS_RX_NOT_EMPTY); +} + +static void shakti_uart_receive(void *opaque, const uint8_t *buf, int size) +{ + ShaktiUartState *s =3D opaque; + + s->uart_rx =3D *buf; + s->uart_status |=3D SHAKTI_UART_STATUS_RX_NOT_EMPTY; +} + +static void shakti_uart_realize(DeviceState *dev, Error **errp) +{ + ShaktiUartState *sus =3D SHAKTI_UART(dev); + qemu_chr_fe_set_handlers(&sus->chr, shakti_uart_can_receive, + shakti_uart_receive, NULL, NULL, sus, NULL, t= rue); +} + +static void shakti_uart_instance_init(Object *obj) +{ + ShaktiUartState *sus =3D SHAKTI_UART(obj); + memory_region_init_io(&sus->mmio, + obj, + &shakti_uart_ops, + sus, + TYPE_SHAKTI_UART, + 0x1000); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &sus->mmio); +} + +static Property shakti_uart_properties[] =3D { + DEFINE_PROP_CHR("chardev", ShaktiUartState, chr), + DEFINE_PROP_END_OF_LIST(), +}; + +static void shakti_uart_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + dc->reset =3D shakti_uart_reset; + dc->realize =3D shakti_uart_realize; + device_class_set_props(dc, shakti_uart_properties); +} + +static const TypeInfo shakti_uart_info =3D { + .name =3D TYPE_SHAKTI_UART, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(ShaktiUartState), + .class_init =3D shakti_uart_class_init, + .instance_init =3D shakti_uart_instance_init, +}; + +static void shakti_uart_register_types(void) +{ + type_register_static(&shakti_uart_info); +} +type_init(shakti_uart_register_types) diff --git a/hw/char/trace-events b/hw/char/trace-events index 81026f6612..54aeeb899c 100644 --- a/hw/char/trace-events +++ b/hw/char/trace-events @@ -80,6 +80,10 @@ cmsdk_apb_uart_set_params(int speed) "CMSDK APB UART: pa= rams set to %d 8N1" nrf51_uart_read(uint64_t addr, uint64_t r, unsigned int size) "addr 0x%" P= RIx64 " value 0x%" PRIx64 " size %u" nrf51_uart_write(uint64_t addr, uint64_t value, unsigned int size) "addr 0= x%" PRIx64 " value 0x%" PRIx64 " size %u" =20 +# shakti_uart.c +shakti_uart_read(uint64_t addr, uint16_t r, unsigned int size) "addr 0x%" = PRIx64 " value 0x%" PRIx16 " size %u" +shakti_uart_write(uint64_t addr, uint64_t value, unsigned int size) "addr = 0x%" PRIx64 " value 0x%" PRIx64 " size %u" + # exynos4210_uart.c exynos_uart_dmabusy(uint32_t channel) "UART%d: DMA busy (Rx buffer empty)" exynos_uart_dmaready(uint32_t channel) "UART%d: DMA ready" diff --git a/include/hw/char/shakti_uart.h b/include/hw/char/shakti_uart.h new file mode 100644 index 0000000000..526c408233 --- /dev/null +++ b/include/hw/char/shakti_uart.h @@ -0,0 +1,74 @@ +/* + * SHAKTI UART + * + * Copyright (c) 2021 Vijai Kumar K + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#ifndef HW_SHAKTI_UART_H +#define HW_SHAKTI_UART_H + +#include "hw/sysbus.h" +#include "chardev/char-fe.h" + +#define SHAKTI_UART_BAUD 0x00 +#define SHAKTI_UART_TX 0x04 +#define SHAKTI_UART_RX 0x08 +#define SHAKTI_UART_STATUS 0x0C +#define SHAKTI_UART_DELAY 0x10 +#define SHAKTI_UART_CONTROL 0x14 +#define SHAKTI_UART_INT_EN 0x18 +#define SHAKTI_UART_IQ_CYCLES 0x1C +#define SHAKTI_UART_RX_THRES 0x20 + +#define SHAKTI_UART_STATUS_TX_EMPTY (1 << 0) +#define SHAKTI_UART_STATUS_TX_FULL (1 << 1) +#define SHAKTI_UART_STATUS_RX_NOT_EMPTY (1 << 2) +#define SHAKTI_UART_STATUS_RX_FULL (1 << 3) +/* 9600 8N1 is the default setting */ +/* Reg value =3D (50000000 Hz)/(16 * 9600)*/ +#define SHAKTI_UART_BAUD_DEFAULT 0x0145 +#define SHAKTI_UART_CONTROL_DEFAULT 0x0100 + +#define TYPE_SHAKTI_UART "shakti-uart" +#define SHAKTI_UART(obj) \ + OBJECT_CHECK(ShaktiUartState, (obj), TYPE_SHAKTI_UART) + +typedef struct { + /* */ + SysBusDevice parent_obj; + + /* */ + MemoryRegion mmio; + + uint32_t uart_baud; + uint32_t uart_tx; + uint32_t uart_rx; + uint32_t uart_status; + uint32_t uart_delay; + uint32_t uart_control; + uint32_t uart_interrupt; + uint32_t uart_iq_cycles; + uint32_t uart_rx_threshold; + + CharBackend chr; +} ShaktiUartState; + +#endif /* HW_SHAKTI_UART_H */ --=20 2.25.1 From nobody Sat May 18 23:23:43 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=vijai@behindbytes.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=fail (Bad Signature) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1617301376812604.5400431703594; Thu, 1 Apr 2021 11:22:56 -0700 (PDT) Received: from localhost ([::1]:44324 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lS1y3-0007rM-ID for importer@patchew.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=103.117.158.51; envelope-from=vijai@behindbytes.com; helo=sender-of-o51.zoho.in X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Vijai Kumar K , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Connect one shakti uart to the shakti_c machine. Signed-off-by: Vijai Kumar K Reviewed-by: Alistair Francis --- hw/riscv/shakti_c.c | 8 ++++++++ include/hw/riscv/shakti_c.h | 2 ++ 2 files changed, 10 insertions(+) diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c index c8205d3f22..e207fa83dd 100644 --- a/hw/riscv/shakti_c.c +++ b/hw/riscv/shakti_c.c @@ -125,6 +125,13 @@ static void shakti_c_soc_state_realize(DeviceState *de= v, Error **errp) SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, SIFIVE_CLINT_TIMEBASE_FREQ, false); =20 + qdev_prop_set_chr(DEVICE(&(sss->uart)), "chardev", serial_hd(0)); + if (!sysbus_realize(SYS_BUS_DEVICE(&sss->uart), errp)) { + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&sss->uart), 0, + shakti_c_memmap[SHAKTI_C_UART].base); + /* ROM */ memory_region_init_rom(&sss->rom, OBJECT(dev), "riscv.shakti.c.rom", shakti_c_memmap[SHAKTI_C_ROM].size, &error_fata= l); @@ -143,6 +150,7 @@ static void shakti_c_soc_instance_init(Object *obj) ShaktiCSoCState *sss =3D RISCV_SHAKTI_SOC(obj); =20 object_initialize_child(obj, "cpus", &sss->cpus, TYPE_RISCV_HART_ARRAY= ); + object_initialize_child(obj, "uart", &sss->uart, TYPE_SHAKTI_UART); =20 /* * CPU type is fixed and we are not supporting passing from commandlin= e yet. diff --git a/include/hw/riscv/shakti_c.h b/include/hw/riscv/shakti_c.h index 8ffc2b0213..50a2b79086 100644 --- a/include/hw/riscv/shakti_c.h +++ b/include/hw/riscv/shakti_c.h @@ -21,6 +21,7 @@ =20 #include "hw/riscv/riscv_hart.h" #include "hw/boards.h" +#include "hw/char/shakti_uart.h" =20 #define TYPE_RISCV_SHAKTI_SOC "riscv.shakti.cclass.soc" #define RISCV_SHAKTI_SOC(obj) \ @@ -33,6 +34,7 @@ typedef struct ShaktiCSoCState { /*< public >*/ RISCVHartArrayState cpus; DeviceState *plic; + ShaktiUartState uart; MemoryRegion rom; =20 } ShaktiCSoCState; --=20 2.25.1