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Thu, 01 Apr 2021 02:27:07 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC v2 1/4] target/riscv: add RNMI cpu feature Date: Thu, 1 Apr 2021 17:26:48 +0800 Message-Id: <20210401092659.12014-2-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210401092659.12014-1-frank.chang@sifive.com> References: <20210401092659.12014-1-frank.chang@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=frank.chang@sifive.com; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Frank Chang , Alistair Francis , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Signed-off-by: Frank Chang --- hw/riscv/riscv_hart.c | 8 +++++++ include/hw/riscv/riscv_hart.h | 2 ++ target/riscv/cpu.c | 40 +++++++++++++++++++++++++++++++++++ target/riscv/cpu.h | 12 ++++++++++- target/riscv/cpu_bits.h | 6 ++++++ 5 files changed, 67 insertions(+), 1 deletion(-) diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c index 613ea2aaa0b..b8cb5088638 100644 --- a/hw/riscv/riscv_hart.c +++ b/hw/riscv/riscv_hart.c @@ -33,6 +33,10 @@ static Property riscv_harts_props[] =3D { DEFINE_PROP_STRING("cpu-type", RISCVHartArrayState, cpu_type), DEFINE_PROP_UINT64("resetvec", RISCVHartArrayState, resetvec, DEFAULT_RSTVEC), + DEFINE_PROP_UINT64("rnmi_irqvec", RISCVHartArrayState, rnmi_irqvec, + DEFAULT_RNMI_IRQVEC), + DEFINE_PROP_UINT64("rnmi_excpvec", RISCVHartArrayState, rnmi_excpvec, + DEFAULT_RNMI_EXCPVEC), DEFINE_PROP_END_OF_LIST(), }; =20 @@ -47,6 +51,10 @@ static bool riscv_hart_realize(RISCVHartArrayState *s, i= nt idx, { object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx], cpu_typ= e); qdev_prop_set_uint64(DEVICE(&s->harts[idx]), "resetvec", s->resetvec); + qdev_prop_set_uint64(DEVICE(&s->harts[idx]), "rnmi_irqvec", + s->rnmi_irqvec); + qdev_prop_set_uint64(DEVICE(&s->harts[idx]), "rnmi_excpvec", + s->rnmi_excpvec); s->harts[idx].env.mhartid =3D s->hartid_base + idx; qemu_register_reset(riscv_harts_cpu_reset, &s->harts[idx]); return qdev_realize(DEVICE(&s->harts[idx]), NULL, errp); diff --git a/include/hw/riscv/riscv_hart.h b/include/hw/riscv/riscv_hart.h index bbc21cdc9a6..48e6730d832 100644 --- a/include/hw/riscv/riscv_hart.h +++ b/include/hw/riscv/riscv_hart.h @@ -38,6 +38,8 @@ struct RISCVHartArrayState { uint32_t hartid_base; char *cpu_type; uint64_t resetvec; + uint64_t rnmi_irqvec; + uint64_t rnmi_excpvec; RISCVCPU *harts; }; =20 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7d6ed80f6b6..9fb6ceb0ad8 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -137,6 +137,14 @@ static void set_feature(CPURISCVState *env, int featur= e) env->features |=3D (1ULL << feature); } =20 +static void set_rnmi_vectors(CPURISCVState *env, int irqvec, int excpvec) +{ +#ifndef CONFIG_USER_ONLY + env->rnmi_irqvec =3D irqvec; + env->rnmi_excpvec =3D excpvec; +#endif +} + static void set_resetvec(CPURISCVState *env, int resetvec) { #ifndef CONFIG_USER_ONLY @@ -373,6 +381,23 @@ static void riscv_cpu_disas_set_info(CPUState *s, disa= ssemble_info *info) } } =20 +#ifndef CONFIG_USER_ONLY +static void riscv_cpu_set_rnmi(void *opaque, int irq, int level) +{ + RISCVCPU *cpu =3D opaque; + CPURISCVState *env =3D &cpu->env; + CPUState *cs =3D CPU(cpu); + + if (level) { + env->nmip |=3D 1 << irq; + cpu_interrupt(cs, CPU_INTERRUPT_RNMI); + } else { + env->nmip &=3D ~(1 << irq); + cpu_reset_interrupt(cs, CPU_INTERRUPT_RNMI); + } +} +#endif + static void riscv_cpu_realize(DeviceState *dev, Error **errp) { CPUState *cs =3D CPU(dev); @@ -416,6 +441,16 @@ static void riscv_cpu_realize(DeviceState *dev, Error = **errp) =20 set_resetvec(env, cpu->cfg.resetvec); =20 + if (cpu->cfg.rnmi) { + set_feature(env, RISCV_FEATURE_RNMI); + set_rnmi_vectors(env, cpu->cfg.rnmi_irqvec, cpu->cfg.rnmi_excpvec); +#ifndef CONFIG_USER_ONLY + env->nmie =3D true; + qdev_init_gpio_in_named(DEVICE(cpu), riscv_cpu_set_rnmi, + "rnmi", TARGET_LONG_BITS); +#endif + } + /* If only XLEN is set for misa, then set misa from properties */ if (env->misa =3D=3D RV32 || env->misa =3D=3D RV64) { /* Do some ISA extension error checking */ @@ -555,6 +590,11 @@ static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC), + DEFINE_PROP_BOOL("rnmi", RISCVCPU, cfg.rnmi, false), + DEFINE_PROP_UINT64("rnmi_irqvec", RISCVCPU, cfg.rnmi_irqvec, + DEFAULT_RNMI_IRQVEC), + DEFINE_PROP_UINT64("rnmi_excpvec", RISCVCPU, cfg.rnmi_excpvec, + DEFAULT_RNMI_EXCPVEC), DEFINE_PROP_END_OF_LIST(), }; =20 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0a33d387ba8..7d2bb7e7003 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -80,7 +80,8 @@ enum { RISCV_FEATURE_MMU, RISCV_FEATURE_PMP, - RISCV_FEATURE_MISA + RISCV_FEATURE_MISA, + RISCV_FEATURE_RNMI, }; =20 #define PRIV_VERSION_1_10_0 0x00011000 @@ -178,6 +179,12 @@ struct CPURISCVState { target_ulong mcause; target_ulong mtval; /* since: priv-1.10.0 */ =20 + /* NMI */ + bool nmie; + target_ulong nmip; + target_ulong rnmi_irqvec; + target_ulong rnmi_excpvec; + /* Hypervisor CSRs */ target_ulong hstatus; target_ulong hedeleg; @@ -304,6 +311,9 @@ struct RISCVCPU { bool mmu; bool pmp; uint64_t resetvec; + bool rnmi; + uint64_t rnmi_irqvec; + uint64_t rnmi_excpvec; } cfg; }; =20 diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index caf45992070..8e5f0be599a 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -526,6 +526,12 @@ /* Default Reset Vector adress */ #define DEFAULT_RSTVEC 0x1000 =20 +/* Default RNMI Interrupt Vector address */ +#define DEFAULT_RNMI_IRQVEC 0x1000 + +/* Default RNMI Exception Vector address */ +#define DEFAULT_RNMI_EXCPVEC 0x1000 + /* Exception causes */ #define EXCP_NONE -1 /* sentinel value */ #define RISCV_EXCP_INST_ADDR_MIS 0x0 --=20 2.17.1 From nobody Tue May 7 08:40:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 01 Apr 2021 02:27:11 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC v2 2/4] target/riscv: add RNMI CSRs Date: Thu, 1 Apr 2021 17:26:49 +0800 Message-Id: <20210401092659.12014-3-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210401092659.12014-1-frank.chang@sifive.com> References: <20210401092659.12014-1-frank.chang@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=frank.chang@sifive.com; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Frank Chang , Alistair Francis , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/cpu.h | 4 +++ target/riscv/cpu_bits.h | 9 +++++++ target/riscv/csr.c | 59 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 72 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7d2bb7e7003..674ee4dc999 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -180,6 +180,10 @@ struct CPURISCVState { target_ulong mtval; /* since: priv-1.10.0 */ =20 /* NMI */ + target_ulong mnscratch; + target_ulong mnepc; + target_ulong mncause; /* mncause without bit XLEN-1 set to 1 */ + target_ulong mnstatus; bool nmie; target_ulong nmip; target_ulong rnmi_irqvec; diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 8e5f0be599a..a376ede0cc5 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -166,6 +166,12 @@ #define CSR_MTVAL 0x343 #define CSR_MIP 0x344 =20 +/* NMI */ +#define CSR_MNSCRATCH 0x350 +#define CSR_MNEPC 0x351 +#define CSR_MNCAUSE 0x352 +#define CSR_MNSTATUS 0x353 + /* Legacy Machine Trap Handling (priv v1.9.1) */ #define CSR_MBADADDR 0x343 =20 @@ -558,6 +564,9 @@ #define RISCV_EXCP_INT_FLAG 0x80000000 #define RISCV_EXCP_INT_MASK 0x7fffffff =20 +/* RNMI mnstatus CSR mask */ +#define MNSTATUS_MPP MSTATUS_MPP + /* Interrupt causes */ #define IRQ_U_SOFT 0 #define IRQ_S_SOFT 1 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d2585395bfb..489d6d90e68 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -188,6 +188,11 @@ static int pmp(CPURISCVState *env, int csrno) { return -!riscv_feature(env, RISCV_FEATURE_PMP); } + +static int nmi(CPURISCVState *env, int csrno) +{ + return -!riscv_feature(env, RISCV_FEATURE_RNMI); +} #endif =20 /* User Floating-Point CSRs */ @@ -713,6 +718,54 @@ static int write_mbadaddr(CPURISCVState *env, int csrn= o, target_ulong val) return 0; } =20 +static int read_mnscratch(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->mnscratch; + return 0; +} + +static int write_mnscratch(CPURISCVState *env, int csrno, target_ulong val) +{ + env->mnscratch =3D val; + return 0; +} + +static int read_mnepc(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->mnepc; + return 0; +} + +static int write_mnepc(CPURISCVState *env, int csrno, target_ulong val) +{ + env->mnepc =3D val; + return 0; +} + +static int read_mncause(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->mncause; + return 0; +} + +static int write_mncause(CPURISCVState *env, int csrno, target_ulong val) +{ + env->mncause =3D val; + return 0; +} + +static int read_mnstatus(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->mnstatus; + return 0; +} + +static int write_mnstatus(CPURISCVState *env, int csrno, target_ulong val) +{ + env->mnstatus =3D val & MNSTATUS_MPP; + return 0; +} + static int rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value, target_ulong new_value, target_ulong write_mask) { @@ -1428,6 +1481,12 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_MBADADDR] =3D { "mbadaddr", any, read_mbadaddr, write_mbadaddr }, [CSR_MIP] =3D { "mip", any, NULL, NULL, rmw_mip }, =20 + /* NMI */ + [CSR_MNSCRATCH] =3D { "mnscratch", nmi, read_mnscratch, write_mnscratc= h }, + [CSR_MNEPC] =3D { "mnepc", nmi, read_mnepc, write_mnepc = }, + [CSR_MNCAUSE] =3D { "mncause", nmi, read_mncause, write_mncause = }, + [CSR_MNSTATUS] =3D { "mnstatus", nmi, read_mnstatus, write_mnstatus= }, + /* Supervisor Trap Setup */ [CSR_SSTATUS] =3D { "sstatus", smode, read_sstatus, write_sst= atus }, [CSR_SIE] =3D { "sie", smode, read_sie, write_sie= }, --=20 2.17.1 From nobody Tue May 7 08:40:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 01 Apr 2021 02:27:14 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC v2 3/4] target/riscv: handle RNMI interrupt and exception Date: Thu, 1 Apr 2021 17:26:50 +0800 Message-Id: <20210401092659.12014-4-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210401092659.12014-1-frank.chang@sifive.com> References: <20210401092659.12014-1-frank.chang@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=frank.chang@sifive.com; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Frank Chang , Alistair Francis , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/cpu_bits.h | 4 ++++ target/riscv/cpu_helper.c | 49 +++++++++++++++++++++++++++++++++++---- 2 files changed, 49 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index a376ede0cc5..937b1f28455 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -607,4 +607,8 @@ #define MIE_UTIE (1 << IRQ_U_TIMER) #define MIE_SSIE (1 << IRQ_S_SOFT) #define MIE_USIE (1 << IRQ_U_SOFT) + +/* RISC-V-specific interrupt pending bits. */ +#define CPU_INTERRUPT_RNMI CPU_INTERRUPT_TGT_EXT_0 + #endif diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 21c54ef5613..67a633154a9 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -38,6 +38,19 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) #ifndef CONFIG_USER_ONLY static int riscv_cpu_local_irq_pending(CPURISCVState *env) { + if (riscv_feature(env, RISCV_FEATURE_RNMI)) { + /* Priority: RNMI > Other interrupt. */ + if (env->nmip && env->nmie) { + return ctz64(env->nmip); /* since non-zero */ + } else if (!env->nmie) { + /* + * We are already in RNMI handler, + * other interrupts cannot preempt. + */ + return EXCP_NONE; + } + } + target_ulong irqs; =20 target_ulong mstatus_mie =3D get_field(env->mstatus, MSTATUS_MIE); @@ -80,7 +93,9 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env) bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { #if !defined(CONFIG_USER_ONLY) - if (interrupt_request & CPU_INTERRUPT_HARD) { + uint32_t mask =3D CPU_INTERRUPT_HARD | CPU_INTERRUPT_RNMI; + + if (interrupt_request & mask) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; int interruptno =3D riscv_cpu_local_irq_pending(env); @@ -909,6 +924,23 @@ void riscv_cpu_do_interrupt(CPUState *cs) target_ulong tval =3D 0; target_ulong htval =3D 0; target_ulong mtval2 =3D 0; + target_ulong nextpc; + bool nmi_execp =3D false; + + if (riscv_feature(env, RISCV_FEATURE_RNMI)) { + nmi_execp =3D !env->nmie && !async; + + if (env->nmip && async) { + env->nmie =3D false; + env->mnstatus =3D set_field(env->mnstatus, MSTATUS_MPP, + env->priv); + env->mncause =3D cause; + env->mnepc =3D env->pc; + env->pc =3D env->rnmi_irqvec; + riscv_cpu_set_mode(env, PRV_M); + goto handled; + } + } =20 if (cause =3D=3D RISCV_EXCP_SEMIHOST) { if (env->priv >=3D PRV_S) { @@ -967,7 +999,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) __func__, env->mhartid, async, cause, env->pc, tval, riscv_cpu_get_trap_name(cause, async)); =20 - if (env->priv <=3D PRV_S && + if (env->priv <=3D PRV_S && !nmi_execp && cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) { /* handle the trap in S-mode */ if (riscv_has_ext(env, RVH)) { @@ -1056,8 +1088,15 @@ void riscv_cpu_do_interrupt(CPUState *cs) env->mepc =3D env->pc; env->mbadaddr =3D tval; env->mtval2 =3D mtval2; - env->pc =3D (env->mtvec >> 2 << 2) + - ((async && (env->mtvec & 3) =3D=3D 1) ? cause * 4 : 0); + + if (nmi_execp) { + nextpc =3D env->rnmi_excpvec; + } else { + nextpc =3D (env->mtvec >> 2 << 2) + + ((async && (env->mtvec & 3) =3D=3D 1) ? cause * 4 : 0); + } + env->pc =3D nextpc; + riscv_cpu_set_mode(env, PRV_M); } =20 @@ -1068,6 +1107,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) */ =20 env->two_stage_lookup =3D false; + +handled: #endif cs->exception_index =3D EXCP_NONE; /* mark handled to qemu */ } --=20 2.17.1 From nobody Tue May 7 08:40:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1617269657; cv=none; d=zohomail.com; s=zohoarc; b=dbuLoCzk/IyfGROVgDGVOWGGOsqLS7fXb+xfGMP5EN2WuVs/dJRYk+oYsJ/Of2kkfOcB2PzZKvDzDo5/j8qIKMqaPQC9U8DdupifUOmM95OObKcvQFzReff8SbYyX7JPsrbM3Iy2FGVymM2ph5H3Ni20fntWPhuWTKCjXJv3N5w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1617269657; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; 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Thu, 01 Apr 2021 02:27:18 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC v2 4/4] target/riscv: add RNMI mnret instruction Date: Thu, 1 Apr 2021 17:26:51 +0800 Message-Id: <20210401092659.12014-5-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210401092659.12014-1-frank.chang@sifive.com> References: <20210401092659.12014-1-frank.chang@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=frank.chang@sifive.com; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Keith Packard , Sagar Karandikar , Frank Chang , Bastian Koppelmann , Bin Meng , Richard Henderson , Alistair Francis , Palmer Dabbelt , =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 3 ++ .../riscv/insn_trans/trans_privileged.c.inc | 13 ++++++++ target/riscv/op_helper.c | 31 +++++++++++++++++++ 4 files changed, 48 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index e3f3f41e891..0914d777d6d 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -65,6 +65,7 @@ DEF_HELPER_4(csrrc, tl, env, tl, tl, tl) #ifndef CONFIG_USER_ONLY DEF_HELPER_2(sret, tl, env, tl) DEF_HELPER_2(mret, tl, env, tl) +DEF_HELPER_2(mnret, tl, env, tl) DEF_HELPER_1(wfi, void, env) DEF_HELPER_1(tlb_flush, void, env) #endif diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 84080dd18ca..557f3394276 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -97,6 +97,9 @@ wfi 0001000 00101 00000 000 00000 1110011 sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm =20 +# *** NMI *** +mnret 0111000 00010 00000 000 00000 1110011 + # *** RV32I Base Instruction Set *** lui .................... ..... 0110111 @u auipc .................... ..... 0010111 @u diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/= insn_trans/trans_privileged.c.inc index 32312be2024..63c49dfe6fb 100644 --- a/target/riscv/insn_trans/trans_privileged.c.inc +++ b/target/riscv/insn_trans/trans_privileged.c.inc @@ -106,6 +106,19 @@ static bool trans_mret(DisasContext *ctx, arg_mret *a) #endif } =20 +static bool trans_mnret(DisasContext *ctx, arg_mnret *a) +{ +#ifndef CONFIG_USER_ONLY + tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); + gen_helper_mnret(cpu_pc, cpu_env, cpu_pc); + exit_tb(ctx); /* no chaining */ + ctx->base.is_jmp =3D DISAS_NORETURN; + return true; +#else + return false; +#endif +} + static bool trans_wfi(DisasContext *ctx, arg_wfi *a) { #ifndef CONFIG_USER_ONLY diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 1eddcb94de7..b9601776153 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -175,6 +175,37 @@ target_ulong helper_mret(CPURISCVState *env, target_ul= ong cpu_pc_deb) return retpc; } =20 +target_ulong helper_mnret(CPURISCVState *env, target_ulong cpu_pc_deb) +{ + if (!riscv_feature(env, RISCV_FEATURE_RNMI)) { + /* RNMI feature is not presented. */ + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + } + + if (!(env->priv >=3D PRV_M)) { + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + } + + /* Get return PC from mnepc CSR. */ + target_ulong retpc =3D env->mnepc; + if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) { + riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC()); + } + + /* Get previous privilege level from mnstatus CSR. */ + target_ulong prev_priv =3D get_field(env->mnstatus, MNSTATUS_MPP); + + if (!pmp_get_num_rules(env) && (prev_priv !=3D PRV_M)) { + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + } + + riscv_cpu_set_mode(env, prev_priv); + + env->nmie =3D true; + + return retpc; +} + void helper_wfi(CPURISCVState *env) { CPUState *cs =3D env_cpu(env); --=20 2.17.1