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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id e17sm6400815wra.65.2021.03.31.08.48.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Mar 2021 08:48:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=2HTH7bfVRFqZSDteSdGJ0DTQfjTvfEroWHTNBGdjjDs=; b=ypcLvtZ05HCLKZnwwSqVJwsKbH2CtWYaz9sds5aR7cYPjqQnv8jZUGl1UvB2S/QbuM 5MjXiL2tjnDQ87D2sW/5L7jl9vw/qM6gOs+LJfLbR68M+OEp53VED86J2yJcDTf8ixW9 zZTWM0i85Wqv5+3RDln9EiOJTJzjg2w/qsjZ4ujjiz/y3GeHTROpJwfjte30pH9yxdCb dt68odwmQvkEsX3cweP0x9TMSB1LU2/xk9EplB6G9ISvw0jV9XZiz6TM11r7lfLGyZkm bMNMJ0DyBoWuPvA6z/rqJ0ol/uhXr4fk25YOMwF2bmDzRZzKw9MMk+N7IsLMFwzGPX/j JtMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=2HTH7bfVRFqZSDteSdGJ0DTQfjTvfEroWHTNBGdjjDs=; b=lhp7m1x+68aicsM40xqP2yZ2rPZXNMOIxYWlMIuuFSHpQUgV7Kkt7IytN4j+ILd1Ce P9xUtTNgLn43mlQQjx3bkW2HlHS4cTtk+A+CsFHbLVDWlQFJGfeMByn6cPaP7MWl4qyC Se21YOFdDFUDvlYNt317TFKC44Q2AJ2hlOcKMejoBOs4JWDjLhmwm0F7VpN4m6iaMo/s lC98V7CEP0PvWnKb8pdcKjO9QzCSZI1dXcCxKOdKVVfn0NuN/LzixmxlmpsAHstIVZ6a SKr9/R/BeteRo78EJP6atyuI9MonZxMkHSjti0v4d6Yaw8PZotzaqRz1jpZbjiYIBedt iOGw== X-Gm-Message-State: AOAM531VgkQL8N+T6uwfM0r5f9prXOsbOH+W7Ryi/P3bOlDjHzPJWF2Y K74aRRcYB1Oxv3YEUze9j9ww5iQUj3sgWqcK X-Google-Smtp-Source: ABdhPJzdudBzTV8CCsS07GMaLUEUEWwxPfS03yCewV04oDXVIgOlcnc35rt31kYUCAtjy9wSJJO0/w== X-Received: by 2002:a5d:6048:: with SMTP id j8mr4599251wrt.115.1617205706755; Wed, 31 Mar 2021 08:48:26 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH for-6.0] Revert "target/arm: Make number of counters in PMCR follow the CPU" Date: Wed, 31 Mar 2021 16:48:22 +0100 Message-Id: <20210331154822.23332-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Zenghui Yu , Marcin Juszkiewicz , Leif Lindholm Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" This reverts commit f7fb73b8cdd3f77e26f9fcff8cf24ff1b58d200f. This change turned out to be a bit half-baked, and doesn't work with KVM, which fails with the error: "qemu-system-aarch64: Failed to retrieve host CPU features" because KVM does not allow accessing of the PMCR_EL0 value in the scratch "query CPU ID registers" VM unless we have first set the KVM_ARM_VCPU_PMU_V3 feature on the VM. Revert the change for 6.0. Reported-by: Zenghui Yu Signed-off-by: Peter Maydell Tested-by: Zenghui Yu --- I suspect the changes required to make KVM work are not very complicated -- it's going to look pretty much like the way we deal with getting SVE vector lengths, where we do it after we have decided we need to enable the feature. But I don't have time to work on this right now, hence punting to 6.1. --- target/arm/cpu.h | 1 - target/arm/cpu64.c | 3 --- target/arm/cpu_tcg.c | 5 ----- target/arm/helper.c | 29 ++++++++++++----------------- target/arm/kvm64.c | 2 -- 5 files changed, 12 insertions(+), 28 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index fe68f464b3a..193a49ec7fa 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -942,7 +942,6 @@ struct ARMCPU { uint64_t id_aa64mmfr2; uint64_t id_aa64dfr0; uint64_t id_aa64dfr1; - uint64_t reset_pmcr_el0; } isar; uint64_t midr; uint32_t revidr; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 5d9d56a33c3..f0a9e968c9c 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -141,7 +141,6 @@ static void aarch64_a57_initfn(Object *obj) cpu->gic_num_lrs =3D 4; cpu->gic_vpribits =3D 5; cpu->gic_vprebits =3D 5; - cpu->isar.reset_pmcr_el0 =3D 0x41013000; define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); } =20 @@ -195,7 +194,6 @@ static void aarch64_a53_initfn(Object *obj) cpu->gic_num_lrs =3D 4; cpu->gic_vpribits =3D 5; cpu->gic_vprebits =3D 5; - cpu->isar.reset_pmcr_el0 =3D 0x41033000; define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); } =20 @@ -247,7 +245,6 @@ static void aarch64_a72_initfn(Object *obj) cpu->gic_num_lrs =3D 4; cpu->gic_vpribits =3D 5; cpu->gic_vprebits =3D 5; - cpu->isar.reset_pmcr_el0 =3D 0x41023000; define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); } =20 diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 8252fd29f90..046e476f65f 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -301,7 +301,6 @@ static void cortex_a8_initfn(Object *obj) cpu->ccsidr[1] =3D 0x2007e01a; /* 16k L1 icache. */ cpu->ccsidr[2] =3D 0xf0000000; /* No L2 icache. */ cpu->reset_auxcr =3D 2; - cpu->isar.reset_pmcr_el0 =3D 0x41002000; define_arm_cp_regs(cpu, cortexa8_cp_reginfo); } =20 @@ -374,7 +373,6 @@ static void cortex_a9_initfn(Object *obj) cpu->clidr =3D (1 << 27) | (1 << 24) | 3; cpu->ccsidr[0] =3D 0xe00fe019; /* 16k L1 dcache. */ cpu->ccsidr[1] =3D 0x200fe019; /* 16k L1 icache. */ - cpu->isar.reset_pmcr_el0 =3D 0x41093000; define_arm_cp_regs(cpu, cortexa9_cp_reginfo); } =20 @@ -445,7 +443,6 @@ static void cortex_a7_initfn(Object *obj) cpu->ccsidr[0] =3D 0x701fe00a; /* 32K L1 dcache */ cpu->ccsidr[1] =3D 0x201fe00a; /* 32K L1 icache */ cpu->ccsidr[2] =3D 0x711fe07a; /* 4096K L2 unified cache */ - cpu->isar.reset_pmcr_el0 =3D 0x41072000; define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ } =20 @@ -488,7 +485,6 @@ static void cortex_a15_initfn(Object *obj) cpu->ccsidr[0] =3D 0x701fe00a; /* 32K L1 dcache */ cpu->ccsidr[1] =3D 0x201fe00a; /* 32K L1 icache */ cpu->ccsidr[2] =3D 0x711fe07a; /* 4096K L2 unified cache */ - cpu->isar.reset_pmcr_el0 =3D 0x410F3000; define_arm_cp_regs(cpu, cortexa15_cp_reginfo); } =20 @@ -721,7 +717,6 @@ static void cortex_r5_initfn(Object *obj) cpu->isar.id_isar6 =3D 0x0; cpu->mp_is_up =3D true; cpu->pmsav7_dregion =3D 16; - cpu->isar.reset_pmcr_el0 =3D 0x41151800; define_arm_cp_regs(cpu, cortexr5_cp_reginfo); } =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index 8fb6cc96e4d..d9220be7c5a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -38,6 +38,7 @@ #endif =20 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ +#define PMCR_NUM_COUNTERS 4 /* QEMU IMPDEF choice */ =20 #ifndef CONFIG_USER_ONLY =20 @@ -1148,9 +1149,7 @@ static const ARMCPRegInfo v6_cp_reginfo[] =3D { =20 static inline uint32_t pmu_num_counters(CPUARMState *env) { - ARMCPU *cpu =3D env_archcpu(env); - - return (cpu->isar.reset_pmcr_el0 & PMCRN_MASK) >> PMCRN_SHIFT; + return (env->cp15.c9_pmcr & PMCRN_MASK) >> PMCRN_SHIFT; } =20 /* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */ @@ -5754,6 +5753,13 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { .resetvalue =3D 0, .writefn =3D gt_hyp_ctl_write, .raw_writefn =3D raw_write }, #endif + /* The only field of MDCR_EL2 that has a defined architectural reset v= alue + * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N. + */ + { .name =3D "MDCR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 1, + .access =3D PL2_RW, .resetvalue =3D PMCR_NUM_COUNTERS, + .fieldoffset =3D offsetof(CPUARMState, cp15.mdcr_el2), }, { .name =3D "HPFAR", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D 0, .opc2 =3D 4, .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, @@ -6683,7 +6689,7 @@ static void define_pmu_regs(ARMCPU *cpu) * field as main ID register, and we implement four counters in * addition to the cycle count register. */ - unsigned int i, pmcrn =3D pmu_num_counters(&cpu->env); + unsigned int i, pmcrn =3D PMCR_NUM_COUNTERS; ARMCPRegInfo pmcr =3D { .name =3D "PMCR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D 0= , .opc2 =3D 0, .access =3D PL0_RW, @@ -6698,10 +6704,10 @@ static void define_pmu_regs(ARMCPU *cpu) .access =3D PL0_RW, .accessfn =3D pmreg_access, .type =3D ARM_CP_IO, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmcr), - .resetvalue =3D cpu->isar.reset_pmcr_el0, + .resetvalue =3D (cpu->midr & 0xff000000) | (pmcrn << PMCRN_SHIFT) | + PMCRLC, .writefn =3D pmcr_write, .raw_writefn =3D raw_write, }; - define_one_arm_cp_reg(cpu, &pmcr); define_one_arm_cp_reg(cpu, &pmcr64); for (i =3D 0; i < pmcrn; i++) { @@ -7819,17 +7825,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) .fieldoffset =3D offsetof(CPUARMState, cp15.vmpidr_el2) }, REGINFO_SENTINEL }; - /* - * The only field of MDCR_EL2 that has a defined architectural res= et - * value is MDCR_EL2.HPMN which should reset to the value of PMCR_= EL0.N. - */ - ARMCPRegInfo mdcr_el2 =3D { - .name =3D "MDCR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 1, - .access =3D PL2_RW, .resetvalue =3D pmu_num_counters(env), - .fieldoffset =3D offsetof(CPUARMState, cp15.mdcr_el2), - }; - define_one_arm_cp_reg(cpu, &mdcr_el2); define_arm_cp_regs(cpu, vpidr_regs); define_arm_cp_regs(cpu, el2_cp_reginfo); if (arm_feature(env, ARM_FEATURE_V8)) { diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 581335e49d3..dff85f6db94 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -566,8 +566,6 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *= ahcf) ARM64_SYS_REG(3, 0, 0, 7, 1)); err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr2, ARM64_SYS_REG(3, 0, 0, 7, 2)); - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0, - ARM64_SYS_REG(3, 3, 9, 12, 0)); =20 /* * Note that if AArch32 support is not present in the host, --=20 2.20.1