From nobody Sun May 19 01:26:43 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1617111037; cv=none; d=zohomail.com; s=zohoarc; b=BUJ5C70S/q9lmykfUG0THlVp1UaPIum85ilsZUuR2UdSCg1T7ofDyTzL1uSP2NTWGbaVOhoSDWhDUJJSWNq2/JGqNz0JmHGv4QGfm6M3kcGiCz3Babgl3wF2Vx4P2Va6dSaOhklWaHxhI8g6fceg0PJVFpS2hoh2KWiGo/gQJLU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1617111037; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=bR9eSdSf4qznX0LV24L+tKEZx+CKvg1TgSxkuks1KkM=; b=oLYtRJ67TANUq4IiYFxw6I8kHRt59Z7T6oz6bJ4XUG7Tj4i+mOWOTDWe4q6DQ2PCsvLnhTKoBLjsRsphi+hMxXnapN1SVQNoERdh+vF38825XUDixTI9vu3Vw6C5B35kHCckp4QzwF9kXFy4p0vDR6EvW42/lAUtFnioLCyYdtM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1617111037837776.352767047613; Tue, 30 Mar 2021 06:30:37 -0700 (PDT) Received: from localhost ([::1]:42238 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lRES4-0003Sq-GP for importer@patchew.org; Tue, 30 Mar 2021 09:30:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41276) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lRENf-0006oS-Rm for qemu-devel@nongnu.org; Tue, 30 Mar 2021 09:26:03 -0400 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]:45980) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lRENb-0003bW-O8 for qemu-devel@nongnu.org; Tue, 30 Mar 2021 09:26:03 -0400 Received: by mail-wr1-x433.google.com with SMTP id j9so14525101wrx.12 for ; Tue, 30 Mar 2021 06:25:59 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id p18sm33140892wrs.68.2021.03.30.06.25.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Mar 2021 06:25:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=bR9eSdSf4qznX0LV24L+tKEZx+CKvg1TgSxkuks1KkM=; b=Mw/LK2+bA1T3fuE+T2rjLweWEJv1Vx3OOyvaUiy9Uxi6X7AcoKS8Pdbj4F+vFwO4Mk +MrL5bbOS39PhttX5WSI3szBDZqPx0RlbjpV0MmcSbjhl4Em3MRHYmXr2jYmuhZ+VLSd E5vMYzh5E9lPuqj0flLWNQ0AUt2aKd+0Iu/EpgZyG2tdxpWDgrxxCLds8eKF9QVF5KSB qlHwB4r97UDYizlwW9FVwUbbCPLaNpSxouH0VHtuWDVsWks2e/Wfda+o0Mwws5sgn0UK wPfKbHUEaw1/Wl2CmXI9riOwN2xGWYSsww2sz8xgOPl5bsuf2D/RfngzJm8oowOwpP+7 4akA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bR9eSdSf4qznX0LV24L+tKEZx+CKvg1TgSxkuks1KkM=; b=YherHVyIU/sVByeDiRt8Y/JrpyUXA3ZU1+wtQDDNRJi1/d4uvsYDL8VpkhT4hcFgVf 5tgbP+ICHF61g37M8ipJVXpI8QBsPp/FydsSIJpfs5Q0MRBgy8p2tWH2KEQc1RvwFCEZ NlwgjGqpT0IFGumSEL+E/OmsIU2kkFcPqU0r/qdLZsuyfCjYDfdJm4WoXu9kVFG6zOlm Tksal5mK3wcoKOGwWFBgSOJCrFaZJcS9nvZU7ZI4KxF3xen2ASQ3p2xmS7EheiLGPq+i yoOAIxmFfQjW8u0m3Xb8XPwku5Ynurc59kNgAnavWyy93BYKf2ZSeHiUJzyb9JrNud5P uLiQ== X-Gm-Message-State: AOAM533uEI64fqsU7PmRpUOmggIrt/WIKZGZ1WxcLyqTGDhqzh9ZsV4B gEwU2zMdy8U9nOy8eRzcZPHWq0e9iDwFV5uY X-Google-Smtp-Source: ABdhPJw/6fCbjS99bQfjmclGM5KfUZEi87MxsINO0zNcGcNhXpOSakhxfffr6xl91nEj99lMzgy89g== X-Received: by 2002:adf:b642:: with SMTP id i2mr33257940wre.8.1617110758101; Tue, 30 Mar 2021 06:25:58 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 1/5] net/npcm7xx_emc.c: Fix handling of receiving packets when RSDR not set Date: Tue, 30 Mar 2021 14:25:51 +0100 Message-Id: <20210330132555.8144-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210330132555.8144-1-peter.maydell@linaro.org> References: <20210330132555.8144-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Doug Evans Turning REG_MCMDR_RXON is enough to start receiving packets. Signed-off-by: Doug Evans Message-id: 20210319195044.741821-1-dje@google.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/net/npcm7xx_emc.c | 4 +++- tests/qtest/npcm7xx_emc-test.c | 30 +++++++++++++++++++++--------- 2 files changed, 24 insertions(+), 10 deletions(-) diff --git a/hw/net/npcm7xx_emc.c b/hw/net/npcm7xx_emc.c index 714a742ba7a..7c892f820fb 100644 --- a/hw/net/npcm7xx_emc.c +++ b/hw/net/npcm7xx_emc.c @@ -702,7 +702,9 @@ static void npcm7xx_emc_write(void *opaque, hwaddr offs= et, !(value & REG_MCMDR_RXON)) { emc->regs[REG_MGSTA] |=3D REG_MGSTA_RXHA; } - if (!(value & REG_MCMDR_RXON)) { + if (value & REG_MCMDR_RXON) { + emc->rx_active =3D true; + } else { emc_halt_rx(emc, 0); } break; diff --git a/tests/qtest/npcm7xx_emc-test.c b/tests/qtest/npcm7xx_emc-test.c index 7a281731950..9eec71d87c1 100644 --- a/tests/qtest/npcm7xx_emc-test.c +++ b/tests/qtest/npcm7xx_emc-test.c @@ -492,9 +492,6 @@ static void enable_tx(QTestState *qts, const EMCModule = *mod, mcmdr |=3D REG_MCMDR_TXON; emc_write(qts, mod, REG_MCMDR, mcmdr); } - - /* Prod the device to send the packet. */ - emc_write(qts, mod, REG_TSDR, 1); } =20 static void emc_send_verify1(QTestState *qts, const EMCModule *mod, int fd, @@ -558,6 +555,9 @@ static void emc_send_verify(QTestState *qts, const EMCM= odule *mod, int fd, enable_tx(qts, mod, &desc[0], NUM_TX_DESCRIPTORS, desc_addr, with_irq ? REG_MIEN_ENTXINTR : 0); =20 + /* Prod the device to send the packet. */ + emc_write(qts, mod, REG_TSDR, 1); + /* * It's problematic to observe the interrupt for each packet. * Instead just wait until all the packets go out. @@ -643,13 +643,10 @@ static void enable_rx(QTestState *qts, const EMCModul= e *mod, mcmdr |=3D REG_MCMDR_RXON | mcmdr_flags; emc_write(qts, mod, REG_MCMDR, mcmdr); } - - /* Prod the device to accept a packet. */ - emc_write(qts, mod, REG_RSDR, 1); } =20 static void emc_recv_verify(QTestState *qts, const EMCModule *mod, int fd, - bool with_irq) + bool with_irq, bool pump_rsdr) { NPCM7xxEMCRxDesc desc[NUM_RX_DESCRIPTORS]; uint32_t desc_addr =3D DESC_ADDR; @@ -679,6 +676,15 @@ static void emc_recv_verify(QTestState *qts, const EMC= Module *mod, int fd, enable_rx(qts, mod, &desc[0], NUM_RX_DESCRIPTORS, desc_addr, with_irq ? REG_MIEN_ENRXINTR : 0, 0); =20 + /* + * If requested, prod the device to accept a packet. + * This isn't necessary, the linux driver doesn't do this. + * Test doing/not-doing this for robustness. + */ + if (pump_rsdr) { + emc_write(qts, mod, REG_RSDR, 1); + } + /* Send test packet to device's socket. */ ret =3D iov_send(fd, iov, 2, 0, sizeof(len) + sizeof(test)); g_assert_cmpint(ret, =3D=3D , sizeof(test) + sizeof(len)); @@ -826,8 +832,14 @@ static void test_rx(gconstpointer test_data) =20 qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic"); =20 - emc_recv_verify(qts, td->module, test_sockets[0], /*with_irq=3D*/false= ); - emc_recv_verify(qts, td->module, test_sockets[0], /*with_irq=3D*/true); + emc_recv_verify(qts, td->module, test_sockets[0], /*with_irq=3D*/false, + /*pump_rsdr=3D*/false); + emc_recv_verify(qts, td->module, test_sockets[0], /*with_irq=3D*/false, + /*pump_rsdr=3D*/true); + emc_recv_verify(qts, td->module, test_sockets[0], /*with_irq=3D*/true, + /*pump_rsdr=3D*/false); + emc_recv_verify(qts, td->module, test_sockets[0], /*with_irq=3D*/true, + /*pump_rsdr=3D*/true); emc_test_ptle(qts, td->module, test_sockets[0]); =20 qtest_quit(qts); --=20 2.20.1 From nobody Sun May 19 01:26:43 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1617110855; cv=none; d=zohomail.com; s=zohoarc; b=Etc5senlgfNuaJHpbMUoUe0edDniMv68e2M4Ey3eDrPkpVz7GDE+gtVO62GQXd25chWzExjx2RESE6072PahxC9MM9pNn3S5ypdou4nKyvtm7c/uC6WustwrHbuB7R5YA487iOKOxQSOEQv/PRVQLly90zMrlQi8DZpbJXOKU9Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1617110855; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Q521bSACgOTA+AcHoRMQbgV3YPYoW/eT88h0y+3lw94=; b=CqDjtJrGHI89UfqTdr3EQkgr3T72Mo7kG/okqg5O0AxS8M3eWY3Qs/0S3mSVN2KstK6/0TF/GiTb0Y+9R6AXJ/LldlwjvQ5ajX0WHlbaBQGfGuaBLt8OtmSTryqheQXIBz9vh5tVRG5YJ4fXWq2h5e3VzkHatxtunlQAn8VxR70= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1617110855521109.34344082050518; Tue, 30 Mar 2021 06:27:35 -0700 (PDT) Received: from localhost ([::1]:33856 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lREP8-0008Se-5M for importer@patchew.org; Tue, 30 Mar 2021 09:27:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41280) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lRENg-0006oh-4c for qemu-devel@nongnu.org; Tue, 30 Mar 2021 09:26:04 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:44634) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lRENc-0003c1-1U for qemu-devel@nongnu.org; Tue, 30 Mar 2021 09:26:03 -0400 Received: by mail-wr1-x432.google.com with SMTP id c8so16222873wrq.11 for ; Tue, 30 Mar 2021 06:25:59 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id p18sm33140892wrs.68.2021.03.30.06.25.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Mar 2021 06:25:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Q521bSACgOTA+AcHoRMQbgV3YPYoW/eT88h0y+3lw94=; b=B9LRHZA/BD0gWoIsS7bCBY1V2nBqwrBP2OfKoG+JkrpYWpNXMwOmJe8swMokVOMMk4 fEGR3b2bnkEAbIvQt2yp+p9z6vxwxr/vjFcLEw/C1D3sB/qegfPcJRfdKEze7EYlqt9B CDaYQcUA294bpO8FERIGUwWz9eDq3jjd4bfVuYa7SNxbKWfygN5HWXqb5QKo3yKPr52Z 128BUcD86iTcz10ewkNpylxZoUlFAJkCaqpeTb80mae9QL6/0LEPf3uVvKIzPQB0zM3P WuyC1qTCFHqdA8OlWYTVIPJZZznh7eYeKm7UIlZ3OZP9X0Hj2fGwbvD9SlQO9+u+6nzb 2OsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Q521bSACgOTA+AcHoRMQbgV3YPYoW/eT88h0y+3lw94=; b=e/NYjwOiPK6V3LnJ2FmWSZL8zKMmITIe6PH1YW4r3xZQ9Ivq4VtqpHJv6iocvsK4U0 //lAy/ZO+qPOmnXLFCWUsKXY6IyW4dhM0AIGzTaxLmBxDhvpIE+SY0DrExw22Chf6zwQ 1EwJATFtZCsERTYc7T5dPZFHfe9wskG9hTdTUMOwpdCCz80fTVf1tPsBG+JEsjMUMwyt pJLS5+GOCVzKy3oB+af4oEryIcf0nSZcf9sKBF/vSAPAqSHgAmvZiPg3d719qr51iWpG p7aFcuzdR77vhSePLNaljBze83nYJ5Wj52isIrWKzcU3mlEufaMWmiv4tAHnPC++tCsq VhxQ== X-Gm-Message-State: AOAM5325w+P5E/Zjl3DYsyk9Hs9YaOhXagqBMuFGbysygdZfFN8FQWM3 C0sej6pz08rXtAljE9hESpQA7QW/VtNW+elQ X-Google-Smtp-Source: ABdhPJy9u75DMdtNq5CgIh+VrOtDCVJ6AVm/AjfK8Y0MfPXTA5iFRPsZZ0Y2ehERjMnPgrJefPQyLA== X-Received: by 2002:a5d:68cd:: with SMTP id p13mr35520132wrw.247.1617110758678; Tue, 30 Mar 2021 06:25:58 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 2/5] hw/display/xlnx_dp: Free FIFOs adding xlnx_dp_finalize() Date: Tue, 30 Mar 2021 14:25:52 +0100 Message-Id: <20210330132555.8144-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210330132555.8144-1-peter.maydell@linaro.org> References: <20210330132555.8144-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Philippe Mathieu-Daud=C3=A9 When building with --enable-sanitizers we get: Direct leak of 16 byte(s) in 1 object(s) allocated from: #0 0x5618479ec7cf in malloc (qemu-system-aarch64+0x233b7cf) #1 0x7f675745f958 in g_malloc (/lib64/libglib-2.0.so.0+0x58958) #2 0x561847c2dcc9 in xlnx_dp_init hw/display/xlnx_dp.c:1259:5 #3 0x56184a5bdab8 in object_init_with_type qom/object.c:375:9 #4 0x56184a5a2bda in object_initialize_with_type qom/object.c:517:5 #5 0x56184a5a24d5 in object_initialize qom/object.c:536:5 #6 0x56184a5a2f6c in object_initialize_child_with_propsv qom/object.c= :566:5 #7 0x56184a5a2e60 in object_initialize_child_with_props qom/object.c:= 549:10 #8 0x56184a5a3a1e in object_initialize_child_internal qom/object.c:60= 3:5 #9 0x5618495aa431 in xlnx_zynqmp_init hw/arm/xlnx-zynqmp.c:273:5 The RX/TX FIFOs are created in xlnx_dp_init(), add xlnx_dp_finalize() to destroy them. Fixes: 58ac482a66d ("introduce xlnx-dp") Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Message-id: 20210323182958.277654-1-f4bug@amsat.org Signed-off-by: Peter Maydell --- hw/display/xlnx_dp.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/hw/display/xlnx_dp.c b/hw/display/xlnx_dp.c index c56e6ec5936..4fd6aeb18b5 100644 --- a/hw/display/xlnx_dp.c +++ b/hw/display/xlnx_dp.c @@ -1260,6 +1260,14 @@ static void xlnx_dp_init(Object *obj) fifo8_create(&s->tx_fifo, 16); } =20 +static void xlnx_dp_finalize(Object *obj) +{ + XlnxDPState *s =3D XLNX_DP(obj); + + fifo8_destroy(&s->tx_fifo); + fifo8_destroy(&s->rx_fifo); +} + static void xlnx_dp_realize(DeviceState *dev, Error **errp) { XlnxDPState *s =3D XLNX_DP(dev); @@ -1359,6 +1367,7 @@ static const TypeInfo xlnx_dp_info =3D { .parent =3D TYPE_SYS_BUS_DEVICE, .instance_size =3D sizeof(XlnxDPState), .instance_init =3D xlnx_dp_init, + .instance_finalize =3D xlnx_dp_finalize, .class_init =3D xlnx_dp_class_init, }; =20 --=20 2.20.1 From nobody Sun May 19 01:26:43 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1617111006; cv=none; d=zohomail.com; s=zohoarc; b=TkYxgzeXFGI5KqWGs8RZC3EcY2ImBsNueq4Dn1I2an4f6VMOgbBFBmmAAapcovA5JlBosuLGqFOjo1lJ/XmXkRm9apVR8aUqGZlC0wG+xbW/PsRdYqU1K2mJ92khWDk/XU4aBnTa3PhWEnGQoseQ0TC95cgR4cE8yIolQOWzMhY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1617111006; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=PNqwnnCZ5fWRV3b8fDgCxIuqTPRmrag5LEpt92bVsfw=; b=CvXN/UtTPLjMtS1e9hL1CAi0mDaUrIgGwuQeZ79xLKZ5iTzWn+KSpvoej1uNXM2Hpi+Nx+b2fPMMAW4saEISmHSdIDL8mlziPxhwO+J9crhNv4mgjtJWrps0T35Ue3JQ5/uXv8gT9CvgDIfp8DtDtUk1fbAH12o2K4i5YmYKr6I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16171110067931000.1188293805768; Tue, 30 Mar 2021 06:30:06 -0700 (PDT) Received: from localhost ([::1]:40746 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lRERZ-0002s8-7H for importer@patchew.org; Tue, 30 Mar 2021 09:30:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41296) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lRENh-0006r6-Hf for qemu-devel@nongnu.org; Tue, 30 Mar 2021 09:26:05 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]:35399) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lRENd-0003cc-QC for qemu-devel@nongnu.org; Tue, 30 Mar 2021 09:26:05 -0400 Received: by mail-wr1-x431.google.com with SMTP id j18so16252814wra.2 for ; Tue, 30 Mar 2021 06:26:00 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id p18sm33140892wrs.68.2021.03.30.06.25.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Mar 2021 06:25:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=PNqwnnCZ5fWRV3b8fDgCxIuqTPRmrag5LEpt92bVsfw=; b=jNxtu40Oty+gxZuTq00zLdgDZjiFxWuJSuccfL4cQ5PNnhG57dwktbtT+FjzYuoSM1 la3H5/8Q6PCnKlmXphlbLkN4H5dtjfCHXZzt/w/Ish/IVWjy17dQ+h4PkTcfulXtWWqb nO6/YCBDD/Lg/HvElFboAvBVAStA84SXZjAQ1BzXV3H+s93giXaNWGNjawfi83WCmqlb gbDmyMhtxJjTxJ0xLNVPiYiqBrjD30VFWZjNC9yu85GlyZNKEBzI0zeV3aZorYABmkzE 69bPEOyzMwMksT2m6fbLstIWAJA5lYGBRCwPk1FkPiXZ14VLIjyh+R6y2OywEbMsLRbd MSUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PNqwnnCZ5fWRV3b8fDgCxIuqTPRmrag5LEpt92bVsfw=; b=TwOpSS7weU1uusfTT6BA0Mt8zoYvBHSZYVZ7P88gGRc/5sBwO1kdeqQnKzYZKtM52D XuTwzlY51A5ZHuOw/XOaZ0qVO/QOQNjeI6h118+GjbP96W+T0CkC5MSR2kj7ax184BTb SzkaYSuH1pGxzDBWSNURM2S36dN/aLpeFh4flJ8wgucbU0UFSipJfk/49s3X3yhjGUzM FOSeqxzC3cPOWyOQnPGNMxjO5PWuKg8eegozTl/LbKic6ldLpoj86PN6P9YOG2iQQyoN jGtgZaSd3dyYoc1/w9tw6wF7toWZtnsAqh/gyO7JxWy9JwUjtQsLvcTyqum43dOeWPjP hAWA== X-Gm-Message-State: AOAM531JYvtlI5FhJQ1Zvlw9QIfETHrU4gzmsU/LDbpzuDd7pVJDTR7P CG1VNZRJhhEO6PTL/9NJoJZNRO3PaQd+I1qf X-Google-Smtp-Source: ABdhPJzGEgAb53wdgt79Sp9YN3LcRxIEkkQdHfUE/eFj8iXY1hVZ/Na86dral5LtmXUfPliobBdvqQ== X-Received: by 2002:adf:e392:: with SMTP id e18mr35015168wrm.189.1617110759245; Tue, 30 Mar 2021 06:25:59 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 3/5] hw/arm/smmuv3: Drop unused CDM_VALID() and is_cd_valid() Date: Tue, 30 Mar 2021 14:25:53 +0100 Message-Id: <20210330132555.8144-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210330132555.8144-1-peter.maydell@linaro.org> References: <20210330132555.8144-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Zenghui Yu They were introduced in commit 9bde7f0674fe ("hw/arm/smmuv3: Implement translate callback") but never actually used. Drop them. Signed-off-by: Zenghui Yu Acked-by: Eric Auger Message-id: 20210325142702.790-1-yuzenghui@huawei.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/smmuv3-internal.h | 7 ------- 1 file changed, 7 deletions(-) diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index b6f7e53b7c7..3dac5766ca3 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -595,13 +595,6 @@ static inline int pa_range(STE *ste) #define CD_A(x) extract32((x)->word[1], 14, 1) #define CD_AARCH64(x) extract32((x)->word[1], 9 , 1) =20 -#define CDM_VALID(x) ((x)->word[0] & 0x1) - -static inline int is_cd_valid(SMMUv3State *s, STE *ste, CD *cd) -{ - return CD_VALID(cd); -} - /** * tg2granule - Decodes the CD translation granule size field according * to the ttbr in use --=20 2.20.1 From nobody Sun May 19 01:26:43 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1617110856; cv=none; d=zohomail.com; s=zohoarc; b=btSFvcDHrG/O2MIdLmp2XORvbrXwdhAdrAIrRtwUo7KtZViM4X/xr3UR1CFyFenE4CxUkd/A+fWEwzt0zzDb994bcGxEC9qW4qJ/CEaG4/0q3zCPJNzRGs068+ZJ5144QpyvE2JQLAFQ84GLXbRHS44VjkfEmTcKQG+M7Z6iHB8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1617110856; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=mh5IX36T8uCqjf6qPRZrX1y8fSZELaua3vUHNVdcG+8=; b=YJWGU5yI6IbYjvts+1S6F1t7eYGaqh4cIC3jjmHizwV9Kvkb/BkIF21KPg/d1FPX845bvYUYGxlcxrmcTAsJ9uhBWHThtOhRryQ/3daSfW0xKDqr7ghFcjnRQj8lQ2IdbG4fp34OT3oyQyy4gDH7pFNc3M91WVtktANUtf6rdQc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1617110856302924.8078604521247; Tue, 30 Mar 2021 06:27:36 -0700 (PDT) Received: from localhost ([::1]:33950 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lREP9-0008Uo-36 for importer@patchew.org; Tue, 30 Mar 2021 09:27:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41286) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lRENg-0006ph-S1 for qemu-devel@nongnu.org; Tue, 30 Mar 2021 09:26:04 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]:36524) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lRENd-0003cm-Qe for qemu-devel@nongnu.org; Tue, 30 Mar 2021 09:26:04 -0400 Received: by mail-wr1-x430.google.com with SMTP id k8so16246163wrc.3 for ; Tue, 30 Mar 2021 06:26:00 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id p18sm33140892wrs.68.2021.03.30.06.25.59 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Mar 2021 06:25:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=mh5IX36T8uCqjf6qPRZrX1y8fSZELaua3vUHNVdcG+8=; b=fA4juvb46bAG0YegzPVTu0bTo1AfA/HDXT6fs2Mm16if14/vZMALR2KE0k/ZnYcOYl alk4h3qVeJe01+FpYQ81QQNwqfqjTkSS5Lal6orgfphHhPaX1pCS1ngq6cH9FoCLpnTh 2bs485qxZUULXcpWFWnDXP90kyJfCmQYvfK5Tl86mDB9fa+iy2Bj+RTSIXvmrcVmWP3O Ni3cCoXkV6+4N13qNnBILvAXP6vyDKyxNcWvvUhMBkI7IlK3ObyKwO2tapEQp3lvGY83 Yefwe/mT4Wodr86VMm0RFtLEkPeKXojdna3BqGX8z9cnZTk92k5yZZAJ8AdtYZdhr4GI j8QA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mh5IX36T8uCqjf6qPRZrX1y8fSZELaua3vUHNVdcG+8=; b=FOWEbZJIBIOnc2NinxNc/69Wy8BIBu/bMhxRykcm0EWnlU5VHFNOSd55KnR8s2BPo0 sp1GO+KV9juZ2+ajZOULybNiG1KZ84a06FVrj7yTm9IWos4j9DXGPw/BRzgeI6Gzvqn7 n6xGeltE7T0ZGgCipxgYm+55zZroaM2hB3OV5flQHU4oiDrDNxEeUCHjQOvusixCFtvk iHp0yz8coOc2psd9U0JTuswKrqq7/YcYwkrmHt4jSkzf1lFRK+la3EtlagIcVjS7IgwX zqxrZ9zI/Ggq95uVqKnyuVg6us51fwLGUw2oW3BfLcz4tkF0IfEEUyo6nS2Kr4ejTUPB FNyg== X-Gm-Message-State: AOAM532ef1S1ULe9FlXBl5WxnsjBGeyKMSGGa4Av95+9DxKbCUILPvvo DGX37uNWUciS+Wqm1jNzK034dWugwA3PMQxh X-Google-Smtp-Source: ABdhPJwD1q7xxc+JTgRgLjyupfXixxoE4/eyW7aFgxCrrE98GgUVSG14kx4RJq539TbMnykV3zmKkw== X-Received: by 2002:a5d:6304:: with SMTP id i4mr33918391wru.155.1617110759899; Tue, 30 Mar 2021 06:25:59 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 4/5] target/arm: Make number of counters in PMCR follow the CPU Date: Tue, 30 Mar 2021 14:25:54 +0100 Message-Id: <20210330132555.8144-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210330132555.8144-1-peter.maydell@linaro.org> References: <20210330132555.8144-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Currently we give all the v7-and-up CPUs a PMU with 4 counters. This means that we don't provide the 6 counters that are required by the Arm BSA (Base System Architecture) specification if the CPU supports the Virtualization extensions. Instead of having a single PMCR_NUM_COUNTERS, make each CPU type specify the PMCR reset value (obtained from the appropriate TRM), and use the 'N' field of that value to define the number of counters provided. This means that we now supply 6 counters for Cortex-A53, A57, A72, A15 and A9 as well as '-cpu max'; Cortex-A7 and A8 stay at 4; and Cortex-R5 goes down to 3. Note that because we now use the PMCR reset value of the specific implementation, we no longer set the LC bit out of reset. This has an UNKNOWN value out of reset for all cores with any AArch32 support, so guest software should be setting it anyway if it wants it. Signed-off-by: Peter Maydell Tested-by: Marcin Juszkiewicz Message-id: 20210311165947.27470-1-peter.maydell@linaro.org Reviewed-by: Richard Henderson --- target/arm/cpu.h | 1 + target/arm/cpu64.c | 3 +++ target/arm/cpu_tcg.c | 5 +++++ target/arm/helper.c | 29 +++++++++++++++++------------ target/arm/kvm64.c | 2 ++ 5 files changed, 28 insertions(+), 12 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 193a49ec7fa..fe68f464b3a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -942,6 +942,7 @@ struct ARMCPU { uint64_t id_aa64mmfr2; uint64_t id_aa64dfr0; uint64_t id_aa64dfr1; + uint64_t reset_pmcr_el0; } isar; uint64_t midr; uint32_t revidr; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index f0a9e968c9c..5d9d56a33c3 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -141,6 +141,7 @@ static void aarch64_a57_initfn(Object *obj) cpu->gic_num_lrs =3D 4; cpu->gic_vpribits =3D 5; cpu->gic_vprebits =3D 5; + cpu->isar.reset_pmcr_el0 =3D 0x41013000; define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); } =20 @@ -194,6 +195,7 @@ static void aarch64_a53_initfn(Object *obj) cpu->gic_num_lrs =3D 4; cpu->gic_vpribits =3D 5; cpu->gic_vprebits =3D 5; + cpu->isar.reset_pmcr_el0 =3D 0x41033000; define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); } =20 @@ -245,6 +247,7 @@ static void aarch64_a72_initfn(Object *obj) cpu->gic_num_lrs =3D 4; cpu->gic_vpribits =3D 5; cpu->gic_vprebits =3D 5; + cpu->isar.reset_pmcr_el0 =3D 0x41023000; define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); } =20 diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 046e476f65f..8252fd29f90 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -301,6 +301,7 @@ static void cortex_a8_initfn(Object *obj) cpu->ccsidr[1] =3D 0x2007e01a; /* 16k L1 icache. */ cpu->ccsidr[2] =3D 0xf0000000; /* No L2 icache. */ cpu->reset_auxcr =3D 2; + cpu->isar.reset_pmcr_el0 =3D 0x41002000; define_arm_cp_regs(cpu, cortexa8_cp_reginfo); } =20 @@ -373,6 +374,7 @@ static void cortex_a9_initfn(Object *obj) cpu->clidr =3D (1 << 27) | (1 << 24) | 3; cpu->ccsidr[0] =3D 0xe00fe019; /* 16k L1 dcache. */ cpu->ccsidr[1] =3D 0x200fe019; /* 16k L1 icache. */ + cpu->isar.reset_pmcr_el0 =3D 0x41093000; define_arm_cp_regs(cpu, cortexa9_cp_reginfo); } =20 @@ -443,6 +445,7 @@ static void cortex_a7_initfn(Object *obj) cpu->ccsidr[0] =3D 0x701fe00a; /* 32K L1 dcache */ cpu->ccsidr[1] =3D 0x201fe00a; /* 32K L1 icache */ cpu->ccsidr[2] =3D 0x711fe07a; /* 4096K L2 unified cache */ + cpu->isar.reset_pmcr_el0 =3D 0x41072000; define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ } =20 @@ -485,6 +488,7 @@ static void cortex_a15_initfn(Object *obj) cpu->ccsidr[0] =3D 0x701fe00a; /* 32K L1 dcache */ cpu->ccsidr[1] =3D 0x201fe00a; /* 32K L1 icache */ cpu->ccsidr[2] =3D 0x711fe07a; /* 4096K L2 unified cache */ + cpu->isar.reset_pmcr_el0 =3D 0x410F3000; define_arm_cp_regs(cpu, cortexa15_cp_reginfo); } =20 @@ -717,6 +721,7 @@ static void cortex_r5_initfn(Object *obj) cpu->isar.id_isar6 =3D 0x0; cpu->mp_is_up =3D true; cpu->pmsav7_dregion =3D 16; + cpu->isar.reset_pmcr_el0 =3D 0x41151800; define_arm_cp_regs(cpu, cortexr5_cp_reginfo); } =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index d9220be7c5a..8fb6cc96e4d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -38,7 +38,6 @@ #endif =20 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ -#define PMCR_NUM_COUNTERS 4 /* QEMU IMPDEF choice */ =20 #ifndef CONFIG_USER_ONLY =20 @@ -1149,7 +1148,9 @@ static const ARMCPRegInfo v6_cp_reginfo[] =3D { =20 static inline uint32_t pmu_num_counters(CPUARMState *env) { - return (env->cp15.c9_pmcr & PMCRN_MASK) >> PMCRN_SHIFT; + ARMCPU *cpu =3D env_archcpu(env); + + return (cpu->isar.reset_pmcr_el0 & PMCRN_MASK) >> PMCRN_SHIFT; } =20 /* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */ @@ -5753,13 +5754,6 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { .resetvalue =3D 0, .writefn =3D gt_hyp_ctl_write, .raw_writefn =3D raw_write }, #endif - /* The only field of MDCR_EL2 that has a defined architectural reset v= alue - * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N. - */ - { .name =3D "MDCR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 1, - .access =3D PL2_RW, .resetvalue =3D PMCR_NUM_COUNTERS, - .fieldoffset =3D offsetof(CPUARMState, cp15.mdcr_el2), }, { .name =3D "HPFAR", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D 0, .opc2 =3D 4, .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, @@ -6689,7 +6683,7 @@ static void define_pmu_regs(ARMCPU *cpu) * field as main ID register, and we implement four counters in * addition to the cycle count register. */ - unsigned int i, pmcrn =3D PMCR_NUM_COUNTERS; + unsigned int i, pmcrn =3D pmu_num_counters(&cpu->env); ARMCPRegInfo pmcr =3D { .name =3D "PMCR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D 0= , .opc2 =3D 0, .access =3D PL0_RW, @@ -6704,10 +6698,10 @@ static void define_pmu_regs(ARMCPU *cpu) .access =3D PL0_RW, .accessfn =3D pmreg_access, .type =3D ARM_CP_IO, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmcr), - .resetvalue =3D (cpu->midr & 0xff000000) | (pmcrn << PMCRN_SHIFT) | - PMCRLC, + .resetvalue =3D cpu->isar.reset_pmcr_el0, .writefn =3D pmcr_write, .raw_writefn =3D raw_write, }; + define_one_arm_cp_reg(cpu, &pmcr); define_one_arm_cp_reg(cpu, &pmcr64); for (i =3D 0; i < pmcrn; i++) { @@ -7825,6 +7819,17 @@ void register_cp_regs_for_features(ARMCPU *cpu) .fieldoffset =3D offsetof(CPUARMState, cp15.vmpidr_el2) }, REGINFO_SENTINEL }; + /* + * The only field of MDCR_EL2 that has a defined architectural res= et + * value is MDCR_EL2.HPMN which should reset to the value of PMCR_= EL0.N. + */ + ARMCPRegInfo mdcr_el2 =3D { + .name =3D "MDCR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 1, + .access =3D PL2_RW, .resetvalue =3D pmu_num_counters(env), + .fieldoffset =3D offsetof(CPUARMState, cp15.mdcr_el2), + }; + define_one_arm_cp_reg(cpu, &mdcr_el2); define_arm_cp_regs(cpu, vpidr_regs); define_arm_cp_regs(cpu, el2_cp_reginfo); if (arm_feature(env, ARM_FEATURE_V8)) { diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index dff85f6db94..581335e49d3 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -566,6 +566,8 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *= ahcf) ARM64_SYS_REG(3, 0, 0, 7, 1)); err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr2, ARM64_SYS_REG(3, 0, 0, 7, 2)); + err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0, + ARM64_SYS_REG(3, 3, 9, 12, 0)); =20 /* * Note that if AArch32 support is not present in the host, --=20 2.20.1 From nobody Sun May 19 01:26:43 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1617111036; cv=none; d=zohomail.com; s=zohoarc; b=RfqtLVaoE/juXxCopq6nWYEXFtcDjArEc/mwxwr/t+6L3nV71a9EKhaVhbMcUvTgBGtDzaTAjjQuMSftp4MInWpDvNZk7QkxuYRAvF6XNub0ca7ewESyfKuOkkQCDJGsQPfAIBeI64bIFKZtT/ewpotIzkLL1KYw3ieZ2yjFj6g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1617111036; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=j2HV5Z8jdtLpsP16bz3qFqgSmKj+sdmtLcdjZjBDvgY=; b=TTfWeuUFEJKJgoXtafx8SUykosYElOd38Cu5RyFh0FUUyYpACh5yxgI98mx+e18qzpf/vnKrcXOQ5hrl/Qxv0VAbBm5to1AEVJJkhDh+tvub8gUynHicS0x5U76Wiq+0CL9Wcuyvn4g7Tt1UslU1NxTr+H1aaovTDP63QlwkqoI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1617111036276986.4394203556075; Tue, 30 Mar 2021 06:30:36 -0700 (PDT) Received: from localhost ([::1]:42050 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lRES3-0003OX-0p for importer@patchew.org; Tue, 30 Mar 2021 09:30:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41282) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lRENg-0006on-4o for qemu-devel@nongnu.org; Tue, 30 Mar 2021 09:26:04 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]:37752) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lRENd-0003cs-TY for qemu-devel@nongnu.org; Tue, 30 Mar 2021 09:26:03 -0400 Received: by mail-wm1-x330.google.com with SMTP id f22-20020a7bc8d60000b029010c024a1407so10311905wml.2 for ; Tue, 30 Mar 2021 06:26:01 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id p18sm33140892wrs.68.2021.03.30.06.25.59 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Mar 2021 06:26:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=j2HV5Z8jdtLpsP16bz3qFqgSmKj+sdmtLcdjZjBDvgY=; b=qEdKpTBYNpKOyajBDYkPCR+mpDBRCubGKpooQiFbT5urIigKfyKiAbesbgawFpm5nk ZGnPGXSwL/V45BhracK2Ciod2mTIjzZmYGz9h3QEubncsLacI1+dMLB40tTQ/0G+YYOP oy+FMF80wuhJv1o6kQ6kwPR+WtANrpPggronWU5teG0AFiNHvrYFDg8MlnHx4z7oi5Y0 DLnIr/7G+OQAjiUAA19dElPI/PERP77p3LwNc4w+wTeclok+Nqy+qlskIk+5Veu4odnz /CnkT2ygYQVEB/XogDYbSMGriNOzCeH41QSyIdNHX17kYCprOIV4EMg/XIDa8eK7qWxm TJaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=j2HV5Z8jdtLpsP16bz3qFqgSmKj+sdmtLcdjZjBDvgY=; b=VLZDPS5g6oe+If58MrSRdvHu8tVk0vAy2VKMKJ2LOJLTEtc7VNOg9O9iswEzz46u70 B1yd3KICVaT0uC0mkla3t+vIzkyPs2p5T7ju/MzKm3KHQNWQWVjG0xpo7Vpr5VT08gZ3 kAA08D9SryYcuwDhvLQKaW9ENe1W11Uo0Cd1ULBnpMqPyngE8ug3lVvjDcAvSJnXYMMg 2Hrm7ohFw+z8IcKrnBZK842arTYYEIGJvI0sZ85e9QJcxqGXkmvYgIeIHqgmeKgVHtR/ a85Ib6Z3QBsdmLCI9qsQSrUzm7hJ8DdAM5jpeQ2SOpw/eeTya78CFDLCiAaqKWnWIcdE gSyg== X-Gm-Message-State: AOAM530L5Otno3NhzJQRgdHnqeC+aGSDMT4boX+skCMkMx4zB4Utxq6o 0a2FCgUrx43Tc/tWNJfJU0X75IhpiRTUi/pT X-Google-Smtp-Source: ABdhPJwgrd1Qvke35+Iow18pNfMJf3aJnsvqGC7b7hW0218JSrtoyRnno5mPbE9fF1h/q9PyyKItxg== X-Received: by 2002:a1c:2308:: with SMTP id j8mr4237349wmj.45.1617110760476; Tue, 30 Mar 2021 06:26:00 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 5/5] hw/timer/renesas_tmr: Add default-case asserts in read_tcnt() Date: Tue, 30 Mar 2021 14:25:55 +0100 Message-Id: <20210330132555.8144-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210330132555.8144-1-peter.maydell@linaro.org> References: <20210330132555.8144-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) In commit 81b3ddaf8772ec we fixed a use of uninitialized data in read_tcnt(). However this change wasn't enough to placate Coverity, which is not smart enough to see that if we read a 2 bit field and then handle cases 0, 1, 2 and 3 then there cannot be a flow of execution through the switch default. Add explicit default cases which assert that they can't be reached, which should help silence Coverity. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20210319162458.13760-1-peter.maydell@linaro.org --- hw/timer/renesas_tmr.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/timer/renesas_tmr.c b/hw/timer/renesas_tmr.c index eed39917fec..d96002e1ee6 100644 --- a/hw/timer/renesas_tmr.c +++ b/hw/timer/renesas_tmr.c @@ -146,6 +146,8 @@ static uint16_t read_tcnt(RTMRState *tmr, unsigned size= , int ch) case CSS_CASCADING: tcnt[1] =3D tmr->tcnt[1]; break; + default: + g_assert_not_reached(); } switch (FIELD_EX8(tmr->tccr[0], TCCR, CSS)) { case CSS_INTERNAL: @@ -159,6 +161,8 @@ static uint16_t read_tcnt(RTMRState *tmr, unsigned size= , int ch) case CSS_EXTERNAL: /* QEMU doesn't implement this */ tcnt[0] =3D tmr->tcnt[0]; break; + default: + g_assert_not_reached(); } } else { tcnt[0] =3D tmr->tcnt[0]; --=20 2.20.1