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b=YSX8uYQAIjdRYpnmLy03miRcfM/O1Mb9jzc7ox70R9XP2ghZhp2GO/1ZdfOOWbYwyzH0 xkvxhlNulRQq6k3qQkB9igy8IG2pntRghYwNrW/osTc9MCjAupScTwn4xcaZza8bg5hU pSfWWoMWLJG2vn4N0/Wfmj6KfIA1VsI7gBXtQa06c9zSt1Lzd9/c8Amg1GbZSABGU0TK YTAploa7N2F3ScW6qZv3HuSOHKwW9Cw0OGCqKl27YB2oJG2o+tEnPKSlqJs41uNrpK3C C0GkQHnKAAmTjE1Wn7CSwBOKYCu2ZHwPaTnuhVJEq0+QuuXAZ2sU5nY2HPpf6OMbhwVn eg== From: Klaus Heinrich Kiwi To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v3 1/2] aspeed: Add Scater-Gather support for HACE Hash Date: Fri, 26 Mar 2021 16:37:44 -0300 Message-Id: <20210326193745.13558-2-klaus@linux.vnet.ibm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210326193745.13558-1-klaus@linux.vnet.ibm.com> References: <20210326193745.13558-1-klaus@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: A7S12yiytvA_yK8FyyuThPPrCXvQqkNg X-Proofpoint-GUID: MH207dG8ZE-L3NbXLhMsXJbMwho9C2Gr X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761 definitions=2021-03-26_11:2021-03-26, 2021-03-26 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 phishscore=0 mlxlogscore=999 mlxscore=0 bulkscore=0 adultscore=0 malwarescore=0 priorityscore=1501 suspectscore=0 clxscore=1015 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2103250000 definitions=main-2103260145 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Complement the Aspeed HACE support with Scatter-Gather hash support for sha256 and sha512. Scatter-Gather is only supported on AST2600-series. Signed-off-by: Klaus Heinrich Kiwi --- docs/system/arm/aspeed.rst | 2 +- hw/misc/aspeed_hace.c | 126 +++++++++++++++++++++++++++++++++++-- 2 files changed, 121 insertions(+), 7 deletions(-) diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst index f9466e6d82..8680fd9409 100644 --- a/docs/system/arm/aspeed.rst +++ b/docs/system/arm/aspeed.rst @@ -49,7 +49,7 @@ Supported devices * Ethernet controllers * Front LEDs (PCA9552 on I2C bus) * LPC Peripheral Controller (a subset of subdevices are supported) - * Hash/Crypto Engine (HACE) - Hash support only, no scatter-gather + * Hash/Crypto Engine (HACE) - Hash support only =20 =20 Missing devices diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c index 6e5b447a48..cbff5a69cf 100644 --- a/hw/misc/aspeed_hace.c +++ b/hw/misc/aspeed_hace.c @@ -57,6 +57,14 @@ /* Other cmd bits */ #define HASH_IRQ_EN BIT(9) #define HASH_SG_EN BIT(18) +/* Scatter-gather data list */ +#define SG_LIST_LEN_SIZE 4 +#define SG_LIST_LEN_MASK 0x0FFFFFFF +#define SG_LIST_LEN_LAST BIT(31) +#define SG_LIST_ADDR_SIZE 4 +#define SG_LIST_ADDR_MASK 0x7FFFFFFF +#define SG_LIST_ENTRY_SIZE (SG_LIST_LEN_SIZE + SG_LIST_ADDR_S= IZE) +#define ASPEED_HACE_MAX_SG 256 /* max number of entrie= s */ =20 static const struct { uint32_t mask; @@ -129,6 +137,114 @@ static int do_hash_operation(AspeedHACEState *s, int = algo) return 0; } =20 +static int do_hash_sg_operation(AspeedHACEState *s, int algo) +{ + hwaddr src, dest, req_size; + uint32_t entry_len, entry_addr; + uint8_t *digest_buf =3D NULL; + unsigned int i =3D 0; + MemTxResult result; + struct iovec iov[ASPEED_HACE_MAX_SG]; + size_t digest_len =3D 0, size =3D 0; + int rc; + + req_size =3D s->regs[R_HASH_SRC_LEN]; + dest =3D s->regs[R_HASH_DEST]; + + while (i < ASPEED_HACE_MAX_SG) { + src =3D s->regs[R_HASH_SRC] + (i * SG_LIST_ENTRY_SIZE); + entry_len =3D address_space_ldl_le(&s->dram_as, src, + MEMTXATTRS_UNSPECIFIED, &result); + if (result !=3D MEMTX_OK) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: failed to load SG Array length entry %"PRIu32" from 0x%"= HWADDR_PRIx"\n", + __func__, i, src); + rc =3D -EACCES; + goto cleanup; + } + entry_addr =3D address_space_ldl_le(&s->dram_as, src + SG_LIST_LEN= _SIZE, + MEMTXATTRS_UNSPECIFIED, &result); + if (result !=3D MEMTX_OK) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: failed to load SG Array address entry %"PRIu32" from 0x%= "HWADDR_PRIx"\n", + __func__, i, src + SG_LIST_LEN_SIZE); + rc =3D -EACCES; + goto cleanup; + } + + iov[i].iov_len =3D (hwaddr) (entry_len & SG_LIST_LEN_MASK); + iov[i].iov_base =3D address_space_map(&s->dram_as, + entry_addr & SG_LIST_ADDR_MASK, + &iov[i].iov_len, false, + MEMTXATTRS_UNSPECIFIED); + if (!iov[i].iov_base) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: failed to map dram for SG array entry %"PRIu32" for regi= on 0x%"PRIx32", len %"PRIu32"\n", + __func__, i, entry_addr & SG_LIST_ADDR_MASK, entry_len & SG_L= IST_LEN_MASK); + rc =3D -EACCES; + goto cleanup; + } + if (iov[i].iov_len !=3D (entry_len & SG_LIST_LEN_MASK)) + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Warning: dram map for SG region entry %"PRIu32" request= ed size %"PRIu32" !=3D mapped size %"PRIu64"\n", + __func__, i, entry_len & SG_LIST_LEN_MASK, iov[i].iov_len); + + size +=3D iov[i].iov_len; + i++; + + if (entry_len & SG_LIST_LEN_LAST) { + break; + } + } + + if (!(entry_len & SG_LIST_LEN_LAST)) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Error: Exhausted maximum of %"PRIu32" SG array e= ntries\n", + __func__, ASPEED_HACE_MAX_SG); + rc =3D -ENOTSUP; + goto cleanup; + } + + if (size !=3D req_size) + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Warning: requested SG total size %"PRIu64" !=3D actual size = %"PRIu64"\n", + __func__, req_size, size); + + rc =3D qcrypto_hash_bytesv(algo, iov, i, &digest_buf, &digest_len, + &error_fatal); + if (rc < 0) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: qcrypto failed\n", + __func__); + goto cleanup; + } + + rc =3D address_space_write(&s->dram_as, dest, MEMTXATTRS_UNSPECIFIED, + digest_buf, digest_len); + if (rc) + qemu_log_mask(LOG_GUEST_ERROR, + "%s: address space write failed\n", __func__); + g_free(digest_buf); + +cleanup: + + for (; i > 0; i--) { + address_space_unmap(&s->dram_as, iov[i - 1].iov_base, + iov[i - 1].iov_len, false, + iov[i - 1].iov_len); + } + + /* + * Set status bits to indicate completion. Testing shows hardware sets + * these irrespective of HASH_IRQ_EN. + */ + if (!rc) { + s->regs[R_STATUS] |=3D HASH_IRQ; + } + + return rc; +} + + =20 static uint64_t aspeed_hace_read(void *opaque, hwaddr addr, unsigned int s= ize) { @@ -187,11 +303,6 @@ static void aspeed_hace_write(void *opaque, hwaddr add= r, uint64_t data, "%s: HMAC engine command mode %"PRIx64" not impl= emented", __func__, (data & HASH_HMAC_MASK) >> 8); } - if (data & HASH_SG_EN) { - qemu_log_mask(LOG_UNIMP, - "%s: Hash scatter gather mode not implemented", - __func__); - } if (data & BIT(1)) { qemu_log_mask(LOG_UNIMP, "%s: Cascaded mode not implemented", @@ -204,7 +315,10 @@ static void aspeed_hace_write(void *opaque, hwaddr add= r, uint64_t data, __func__, data & ahc->hash_mask); break; } - do_hash_operation(s, algo); + if (data & HASH_SG_EN) + do_hash_sg_operation(s, algo); + else + do_hash_operation(s, algo); =20 if (data & HASH_IRQ_EN) { qemu_irq_raise(s->irq); --=20 2.25.1 From nobody Tue May 7 22:27:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 26 Mar 2021 19:37:56 GMT Received: from b01ledav005.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C7E29AE05F; Fri, 26 Mar 2021 19:37:56 +0000 (GMT) Received: from b01ledav005.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 0B069AE060; Fri, 26 Mar 2021 19:37:55 +0000 (GMT) Received: from T480-KlausKiwi.localdomain (unknown [9.85.195.191]) by b01ledav005.gho.pok.ibm.com (Postfix) with ESMTP; Fri, 26 Mar 2021 19:37:54 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pp1; bh=Fp3n5dCo2BxE/gVU37+Ap2bBN1zADYnyVn6BUOzKNRY=; b=jP8ID1icUBiYhop95ry2eaxIXeYhAYjDw8/75qzxt348/vrv1slZkTizrx0T90ddSltL VWGzLUHOEiU2r69p0Y3VCyA6nD6jiopvewmzlo5ZOAifm/V/CGs5EcjeF/yvFe7ULtKA n2Otce409bYoy/JQkV+ArgGMxTzbbkbIwI4z+Q9FnbP6iIt5dls3e8vZNOY1D9TImGrM ji499MFmX4U/MK/3fPkheR8u/aX6LJ+SbhQTA+pIFrfzuCJTA9YxmeZ5uarTpkEKvjFc g/33Il1CPrIuucFHm+YwXQXK2dIbt3GslU947EBbqYp502ItKJq9zxIiro+EcztSw1VS EQ== From: Klaus Heinrich Kiwi To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v3 2/2] tests: Aspeed HACE Scatter-Gather tests Date: Fri, 26 Mar 2021 16:37:45 -0300 Message-Id: <20210326193745.13558-3-klaus@linux.vnet.ibm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210326193745.13558-1-klaus@linux.vnet.ibm.com> References: <20210326193745.13558-1-klaus@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: 7-QBQY0Q5CBQAYAESikIYUFPk9Bka-5a X-Proofpoint-GUID: uqK-w4TkrFF8kOeYxezGvdrjxytd2Vml X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761 definitions=2021-03-26_11:2021-03-26, 2021-03-26 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 phishscore=0 adultscore=0 suspectscore=0 bulkscore=0 spamscore=0 lowpriorityscore=0 impostorscore=0 priorityscore=1501 malwarescore=0 mlxscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2103250000 definitions=main-2103260145 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=148.163.158.5; envelope-from=klaus@linux.vnet.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Thomas Huth , Andrew Jeffery , Klaus Heinrich Kiwi , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Paolo Bonzini , Joel Stanley Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Expand current Aspeed HACE testsuite to also include Scatter-Gather of sha256 and sha512 operations. Signed-off-by: Klaus Heinrich Kiwi --- tests/qtest/aspeed_hace-test.c | 156 +++++++++++++++++++++++++++++++-- 1 file changed, 147 insertions(+), 9 deletions(-) diff --git a/tests/qtest/aspeed_hace-test.c b/tests/qtest/aspeed_hace-test.c index 2b624b6b09..d259f1a09c 100644 --- a/tests/qtest/aspeed_hace-test.c +++ b/tests/qtest/aspeed_hace-test.c @@ -34,6 +34,12 @@ #define HACE_HASH_KEY_BUFF 0x28 #define HACE_HASH_DATA_LEN 0x2c #define HACE_HASH_CMD 0x30 +/* Scatter-Gather Hash */ +#define SG_LIST_LEN_LAST BIT(31) +struct AspeedSgList { + uint32_t len; + uint32_t addr; +} __attribute__ ((__packed__)); =20 /* * Test vector is the ascii "abc" @@ -63,6 +69,33 @@ static const uint8_t test_result_md5[] =3D { 0x90, 0x01, 0x50, 0x98, 0x3c, 0xd2, 0x4f, 0xb0, 0xd6, 0x96, 0x3f, 0x7d, 0x28, 0xe1, 0x7f, 0x72}; =20 +/* + * The Scatter-Gather Test vector is the ascii "abc" "def" "ghi", broken + * into blocks of 3 characters as shown + * + * Expected results were generated using command line utitiles: + * + * echo -n -e 'abcdefghi' | dd of=3D/tmp/test + * for hash in sha512sum sha256sum; do $hash /tmp/test; done + * + */ +static const uint8_t test_vector_sg1[] =3D {0x61, 0x62, 0x63}; +static const uint8_t test_vector_sg2[] =3D {0x64, 0x65, 0x66}; +static const uint8_t test_vector_sg3[] =3D {0x67, 0x68, 0x69}; + +static const uint8_t test_result_sg_sha512[] =3D { + 0xf2, 0x2d, 0x51, 0xd2, 0x52, 0x92, 0xca, 0x1d, 0x0f, 0x68, 0xf6, 0x9a, + 0xed, 0xc7, 0x89, 0x70, 0x19, 0x30, 0x8c, 0xc9, 0xdb, 0x46, 0xef, 0xb7, + 0x5a, 0x03, 0xdd, 0x49, 0x4f, 0xc7, 0xf1, 0x26, 0xc0, 0x10, 0xe8, 0xad, + 0xe6, 0xa0, 0x0a, 0x0c, 0x1a, 0x5f, 0x1b, 0x75, 0xd8, 0x1e, 0x0e, 0xd5, + 0xa9, 0x3c, 0xe9, 0x8d, 0xc9, 0xb8, 0x33, 0xdb, 0x78, 0x39, 0x24, 0x7b, + 0x1d, 0x9c, 0x24, 0xfe}; + +static const uint8_t test_result_sg_sha256[] =3D { + 0x19, 0xcc, 0x02, 0xf2, 0x6d, 0xf4, 0x3c, 0xc5, 0x71, 0xbc, 0x9e, 0xd7, + 0xb0, 0xc4, 0xd2, 0x92, 0x24, 0xa3, 0xec, 0x22, 0x95, 0x29, 0x22, 0x17, + 0x25, 0xef, 0x76, 0xd0, 0x21, 0xc8, 0x32, 0x6f}; + =20 static void write_regs(QTestState *s, uint32_t base, uint32_t src, uint32_t length, uint32_t out, uint32_t method) @@ -167,6 +200,98 @@ static void test_sha512(const char *machine, const uin= t32_t base, test_result_sha512, sizeof(digest)); } =20 +static void test_sha256_sg(const char *machine, const uint32_t base, + const uint32_t src_addr) +{ + QTestState *s =3D qtest_init(machine); + + const uint32_t src_addr_1 =3D src_addr + 0x1000000; + const uint32_t src_addr_2 =3D src_addr + 0x2000000; + const uint32_t src_addr_3 =3D src_addr + 0x3000000; + const uint32_t digest_addr =3D src_addr + 0x4000000; + uint8_t digest[32] =3D {0}; + struct AspeedSgList array[] =3D { + { sizeof(test_vector_sg1), src_addr_1}, + { sizeof(test_vector_sg2), src_addr_2}, + { sizeof(test_vector_sg3) | SG_LIST_LEN_LAST, src_addr_3}, + }; + + /* Check engine is idle, no busy or irq bits set */ + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); + + /* Write test vector into memory */ + qtest_memwrite(s, src_addr_1, test_vector_sg1, sizeof(test_vector_sg1)= ); + qtest_memwrite(s, src_addr_2, test_vector_sg2, sizeof(test_vector_sg2)= ); + qtest_memwrite(s, src_addr_3, test_vector_sg3, sizeof(test_vector_sg3)= ); + qtest_memwrite(s, src_addr, array, sizeof(array)); + + write_regs(s, base, src_addr, + (sizeof(test_vector_sg1) + + sizeof(test_vector_sg2) + + sizeof(test_vector_sg3)), + digest_addr, HACE_ALGO_SHA256 | HACE_SG_EN); + + /* Check hash IRQ status is asserted */ + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0x00000200); + + /* Clear IRQ status and check status is deasserted */ + qtest_writel(s, base + HACE_STS, 0x00000200); + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); + + /* Read computed digest from memory */ + qtest_memread(s, digest_addr, digest, sizeof(digest)); + + /* Check result of computation */ + g_assert_cmpmem(digest, sizeof(digest), + test_result_sg_sha256, sizeof(digest)); +} + +static void test_sha512_sg(const char *machine, const uint32_t base, + const uint32_t src_addr) +{ + QTestState *s =3D qtest_init(machine); + + const uint32_t src_addr_1 =3D src_addr + 0x1000000; + const uint32_t src_addr_2 =3D src_addr + 0x2000000; + const uint32_t src_addr_3 =3D src_addr + 0x3000000; + const uint32_t digest_addr =3D src_addr + 0x4000000; + uint8_t digest[64] =3D {0}; + struct AspeedSgList array[] =3D { + { sizeof(test_vector_sg1), src_addr_1}, + { sizeof(test_vector_sg2), src_addr_2}, + { sizeof(test_vector_sg3) | SG_LIST_LEN_LAST, src_addr_3}, + }; + + /* Check engine is idle, no busy or irq bits set */ + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); + + /* Write test vector into memory */ + qtest_memwrite(s, src_addr_1, test_vector_sg1, sizeof(test_vector_sg1)= ); + qtest_memwrite(s, src_addr_2, test_vector_sg2, sizeof(test_vector_sg2)= ); + qtest_memwrite(s, src_addr_3, test_vector_sg3, sizeof(test_vector_sg3)= ); + qtest_memwrite(s, src_addr, array, sizeof(array)); + + write_regs(s, base, src_addr, + (sizeof(test_vector_sg1) + + sizeof(test_vector_sg2) + + sizeof(test_vector_sg3)), + digest_addr, HACE_ALGO_SHA512 | HACE_SG_EN); + + /* Check hash IRQ status is asserted */ + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0x00000200); + + /* Clear IRQ status and check status is deasserted */ + qtest_writel(s, base + HACE_STS, 0x00000200); + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); + + /* Read computed digest from memory */ + qtest_memread(s, digest_addr, digest, sizeof(digest)); + + /* Check result of computation */ + g_assert_cmpmem(digest, sizeof(digest), + test_result_sg_sha512, sizeof(digest)); +} + struct masks { uint32_t src; uint32_t dest; @@ -174,21 +299,21 @@ struct masks { }; =20 static const struct masks ast2600_masks =3D { - .src =3D 0x7fffffff, - .dest =3D 0x7ffffff8, - .len =3D 0x0fffffff, + .src =3D 0x7fffffff, + .dest =3D 0x7ffffff8, + .len =3D 0x0fffffff, }; =20 static const struct masks ast2500_masks =3D { - .src =3D 0x3fffffff, - .dest =3D 0x3ffffff8, - .len =3D 0x0fffffff, + .src =3D 0x3fffffff, + .dest =3D 0x3ffffff8, + .len =3D 0x0fffffff, }; =20 static const struct masks ast2400_masks =3D { - .src =3D 0x0fffffff, - .dest =3D 0x0ffffff8, - .len =3D 0x0fffffff, + .src =3D 0x0fffffff, + .dest =3D 0x0ffffff8, + .len =3D 0x0fffffff, }; =20 static void test_addresses(const char *machine, const uint32_t base, @@ -238,11 +363,21 @@ static void test_sha256_ast2600(void) test_sha256("-machine ast2600-evb", 0x1e6d0000, 0x80000000); } =20 +static void test_sha256_sg_ast2600(void) +{ + test_sha256_sg("-machine ast2600-evb", 0x1e6d0000, 0x80000000); +} + static void test_sha512_ast2600(void) { test_sha512("-machine ast2600-evb", 0x1e6d0000, 0x80000000); } =20 +static void test_sha512_sg_ast2600(void) +{ + test_sha512_sg("-machine ast2600-evb", 0x1e6d0000, 0x80000000); +} + static void test_addresses_ast2600(void) { test_addresses("-machine ast2600-evb", 0x1e6d0000, &ast2600_masks); @@ -299,6 +434,9 @@ int main(int argc, char **argv) qtest_add_func("ast2600/hace/sha256", test_sha256_ast2600); qtest_add_func("ast2600/hace/md5", test_md5_ast2600); =20 + qtest_add_func("ast2600/hace/sha512_sg", test_sha512_sg_ast2600); + qtest_add_func("ast2600/hace/sha256_sg", test_sha256_sg_ast2600); + qtest_add_func("ast2500/hace/addresses", test_addresses_ast2500); qtest_add_func("ast2500/hace/sha512", test_sha512_ast2500); qtest_add_func("ast2500/hace/sha256", test_sha256_ast2500); --=20 2.25.1