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From: Alistair Francis <alistair.francis@wdc.com>
To: peter.maydell@linaro.org
Subject: [PULL 12/16] target/riscv: Add proper two-stage lookup exception
detection
Date: Mon, 22 Mar 2021 21:57:52 -0400
Message-Id: <20210323015756.3168650-13-alistair.francis@wdc.com>
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Cc: alistair23@gmail.com, Alistair Francis <alistair.francis@wdc.com>,
qemu-devel@nongnu.org, Georg Kotheimer <georg.kotheimer@kernkonzept.com>
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From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
The current two-stage lookup detection in riscv_cpu_do_interrupt falls
short of its purpose, as all it checks is whether two-stage address
translation either via the hypervisor-load store instructions or the
MPRV feature would be allowed.
What we really need instead is whether two-stage address translation was
active when the exception was raised. However, in riscv_cpu_do_interrupt
we do not have the information to reliably detect this. Therefore, when
we raise a memory fault exception we have to record whether two-stage
address translation is active.
Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210319141459.1196741-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 4 ++++
target/riscv/cpu.c | 1 +
target/riscv/cpu_helper.c | 21 ++++++++-------------
3 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 0edb2826a2..0a33d387ba 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -213,6 +213,10 @@ struct CPURISCVState {
target_ulong satp_hs;
uint64_t mstatus_hs;
=20
+ /* Signals whether the current exception occurred with two-stage addre=
ss
+ translation active. */
+ bool two_stage_lookup;
+
target_ulong scounteren;
target_ulong mcounteren;
=20
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 2a990f6253..7d6ed80f6b 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -356,6 +356,7 @@ static void riscv_cpu_reset(DeviceState *dev)
env->mstatus &=3D ~(MSTATUS_MIE | MSTATUS_MPRV);
env->mcause =3D 0;
env->pc =3D env->resetvec;
+ env->two_stage_lookup =3D false;
#endif
cs->exception_index =3D EXCP_NONE;
env->load_res =3D -1;
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 8d4a62988d..21c54ef561 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -654,6 +654,7 @@ static void raise_mmu_exception(CPURISCVState *env, tar=
get_ulong address,
g_assert_not_reached();
}
env->badaddr =3D address;
+ env->two_stage_lookup =3D two_stage;
}
=20
hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
@@ -695,6 +696,8 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwad=
dr physaddr,
}
=20
env->badaddr =3D addr;
+ env->two_stage_lookup =3D riscv_cpu_virt_enabled(env) ||
+ riscv_cpu_two_stage_lookup(mmu_idx);
riscv_raise_exception(&cpu->env, cs->exception_index, retaddr);
}
=20
@@ -718,6 +721,8 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr =
addr,
g_assert_not_reached();
}
env->badaddr =3D addr;
+ env->two_stage_lookup =3D riscv_cpu_virt_enabled(env) ||
+ riscv_cpu_two_stage_lookup(mmu_idx);
riscv_raise_exception(env, cs->exception_index, retaddr);
}
#endif /* !CONFIG_USER_ONLY */
@@ -967,16 +972,8 @@ void riscv_cpu_do_interrupt(CPUState *cs)
/* handle the trap in S-mode */
if (riscv_has_ext(env, RVH)) {
target_ulong hdeleg =3D async ? env->hideleg : env->hedeleg;
- bool two_stage_lookup =3D false;
=20
- if (env->priv =3D=3D PRV_M ||
- (env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(env)) ||
- (env->priv =3D=3D PRV_U && !riscv_cpu_virt_enabled(env) &&
- get_field(env->hstatus, HSTATUS_HU))) {
- two_stage_lookup =3D true;
- }
-
- if ((riscv_cpu_virt_enabled(env) || two_stage_lookup) && write=
_tval) {
+ if (env->two_stage_lookup && write_tval) {
/*
* If we are writing a guest virtual address to stval, set
* this to 1. If we are trapping to VS we will set this to=
0
@@ -1014,10 +1011,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
riscv_cpu_set_force_hs_excep(env, 0);
} else {
/* Trap into HS mode */
- if (!two_stage_lookup) {
- env->hstatus =3D set_field(env->hstatus, HSTATUS_SPV,
- riscv_cpu_virt_enabled(env));
- }
+ env->hstatus =3D set_field(env->hstatus, HSTATUS_SPV, fals=
e);
htval =3D env->guest_phys_fault_addr;
}
}
@@ -1073,6 +1067,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
* RISC-V ISA Specification.
*/
=20
+ env->two_stage_lookup =3D false;
#endif
cs->exception_index =3D EXCP_NONE; /* mark handled to qemu */
}
--=20
2.30.1