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From: Alistair Francis <alistair.francis@wdc.com>
To: peter.maydell@linaro.org
Subject: [PULL 09/16] hw/riscv: Add fw_cfg support to virt
Date: Mon, 22 Mar 2021 21:57:49 -0400
Message-Id: <20210323015756.3168650-10-alistair.francis@wdc.com>
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Cc: alistair23@gmail.com, Bin Meng <bmeng.cn@gmail.com>,
Alistair Francis <alistair.francis@wdc.com>, qemu-devel@nongnu.org,
Asherah Connor <ashe@kivikakk.ee>
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From: Asherah Connor <ashe@kivikakk.ee>
Provides fw_cfg for the virt machine on riscv. This enables
using e.g. ramfb later.
Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210318235041.17175-2-ashe@kivikakk.ee
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/virt.h | 2 ++
hw/riscv/virt.c | 30 ++++++++++++++++++++++++++++++
hw/riscv/Kconfig | 1 +
3 files changed, 33 insertions(+)
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index 632da52018..349fee1f89 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -40,6 +40,7 @@ struct RISCVVirtState {
RISCVHartArrayState soc[VIRT_SOCKETS_MAX];
DeviceState *plic[VIRT_SOCKETS_MAX];
PFlashCFI01 *flash[2];
+ FWCfgState *fw_cfg;
=20
int fdt_size;
};
@@ -53,6 +54,7 @@ enum {
VIRT_PLIC,
VIRT_UART0,
VIRT_VIRTIO,
+ VIRT_FW_CFG,
VIRT_FLASH,
VIRT_DRAM,
VIRT_PCIE_MMIO,
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 0b39101a5e..e96ec4cbbc 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -53,6 +53,7 @@ static const MemMapEntry virt_memmap[] =3D {
[VIRT_PLIC] =3D { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2)=
},
[VIRT_UART0] =3D { 0x10000000, 0x100 },
[VIRT_VIRTIO] =3D { 0x10001000, 0x1000 },
+ [VIRT_FW_CFG] =3D { 0x10100000, 0x18 },
[VIRT_FLASH] =3D { 0x20000000, 0x4000000 },
[VIRT_PCIE_ECAM] =3D { 0x30000000, 0x10000000 },
[VIRT_PCIE_MMIO] =3D { 0x40000000, 0x40000000 },
@@ -507,6 +508,28 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion=
*sys_mem,
return dev;
}
=20
+static FWCfgState *create_fw_cfg(const MachineState *mc)
+{
+ hwaddr base =3D virt_memmap[VIRT_FW_CFG].base;
+ hwaddr size =3D virt_memmap[VIRT_FW_CFG].size;
+ FWCfgState *fw_cfg;
+ char *nodename;
+
+ fw_cfg =3D fw_cfg_init_mem_wide(base + 8, base, 8, base + 16,
+ &address_space_memory);
+ fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus);
+
+ nodename =3D g_strdup_printf("/fw-cfg@%" PRIx64, base);
+ qemu_fdt_add_subnode(mc->fdt, nodename);
+ qemu_fdt_setprop_string(mc->fdt, nodename,
+ "compatible", "qemu,fw-cfg-mmio");
+ qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg",
+ 2, base, 2, size);
+ qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0);
+ g_free(nodename);
+ return fw_cfg;
+}
+
static void virt_machine_init(MachineState *machine)
{
const MemMapEntry *memmap =3D virt_memmap;
@@ -688,6 +711,13 @@ static void virt_machine_init(MachineState *machine)
start_addr =3D virt_memmap[VIRT_FLASH].base;
}
=20
+ /*
+ * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the dev=
ice
+ * tree cannot be altered and we get FDT_ERR_NOSPACE.
+ */
+ s->fw_cfg =3D create_fw_cfg(machine);
+ rom_set_fw(s->fw_cfg);
+
/* Compute the fdt load address in dram */
fdt_load_addr =3D riscv_load_fdt(memmap[VIRT_DRAM].base,
machine->ram_size, machine->fdt);
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index d139074b02..1de18cdcf1 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -33,6 +33,7 @@ config RISCV_VIRT
select SIFIVE_PLIC
select SIFIVE_TEST
select VIRTIO_MMIO
+ select FW_CFG_DMA
=20
config SIFIVE_E
bool
--=20
2.30.1