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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=705762e65=atish.patra@wdc.com; helo=esa1.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Sagar Karandikar , Bastian Koppelmann , anup.patel@wdc.com, Atish Patra , Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" As per the privilege specification v1.11, mcountinhibit allows to start/stop a pmu counter selectively. Signed-off-by: Atish Patra Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 2 ++ target/riscv/cpu_bits.h | 4 ++++ target/riscv/csr.c | 23 +++++++++++++++++++++++ target/riscv/machine.c | 1 + 4 files changed, 30 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7bee351f3c99..ef2a7fdc3980 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -214,6 +214,8 @@ struct CPURISCVState { target_ulong scounteren; target_ulong mcounteren; =20 + target_ulong mcountinhibit; + target_ulong sscratch; target_ulong mscratch; =20 diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index b42dd4f8d8b1..7514d611cd0b 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -283,6 +283,10 @@ #define CSR_MHPMCOUNTER29 0xb1d #define CSR_MHPMCOUNTER30 0xb1e #define CSR_MHPMCOUNTER31 0xb1f + +/* Machine counter-inhibit register */ +#define CSR_MCOUNTINHIBIT 0x320 + #define CSR_MHPMEVENT3 0x323 #define CSR_MHPMEVENT4 0x324 #define CSR_MHPMEVENT5 0x325 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 7166f8d710a8..b9d795389532 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -631,6 +631,26 @@ static int write_mtvec(CPURISCVState *env, int csrno, = target_ulong val) return 0; } =20 +static int read_mcountinhibit(CPURISCVState *env, int csrno, target_ulong = *val) +{ + if (env->priv_ver < PRIV_VERSION_1_11_0) { + return -RISCV_EXCP_ILLEGAL_INST; + } + + *val =3D env->mcountinhibit; + return 0; +} + +static int write_mcountinhibit(CPURISCVState *env, int csrno, target_ulong= val) +{ + if (env->priv_ver < PRIV_VERSION_1_11_0) { + return -RISCV_EXCP_ILLEGAL_INST; + } + + env->mcountinhibit =3D val; + return 0; +} + static int read_mcounteren(CPURISCVState *env, int csrno, target_ulong *va= l) { *val =3D env->mcounteren; @@ -1533,6 +1553,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_MHPMCOUNTER30] =3D { "mhpmcounter30", any, read_zero }, [CSR_MHPMCOUNTER31] =3D { "mhpmcounter31", any, read_zero }, =20 + [CSR_MCOUNTINHIBIT] =3D { "mcountinhibi", any, read_mcountinhibi= t, + write_mcountinhibit= }, + [CSR_MHPMEVENT3] =3D { "mhpmevent3", any, read_zero }, [CSR_MHPMEVENT4] =3D { "mhpmevent4", any, read_zero }, [CSR_MHPMEVENT5] =3D { "mhpmevent5", any, read_zero }, diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 27fcc770aa4b..cb7ec8a4c656 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -177,6 +177,7 @@ const VMStateDescription vmstate_riscv_cpu =3D { VMSTATE_UINTTL(env.mtval, RISCVCPU), VMSTATE_UINTTL(env.scounteren, RISCVCPU), VMSTATE_UINTTL(env.mcounteren, RISCVCPU), + VMSTATE_UINTTL(env.mcountinhibit, RISCVCPU), VMSTATE_UINTTL(env.sscratch, RISCVCPU), VMSTATE_UINTTL(env.mscratch, RISCVCPU), VMSTATE_UINT64(env.mfromhost, RISCVCPU), --=20 2.25.1