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IronPort-SDR: M77SSqArd5UN4gyDA0dTO47acQ/cA67Bq9PPmrWma4OlzgtRB+1dPT3ubY/h+HSQHNA602a1Lr zorcL21gZXWyX8flfuvEAUfzRFD0LYza278XSnTxTVQi3Eo4EWuMbkhIX6qpOMF560cLYCX6lZ MwlmjyUTJ7M2c+Y7nx19WNiIILfKizEXdhYzqMloCM+ZWmj8ucM9YEtNUXZRSdXYiioUrP7NSh nXkPzRq3lrjBwsThxzn2Z4KT8UQWgh9ETIYyJ3rBiVU4r01pI1jY8BDerDNO/L+4DcaSziKMse XA4= X-IronPort-AV: E=Sophos;i="5.81,262,1610380800"; d="scan'208";a="273319147" IronPort-SDR: KkkLOqisNHF6qXcwmz0vy0lfnObkJkpa3Xz7gK0w4+OUxFv/uPdDw9t3ca/LBGvet7l71X2Xoe f3InSW93dVNgp6753zF/w5WBHU2HyADONt8lwSMrkIuSrNBX0WoX4+l32mSwn2VVIcG8jkiAzg pK1Eieh4QAIGqzlFELYguLywKA3OFiGa/X4ltVtJlD5DKJ9VotF7HIlSn8w08JB8z6MluJNHJr QmO7mNG+pAUBDwMfnX6h9znPDWUmEtnP1tXcSVgbGdGRvDgZcu95z8JtRErh7f3XEXNUwLgzmA EiakiwHf1ccV/ahsBdsyx50L IronPort-SDR: Za3aLZ+pAblb1yk7AuQ/6SQqEWtxHJocVFMkgwtgrxJLNOqYYH/CB0agZ+vYeghHIPc4tGyzlF u/VS2m/6ACf+6AMImunRNhuH2eK/LT8izs8egKX0K/rJnKKhP3RS2QH+bqBXgxwrIrDeDaxw8G T2AoTZOtWN3Fj13a0xwcsTnSL+7shR8ZJC+JxV6U30weI1PQHcBDAXpIEIe+T/5HtyCAycp6jG FFR+fWSrv/315z/0UtYjSdAPqKzZi+6+/Dwd+ho7V5lt44iCims06s0WHtRr3ZTZ6VGkJtFuq1 Tfo= WDCIronportException: Internal From: Atish Patra To: qemu-devel@nongnu.org Subject: [ RFC 1/6] target/riscv: Remove privilege v1.9 specific CSR related code Date: Fri, 19 Mar 2021 12:45:29 -0700 Message-Id: <20210319194534.2082397-2-atish.patra@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210319194534.2082397-1-atish.patra@wdc.com> References: <20210319194534.2082397-1-atish.patra@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=705762e65=atish.patra@wdc.com; helo=esa1.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Sagar Karandikar , Bastian Koppelmann , anup.patel@wdc.com, Atish Patra , Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Qemu doesn't support RISC-V privilege specification v1.9. Remove the remaining v1.9 specific references from the implementation. Signed-off-by: Atish Patra --- target/riscv/cpu.c | 2 +- target/riscv/cpu.h | 4 +--- target/riscv/cpu_bits.h | 23 --------------------- target/riscv/cpu_helper.c | 12 +++++------ target/riscv/csr.c | 43 ++++++++++----------------------------- target/riscv/machine.c | 4 +--- target/riscv/translate.c | 4 ++-- 7 files changed, 22 insertions(+), 70 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ddea8fbeeb39..c76e4c1a09c9 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -282,7 +282,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f,= int flags) qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vscause ", env->vscaus= e); } qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval ", env->mtval); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->sbadaddr); + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->stval); if (riscv_has_ext(env, RVH)) { qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval); qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2); diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0edb2826a27a..7bee351f3c99 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -163,10 +163,8 @@ struct CPURISCVState { target_ulong mie; target_ulong mideleg; =20 - target_ulong sptbr; /* until: priv-1.9.1 */ target_ulong satp; /* since: priv-1.10.0 */ - target_ulong sbadaddr; - target_ulong mbadaddr; + target_ulong stval; target_ulong medeleg; =20 target_ulong stvec; diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index caf45992070a..b42dd4f8d8b1 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -153,12 +153,6 @@ /* 32-bit only */ #define CSR_MSTATUSH 0x310 =20 -/* Legacy Counter Setup (priv v1.9.1) */ -/* Update to #define CSR_MCOUNTINHIBIT 0x320 for 1.11.0 */ -#define CSR_MUCOUNTEREN 0x320 -#define CSR_MSCOUNTEREN 0x321 -#define CSR_MHCOUNTEREN 0x322 - /* Machine Trap Handling */ #define CSR_MSCRATCH 0x340 #define CSR_MEPC 0x341 @@ -166,9 +160,6 @@ #define CSR_MTVAL 0x343 #define CSR_MIP 0x344 =20 -/* Legacy Machine Trap Handling (priv v1.9.1) */ -#define CSR_MBADADDR 0x343 - /* Supervisor Trap Setup */ #define CSR_SSTATUS 0x100 #define CSR_SEDELEG 0x102 @@ -184,9 +175,6 @@ #define CSR_STVAL 0x143 #define CSR_SIP 0x144 =20 -/* Legacy Supervisor Trap Handling (priv v1.9.1) */ -#define CSR_SBADADDR 0x143 - /* Supervisor Protection and Translation */ #define CSR_SPTBR 0x180 #define CSR_SATP 0x180 @@ -354,14 +342,6 @@ #define CSR_MHPMCOUNTER30H 0xb9e #define CSR_MHPMCOUNTER31H 0xb9f =20 -/* Legacy Machine Protection and Translation (priv v1.9.1) */ -#define CSR_MBASE 0x380 -#define CSR_MBOUND 0x381 -#define CSR_MIBASE 0x382 -#define CSR_MIBOUND 0x383 -#define CSR_MDBASE 0x384 -#define CSR_MDBOUND 0x385 - /* mstatus CSR bits */ #define MSTATUS_UIE 0x00000001 #define MSTATUS_SIE 0x00000002 @@ -375,10 +355,8 @@ #define MSTATUS_FS 0x00006000 #define MSTATUS_XS 0x00018000 #define MSTATUS_MPRV 0x00020000 -#define MSTATUS_PUM 0x00040000 /* until: priv-1.9.1 */ #define MSTATUS_SUM 0x00040000 /* since: priv-1.10 */ #define MSTATUS_MXR 0x00080000 -#define MSTATUS_VM 0x1F000000 /* until: priv-1.9.1 */ #define MSTATUS_TVM 0x00100000 /* since: priv-1.10 */ #define MSTATUS_TW 0x00200000 /* since: priv-1.10 */ #define MSTATUS_TSR 0x00400000 /* since: priv-1.10 */ @@ -416,7 +394,6 @@ #define SSTATUS_SPP 0x00000100 #define SSTATUS_FS 0x00006000 #define SSTATUS_XS 0x00018000 -#define SSTATUS_PUM 0x00040000 /* until: priv-1.9.1 */ #define SSTATUS_SUM 0x00040000 /* since: priv-1.10 */ #define SSTATUS_MXR 0x00080000 =20 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 2f43939fb6d4..bb0a709c9cab 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -136,8 +136,8 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) env->vscause =3D env->scause; env->scause =3D env->scause_hs; =20 - env->vstval =3D env->sbadaddr; - env->sbadaddr =3D env->stval_hs; + env->vstval =3D env->stval; + env->stval =3D env->stval_hs; =20 env->vsatp =3D env->satp; env->satp =3D env->satp_hs; @@ -159,8 +159,8 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) env->scause_hs =3D env->scause; env->scause =3D env->vscause; =20 - env->stval_hs =3D env->sbadaddr; - env->sbadaddr =3D env->vstval; + env->stval_hs =3D env->stval; + env->stval =3D env->vstval; =20 env->satp_hs =3D env->satp; env->satp =3D env->vsatp; @@ -972,7 +972,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) env->mstatus =3D s; env->scause =3D cause | ((target_ulong)async << (TARGET_LONG_BITS = - 1)); env->sepc =3D env->pc; - env->sbadaddr =3D tval; + env->stval =3D tval; env->htval =3D htval; env->pc =3D (env->stvec >> 2 << 2) + ((async && (env->stvec & 3) =3D=3D 1) ? cause * 4 : 0); @@ -1003,7 +1003,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) env->mstatus =3D s; env->mcause =3D cause | ~(((target_ulong)-1) >> async); env->mepc =3D env->pc; - env->mbadaddr =3D tval; + env->mtval =3D tval; env->mtval2 =3D mtval2; env->pc =3D (env->mtvec >> 2 << 2) + ((async && (env->mtvec & 3) =3D=3D 1) ? cause * 4 : 0); diff --git a/target/riscv/csr.c b/target/riscv/csr.c index fd2e6363f397..7166f8d710a8 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -643,26 +643,6 @@ static int write_mcounteren(CPURISCVState *env, int cs= rno, target_ulong val) return 0; } =20 -/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */ -static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *v= al) -{ - if (env->priv_ver < PRIV_VERSION_1_11_0) { - return -RISCV_EXCP_ILLEGAL_INST; - } - *val =3D env->mcounteren; - return 0; -} - -/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */ -static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong v= al) -{ - if (env->priv_ver < PRIV_VERSION_1_11_0) { - return -RISCV_EXCP_ILLEGAL_INST; - } - env->mcounteren =3D val; - return 0; -} - /* Machine Trap Handling */ static int read_mscratch(CPURISCVState *env, int csrno, target_ulong *val) { @@ -700,15 +680,15 @@ static int write_mcause(CPURISCVState *env, int csrno= , target_ulong val) return 0; } =20 -static int read_mbadaddr(CPURISCVState *env, int csrno, target_ulong *val) +static int read_mtval(CPURISCVState *env, int csrno, target_ulong *val) { - *val =3D env->mbadaddr; + *val =3D env->mtval; return 0; } =20 -static int write_mbadaddr(CPURISCVState *env, int csrno, target_ulong val) +static int write_mtval(CPURISCVState *env, int csrno, target_ulong val) { - env->mbadaddr =3D val; + env->mtval =3D val; return 0; } =20 @@ -840,18 +820,19 @@ static int write_scause(CPURISCVState *env, int csrno= , target_ulong val) return 0; } =20 -static int read_sbadaddr(CPURISCVState *env, int csrno, target_ulong *val) +static int read_stval(CPURISCVState *env, int csrno, target_ulong *val) { - *val =3D env->sbadaddr; + *val =3D env->stval; return 0; } =20 -static int write_sbadaddr(CPURISCVState *env, int csrno, target_ulong val) +static int write_stval(CPURISCVState *env, int csrno, target_ulong val) { - env->sbadaddr =3D val; + env->stval =3D val; return 0; } =20 + static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value, target_ulong new_value, target_ulong write_mask) { @@ -1418,13 +1399,11 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { =20 [CSR_MSTATUSH] =3D { "mstatush", any32, read_mstatush, write_m= statush }, =20 - [CSR_MSCOUNTEREN] =3D { "msounteren", any, read_mscounteren, write_m= scounteren }, - /* Machine Trap Handling */ [CSR_MSCRATCH] =3D { "mscratch", any, read_mscratch, write_mscratch }, [CSR_MEPC] =3D { "mepc", any, read_mepc, write_mepc }, [CSR_MCAUSE] =3D { "mcause", any, read_mcause, write_mcause }, - [CSR_MBADADDR] =3D { "mbadaddr", any, read_mbadaddr, write_mbadaddr }, + [CSR_MTVAL] =3D { "mtval", any, read_mtval, write_mtval }, [CSR_MIP] =3D { "mip", any, NULL, NULL, rmw_mip }, =20 /* Supervisor Trap Setup */ @@ -1437,7 +1416,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_SSCRATCH] =3D { "sscratch", smode, read_sscratch, write_sscratch = }, [CSR_SEPC] =3D { "sepc", smode, read_sepc, write_sepc = }, [CSR_SCAUSE] =3D { "scause", smode, read_scause, write_scause = }, - [CSR_SBADADDR] =3D { "sbadaddr", smode, read_sbadaddr, write_sbadaddr = }, + [CSR_STVAL] =3D { "stval", smode, read_stval, write_stval }, [CSR_SIP] =3D { "sip", smode, NULL, NULL, rmw_sip = }, =20 /* Supervisor Protection and Translation */ diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 44d4015bd675..27fcc770aa4b 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -165,10 +165,8 @@ const VMStateDescription vmstate_riscv_cpu =3D { VMSTATE_UINT32(env.miclaim, RISCVCPU), VMSTATE_UINTTL(env.mie, RISCVCPU), VMSTATE_UINTTL(env.mideleg, RISCVCPU), - VMSTATE_UINTTL(env.sptbr, RISCVCPU), VMSTATE_UINTTL(env.satp, RISCVCPU), - VMSTATE_UINTTL(env.sbadaddr, RISCVCPU), - VMSTATE_UINTTL(env.mbadaddr, RISCVCPU), + VMSTATE_UINTTL(env.stval, RISCVCPU), VMSTATE_UINTTL(env.medeleg, RISCVCPU), VMSTATE_UINTTL(env.stvec, RISCVCPU), VMSTATE_UINTTL(env.sepc, RISCVCPU), diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 0f28b5f41e4f..1740be3d4bd9 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -130,7 +130,7 @@ static void generate_exception(DisasContext *ctx, int e= xcp) ctx->base.is_jmp =3D DISAS_NORETURN; } =20 -static void generate_exception_mbadaddr(DisasContext *ctx, int excp) +static void generate_exception_mtval(DisasContext *ctx, int excp) { tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr)); @@ -174,7 +174,7 @@ static void gen_exception_illegal(DisasContext *ctx) =20 static void gen_exception_inst_addr_mis(DisasContext *ctx) { - generate_exception_mbadaddr(ctx, RISCV_EXCP_INST_ADDR_MIS); + generate_exception_mtval(ctx, RISCV_EXCP_INST_ADDR_MIS); } =20 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) --=20 2.25.1 From nobody Wed May 1 11:22:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1616183250; cv=none; d=zohomail.com; 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d="scan'208";a="273319148" IronPort-SDR: E4NQOtXcm2OEZDdzOWYF09bMb3leSSvaRzDdHCx44aGOXRUzpXd7Dd8E86v01h+WedkvCSkg68 YUQ8NZPFRtiyDPnVX5rKYtjaL0iP62nzWwGHMAo2OGTJk7w+knM5MrkT6HCfRo2pDyYlEXubcu 4X8m/3CisZc6qy1zEX2qYQKmfhK35c8ljNKCrgsG2JIAWf9gYh6JulmwoNYLSI8aU739Axn4B/ qmwWMGiNHRH22mtKDBzbZNruM5hq73iGIs/4NYQmRpPdOibart5gs9Qz5u8kxj1g2EuxSi71bF gLT0IsXlligbPiMTsg9UYmKn IronPort-SDR: kxCCkn49GBP7d0xFBi9D44tiNviCZny6mqDEm04e9Zy0qyz+nV94pm5t8tmNcua6gJROnVRWJ+ W/WL4qo54PT+pKuThlMNNan3Ns2QN1o5ygrZ5+QHwj4DYFLO1cId997HuP3rykXuRiCjZMrqKL ekMWRVb2KcQu+xiySQycp5LZ3e4DbYnfXMGb3F/m3+DvsKYgOoAREPj2N7FfRc0KLdd9xa9zBJ HipJfjbpVz/E9ZjEXisFON3dK3KXCYej4E+Z9x8HBramYDxcR60UE/qqWlRdl85OEBbDw06bev QR8= WDCIronportException: Internal From: Atish Patra To: qemu-devel@nongnu.org Subject: [ RFC 2/6] target/riscv: Implement mcountinhibit CSR Date: Fri, 19 Mar 2021 12:45:30 -0700 Message-Id: <20210319194534.2082397-3-atish.patra@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210319194534.2082397-1-atish.patra@wdc.com> References: <20210319194534.2082397-1-atish.patra@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=705762e65=atish.patra@wdc.com; helo=esa1.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Sagar Karandikar , Bastian Koppelmann , anup.patel@wdc.com, Atish Patra , Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" As per the privilege specification v1.11, mcountinhibit allows to start/stop a pmu counter selectively. Signed-off-by: Atish Patra Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 2 ++ target/riscv/cpu_bits.h | 4 ++++ target/riscv/csr.c | 23 +++++++++++++++++++++++ target/riscv/machine.c | 1 + 4 files changed, 30 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7bee351f3c99..ef2a7fdc3980 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -214,6 +214,8 @@ struct CPURISCVState { target_ulong scounteren; target_ulong mcounteren; =20 + target_ulong mcountinhibit; + target_ulong sscratch; target_ulong mscratch; =20 diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index b42dd4f8d8b1..7514d611cd0b 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -283,6 +283,10 @@ #define CSR_MHPMCOUNTER29 0xb1d #define CSR_MHPMCOUNTER30 0xb1e #define CSR_MHPMCOUNTER31 0xb1f + +/* Machine counter-inhibit register */ +#define CSR_MCOUNTINHIBIT 0x320 + #define CSR_MHPMEVENT3 0x323 #define CSR_MHPMEVENT4 0x324 #define CSR_MHPMEVENT5 0x325 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 7166f8d710a8..b9d795389532 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -631,6 +631,26 @@ static int write_mtvec(CPURISCVState *env, int csrno, = target_ulong val) return 0; } =20 +static int read_mcountinhibit(CPURISCVState *env, int csrno, target_ulong = *val) +{ + if (env->priv_ver < PRIV_VERSION_1_11_0) { + return -RISCV_EXCP_ILLEGAL_INST; + } + + *val =3D env->mcountinhibit; + return 0; +} + +static int write_mcountinhibit(CPURISCVState *env, int csrno, target_ulong= val) +{ + if (env->priv_ver < PRIV_VERSION_1_11_0) { + return -RISCV_EXCP_ILLEGAL_INST; + } + + env->mcountinhibit =3D val; + return 0; +} + static int read_mcounteren(CPURISCVState *env, int csrno, target_ulong *va= l) { *val =3D env->mcounteren; @@ -1533,6 +1553,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_MHPMCOUNTER30] =3D { "mhpmcounter30", any, read_zero }, [CSR_MHPMCOUNTER31] =3D { "mhpmcounter31", any, read_zero }, =20 + [CSR_MCOUNTINHIBIT] =3D { "mcountinhibi", any, read_mcountinhibi= t, + write_mcountinhibit= }, + [CSR_MHPMEVENT3] =3D { "mhpmevent3", any, read_zero }, [CSR_MHPMEVENT4] =3D { "mhpmevent4", any, read_zero }, [CSR_MHPMEVENT5] =3D { "mhpmevent5", any, read_zero }, diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 27fcc770aa4b..cb7ec8a4c656 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -177,6 +177,7 @@ const VMStateDescription vmstate_riscv_cpu =3D { VMSTATE_UINTTL(env.mtval, RISCVCPU), VMSTATE_UINTTL(env.scounteren, RISCVCPU), VMSTATE_UINTTL(env.mcounteren, RISCVCPU), + VMSTATE_UINTTL(env.mcountinhibit, RISCVCPU), VMSTATE_UINTTL(env.sscratch, RISCVCPU), VMSTATE_UINTTL(env.mscratch, RISCVCPU), VMSTATE_UINT64(env.mfromhost, RISCVCPU), --=20 2.25.1 From nobody Wed May 1 11:22:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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IronPort-SDR: SV/yRWK/WL1Tw3AN7KV7apVUZ4Z9jChA0dpmTdlv2kXW+0z+eE+HCdvzLbttaWYtxOuZRUG/B2 LA00BYEr8Hm6oZ6Vxoegh2IiU99znBuXgj1hhYqc8C8wZYZkN80a2b4cC3jkdXyBA3JPYmDwPY pKuob0hpdUNQ4OlzciFiZdLyRCO0lxA9kSomOtbnIcfXEnVOGCCaWBJoivMwga6SZpqxezuqJ0 OqdIKRX4f40dttobJEQLpuVEfWWueok+KqoZdJdQ6anvhnqPpDYvoj3CeNDJFXJBMsqChuzZRQ dLI= X-IronPort-AV: E=Sophos;i="5.81,262,1610380800"; d="scan'208";a="273319149" IronPort-SDR: useaK0QsLR2xYrDZ1J09ljkmXjcXE868bv7coDgptCZgd4Yowr2xpAeDGXb2UEFzt3qz300++S V1TAxRcQn7u9ONef/jaJRyBkZhar1ty3W5zxl+RVM+Dk5ZQMF7BsgizwZUsWDjezUkhZWGNBQm 3K0mW7z4cwICvlx2zGYcfqxSrmLTO3mbxIg1mXUbv5SY6Resh/kqOOE1/dBuDfWCIcapfKmTeM E8x07cWTIE9M3hR9mumf/x4WrHKvOP7R/1189MYcJGNLJ2Urfx+7XLHk6yCdivNRyMzmg+V2CQ Z0VAe7BBSo+uPRtzX/1iHgP0 IronPort-SDR: lcnJtM0qFl1VYLY5qU+amovCOBqRdkT4GZ+lO1Re3sS2d1pA8KOuDxjYB9o/HPK5zAp5eaXhwJ o0cZ/+PTjDvrb1NkLxbisZEidSthZdrDca769RTlSrO8poYM0EUkSAnKiQibC5DoO5tHGibELn 57iqp4awt3i8m1AzabIJtyi9eahompCpG7f51bXxmOl1w1Rhjv4Jj/t1YilkD/AAQzgY09b31r hzhqBlEBhgrn3iZuKinJPJAz8kptD6e1HkM5yi7BfNM7KyxzPcZj3SOXLRIpXyX5jG97i1pcjQ AN8= WDCIronportException: Internal From: Atish Patra To: qemu-devel@nongnu.org Subject: [ RFC 3/6] target/riscv: Support mcycle/minstret write operation Date: Fri, 19 Mar 2021 12:45:31 -0700 Message-Id: <20210319194534.2082397-4-atish.patra@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210319194534.2082397-1-atish.patra@wdc.com> References: <20210319194534.2082397-1-atish.patra@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=705762e65=atish.patra@wdc.com; helo=esa1.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Sagar Karandikar , Bastian Koppelmann , anup.patel@wdc.com, Atish Patra , Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" mcycle/minstret are actually WARL registers and can be written with any given value. With SBI PMU extension, it will be used to store a initial value provided from supervisor OS. The Qemu also need prohibit the counter increment if mcountinhibit is set. Signed-off-by: Atish Patra Acked-by: Alistair Francis --- target/riscv/cpu.h | 8 +++ target/riscv/csr.c | 111 ++++++++++++++++++++++++++++++++++------- target/riscv/machine.c | 4 ++ 3 files changed, 105 insertions(+), 18 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index ef2a7fdc3980..47d6caeb7354 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -216,6 +216,14 @@ struct CPURISCVState { =20 target_ulong mcountinhibit; =20 + /* Snapshot values for mcycle & minstret */ + target_ulong mcycle_prev; + target_ulong minstret_prev; + + /* for RV32 */ + target_ulong mcycleh_prev; + target_ulong minstreth_prev; + target_ulong sscratch; target_ulong mscratch; =20 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index b9d795389532..61036649b044 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -319,31 +319,106 @@ static int write_vstart(CPURISCVState *env, int csrn= o, target_ulong val) } =20 /* User Timers and Counters */ -static int read_instret(CPURISCVState *env, int csrno, target_ulong *val) + +static target_ulong get_icount_ticks(bool brv32) { + int64_t val; + target_ulong result; + #if !defined(CONFIG_USER_ONLY) if (icount_enabled()) { - *val =3D icount_get(); + val =3D icount_get(); } else { - *val =3D cpu_get_host_ticks(); + val =3D cpu_get_host_ticks(); } #else - *val =3D cpu_get_host_ticks(); + val =3D cpu_get_host_ticks(); #endif + + if (brv32) { + result =3D val >> 32; + } else { + result =3D val; + } + + return result; +} + +static int read_cycle(CPURISCVState *env, int csrno, target_ulong *val) +{ + if (get_field(env->mcountinhibit, HCOUNTEREN_CY)) { + /** + * Counter should not increment if inhibit bit is set. We can't re= ally + * stop the icount counting. Just return the previous value to ind= icate + * that counter was not incremented. + */ + *val =3D env->mcycle_prev; + return 0; + } + + *val =3D get_icount_ticks(false); + + if (*val > env->mcycle_prev) + *val =3D *val - env->mcycle_prev + env->mphmcounter_val[0]; + else + /* Overflow scenario */ + *val =3D UINT64_MAX - env->mcycle_prev + 1 + env->mphmcounter_val[= 0] + *val; + + return 0; +} + +static int read_instret(CPURISCVState *env, int csrno, target_ulong *val) +{ + if (get_field(env->mcountinhibit, HCOUNTEREN_IR)) { + *val =3D env->minstret_prev; + return 0; + } + + *val =3D get_icount_ticks(false); + + if (*val > env->minstret_prev) + *val =3D *val - env->minstret_prev + env->mphmcounter_val[2]; + else + /* Overflow scenario */ + *val =3D UINT64_MAX - env->minstret_prev + 1 + env->mphmcounter_va= l[2] + *val; + + return 0; +} + +static int read_cycleh(CPURISCVState *env, int csrno, target_ulong *val) +{ + + if (get_field(env->mcountinhibit, HCOUNTEREN_CY)) { + *val =3D env->mcycleh_prev; + return 0; + } + + *val =3D get_icount_ticks(true); + + if (*val > env->mcycleh_prev) + *val =3D *val - env->mcycleh_prev + env->mphmcounterh_val[0]; + else + /* Overflow scenario */ + *val =3D UINT32_MAX - env->mcycleh_prev + 1 + env->mphmcounterh_va= l[0] + *val; + return 0; } =20 static int read_instreth(CPURISCVState *env, int csrno, target_ulong *val) { -#if !defined(CONFIG_USER_ONLY) - if (icount_enabled()) { - *val =3D icount_get() >> 32; - } else { - *val =3D cpu_get_host_ticks() >> 32; + if (get_field(env->mcountinhibit, HCOUNTEREN_IR)) { + *val =3D env->minstreth_prev; + return 0; } -#else - *val =3D cpu_get_host_ticks() >> 32; -#endif + + *val =3D get_icount_ticks(true); + + if (*val > env->minstreth_prev) + *val =3D *val - env->minstreth_prev + env->mphmcounterh_val[2]; + else + /* Overflow scenario */ + *val =3D UINT32_MAX - env->minstreth_prev + 1 + env->mphmcounterh_= val[2] + *val; + return 0; } =20 @@ -1383,9 +1458,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_VL] =3D { "vl", vs, read_vl }, [CSR_VTYPE] =3D { "vtype", vs, read_vtype }, /* User Timers and Counters */ - [CSR_CYCLE] =3D { "cycle", ctr, read_instret }, + [CSR_CYCLE] =3D { "cycle", ctr, read_cycle }, [CSR_INSTRET] =3D { "instret", ctr, read_instret }, - [CSR_CYCLEH] =3D { "cycleh", ctr32, read_instreth }, + [CSR_CYCLEH] =3D { "cycleh", ctr32, read_cycleh }, [CSR_INSTRETH] =3D { "instreth", ctr32, read_instreth }, =20 /* @@ -1397,10 +1472,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { =20 #if !defined(CONFIG_USER_ONLY) /* Machine Timers and Counters */ - [CSR_MCYCLE] =3D { "mcycle", any, read_instret }, - [CSR_MINSTRET] =3D { "minstret", any, read_instret }, - [CSR_MCYCLEH] =3D { "mcycleh", any32, read_instreth }, - [CSR_MINSTRETH] =3D { "minstreth", any32, read_instreth }, + [CSR_MCYCLE] =3D { "mcycle", any, read_cycle , write_mhpmcoun= ter}, + [CSR_MINSTRET] =3D { "minstret", any, read_instret, write_mhpmcoun= ter}, + [CSR_MCYCLEH] =3D { "mcycleh", any32, read_cycleh , write_mhpmcoun= terh}, + [CSR_MINSTRETH] =3D { "minstreth", any32, read_instreth , write_mhpmco= unterh}, =20 /* Machine Information Registers */ [CSR_MVENDORID] =3D { "mvendorid", any, read_zero }, diff --git a/target/riscv/machine.c b/target/riscv/machine.c index cb7ec8a4c656..b1410419cc1f 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -178,6 +178,10 @@ const VMStateDescription vmstate_riscv_cpu =3D { VMSTATE_UINTTL(env.scounteren, RISCVCPU), VMSTATE_UINTTL(env.mcounteren, RISCVCPU), VMSTATE_UINTTL(env.mcountinhibit, RISCVCPU), + VMSTATE_UINTTL(env.mcycle_prev, RISCVCPU), + VMSTATE_UINTTL(env.mcycleh_prev, RISCVCPU), + VMSTATE_UINTTL(env.minstret_prev, RISCVCPU), + VMSTATE_UINTTL(env.minstreth_prev, RISCVCPU), VMSTATE_UINTTL(env.sscratch, RISCVCPU), VMSTATE_UINTTL(env.mscratch, RISCVCPU), VMSTATE_UINT64(env.mfromhost, RISCVCPU), --=20 2.25.1 From nobody Wed May 1 11:22:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=705762e65=atish.patra@wdc.com; helo=esa1.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Sagar Karandikar , Bastian Koppelmann , anup.patel@wdc.com, Atish Patra , Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" With SBI PMU extension, user can use any of the available hpmcounters to track any perf events based on the value written to mhpmevent csr. Add read/write functionality for these csrs. Signed-off-by: Atish Patra Acked-by: Alistair Francis --- target/riscv/cpu.h | 7 + target/riscv/csr.c | 444 +++++++++++++++++++++++++++-------------- target/riscv/machine.c | 3 + 3 files changed, 302 insertions(+), 152 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 47d6caeb7354..0a2b6da78110 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -220,9 +220,16 @@ struct CPURISCVState { target_ulong mcycle_prev; target_ulong minstret_prev; =20 + /* PMU counter configured values */ + target_ulong mphmcounter_val[32]; + /* for RV32 */ target_ulong mcycleh_prev; target_ulong minstreth_prev; + target_ulong mphmcounterh_val[32]; + + /* PMU event selector configured values */ + target_ulong mphmevent_val[29]; =20 target_ulong sscratch; target_ulong mscratch; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 61036649b044..a0430bbbd145 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -422,6 +422,88 @@ static int read_instreth(CPURISCVState *env, int csrno= , target_ulong *val) return 0; } =20 +static int read_mhpmevent(CPURISCVState *env, int csrno, target_ulong *val) +{ + int evt_index =3D csrno - CSR_MHPMEVENT3; + + *val =3D env->mphmcounter_val[evt_index]; + + return 0; +} + +static int write_mhpmevent(CPURISCVState *env, int csrno, target_ulong val) +{ + int evt_index =3D csrno - CSR_MHPMEVENT3; + + env->mphmevent_val[evt_index] =3D val; + + return 0; +} + +static int write_mhpmcounter(CPURISCVState *env, int csrno, target_ulong v= al) +{ + int ctr_index =3D csrno - CSR_MHPMCOUNTER3 + 3; + + if (csrno =3D=3D CSR_MCYCLE) { + env->mphmcounter_val[0] =3D val; + env->mcycle_prev =3D get_icount_ticks(false); + } else if (csrno =3D=3D CSR_MINSTRET) { + env->mphmcounter_val[2] =3D val; + env->minstret_prev =3D get_icount_ticks(false); + } else { + env->mphmcounter_val[ctr_index] =3D val; + } + + return 0; +} + +static int write_mhpmcounterh(CPURISCVState *env, int csrno, target_ulong = val) +{ + int ctr_index =3D csrno - CSR_MHPMCOUNTER3 + 3; + + if (csrno =3D=3D CSR_MCYCLEH) { + env->mphmcounterh_val[0] =3D val; + env->mcycleh_prev =3D get_icount_ticks(true); + } else if (csrno =3D=3D CSR_MINSTRETH) { + env->mphmcounterh_val[2] =3D val; + env->minstreth_prev =3D get_icount_ticks(true); + } else { + env->mphmcounterh_val[ctr_index] =3D val; + } + + return 0; +} + +static int read_hpmcounter(CPURISCVState *env, int csrno, target_ulong *va= l) +{ + int ctr_index; + + if (env->priv =3D=3D PRV_M) { + ctr_index =3D csrno - CSR_MHPMCOUNTER3 + 3; + } else { + ctr_index =3D csrno - CSR_HPMCOUNTER3 + 3; + } + *val =3D env->mphmcounter_val[ctr_index]; + + return 0; +} + +static int read_hpmcounterh(CPURISCVState *env, int csrno, target_ulong *v= al) +{ + int ctr_index; + + if (env->priv =3D=3D PRV_M) { + ctr_index =3D csrno - CSR_MHPMCOUNTER3 + 3; + } else { + ctr_index =3D csrno - CSR_HPMCOUNTER3 + 3; + } + + *val =3D env->mphmcounterh_val[ctr_index]; + + return 0; +} + + #if defined(CONFIG_USER_ONLY) static int read_time(CPURISCVState *env, int csrno, target_ulong *val) { @@ -1568,157 +1650,215 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_PMPADDR15] =3D { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr }, =20 /* Performance Counters */ - [CSR_HPMCOUNTER3] =3D { "hpmcounter3", ctr, read_zero }, - [CSR_HPMCOUNTER4] =3D { "hpmcounter4", ctr, read_zero }, - [CSR_HPMCOUNTER5] =3D { "hpmcounter5", ctr, read_zero }, - [CSR_HPMCOUNTER6] =3D { "hpmcounter6", ctr, read_zero }, - [CSR_HPMCOUNTER7] =3D { "hpmcounter7", ctr, read_zero }, - [CSR_HPMCOUNTER8] =3D { "hpmcounter8", ctr, read_zero }, - [CSR_HPMCOUNTER9] =3D { "hpmcounter9", ctr, read_zero }, - [CSR_HPMCOUNTER10] =3D { "hpmcounter10", ctr, read_zero }, - [CSR_HPMCOUNTER11] =3D { "hpmcounter11", ctr, read_zero }, - [CSR_HPMCOUNTER12] =3D { "hpmcounter12", ctr, read_zero }, - [CSR_HPMCOUNTER13] =3D { "hpmcounter13", ctr, read_zero }, - [CSR_HPMCOUNTER14] =3D { "hpmcounter14", ctr, read_zero }, - [CSR_HPMCOUNTER15] =3D { "hpmcounter15", ctr, read_zero }, - [CSR_HPMCOUNTER16] =3D { "hpmcounter16", ctr, read_zero }, - [CSR_HPMCOUNTER17] =3D { "hpmcounter17", ctr, read_zero }, - [CSR_HPMCOUNTER18] =3D { "hpmcounter18", ctr, read_zero }, - [CSR_HPMCOUNTER19] =3D { "hpmcounter19", ctr, read_zero }, - [CSR_HPMCOUNTER20] =3D { "hpmcounter20", ctr, read_zero }, - [CSR_HPMCOUNTER21] =3D { "hpmcounter21", ctr, read_zero }, - [CSR_HPMCOUNTER22] =3D { "hpmcounter22", ctr, read_zero }, - [CSR_HPMCOUNTER23] =3D { "hpmcounter23", ctr, read_zero }, - [CSR_HPMCOUNTER24] =3D { "hpmcounter24", ctr, read_zero }, - [CSR_HPMCOUNTER25] =3D { "hpmcounter25", ctr, read_zero }, - [CSR_HPMCOUNTER26] =3D { "hpmcounter26", ctr, read_zero }, - [CSR_HPMCOUNTER27] =3D { "hpmcounter27", ctr, read_zero }, - [CSR_HPMCOUNTER28] =3D { "hpmcounter28", ctr, read_zero }, - [CSR_HPMCOUNTER29] =3D { "hpmcounter29", ctr, read_zero }, - [CSR_HPMCOUNTER30] =3D { "hpmcounter30", ctr, read_zero }, - [CSR_HPMCOUNTER31] =3D { "hpmcounter31", ctr, read_zero }, - - [CSR_MHPMCOUNTER3] =3D { "mhpmcounter3", any, read_zero }, - [CSR_MHPMCOUNTER4] =3D { "mhpmcounter4", any, read_zero }, - [CSR_MHPMCOUNTER5] =3D { "mhpmcounter5", any, read_zero }, - [CSR_MHPMCOUNTER6] =3D { "mhpmcounter6", any, read_zero }, - [CSR_MHPMCOUNTER7] =3D { "mhpmcounter7", any, read_zero }, - [CSR_MHPMCOUNTER8] =3D { "mhpmcounter8", any, read_zero }, - [CSR_MHPMCOUNTER9] =3D { "mhpmcounter9", any, read_zero }, - [CSR_MHPMCOUNTER10] =3D { "mhpmcounter10", any, read_zero }, - [CSR_MHPMCOUNTER11] =3D { "mhpmcounter11", any, read_zero }, - [CSR_MHPMCOUNTER12] =3D { "mhpmcounter12", any, read_zero }, - [CSR_MHPMCOUNTER13] =3D { "mhpmcounter13", any, read_zero }, - [CSR_MHPMCOUNTER14] =3D { "mhpmcounter14", any, read_zero }, - [CSR_MHPMCOUNTER15] =3D { "mhpmcounter15", any, read_zero }, - [CSR_MHPMCOUNTER16] =3D { "mhpmcounter16", any, read_zero }, - [CSR_MHPMCOUNTER17] =3D { "mhpmcounter17", any, read_zero }, - [CSR_MHPMCOUNTER18] =3D { "mhpmcounter18", any, read_zero }, - [CSR_MHPMCOUNTER19] =3D { "mhpmcounter19", any, read_zero }, - [CSR_MHPMCOUNTER20] =3D { "mhpmcounter20", any, read_zero }, - [CSR_MHPMCOUNTER21] =3D { "mhpmcounter21", any, read_zero }, - [CSR_MHPMCOUNTER22] =3D { "mhpmcounter22", any, read_zero }, - [CSR_MHPMCOUNTER23] =3D { "mhpmcounter23", any, read_zero }, - [CSR_MHPMCOUNTER24] =3D { "mhpmcounter24", any, read_zero }, - [CSR_MHPMCOUNTER25] =3D { "mhpmcounter25", any, read_zero }, - [CSR_MHPMCOUNTER26] =3D { "mhpmcounter26", any, read_zero }, - [CSR_MHPMCOUNTER27] =3D { "mhpmcounter27", any, read_zero }, - [CSR_MHPMCOUNTER28] =3D { "mhpmcounter28", any, read_zero }, - [CSR_MHPMCOUNTER29] =3D { "mhpmcounter29", any, read_zero }, - [CSR_MHPMCOUNTER30] =3D { "mhpmcounter30", any, read_zero }, - [CSR_MHPMCOUNTER31] =3D { "mhpmcounter31", any, read_zero }, - - [CSR_MCOUNTINHIBIT] =3D { "mcountinhibi", any, read_mcountinhibi= t, - write_mcountinhibit= }, - - [CSR_MHPMEVENT3] =3D { "mhpmevent3", any, read_zero }, - [CSR_MHPMEVENT4] =3D { "mhpmevent4", any, read_zero }, - [CSR_MHPMEVENT5] =3D { "mhpmevent5", any, read_zero }, - [CSR_MHPMEVENT6] =3D { "mhpmevent6", any, read_zero }, - [CSR_MHPMEVENT7] =3D { "mhpmevent7", any, read_zero }, - [CSR_MHPMEVENT8] =3D { "mhpmevent8", any, read_zero }, - [CSR_MHPMEVENT9] =3D { "mhpmevent9", any, read_zero }, - [CSR_MHPMEVENT10] =3D { "mhpmevent10", any, read_zero }, - [CSR_MHPMEVENT11] =3D { "mhpmevent11", any, read_zero }, - [CSR_MHPMEVENT12] =3D { "mhpmevent12", any, read_zero }, - [CSR_MHPMEVENT13] =3D { "mhpmevent13", any, read_zero }, - [CSR_MHPMEVENT14] =3D { "mhpmevent14", any, read_zero }, - [CSR_MHPMEVENT15] =3D { "mhpmevent15", any, read_zero }, - [CSR_MHPMEVENT16] =3D { "mhpmevent16", any, read_zero }, - [CSR_MHPMEVENT17] =3D { "mhpmevent17", any, read_zero }, - [CSR_MHPMEVENT18] =3D { "mhpmevent18", any, read_zero }, - [CSR_MHPMEVENT19] =3D { "mhpmevent19", any, read_zero }, - [CSR_MHPMEVENT20] =3D { "mhpmevent20", any, read_zero }, - [CSR_MHPMEVENT21] =3D { "mhpmevent21", any, read_zero }, - [CSR_MHPMEVENT22] =3D { "mhpmevent22", any, read_zero }, - [CSR_MHPMEVENT23] =3D { "mhpmevent23", any, read_zero }, - [CSR_MHPMEVENT24] =3D { "mhpmevent24", any, read_zero }, - [CSR_MHPMEVENT25] =3D { "mhpmevent25", any, read_zero }, - [CSR_MHPMEVENT26] =3D { "mhpmevent26", any, read_zero }, - [CSR_MHPMEVENT27] =3D { "mhpmevent27", any, read_zero }, - [CSR_MHPMEVENT28] =3D { "mhpmevent28", any, read_zero }, - [CSR_MHPMEVENT29] =3D { "mhpmevent29", any, read_zero }, - [CSR_MHPMEVENT30] =3D { "mhpmevent30", any, read_zero }, - [CSR_MHPMEVENT31] =3D { "mhpmevent31", any, read_zero }, - - [CSR_HPMCOUNTER3H] =3D { "hpmcounter3h", ctr32, read_zero }, - [CSR_HPMCOUNTER4H] =3D { "hpmcounter4h", ctr32, read_zero }, - [CSR_HPMCOUNTER5H] =3D { "hpmcounter5h", ctr32, read_zero }, - [CSR_HPMCOUNTER6H] =3D { "hpmcounter6h", ctr32, read_zero }, - [CSR_HPMCOUNTER7H] =3D { "hpmcounter7h", ctr32, read_zero }, - [CSR_HPMCOUNTER8H] =3D { "hpmcounter8h", ctr32, read_zero }, - [CSR_HPMCOUNTER9H] =3D { "hpmcounter9h", ctr32, read_zero }, - [CSR_HPMCOUNTER10H] =3D { "hpmcounter10h", ctr32, read_zero }, - [CSR_HPMCOUNTER11H] =3D { "hpmcounter11h", ctr32, read_zero }, - [CSR_HPMCOUNTER12H] =3D { "hpmcounter12h", ctr32, read_zero }, - [CSR_HPMCOUNTER13H] =3D { "hpmcounter13h", ctr32, read_zero }, - [CSR_HPMCOUNTER14H] =3D { "hpmcounter14h", ctr32, read_zero }, - [CSR_HPMCOUNTER15H] =3D { "hpmcounter15h", ctr32, read_zero }, - [CSR_HPMCOUNTER16H] =3D { "hpmcounter16h", ctr32, read_zero }, - [CSR_HPMCOUNTER17H] =3D { "hpmcounter17h", ctr32, read_zero }, - [CSR_HPMCOUNTER18H] =3D { "hpmcounter18h", ctr32, read_zero }, - [CSR_HPMCOUNTER19H] =3D { "hpmcounter19h", ctr32, read_zero }, - [CSR_HPMCOUNTER20H] =3D { "hpmcounter20h", ctr32, read_zero }, - [CSR_HPMCOUNTER21H] =3D { "hpmcounter21h", ctr32, read_zero }, - [CSR_HPMCOUNTER22H] =3D { "hpmcounter22h", ctr32, read_zero }, - [CSR_HPMCOUNTER23H] =3D { "hpmcounter23h", ctr32, read_zero }, - [CSR_HPMCOUNTER24H] =3D { "hpmcounter24h", ctr32, read_zero }, - [CSR_HPMCOUNTER25H] =3D { "hpmcounter25h", ctr32, read_zero }, - [CSR_HPMCOUNTER26H] =3D { "hpmcounter26h", ctr32, read_zero }, - [CSR_HPMCOUNTER27H] =3D { "hpmcounter27h", ctr32, read_zero }, - [CSR_HPMCOUNTER28H] =3D { "hpmcounter28h", ctr32, read_zero }, - [CSR_HPMCOUNTER29H] =3D { "hpmcounter29h", ctr32, read_zero }, - [CSR_HPMCOUNTER30H] =3D { "hpmcounter30h", ctr32, read_zero }, - [CSR_HPMCOUNTER31H] =3D { "hpmcounter31h", ctr32, read_zero }, - - [CSR_MHPMCOUNTER3H] =3D { "mhpmcounter3h", any32, read_zero }, - [CSR_MHPMCOUNTER4H] =3D { "mhpmcounter4h", any32, read_zero }, - [CSR_MHPMCOUNTER5H] =3D { "mhpmcounter5h", any32, read_zero }, - [CSR_MHPMCOUNTER6H] =3D { "mhpmcounter6h", any32, read_zero }, - [CSR_MHPMCOUNTER7H] =3D { "mhpmcounter7h", any32, read_zero }, - [CSR_MHPMCOUNTER8H] =3D { "mhpmcounter8h", any32, read_zero }, - [CSR_MHPMCOUNTER9H] =3D { "mhpmcounter9h", any32, read_zero }, - [CSR_MHPMCOUNTER10H] =3D { "mhpmcounter10h", any32, read_zero }, - [CSR_MHPMCOUNTER11H] =3D { "mhpmcounter11h", any32, read_zero }, - [CSR_MHPMCOUNTER12H] =3D { "mhpmcounter12h", any32, read_zero }, - [CSR_MHPMCOUNTER13H] =3D { "mhpmcounter13h", any32, read_zero }, - [CSR_MHPMCOUNTER14H] =3D { "mhpmcounter14h", any32, read_zero }, - [CSR_MHPMCOUNTER15H] =3D { "mhpmcounter15h", any32, read_zero }, - [CSR_MHPMCOUNTER16H] =3D { "mhpmcounter16h", any32, read_zero }, - [CSR_MHPMCOUNTER17H] =3D { "mhpmcounter17h", any32, read_zero }, - [CSR_MHPMCOUNTER18H] =3D { "mhpmcounter18h", any32, read_zero }, - [CSR_MHPMCOUNTER19H] =3D { "mhpmcounter19h", any32, read_zero }, - [CSR_MHPMCOUNTER20H] =3D { "mhpmcounter20h", any32, read_zero }, - [CSR_MHPMCOUNTER21H] =3D { "mhpmcounter21h", any32, read_zero }, - [CSR_MHPMCOUNTER22H] =3D { "mhpmcounter22h", any32, read_zero }, - [CSR_MHPMCOUNTER23H] =3D { "mhpmcounter23h", any32, read_zero }, - [CSR_MHPMCOUNTER24H] =3D { "mhpmcounter24h", any32, read_zero }, - [CSR_MHPMCOUNTER25H] =3D { "mhpmcounter25h", any32, read_zero }, - [CSR_MHPMCOUNTER26H] =3D { "mhpmcounter26h", any32, read_zero }, - [CSR_MHPMCOUNTER27H] =3D { "mhpmcounter27h", any32, read_zero }, - [CSR_MHPMCOUNTER28H] =3D { "mhpmcounter28h", any32, read_zero }, - [CSR_MHPMCOUNTER29H] =3D { "mhpmcounter29h", any32, read_zero }, - [CSR_MHPMCOUNTER30H] =3D { "mhpmcounter30h", any32, read_zero }, - [CSR_MHPMCOUNTER31H] =3D { "mhpmcounter31h", any32, read_zero }, + [CSR_HPMCOUNTER3] =3D { "hpmcounter3", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER4] =3D { "hpmcounter4", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER5] =3D { "hpmcounter5", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER6] =3D { "hpmcounter6", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER7] =3D { "hpmcounter7", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER8] =3D { "hpmcounter8", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER9] =3D { "hpmcounter9", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER10] =3D { "hpmcounter10", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER11] =3D { "hpmcounter11", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER12] =3D { "hpmcounter12", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER13] =3D { "hpmcounter13", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER14] =3D { "hpmcounter14", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER15] =3D { "hpmcounter15", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER16] =3D { "hpmcounter16", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER17] =3D { "hpmcounter17", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER18] =3D { "hpmcounter18", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER19] =3D { "hpmcounter19", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER20] =3D { "hpmcounter20", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER21] =3D { "hpmcounter21", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER22] =3D { "hpmcounter22", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER23] =3D { "hpmcounter23", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER24] =3D { "hpmcounter24", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER25] =3D { "hpmcounter25", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER26] =3D { "hpmcounter26", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER27] =3D { "hpmcounter27", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER28] =3D { "hpmcounter28", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER29] =3D { "hpmcounter29", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER30] =3D { "hpmcounter30", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER31] =3D { "hpmcounter31", ctr, read_hpmcounter }, + + [CSR_MHPMCOUNTER3] =3D { "mhpmcounter3", any, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER4] =3D { "mhpmcounter4", any, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER5] =3D { "mhpmcounter5", any, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER6] =3D { "mhpmcounter6", any, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER7] =3D { "mhpmcounter7", any, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER8] =3D { "mhpmcounter8", any, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER9] =3D { "mhpmcounter9", any, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER10] =3D { "mhpmcounter10", any, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER11] =3D { "mhpmcounter11", any, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER12] =3D { "mhpmcounter12", any, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER13] =3D { "mhpmcounter13", any, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER14] =3D { "mhpmcounter14", any, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER15] =3D { "mhpmcounter15", any, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER16] =3D { "mhpmcounter16", any, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER17] =3D { "mhpmcounter17", any, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER18] =3D { "mhpmcounter18", any, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER19] =3D { "mhpmcounter19", any, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER20] =3D { "mhpmcounter20", any, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER21] =3D { "mhpmcounter21", any, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER22] =3D { "mhpmcounter22", any, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER23] =3D { "mhpmcounter23", any, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER24] =3D { "mhpmcounter24", any, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER25] =3D { "mhpmcounter25", any, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER26] =3D { "mhpmcounter26", any, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER27] =3D { "mhpmcounter27", any, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER28] =3D { "mhpmcounter28", any, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER29] =3D { "mhpmcounter29", any, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER30] =3D { "mhpmcounter30", any, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER31] =3D { "mhpmcounter31", any, read_hpmcounter, + write_mhpmcounter }, + + [CSR_MCOUNTINHIBIT] =3D { "mcountinhibit", any, read_mcountinhibit, + write_mcountinhibit }, + + [CSR_MHPMEVENT3] =3D { "mhpmevent3", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT4] =3D { "mhpmevent4", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT5] =3D { "mhpmevent5", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT6] =3D { "mhpmevent6", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT7] =3D { "mhpmevent7", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT8] =3D { "mhpmevent8", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT9] =3D { "mhpmevent9", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT10] =3D { "mhpmevent10", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT11] =3D { "mhpmevent11", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT12] =3D { "mhpmevent12", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT13] =3D { "mhpmevent13", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT14] =3D { "mhpmevent14", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT15] =3D { "mhpmevent15", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT16] =3D { "mhpmevent16", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT17] =3D { "mhpmevent17", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT18] =3D { "mhpmevent18", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT19] =3D { "mhpmevent19", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT20] =3D { "mhpmevent20", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT21] =3D { "mhpmevent21", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT22] =3D { "mhpmevent22", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT23] =3D { "mhpmevent23", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT24] =3D { "mhpmevent24", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT25] =3D { "mhpmevent25", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT26] =3D { "mhpmevent26", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT27] =3D { "mhpmevent27", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT28] =3D { "mhpmevent28", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT29] =3D { "mhpmevent29", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT30] =3D { "mhpmevent30", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT31] =3D { "mhpmevent31", any, read_mhpmevent, + write_mhpmevent }, + + [CSR_HPMCOUNTER3H] =3D { "hpmcounter3h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER4H] =3D { "hpmcounter4h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER5H] =3D { "hpmcounter5h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER6H] =3D { "hpmcounter6h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER7H] =3D { "hpmcounter7h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER8H] =3D { "hpmcounter8h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER9H] =3D { "hpmcounter9h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER10H] =3D { "hpmcounter10h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER11H] =3D { "hpmcounter11h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER12H] =3D { "hpmcounter12h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER13H] =3D { "hpmcounter13h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER14H] =3D { "hpmcounter14h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER15H] =3D { "hpmcounter15h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER16H] =3D { "hpmcounter16h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER17H] =3D { "hpmcounter17h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER18H] =3D { "hpmcounter18h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER19H] =3D { "hpmcounter19h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER20H] =3D { "hpmcounter20h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER21H] =3D { "hpmcounter21h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER22H] =3D { "hpmcounter22h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER23H] =3D { "hpmcounter23h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER24H] =3D { "hpmcounter24h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER25H] =3D { "hpmcounter25h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER26H] =3D { "hpmcounter26h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER27H] =3D { "hpmcounter27h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER28H] =3D { "hpmcounter28h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER29H] =3D { "hpmcounter29h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER30H] =3D { "hpmcounter30h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER31H] =3D { "hpmcounter31h", ctr32, read_hpmcounterh = }, + + [CSR_MHPMCOUNTER3H] =3D { "mhpmcounter3h", any32, read_hpmcounterh = }, + [CSR_MHPMCOUNTER4H] =3D { "mhpmcounter4h", any32, read_hpmcounterh = }, + [CSR_MHPMCOUNTER5H] =3D { "mhpmcounter5h", any32, read_hpmcounterh = }, + [CSR_MHPMCOUNTER6H] =3D { "mhpmcounter6h", any32, read_hpmcounterh = }, + [CSR_MHPMCOUNTER7H] =3D { "mhpmcounter7h", any32, read_hpmcounterh = }, + [CSR_MHPMCOUNTER8H] =3D { "mhpmcounter8h", any32, read_hpmcounterh = }, + [CSR_MHPMCOUNTER9H] =3D { "mhpmcounter9h", any32, read_hpmcounterh = }, + [CSR_MHPMCOUNTER10H] =3D { "mhpmcounter10h", any32, read_hpmcounterh = }, + [CSR_MHPMCOUNTER11H] =3D { "mhpmcounter11h", any32, read_hpmcounterh = }, + [CSR_MHPMCOUNTER12H] =3D { "mhpmcounter12h", any32, read_hpmcounterh = }, + [CSR_MHPMCOUNTER13H] =3D { "mhpmcounter13h", any32, read_hpmcounterh = }, + [CSR_MHPMCOUNTER14H] =3D { "mhpmcounter14h", any32, read_hpmcounterh = }, + [CSR_MHPMCOUNTER15H] =3D { "mhpmcounter15h", any32, read_hpmcounterh = }, + [CSR_MHPMCOUNTER16H] =3D { "mhpmcounter16h", any32, read_hpmcounterh = }, + [CSR_MHPMCOUNTER17H] =3D { "mhpmcounter17h", any32, read_hpmcounterh = }, + [CSR_MHPMCOUNTER18H] =3D { "mhpmcounter18h", any32, read_hpmcounterh = }, + [CSR_MHPMCOUNTER19H] =3D { "mhpmcounter19h", any32, read_hpmcounterh = }, + [CSR_MHPMCOUNTER20H] =3D { "mhpmcounter20h", any32, read_hpmcounterh = }, + [CSR_MHPMCOUNTER21H] =3D { "mhpmcounter21h", any32, read_hpmcounterh = }, + [CSR_MHPMCOUNTER22H] =3D { "mhpmcounter22h", any32, read_hpmcounterh = }, + [CSR_MHPMCOUNTER23H] =3D { "mhpmcounter23h", any32, read_hpmcounterh = }, + [CSR_MHPMCOUNTER24H] =3D { "mhpmcounter24h", any32, read_hpmcounterh = }, + [CSR_MHPMCOUNTER25H] =3D { "mhpmcounter25h", any32, read_hpmcounterh = }, + [CSR_MHPMCOUNTER26H] =3D { "mhpmcounter26h", any32, read_hpmcounterh = }, + [CSR_MHPMCOUNTER27H] =3D { "mhpmcounter27h", any32, read_hpmcounterh = }, + [CSR_MHPMCOUNTER28H] =3D { "mhpmcounter28h", any32, read_hpmcounterh = }, + [CSR_MHPMCOUNTER29H] =3D { "mhpmcounter29h", any32, read_hpmcounterh = }, + [CSR_MHPMCOUNTER30H] =3D { "mhpmcounter30h", any32, read_hpmcounterh = }, + [CSR_MHPMCOUNTER31H] =3D { "mhpmcounter31h", any32, read_hpmcounterh = }, #endif /* !CONFIG_USER_ONLY */ }; diff --git a/target/riscv/machine.c b/target/riscv/machine.c index b1410419cc1f..d70531402d86 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -182,6 +182,9 @@ const VMStateDescription vmstate_riscv_cpu =3D { VMSTATE_UINTTL(env.mcycleh_prev, RISCVCPU), VMSTATE_UINTTL(env.minstret_prev, RISCVCPU), VMSTATE_UINTTL(env.minstreth_prev, RISCVCPU), + VMSTATE_UINTTL_ARRAY(env.mphmcounter_val, RISCVCPU, 32), + VMSTATE_UINTTL_ARRAY(env.mphmcounterh_val, RISCVCPU, 32), + VMSTATE_UINTTL_ARRAY(env.mphmevent_val, RISCVCPU, 29), VMSTATE_UINTTL(env.sscratch, RISCVCPU), VMSTATE_UINTTL(env.mscratch, RISCVCPU), VMSTATE_UINT64(env.mfromhost, RISCVCPU), --=20 2.25.1 From nobody Wed May 1 11:22:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1616183390; cv=none; d=zohomail.com; s=zohoarc; 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Atish Patra To: qemu-devel@nongnu.org Subject: [ RFC 5/6] hw/riscv: virt: Add PMU device tree node to support SBI PMU extension Date: Fri, 19 Mar 2021 12:45:33 -0700 Message-Id: <20210319194534.2082397-6-atish.patra@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210319194534.2082397-1-atish.patra@wdc.com> References: <20210319194534.2082397-1-atish.patra@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=705762e65=atish.patra@wdc.com; helo=esa1.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Sagar Karandikar , Bastian Koppelmann , anup.patel@wdc.com, Atish Patra , Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Qemu can't really support any PMU events other than cycle & instructions counters. Add a PMU device tree node only for these events based on device tree bindings defined in OpenSBI Signed-off-by: Atish Patra --- hw/riscv/virt.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 4f0c2fbca071..84570ad6425b 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -42,6 +42,7 @@ #include "sysemu/sysemu.h" #include "hw/pci/pci.h" #include "hw/pci-host/gpex.h" +#include =20 static const MemMapEntry virt_memmap[] =3D { [VIRT_DEBUG] =3D { 0x0, 0x100 }, @@ -180,7 +181,7 @@ static void create_fdt(RISCVVirtState *s, const MemMapE= ntry *memmap, uint64_t mem_size, const char *cmdline, bool is_32_= bit) { void *fdt; - int i, cpu, socket; + int i, cpu, socket, rc; MachineState *mc =3D MACHINE(s); uint64_t addr, size; uint32_t *clint_cells, *plic_cells; @@ -190,9 +191,10 @@ static void create_fdt(RISCVVirtState *s, const MemMap= Entry *memmap, uint32_t phandle =3D 1, plic_mmio_phandle =3D 1; uint32_t plic_pcie_phandle =3D 1, plic_virtio_phandle =3D 1; char *mem_name, *cpu_name, *core_name, *intc_name; - char *name, *clint_name, *plic_name, *clust_name; + char *name, *clint_name, *plic_name, *clust_name, *pmu_name; hwaddr flashsize =3D virt_memmap[VIRT_FLASH].size / 2; hwaddr flashbase =3D virt_memmap[VIRT_FLASH].base; + uint32_t pmu_event_ctr_map[6] =3D {}; =20 if (mc->dtb) { fdt =3D s->fdt =3D load_device_tree(mc->dtb, &s->fdt_size); @@ -284,6 +286,22 @@ static void create_fdt(RISCVVirtState *s, const MemMap= Entry *memmap, g_free(cpu_name); } =20 + rc =3D fdt_path_offset(fdt, "/pmu"); + if (rc =3D=3D -FDT_ERR_NOTFOUND) { + pmu_name =3D g_strdup_printf("/pmu"); + qemu_fdt_add_subnode(fdt, pmu_name); + qemu_fdt_setprop_string(fdt, pmu_name, "compatible", + "riscv,pmu"); + pmu_event_ctr_map[0] =3D cpu_to_be32(0x00000001); + pmu_event_ctr_map[1] =3D cpu_to_be32(0x00000001); + pmu_event_ctr_map[2] =3D cpu_to_be32(0x00000001); + pmu_event_ctr_map[3] =3D cpu_to_be32(0x00000002); + pmu_event_ctr_map[4] =3D cpu_to_be32(0x00000002); + pmu_event_ctr_map[5] =3D cpu_to_be32(0x00000004); + qemu_fdt_setprop(fdt, pmu_name, "opensbi,event-to-counters= ", + pmu_event_ctr_map, sizeof(pmu_event_ctr_m= ap)); + g_free(pmu_name); + } addr =3D memmap[VIRT_DRAM].base + riscv_socket_mem_offset(mc, sock= et); size =3D riscv_socket_mem_size(mc, socket); mem_name =3D g_strdup_printf("/memory@%lx", (long)addr); --=20 2.25.1 From nobody Wed May 1 11:22:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1616183474; cv=none; d=zohomail.com; s=zohoarc; b=iJMMtbJBFWewrny77vweYL64FKix8orgfZkILlHyjJArwT8j67HHhe5Enu9Be+Kfl+EpKp5FbfrhhFKd+fhX7modDrj3GBl0/c7psn2OcFeCuR82l6KhjlgbrtKmkRVjC6gisVeZ0lOciVM8lo0E3xU4MKkzAAxFLC/ydHYCdRk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=705762e65=atish.patra@wdc.com; helo=esa1.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Sagar Karandikar , Bastian Koppelmann , anup.patel@wdc.com, Atish Patra , Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" ** DO NOT MERGE IT ** This is just a test patch to test various kinds of PMU events. The counters don't actually increment as virt machine doesn't support any of the PMU events. However, it helps to test the OpenSBI/Kernel implementation. Please ignore this patch while merging it. Signed-off-by: Atish Patra --- hw/riscv/virt.c | 34 ++++++++++++++++++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 84570ad6425b..59d8325bf2a1 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -194,7 +194,9 @@ static void create_fdt(RISCVVirtState *s, const MemMapE= ntry *memmap, char *name, *clint_name, *plic_name, *clust_name, *pmu_name; hwaddr flashsize =3D virt_memmap[VIRT_FLASH].size / 2; hwaddr flashbase =3D virt_memmap[VIRT_FLASH].base; - uint32_t pmu_event_ctr_map[6] =3D {}; + uint32_t pmu_event_map[6] =3D {}; + uint32_t pmu_event_ctr_map[12] =3D {}; + uint32_t pmu_raw_event_ctr_map[6] =3D {}; =20 if (mc->dtb) { fdt =3D s->fdt =3D load_device_tree(mc->dtb, &s->fdt_size); @@ -288,18 +290,46 @@ static void create_fdt(RISCVVirtState *s, const MemMa= pEntry *memmap, =20 rc =3D fdt_path_offset(fdt, "/pmu"); if (rc =3D=3D -FDT_ERR_NOTFOUND) { + pmu_event_map[0] =3D cpu_to_be32(0x00000009); + pmu_event_map[1] =3D cpu_to_be32(0x00000000); + pmu_event_map[2] =3D cpu_to_be32(0x00000200); + pmu_event_map[3] =3D cpu_to_be32(0x00010000); + pmu_event_map[4] =3D cpu_to_be32(0x00000100); + pmu_event_map[5] =3D cpu_to_be32(0x00000002); pmu_name =3D g_strdup_printf("/pmu"); qemu_fdt_add_subnode(fdt, pmu_name); qemu_fdt_setprop_string(fdt, pmu_name, "compatible", "riscv,pmu"); + qemu_fdt_setprop(fdt, pmu_name, "opensbi,event-to-mhpmeven= t", + pmu_event_map, sizeof(pmu_event_map)); + pmu_event_ctr_map[0] =3D cpu_to_be32(0x00000001); pmu_event_ctr_map[1] =3D cpu_to_be32(0x00000001); pmu_event_ctr_map[2] =3D cpu_to_be32(0x00000001); pmu_event_ctr_map[3] =3D cpu_to_be32(0x00000002); pmu_event_ctr_map[4] =3D cpu_to_be32(0x00000002); pmu_event_ctr_map[5] =3D cpu_to_be32(0x00000004); + + pmu_event_ctr_map[6] =3D cpu_to_be32(0x00000003); + pmu_event_ctr_map[7] =3D cpu_to_be32(0x0000000A); + pmu_event_ctr_map[8] =3D cpu_to_be32(0x00000FF8); + pmu_event_ctr_map[9] =3D cpu_to_be32(0x00010000); + pmu_event_ctr_map[10] =3D cpu_to_be32(0x001C000); + pmu_event_ctr_map[11] =3D cpu_to_be32(0x00001F0); + qemu_fdt_setprop(fdt, pmu_name, "opensbi,event-to-counters= ", - pmu_event_ctr_map, sizeof(pmu_event_ctr_m= ap)); + pmu_event_ctr_map, sizeof(pmu_event_ctr_map)); + + pmu_raw_event_ctr_map[0] =3D cpu_to_be32(0x00000000); + pmu_raw_event_ctr_map[1] =3D cpu_to_be32(0x00000002); + pmu_raw_event_ctr_map[2] =3D cpu_to_be32(0x00000F00); + pmu_raw_event_ctr_map[3] =3D cpu_to_be32(0x00000000); + pmu_raw_event_ctr_map[4] =3D cpu_to_be32(0x00000003); + pmu_raw_event_ctr_map[5] =3D cpu_to_be32(0x000000F0); + qemu_fdt_setprop(fdt, pmu_name, "opensbi,raw-event-to-coun= ters", + pmu_raw_event_ctr_map, + sizeof(pmu_raw_event_ctr_map)); + g_free(pmu_name); } addr =3D memmap[VIRT_DRAM].base + riscv_socket_mem_offset(mc, sock= et); --=20 2.25.1