From nobody Tue May 7 16:16:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1616163731; cv=none; d=zohomail.com; s=zohoarc; b=VSdhhoTBMOOsdbWDulM8wAiPtRdmbgeQhIkNzLFwKsVR0bskUmpcvomly7CCAMPMmia4B1CCEFm0lf9YQR7bSFU8zw2W8W0dY6K2y/TOfH9G1IJu5fW/hprdcTComyuDtPsBcdAh3qQKJXO8RDaBggcUuqi72shvvIAfD6zE63M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1616163731; h=Content-Transfer-Encoding:Cc:Date:From:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:To; bh=IQ0kOFa1I9InV3UNIj7AbK06GVpvT2T/K8M2Hz6Z65w=; b=TMYoyFYsq6CADFTUgz4u6QeC6ajapEMCXCcklr2FdlXCf3yvaypNDMGnaKqnaVV6V6eyOzKFDe7uU/5qUTYL4brKt/KR4R8sbDci7G3YoSwgxaxN8tnqKi0djLfDwgC/p+onNXWBu80wGq9seraAtN5z5A6km6hfNJyUySe2hFg= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16161637315081021.903579750204; Fri, 19 Mar 2021 07:22:11 -0700 (PDT) Received: from localhost ([::1]:34430 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lNFw2-0000mB-QI for importer@patchew.org; Fri, 19 Mar 2021 10:17:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46242) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lNFuv-00005D-HM; Fri, 19 Mar 2021 10:15:57 -0400 Received: from serv1.kernkonzept.com ([2a01:4f8:1c1c:b490::2]:47627 helo=mx.kernkonzept.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lNFut-0007Cm-AW; Fri, 19 Mar 2021 10:15:57 -0400 Received: from [89.16.135.166] (helo=broc.lan) by mx.kernkonzept.com with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) id 1lNFuo-0001S2-K4; Fri, 19 Mar 2021 15:15:50 +0100 From: Georg Kotheimer To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2] target/riscv: Add proper two-stage lookup exception detection Date: Fri, 19 Mar 2021 15:14:59 +0100 Message-Id: <20210319141459.1196741-1-georg.kotheimer@kernkonzept.com> X-Mailer: git-send-email 2.31.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=2a01:4f8:1c1c:b490::2; envelope-from=georg.kotheimer@kernkonzept.com; helo=mx.kernkonzept.com X-Spam_score_int: -7 X-Spam_score: -0.8 X-Spam_bar: / X-Spam_report: (-0.8 / 5.0 requ) BAYES_00=-1.9, KHOP_HELO_FCRDNS=0.399, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Richard Henderson , Georg Kotheimer Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The current two-stage lookup detection in riscv_cpu_do_interrupt falls short of its purpose, as all it checks is whether two-stage address translation either via the hypervisor-load store instructions or the MPRV feature would be allowed. What we really need instead is whether two-stage address translation was active when the exception was raised. However, in riscv_cpu_do_interrupt we do not have the information to reliably detect this. Therefore, when we raise a memory fault exception we have to record whether two-stage address translation is active. Signed-off-by: Georg Kotheimer Reviewed-by: Alistair Francis --- Unfortunately, I tested the previous version of the patch only against the RISC-V softmmu target, not against the linux-user target. I modified the patch, so that the two_stage_lookup is neither present nor updated for the linux-user target. target/riscv/cpu.c | 1 + target/riscv/cpu.h | 4 ++++ target/riscv/cpu_helper.c | 21 ++++++++------------- 3 files changed, 13 insertions(+), 13 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ddea8fbeeb..e8c4455525 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -356,6 +356,7 @@ static void riscv_cpu_reset(DeviceState *dev) env->mstatus &=3D ~(MSTATUS_MIE | MSTATUS_MPRV); env->mcause =3D 0; env->pc =3D env->resetvec; + env->two_stage_lookup =3D false; #endif cs->exception_index =3D EXCP_NONE; env->load_res =3D -1; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0edb2826a2..0a33d387ba 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -213,6 +213,10 @@ struct CPURISCVState { target_ulong satp_hs; uint64_t mstatus_hs; =20 + /* Signals whether the current exception occurred with two-stage addre= ss + translation active. */ + bool two_stage_lookup; + target_ulong scounteren; target_ulong mcounteren; =20 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 2f43939fb6..af00728829 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -605,6 +605,7 @@ static void raise_mmu_exception(CPURISCVState *env, tar= get_ulong address, g_assert_not_reached(); } env->badaddr =3D address; + env->two_stage_lookup =3D two_stage; } =20 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) @@ -646,6 +647,8 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwad= dr physaddr, } =20 env->badaddr =3D addr; + env->two_stage_lookup =3D riscv_cpu_virt_enabled(env) || + riscv_cpu_two_stage_lookup(mmu_idx); riscv_raise_exception(&cpu->env, cs->exception_index, retaddr); } =20 @@ -669,6 +672,8 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr = addr, g_assert_not_reached(); } env->badaddr =3D addr; + env->two_stage_lookup =3D riscv_cpu_virt_enabled(env) || + riscv_cpu_two_stage_lookup(mmu_idx); riscv_raise_exception(env, cs->exception_index, retaddr); } #endif /* !CONFIG_USER_ONLY */ @@ -910,16 +915,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) /* handle the trap in S-mode */ if (riscv_has_ext(env, RVH)) { target_ulong hdeleg =3D async ? env->hideleg : env->hedeleg; - bool two_stage_lookup =3D false; =20 - if (env->priv =3D=3D PRV_M || - (env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(env)) || - (env->priv =3D=3D PRV_U && !riscv_cpu_virt_enabled(env) && - get_field(env->hstatus, HSTATUS_HU))) { - two_stage_lookup =3D true; - } - - if ((riscv_cpu_virt_enabled(env) || two_stage_lookup) && write= _tval) { + if (env->two_stage_lookup && write_tval) { /* * If we are writing a guest virtual address to stval, set * this to 1. If we are trapping to VS we will set this to= 0 @@ -957,10 +954,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) riscv_cpu_set_force_hs_excep(env, 0); } else { /* Trap into HS mode */ - if (!two_stage_lookup) { - env->hstatus =3D set_field(env->hstatus, HSTATUS_SPV, - riscv_cpu_virt_enabled(env)); - } + env->hstatus =3D set_field(env->hstatus, HSTATUS_SPV, fals= e); htval =3D env->guest_phys_fault_addr; } } @@ -1016,6 +1010,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) * RISC-V ISA Specification. */ =20 + env->two_stage_lookup =3D false; #endif cs->exception_index =3D EXCP_NONE; /* mark handled to qemu */ } --=20 2.31.0