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Thu, 18 Mar 2021 11:00:53 -0400 Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-508-t_xoT7QsNb-c5ahAkOhNPQ-1; Thu, 18 Mar 2021 11:00:47 -0400 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 7539318B62B0 for ; Thu, 18 Mar 2021 15:00:24 +0000 (UTC) Received: from virtlab701.virt.lab.eng.bos.redhat.com (virtlab701.virt.lab.eng.bos.redhat.com [10.19.152.228]) by smtp.corp.redhat.com (Postfix) with ESMTP id 3BCC371C5A for ; Thu, 18 Mar 2021 15:00:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1616079649; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=lbx3h2wgmuMMFM6fNTXWmbXv2R9WG/zi/CgrGegFDfY=; b=hWq8lI0vZ524F8AsYibwuruJvgRaftqc4EvGYY0pPBCnmZ3r5iyJAdtqn8d5PG7NgE4qcY jRyY6meujCf36na3xPyF0gxeScLpI6uAldhvCsofNPPKfYMg/MqhtI/rkaW5ESS39W1dhO 1PHR4D5VvujTQw7uSVBtZsIt4DhPsfs= X-MC-Unique: t_xoT7QsNb-c5ahAkOhNPQ-1 From: Paolo Bonzini To: qemu-devel@nongnu.org Subject: [PATCH 1/3] target/i386: allow modifying TCG phys-addr-bits Date: Thu, 18 Mar 2021 11:00:20 -0400 Message-Id: <20210318150022.1824646-2-pbonzini@redhat.com> In-Reply-To: <20210318150022.1824646-1-pbonzini@redhat.com> References: <20210318150022.1824646-1-pbonzini@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=pbonzini@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=63.128.21.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.249, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @redhat.com) Content-Type: text/plain; charset="utf-8" TCG can support any number of physical address bits as long as the core memory API does. We only need to compute the reserved bits mask dynamically. Signed-off-by: Paolo Bonzini --- target/i386/cpu.c | 23 ++++++++--------------- target/i386/cpu.h | 1 - target/i386/tcg/excp_helper.c | 7 ++++--- target/i386/tcg/helper-tcg.h | 12 ++++-------- 4 files changed, 16 insertions(+), 27 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index ae9fd9f31d..6b3e9467f1 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6785,21 +6785,14 @@ static void x86_cpu_realizefn(DeviceState *dev, Err= or **errp) cpu->phys_bits =3D cpu->host_phys_bits_limit; } } - - if (cpu->phys_bits && - (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS || - cpu->phys_bits < 32)) { - error_setg(errp, "phys-bits should be between 32 and %u " - " (but is %u)", - TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bi= ts); - return; - } - } else { - if (cpu->phys_bits && cpu->phys_bits !=3D TCG_PHYS_ADDR_BITS) { - error_setg(errp, "TCG only supports phys-bits=3D%u", - TCG_PHYS_ADDR_BITS); - return; - } + } + if (cpu->phys_bits && + (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS || + cpu->phys_bits < 32)) { + error_setg(errp, "phys-bits should be between 32 and %u " + " (but is %u)", + TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits); + return; } /* 0 means it was not explicitly set by the user (or by machine * compat_props or by the host code above). In this case, the defa= ult diff --git a/target/i386/cpu.h b/target/i386/cpu.h index b4b136cd0d..570f916878 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -290,7 +290,6 @@ typedef enum X86Seg { #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT) #define PG_PSE_PAT_MASK (1 << PG_PSE_PAT_BIT) #define PG_ADDRESS_MASK 0x000ffffffffff000LL -#define PG_HI_RSVD_MASK (PG_ADDRESS_MASK & ~PHYS_ADDR_MASK) #define PG_HI_USER_MASK 0x7ff0000000000000LL #define PG_PKRU_MASK (15ULL << PG_PKRU_BIT) #define PG_NX_MASK (1ULL << PG_NX_BIT) diff --git a/target/i386/tcg/excp_helper.c b/target/i386/tcg/excp_helper.c index b7d6259e4a..1e71e44510 100644 --- a/target/i386/tcg/excp_helper.c +++ b/target/i386/tcg/excp_helper.c @@ -142,8 +142,9 @@ void raise_exception_ra(CPUX86State *env, int exception= _index, uintptr_t retaddr static hwaddr get_hphys(CPUState *cs, hwaddr gphys, MMUAccessType access_t= ype, int *prot) { - CPUX86State *env =3D &X86_CPU(cs)->env; - uint64_t rsvd_mask =3D PG_HI_RSVD_MASK; + X86CPU *cpu =3D X86_CPU(cs); + CPUX86State *env =3D &cpu->env; + uint64_t rsvd_mask =3D PG_ADDRESS_MASK & ~MAKE_64BIT_MASK(0, cpu->phys= _bits); uint64_t ptep, pte; uint64_t exit_info_1 =3D 0; target_ulong pde_addr, pte_addr; @@ -358,7 +359,7 @@ static int handle_mmu_fault(CPUState *cs, vaddr addr, i= nt size, int error_code =3D 0; int is_dirty, prot, page_size, is_write, is_user; hwaddr paddr; - uint64_t rsvd_mask =3D PG_HI_RSVD_MASK; + uint64_t rsvd_mask =3D PG_ADDRESS_MASK & ~MAKE_64BIT_MASK(0, cpu->phys= _bits); uint32_t page_offset; target_ulong vaddr; uint32_t pkr; diff --git a/target/i386/tcg/helper-tcg.h b/target/i386/tcg/helper-tcg.h index c133c63555..ef60e2e04b 100644 --- a/target/i386/tcg/helper-tcg.h +++ b/target/i386/tcg/helper-tcg.h @@ -25,17 +25,13 @@ /* Maximum instruction code size */ #define TARGET_MAX_INSN_SIZE 16 =20 -/* - * XXX: This value should match the one returned by CPUID - * and in exec.c - */ -# if defined(TARGET_X86_64) +#if defined(TARGET_X86_64) # define TCG_PHYS_ADDR_BITS 40 -# else +#else # define TCG_PHYS_ADDR_BITS 36 -# endif +#endif =20 -#define PHYS_ADDR_MASK MAKE_64BIT_MASK(0, TCG_PHYS_ADDR_BITS) +QEMU_BUILD_BUG_ON(TCG_PHYS_ADDR_BITS > TARGET_PHYS_ADDR_SPACE_BITS); =20 /** * x86_cpu_do_interrupt: --=20 2.26.2 From nobody Tue Oct 7 10:00:50 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1616080037; cv=none; d=zohomail.com; s=zohoarc; b=C+NBeXAStYAwitIw9MVlT8nSxba5dkf30V3NhrGiaZUllEaix3uk8CmrVccZ3l78itYxE4iek3ojBgu4yKVMN5cTEJ7C12++csZM8p/nPLOE1o6KI5dg+JXMqT16woXmzvMugAcw+FJ5X29VdJ2EBI1GryYDwnSS1PMv9xL8k5E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1616080037; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=gF8shkL9d4p69aJ98TkRkFFQDtlC4V3fo6jb0Wtc7Xk=; b=l7TbQPye9JLJoZyupMo4Um90lvPTOQSM7h+hODAGEwYmmV7WCNN5Zp6+bAm3H7XPFJbuHV6htggvQe3+kl/cjM4LrgSl7+Vx7Sa+4XZ7QIUsEHX7nSBHtTsiG6ajrmDrRpKpmDWd0pTPSPOLL+GPxe7ST6si9alyih8ejTpoSZo= ARC-Authentication-Results: i=1; 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Thu, 18 Mar 2021 11:00:54 -0400 Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-234-ciz0YISWMOC19ODtD51cew-1; Thu, 18 Mar 2021 11:00:49 -0400 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id CCF3D8CD8CE for ; Thu, 18 Mar 2021 15:00:24 +0000 (UTC) Received: from virtlab701.virt.lab.eng.bos.redhat.com (virtlab701.virt.lab.eng.bos.redhat.com [10.19.152.228]) by smtp.corp.redhat.com (Postfix) with ESMTP id 8D3DC71928 for ; Thu, 18 Mar 2021 15:00:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1616079651; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=gF8shkL9d4p69aJ98TkRkFFQDtlC4V3fo6jb0Wtc7Xk=; b=VWRvE9L5zGjCKdzSPt8xr2Gbc7O3Y1V0CjeK5AqN9kleBFm8HmOA82fAKA72kHFa42RG7m bf7di2Q2UfNk9uFm+VdjvmRG9u8sK9FaaWQ7Kb4fz57fU8GmpyXBPnkM/ilsbpVa+IXSGU NC9lmwQuUmilrW75CLlUsuS53H85My8= X-MC-Unique: ciz0YISWMOC19ODtD51cew-1 From: Paolo Bonzini To: qemu-devel@nongnu.org Subject: [PATCH 2/3] target/i386: fail if toggling LA57 in 64-bit mode Date: Thu, 18 Mar 2021 11:00:21 -0400 Message-Id: <20210318150022.1824646-3-pbonzini@redhat.com> In-Reply-To: <20210318150022.1824646-1-pbonzini@redhat.com> References: <20210318150022.1824646-1-pbonzini@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=pbonzini@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.249, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @redhat.com) Content-Type: text/plain; charset="utf-8" This fixes kvm-unit-tests access.flat with -cpu qemu64,la57. Signed-off-by: Paolo Bonzini --- target/i386/tcg/misc_helper.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/i386/tcg/misc_helper.c b/target/i386/tcg/misc_helper.c index 90b87fdef0..a25428c36e 100644 --- a/target/i386/tcg/misc_helper.c +++ b/target/i386/tcg/misc_helper.c @@ -167,6 +167,10 @@ void helper_write_crN(CPUX86State *env, int reg, targe= t_ulong t0) cpu_x86_update_cr3(env, t0); break; case 4: + if (((t0 ^ env->cr[4]) & CR4_LA57_MASK) && + (env->hflags & HF_CS64_MASK)) { + raise_exception_ra(env, EXCP0D_GPF, GETPC()); + } cpu_x86_update_cr4(env, t0); break; case 8: --=20 2.26.2 From nobody Tue Oct 7 10:00:50 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1616080020; cv=none; d=zohomail.com; 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Thu, 18 Mar 2021 15:00:25 +0000 (UTC) Received: from virtlab701.virt.lab.eng.bos.redhat.com (virtlab701.virt.lab.eng.bos.redhat.com [10.19.152.228]) by smtp.corp.redhat.com (Postfix) with ESMTP id DE86667879 for ; Thu, 18 Mar 2021 15:00:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1616079645; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=wlKHFHC0Q0JoUnvY6Xg/B0UUnONgzKq6R19/MfSXZJg=; b=blqtNE7CFaL+x5mFH3Yuze6I7+GbJxPdoIW8vhCRlsdOAk6YQUcsDm0Ma/BHY/KxHKzS8f DWKxgKix6NoVBe5tbvtk/HwFjUbWt2o9SV8Jn4+emQcqMzEazp/lhHNZC1FJGwq2JrrYTJ YEqBOhBA8NBqepbWsEQKX/2Q0pQ8Jhw= X-MC-Unique: v16nf2eiNC-I8tB4kvN7iA-1 From: Paolo Bonzini To: qemu-devel@nongnu.org Subject: [PATCH 3/3] target/i386: svm: do not discard high 32 bits of EXITINFO1 Date: Thu, 18 Mar 2021 11:00:22 -0400 Message-Id: <20210318150022.1824646-4-pbonzini@redhat.com> In-Reply-To: <20210318150022.1824646-1-pbonzini@redhat.com> References: <20210318150022.1824646-1-pbonzini@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 Authentication-Results: relay.mimecast.com; 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charset="utf-8" env->error_code is only 32-bits wide, so the high 32 bits of EXITINFO1 are being lost. However, even though saving guest state and restoring host state must be delayed to do_vmexit, because they might take tb_lock, it is always possible to write to the VMCB. So do this for the exit code and EXITINFO1, just like it is already being done for EXITINFO2. Signed-off-by: Paolo Bonzini --- target/i386/tcg/helper-tcg.h | 2 +- target/i386/tcg/seg_helper.c | 4 ++-- target/i386/tcg/svm_helper.c | 15 +++++++-------- 3 files changed, 10 insertions(+), 11 deletions(-) diff --git a/target/i386/tcg/helper-tcg.h b/target/i386/tcg/helper-tcg.h index ef60e2e04b..bcdfca06f6 100644 --- a/target/i386/tcg/helper-tcg.h +++ b/target/i386/tcg/helper-tcg.h @@ -80,7 +80,7 @@ void cpu_load_eflags(CPUX86State *env, int eflags, int up= date_mask); /* svm_helper.c */ void QEMU_NORETURN cpu_vmexit(CPUX86State *nenv, uint32_t exit_code, uint64_t exit_info_1, uintptr_t retaddr); -void do_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1); +void do_vmexit(CPUX86State *env); =20 /* seg_helper.c */ void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw); diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c index 180d47f0e9..d180a381d1 100644 --- a/target/i386/tcg/seg_helper.c +++ b/target/i386/tcg/seg_helper.c @@ -1305,9 +1305,9 @@ void x86_cpu_do_interrupt(CPUState *cs) /* successfully delivered */ env->old_exception =3D -1; #else - if (cs->exception_index >=3D EXCP_VMEXIT) { + if (cs->exception_index =3D=3D EXCP_VMEXIT) { assert(env->old_exception =3D=3D -1); - do_vmexit(env, cs->exception_index - EXCP_VMEXIT, env->error_code); + do_vmexit(env); } else { do_interrupt_all(cpu, cs->exception_index, env->exception_is_int, diff --git a/target/i386/tcg/svm_helper.c b/target/i386/tcg/svm_helper.c index 097bb9b83d..0145afceae 100644 --- a/target/i386/tcg/svm_helper.c +++ b/target/i386/tcg/svm_helper.c @@ -621,15 +621,19 @@ void cpu_vmexit(CPUX86State *env, uint32_t exit_code,= uint64_t exit_info_1, control.exit_info_2)), env->eip); =20 - cs->exception_index =3D EXCP_VMEXIT + exit_code; - env->error_code =3D exit_info_1; + cs->exception_index =3D EXCP_VMEXIT; + x86_stq_phys(cs, env->vm_vmcb + offsetof(struct vmcb, control.exit_cod= e), + exit_code); + + x86_stq_phys(cs, env->vm_vmcb + offsetof(struct vmcb, + control.exit_info_1), exit_in= fo_1), =20 /* remove any pending exception */ env->old_exception =3D -1; cpu_loop_exit(cs); } =20 -void do_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1) +void do_vmexit(CPUX86State *env) { CPUState *cs =3D env_cpu(env); uint32_t int_ctl; @@ -762,11 +766,6 @@ void do_vmexit(CPUX86State *env, uint32_t exit_code, u= int64_t exit_info_1) env->vm_hsave + offsetof(struct vmcb, save.dr7)); =20 /* other setups */ - x86_stq_phys(cs, env->vm_vmcb + offsetof(struct vmcb, control.exit_cod= e), - exit_code); - x86_stq_phys(cs, env->vm_vmcb + offsetof(struct vmcb, control.exit_inf= o_1), - exit_info_1); - x86_stl_phys(cs, env->vm_vmcb + offsetof(struct vmcb, control.exit_int_info), x86_ldl_phys(cs, env->vm_vmcb + offsetof(struct vmcb, --=20 2.26.2