From nobody Tue Feb 10 19:08:58 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1616024308; cv=none; d=zohomail.com; s=zohoarc; b=aF7zl+1O6qrOoqKVADOTvHDlIW8U3EJWdhPnBK+tZSYFxoCNtTqEHvSerZAFhCw4aE2j1zKLP2oH0yGcXHPAr2fmi0aYY5G3TF4SvyJSBbLrN56Xf+OBjgCAqsfU36+yJ9IRX57JyOOq7xnMHOhIQzFOG+UUErSE1713ombMlL4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1616024308; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=isLK5SgCVgmU05FBFa6ZughRqyflJB/ni8lS60DTSH8=; b=P4rHbONWgkrU3Kl+ri7kmGqDqw4+TnoJKHgHEIW0/QsoQYHuDBhLn738nAYTT6ANGxtFi4SlHXxR4CAdxLugeRYqXVbIgPIeUeb4QdCrVWuDncC+yBRjnPFX9Nm8E+wnbbPmEk7n2tG1vFTczQsBJL0DS2Yc7S1N50+n94Xq3fg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1616024308722705.3261112379798; Wed, 17 Mar 2021 16:38:28 -0700 (PDT) Received: from localhost ([::1]:45592 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lMfkA-0000Vi-PG for importer@patchew.org; Wed, 17 Mar 2021 19:38:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48592) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lMff7-0004L6-KN for qemu-devel@nongnu.org; Wed, 17 Mar 2021 19:33:13 -0400 Received: from mail-io1-xd2e.google.com ([2607:f8b0:4864:20::d2e]:40601) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lMff4-0001tx-Ne for qemu-devel@nongnu.org; Wed, 17 Mar 2021 19:33:13 -0400 Received: by mail-io1-xd2e.google.com with SMTP id n21so378601ioa.7 for ; Wed, 17 Mar 2021 16:33:10 -0700 (PDT) Received: from cube.int.bluestop.org (c-174-52-16-57.hsd1.ut.comcast.net. [174.52.16.57]) by smtp.gmail.com with ESMTPSA id k12sm235183ios.2.2021.03.17.16.33.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Mar 2021 16:33:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=isLK5SgCVgmU05FBFa6ZughRqyflJB/ni8lS60DTSH8=; b=sRUd4R/w+jHBbh5/u0kXMXm3q0KS+NxS3womL6TX1qnogInbtZJiRuk+VXSKNvaSGN Unvp/vWq3V7GEDJ1swHvJCJDqz9vzvInXoa+JHPjCVWtBJN07uQNro8TBAZdc5na53r4 TNyQrBqXkbpNHLLfZMfHIHNZWImAsRtS6r4HzOsflUOyKRJFEfTOv7O0zVt6BDPfw3mv bE9+wejfuU954Ik2lbVUOl2uqhwog2kpMSs3u2ZXv85Q1oVbRLs9aFnBejHSaRP/NYzG uLd3nR8DjBM8YegQ0IWUcdEVZ5DuG/3oLKc1QQRFODm/Oh+218kRUA40SoI+brecAJ47 ffLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=isLK5SgCVgmU05FBFa6ZughRqyflJB/ni8lS60DTSH8=; b=mNBj6uGnWZTcs+3ecUxPbXN6OfFwjewoijzYTDlY3gux9z8LAcfXwvi9thm56ROpLG NXDA0Vr01N1uWclaQ1RaOhIjHOCpzpN7Hzqi5QDqIQrilkspwD3tLkOJSwEqTJ5X7KO9 hLQgIOTW1r5bpfwnTp77zheRndLrOaWCmxQcXgg+IGTgBpbrqf9WGfXd2/sT4u7VdsYl oQu3IisjcVpSMvAEeb2oEKVRN65CiHJIPpXFJ42x+dm/6TCU9dzjvVeazw29vdHQKPlx Y0jiMOI/ve5eNdIZzxl7Z0MJ+WspVFJVRWj6iZaT+aIsEgwJhbm7NjVktOe+j0QOCqPF qOMw== X-Gm-Message-State: AOAM5316T5EJ1r8ov3jStDm4x2A6+zxssH2pW7qY32FvkV4ycK6EwOU1 +DkbBUPpa72T0M9jiFfxI2/H7Jtrpdhl7w== X-Google-Smtp-Source: ABdhPJzpvck1BOYcOuQG3xT53Ylh37kYDfRHJvkr0UEQemwgVdomVHs6vOZXWOUK0was5jGDL6PD/Q== X-Received: by 2002:a02:714f:: with SMTP id n15mr4856603jaf.6.1616023989858; Wed, 17 Mar 2021 16:33:09 -0700 (PDT) From: Rebecca Cran To: Peter Maydell , Richard Henderson , qemu-arm@nongnu.org Subject: [PATCH v5 3/4] target/arm: Add support for FEAT_TLBIOS Date: Wed, 17 Mar 2021 17:33:00 -0600 Message-Id: <20210317233301.4130-4-rebecca@nuviainc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210317233301.4130-1-rebecca@nuviainc.com> References: <20210317233301.4130-1-rebecca@nuviainc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::d2e; envelope-from=rebecca@nuviainc.com; helo=mail-io1-xd2e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rebecca Cran , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @nuviainc-com.20150623.gappssmtp.com) Content-Type: text/plain; charset="utf-8" ARMv8.4 adds the mandatory FEAT_TLBIOS. It provides TLBI maintenance instructions that extend to the Outer Shareable domain. Signed-off-by: Rebecca Cran --- target/arm/cpu.h | 5 ++ target/arm/helper.c | 75 ++++++++++++++++++++ 2 files changed, 80 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 32b78a4ef587..272fde83ca4e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -4043,6 +4043,11 @@ static inline bool isar_feature_aa64_tlbirange(const= ARMISARegisters *id) return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) =3D=3D 2; } =20 +static inline bool isar_feature_aa64_tlbios(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) !=3D 0; +} + static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) !=3D 0; diff --git a/target/arm/helper.c b/target/arm/helper.c index ce913deff490..5b10f179b761 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7211,6 +7211,78 @@ static const ARMCPRegInfo tlbirange_reginfo[] =3D { REGINFO_SENTINEL }; =20 +static const ARMCPRegInfo tlbios_reginfo[] =3D { + { .name =3D "TLBI_VMALLE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 0, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_vmalle1is_write }, + { .name =3D "TLBI_ASIDE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 2, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_vmalle1is_write }, + { .name =3D "TLBI_RVAE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 5, .opc2 =3D 1, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1is_write }, + { .name =3D "TLBI_RVAAE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 5, .opc2 =3D 3, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1is_write }, + { .name =3D "TLBI_RVALE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 5, .opc2 =3D 5, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1is_write }, + { .name =3D "TLBI_RVAALE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 5, .opc2 =3D 7, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1is_write }, + { .name =3D "TLBI_ALLE2OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 0, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_alle2is_write }, + { .name =3D "TLBI_ALLE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 4, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_alle1is_write }, + { .name =3D "TLBI_VMALLS12E1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 6, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_alle1is_write }, + { .name =3D "TLBI_IPAS2E1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 0, + .access =3D PL2_W, .type =3D ARM_CP_NOP }, + { .name =3D "TLBI_RIPAS2E1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 3, + .access =3D PL2_W, .type =3D ARM_CP_NOP }, + { .name =3D "TLBI_IPAS2LE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 4, + .access =3D PL2_W, .type =3D ARM_CP_NOP }, + { .name =3D "TLBI_RIPAS2LE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 7, + .access =3D PL2_W, .type =3D ARM_CP_NOP }, + { .name =3D "TLBI_RVAE2OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 5, .opc2 =3D 1, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae2is_write }, + { .name =3D "TLBI_RVALE2OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 5, .opc2 =3D 5, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae2is_write }, + { .name =3D "TLBI_ALLE3OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 1, .opc2 =3D 0, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_alle3is_write }, + { .name =3D "TLBI_RVAE3OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 5, .opc2 =3D 1, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae3is_write }, + { .name =3D "TLBI_RVALE3OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 5, .opc2 =3D 5, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae3is_write }, + REGINFO_SENTINEL +}; + static uint64_t rndr_readfn(CPUARMState *env, const ARMCPRegInfo *ri) { Error *err =3D NULL; @@ -8583,6 +8655,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_tlbirange, cpu)) { define_arm_cp_regs(cpu, tlbirange_reginfo); } + if (cpu_isar_feature(aa64_tlbios, cpu)) { + define_arm_cp_regs(cpu, tlbios_reginfo); + } #ifndef CONFIG_USER_ONLY /* Data Cache clean instructions up to PoP */ if (cpu_isar_feature(aa64_dcpop, cpu)) { --=20 2.26.2