From nobody Wed Nov 19 14:04:59 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1616007581; cv=none; d=zohomail.com; s=zohoarc; b=eMWCKHc+31uw251SjqbZi6IriJxZjAE4jNTco1xp1viDQR1AqaPt1VJcChW2DWCXY6mK4NwvyDnSJhjREInwHdYwnFU0MOoeVsTBnUYHz/5E+H4OhgxECTov55fy9NlGKn4+APoKpX0RCTr6e5UF9IFL8fxzKfBBAJ/iF8XGnpA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1616007581; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=yv/cV1oox0xu7K+B1Q54NWTLDSn6sh+12YlcgNKRM40=; b=AsWIos9rIvwOaFyzb+PFhuozH9+O7b1Idijs/3gkxANIkw25vfR0iJ3l7+QTe3xrel8R8RyIB69h326nOjpJXZVfRs9dRXHiiix40q7r7Z0LWrEH+j2is8LCKBbhUzdOFzwj0wYdJKi2zD+SYuxIAfIdCfrylnDZAanTShSmdlM= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1616007581304926.889469877421; Wed, 17 Mar 2021 11:59:41 -0700 (PDT) Received: from localhost ([::1]:42114 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lMbON-0001D5-Mw for importer@patchew.org; Wed, 17 Mar 2021 14:59:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39616) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lMawl-0004H3-Ci for qemu-devel@nongnu.org; Wed, 17 Mar 2021 14:31:08 -0400 Received: from mx2.suse.de ([195.135.220.15]:48488) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lMawX-0007mm-Jd for qemu-devel@nongnu.org; Wed, 17 Mar 2021 14:31:07 -0400 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 218FEAE91; Wed, 17 Mar 2021 18:30:27 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [RFC v9 24/50] target/arm: refactor exception and cpu code Date: Wed, 17 Mar 2021 19:29:47 +0100 Message-Id: <20210317183013.25772-25-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210317183013.25772-1-cfontana@suse.de> References: <20210317183013.25772-1-cfontana@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -36 X-Spam_score: -3.7 X-Spam_bar: --- X-Spam_report: (-3.7 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URI_NOVOWEL=0.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Roman Bolshakov , Claudio Fontana , Eduardo Habkost , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" move exception code out of tcg/ as we need part of it for KVM too. put the exception code into separate cpu modules as appropriate, including: cpu-sysemu.c tcg/tcg-cpu.c tcg/sysemu/tcg-cpu.c to avoid naming confusion with the existing cpu_tcg.c, containg cpu models definitions for 32bit TCG-only cpus, rename this file as tcg/tcg-cpu-models.c The 64bit cpu models (a53/a57/a72/max) for both TCG and KVM remain in cpu64.c . Signed-off-by: Claudio Fontana --- target/arm/cpu.h | 1 - target/arm/internals.h | 5 - target/arm/tcg/tcg-cpu.h | 37 + target/arm/cpu-sysemu.c | 669 ++++++++++++++++ target/arm/cpu.c | 209 +---- target/arm/tcg/helper.c | 724 +----------------- target/arm/tcg/sysemu/tcg-cpu.c | 73 ++ .../arm/{cpu_tcg.c =3D> tcg/tcg-cpu-models.c} | 12 +- target/arm/tcg/tcg-cpu.c | 229 ++++++ target/arm/meson.build | 5 - target/arm/tcg/meson.build | 4 +- target/arm/tcg/sysemu/meson.build | 1 + 12 files changed, 1018 insertions(+), 951 deletions(-) create mode 100644 target/arm/tcg/tcg-cpu.h create mode 100644 target/arm/tcg/sysemu/tcg-cpu.c rename target/arm/{cpu_tcg.c =3D> tcg/tcg-cpu-models.c} (99%) create mode 100644 target/arm/tcg/tcg-cpu.c diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ea1e63f7f6..3911b49399 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1024,7 +1024,6 @@ extern const VMStateDescription vmstate_arm_cpu; =20 void arm_cpu_do_interrupt(CPUState *cpu); void arm_v7m_cpu_do_interrupt(CPUState *cpu); -bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req); =20 int arm32_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int arm32_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); diff --git a/target/arm/internals.h b/target/arm/internals.h index e137bb0ac0..811e029f83 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -172,11 +172,6 @@ static inline int r14_bank_number(int mode) void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu); void arm_translate_init(void); =20 -#ifdef CONFIG_TCG -void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb); -#endif /* CONFIG_TCG */ - - enum arm_fprounding { FPROUNDING_TIEEVEN, FPROUNDING_POSINF, diff --git a/target/arm/tcg/tcg-cpu.h b/target/arm/tcg/tcg-cpu.h new file mode 100644 index 0000000000..d93c6a6749 --- /dev/null +++ b/target/arm/tcg/tcg-cpu.h @@ -0,0 +1,37 @@ +/* + * QEMU ARM CPU + * + * Copyright (c) 2012 SUSE LINUX Products GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see + * + */ +#ifndef ARM_TCG_CPU_H +#define ARM_TCG_CPU_H + +#include "cpu.h" +#include "hw/core/tcg-cpu-ops.h" + +void arm_cpu_synchronize_from_tb(CPUState *cs, + const TranslationBlock *tb); + +extern struct TCGCPUOps arm_tcg_ops; + +#ifndef CONFIG_USER_ONLY +/* Do semihosting call and set the appropriate return value. */ +void tcg_handle_semihosting(CPUState *cs); + +#endif /* !CONFIG_USER_ONLY */ + +#endif /* ARM_TCG_CPU_H */ diff --git a/target/arm/cpu-sysemu.c b/target/arm/cpu-sysemu.c index 5265de1c87..126263dbf4 100644 --- a/target/arm/cpu-sysemu.c +++ b/target/arm/cpu-sysemu.c @@ -19,10 +19,17 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/main-loop.h" #include "cpu.h" #include "internals.h" #include "sysemu/hw_accel.h" #include "kvm_arm.h" +#include "sysemu/tcg.h" + +#ifdef CONFIG_TCG +#include "tcg/tcg-cpu.h" +#endif /* CONFIG_TCG */ =20 void arm_cpu_set_irq(void *opaque, int irq, int level) { @@ -410,3 +417,665 @@ int sve_exception_el(CPUARMState *env, int el) } return 0; } + +static void take_aarch32_exception(CPUARMState *env, int new_mode, + uint32_t mask, uint32_t offset, + uint32_t newpc) +{ + int new_el; + + /* Change the CPU state so as to actually take the exception. */ + switch_mode(env, new_mode); + + /* + * For exceptions taken to AArch32 we must clear the SS bit in both + * PSTATE and in the old-state value we save to SPSR_, so zero i= t now. + */ + env->pstate &=3D ~PSTATE_SS; + env->spsr =3D cpsr_read(env); + /* Clear IT bits. */ + env->condexec_bits =3D 0; + /* Switch to the new mode, and to the correct instruction set. */ + env->uncached_cpsr =3D (env->uncached_cpsr & ~CPSR_M) | new_mode; + + /* This must be after mode switching. */ + new_el =3D arm_current_el(env); + + /* Set new mode endianness */ + env->uncached_cpsr &=3D ~CPSR_E; + if (env->cp15.sctlr_el[new_el] & SCTLR_EE) { + env->uncached_cpsr |=3D CPSR_E; + } + /* J and IL must always be cleared for exception entry */ + env->uncached_cpsr &=3D ~(CPSR_IL | CPSR_J); + env->daif |=3D mask; + + if (new_mode =3D=3D ARM_CPU_MODE_HYP) { + env->thumb =3D (env->cp15.sctlr_el[2] & SCTLR_TE) !=3D 0; + env->elr_el[2] =3D env->regs[15]; + } else { + /* CPSR.PAN is normally preserved preserved unless... */ + if (cpu_isar_feature(aa32_pan, env_archcpu(env))) { + switch (new_el) { + case 3: + if (!arm_is_secure_below_el3(env)) { + /* ... the target is EL3, from non-secure state. */ + env->uncached_cpsr &=3D ~CPSR_PAN; + break; + } + /* ... the target is EL3, from secure state ... */ + /* fall through */ + case 1: + /* ... the target is EL1 and SCTLR.SPAN is 0. */ + if (!(env->cp15.sctlr_el[new_el] & SCTLR_SPAN)) { + env->uncached_cpsr |=3D CPSR_PAN; + } + break; + } + } + /* + * this is a lie, as there was no c1_sys on V4T/V5, but who cares + * and we should just guard the thumb mode on V4 + */ + if (arm_feature(env, ARM_FEATURE_V4T)) { + env->thumb =3D + (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_TE) !=3D 0; + } + env->regs[14] =3D env->regs[15] + offset; + } + env->regs[15] =3D newpc; +#ifdef CONFIG_TCG + arm_rebuild_hflags(env); +#endif /* CONFIG_TCG */ +} + +static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs) +{ + /* + * Handle exception entry to Hyp mode; this is sufficiently + * different to entry to other AArch32 modes that we handle it + * separately here. + * + * The vector table entry used is always the 0x14 Hyp mode entry point, + * unless this is an UNDEF/HVC/abort taken from Hyp to Hyp. + * The offset applied to the preferred return address is always zero + * (see DDI0487C.a section G1.12.3). + * PSTATE A/I/F masks are set based only on the SCR.EA/IRQ/FIQ values. + */ + uint32_t addr, mask; + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + + switch (cs->exception_index) { + case EXCP_UDEF: + addr =3D 0x04; + break; + case EXCP_SWI: + addr =3D 0x14; + break; + case EXCP_BKPT: + /* Fall through to prefetch abort. */ + case EXCP_PREFETCH_ABORT: + env->cp15.ifar_s =3D env->exception.vaddress; + qemu_log_mask(CPU_LOG_INT, "...with HIFAR 0x%x\n", + (uint32_t)env->exception.vaddress); + addr =3D 0x0c; + break; + case EXCP_DATA_ABORT: + env->cp15.dfar_s =3D env->exception.vaddress; + qemu_log_mask(CPU_LOG_INT, "...with HDFAR 0x%x\n", + (uint32_t)env->exception.vaddress); + addr =3D 0x10; + break; + case EXCP_IRQ: + addr =3D 0x18; + break; + case EXCP_FIQ: + addr =3D 0x1c; + break; + case EXCP_HVC: + addr =3D 0x08; + break; + case EXCP_HYP_TRAP: + addr =3D 0x14; + break; + default: + cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); + } + + if (cs->exception_index !=3D EXCP_IRQ && cs->exception_index !=3D EXCP= _FIQ) { + if (!arm_feature(env, ARM_FEATURE_V8)) { + /* + * QEMU syndrome values are v8-style. v7 has the IL bit + * UNK/SBZP for "field not valid" cases, where v8 uses RES1. + * If this is a v7 CPU, squash the IL bit in those cases. + */ + if (cs->exception_index =3D=3D EXCP_PREFETCH_ABORT || + (cs->exception_index =3D=3D EXCP_DATA_ABORT && + !(env->exception.syndrome & ARM_EL_ISV)) || + syn_get_ec(env->exception.syndrome) =3D=3D EC_UNCATEGORIZE= D) { + env->exception.syndrome &=3D ~ARM_EL_IL; + } + } + env->cp15.esr_el[2] =3D env->exception.syndrome; + } + + if (arm_current_el(env) !=3D 2 && addr < 0x14) { + addr =3D 0x14; + } + + mask =3D 0; + if (!(env->cp15.scr_el3 & SCR_EA)) { + mask |=3D CPSR_A; + } + if (!(env->cp15.scr_el3 & SCR_IRQ)) { + mask |=3D CPSR_I; + } + if (!(env->cp15.scr_el3 & SCR_FIQ)) { + mask |=3D CPSR_F; + } + + addr +=3D env->cp15.hvbar; + + take_aarch32_exception(env, ARM_CPU_MODE_HYP, mask, 0, addr); +} + +static void arm_cpu_do_interrupt_aarch32(CPUState *cs) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + uint32_t addr; + uint32_t mask; + int new_mode; + uint32_t offset; + uint32_t moe; + + /* If this is a debug exception we must update the DBGDSCR.MOE bits */ + switch (syn_get_ec(env->exception.syndrome)) { + case EC_BREAKPOINT: + case EC_BREAKPOINT_SAME_EL: + moe =3D 1; + break; + case EC_WATCHPOINT: + case EC_WATCHPOINT_SAME_EL: + moe =3D 10; + break; + case EC_AA32_BKPT: + moe =3D 3; + break; + case EC_VECTORCATCH: + moe =3D 5; + break; + default: + moe =3D 0; + break; + } + + if (moe) { + env->cp15.mdscr_el1 =3D deposit64(env->cp15.mdscr_el1, 2, 4, moe); + } + + if (env->exception.target_el =3D=3D 2) { + arm_cpu_do_interrupt_aarch32_hyp(cs); + return; + } + + switch (cs->exception_index) { + case EXCP_UDEF: + new_mode =3D ARM_CPU_MODE_UND; + addr =3D 0x04; + mask =3D CPSR_I; + if (env->thumb) + offset =3D 2; + else + offset =3D 4; + break; + case EXCP_SWI: + new_mode =3D ARM_CPU_MODE_SVC; + addr =3D 0x08; + mask =3D CPSR_I; + /* The PC already points to the next instruction. */ + offset =3D 0; + break; + case EXCP_BKPT: + /* Fall through to prefetch abort. */ + case EXCP_PREFETCH_ABORT: + A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr); + A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress); + qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n", + env->exception.fsr, (uint32_t)env->exception.vaddres= s); + new_mode =3D ARM_CPU_MODE_ABT; + addr =3D 0x0c; + mask =3D CPSR_A | CPSR_I; + offset =3D 4; + break; + case EXCP_DATA_ABORT: + A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); + A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress); + qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n", + env->exception.fsr, + (uint32_t)env->exception.vaddress); + new_mode =3D ARM_CPU_MODE_ABT; + addr =3D 0x10; + mask =3D CPSR_A | CPSR_I; + offset =3D 8; + break; + case EXCP_IRQ: + new_mode =3D ARM_CPU_MODE_IRQ; + addr =3D 0x18; + /* Disable IRQ and imprecise data aborts. */ + mask =3D CPSR_A | CPSR_I; + offset =3D 4; + if (env->cp15.scr_el3 & SCR_IRQ) { + /* IRQ routed to monitor mode */ + new_mode =3D ARM_CPU_MODE_MON; + mask |=3D CPSR_F; + } + break; + case EXCP_FIQ: + new_mode =3D ARM_CPU_MODE_FIQ; + addr =3D 0x1c; + /* Disable FIQ, IRQ and imprecise data aborts. */ + mask =3D CPSR_A | CPSR_I | CPSR_F; + if (env->cp15.scr_el3 & SCR_FIQ) { + /* FIQ routed to monitor mode */ + new_mode =3D ARM_CPU_MODE_MON; + } + offset =3D 4; + break; + case EXCP_VIRQ: + new_mode =3D ARM_CPU_MODE_IRQ; + addr =3D 0x18; + /* Disable IRQ and imprecise data aborts. */ + mask =3D CPSR_A | CPSR_I; + offset =3D 4; + break; + case EXCP_VFIQ: + new_mode =3D ARM_CPU_MODE_FIQ; + addr =3D 0x1c; + /* Disable FIQ, IRQ and imprecise data aborts. */ + mask =3D CPSR_A | CPSR_I | CPSR_F; + offset =3D 4; + break; + case EXCP_SMC: + new_mode =3D ARM_CPU_MODE_MON; + addr =3D 0x08; + mask =3D CPSR_A | CPSR_I | CPSR_F; + offset =3D 0; + break; + default: + cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); + return; /* Never happens. Keep compiler happy. */ + } + + if (new_mode =3D=3D ARM_CPU_MODE_MON) { + addr +=3D env->cp15.mvbar; + } else if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { + /* High vectors. When enabled, base address cannot be remapped. */ + addr +=3D 0xffff0000; + } else { + /* ARM v7 architectures provide a vector base address register to = remap + * the interrupt vector table. + * This register is only followed in non-monitor mode, and is bank= ed. + * Note: only bits 31:5 are valid. + */ + addr +=3D A32_BANKED_CURRENT_REG_GET(env, vbar); + } + + if ((env->uncached_cpsr & CPSR_M) =3D=3D ARM_CPU_MODE_MON) { + env->cp15.scr_el3 &=3D ~SCR_NS; + } + + take_aarch32_exception(env, new_mode, mask, offset, addr); +} + +static int aarch64_regnum(CPUARMState *env, int aarch32_reg) +{ + /* + * Return the register number of the AArch64 view of the AArch32 + * register @aarch32_reg. The CPUARMState CPSR is assumed to still + * be that of the AArch32 mode the exception came from. + */ + int mode =3D env->uncached_cpsr & CPSR_M; + + switch (aarch32_reg) { + case 0 ... 7: + return aarch32_reg; + case 8 ... 12: + return mode =3D=3D ARM_CPU_MODE_FIQ ? aarch32_reg + 16 : aarch32_r= eg; + case 13: + switch (mode) { + case ARM_CPU_MODE_USR: + case ARM_CPU_MODE_SYS: + return 13; + case ARM_CPU_MODE_HYP: + return 15; + case ARM_CPU_MODE_IRQ: + return 17; + case ARM_CPU_MODE_SVC: + return 19; + case ARM_CPU_MODE_ABT: + return 21; + case ARM_CPU_MODE_UND: + return 23; + case ARM_CPU_MODE_FIQ: + return 29; + default: + g_assert_not_reached(); + } + case 14: + switch (mode) { + case ARM_CPU_MODE_USR: + case ARM_CPU_MODE_SYS: + case ARM_CPU_MODE_HYP: + return 14; + case ARM_CPU_MODE_IRQ: + return 16; + case ARM_CPU_MODE_SVC: + return 18; + case ARM_CPU_MODE_ABT: + return 20; + case ARM_CPU_MODE_UND: + return 22; + case ARM_CPU_MODE_FIQ: + return 30; + default: + g_assert_not_reached(); + } + case 15: + return 31; + default: + g_assert_not_reached(); + } +} + +static uint32_t cpsr_read_for_spsr_elx(CPUARMState *env) +{ + uint32_t ret =3D cpsr_read(env); + + /* Move DIT to the correct location for SPSR_ELx */ + if (ret & CPSR_DIT) { + ret &=3D ~CPSR_DIT; + ret |=3D PSTATE_DIT; + } + /* Merge PSTATE.SS into SPSR_ELx */ + ret |=3D env->pstate & PSTATE_SS; + + return ret; +} + +/* Handle exception entry to a target EL which is using AArch64 */ +static void arm_cpu_do_interrupt_aarch64(CPUState *cs) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + unsigned int new_el =3D env->exception.target_el; + target_ulong addr =3D env->cp15.vbar_el[new_el]; + unsigned int new_mode =3D aarch64_pstate_mode(new_el, true); + unsigned int old_mode; + unsigned int cur_el =3D arm_current_el(env); + int rt; + + /* + * Note that new_el can never be 0. If cur_el is 0, then + * el0_a64 is is_a64(), else el0_a64 is ignored. + */ + aarch64_sve_change_el(env, cur_el, new_el, is_a64(env)); + + if (cur_el < new_el) { + /* Entry vector offset depends on whether the implemented EL + * immediately lower than the target level is using AArch32 or AAr= ch64 + */ + bool is_aa64; + uint64_t hcr; + + switch (new_el) { + case 3: + is_aa64 =3D (env->cp15.scr_el3 & SCR_RW) !=3D 0; + break; + case 2: + hcr =3D arm_hcr_el2_eff(env); + if ((hcr & (HCR_E2H | HCR_TGE)) !=3D (HCR_E2H | HCR_TGE)) { + is_aa64 =3D (hcr & HCR_RW) !=3D 0; + break; + } + /* fall through */ + case 1: + is_aa64 =3D is_a64(env); + break; + default: + g_assert_not_reached(); + } + + if (is_aa64) { + addr +=3D 0x400; + } else { + addr +=3D 0x600; + } + } else if (pstate_read(env) & PSTATE_SP) { + addr +=3D 0x200; + } + + switch (cs->exception_index) { + case EXCP_PREFETCH_ABORT: + case EXCP_DATA_ABORT: + env->cp15.far_el[new_el] =3D env->exception.vaddress; + qemu_log_mask(CPU_LOG_INT, "...with FAR 0x%" PRIx64 "\n", + env->cp15.far_el[new_el]); + /* fall through */ + case EXCP_BKPT: + case EXCP_UDEF: + case EXCP_SWI: + case EXCP_HVC: + case EXCP_HYP_TRAP: + case EXCP_SMC: + switch (syn_get_ec(env->exception.syndrome)) { + case EC_ADVSIMDFPACCESSTRAP: + /* + * QEMU internal FP/SIMD syndromes from AArch32 include the + * TA and coproc fields which are only exposed if the exception + * is taken to AArch32 Hyp mode. Mask them out to get a valid + * AArch64 format syndrome. + */ + env->exception.syndrome &=3D ~MAKE_64BIT_MASK(0, 20); + break; + case EC_CP14RTTRAP: + case EC_CP15RTTRAP: + case EC_CP14DTTRAP: + /* + * For a trap on AArch32 MRC/MCR/LDC/STC the Rt field is curre= ntly + * the raw register field from the insn; when taking this to + * AArch64 we must convert it to the AArch64 view of the regis= ter + * number. Notice that we read a 4-bit AArch32 register number= and + * write back a 5-bit AArch64 one. + */ + rt =3D extract32(env->exception.syndrome, 5, 4); + rt =3D aarch64_regnum(env, rt); + env->exception.syndrome =3D deposit32(env->exception.syndrome, + 5, 5, rt); + break; + case EC_CP15RRTTRAP: + case EC_CP14RRTTRAP: + /* Similarly for MRRC/MCRR traps for Rt and Rt2 fields */ + rt =3D extract32(env->exception.syndrome, 5, 4); + rt =3D aarch64_regnum(env, rt); + env->exception.syndrome =3D deposit32(env->exception.syndrome, + 5, 5, rt); + rt =3D extract32(env->exception.syndrome, 10, 4); + rt =3D aarch64_regnum(env, rt); + env->exception.syndrome =3D deposit32(env->exception.syndrome, + 10, 5, rt); + break; + } + env->cp15.esr_el[new_el] =3D env->exception.syndrome; + break; + case EXCP_IRQ: + case EXCP_VIRQ: + addr +=3D 0x80; + break; + case EXCP_FIQ: + case EXCP_VFIQ: + addr +=3D 0x100; + break; + default: + cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); + } + + if (is_a64(env)) { + old_mode =3D pstate_read(env); + aarch64_save_sp(env, arm_current_el(env)); + env->elr_el[new_el] =3D env->pc; + } else { + old_mode =3D cpsr_read_for_spsr_elx(env); + env->elr_el[new_el] =3D env->regs[15]; + + aarch64_sync_32_to_64(env); + + env->condexec_bits =3D 0; + } + env->banked_spsr[aarch64_banked_spsr_index(new_el)] =3D old_mode; + + qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n", + env->elr_el[new_el]); + + if (cpu_isar_feature(aa64_pan, cpu)) { + /* The value of PSTATE.PAN is normally preserved, except when ... = */ + new_mode |=3D old_mode & PSTATE_PAN; + switch (new_el) { + case 2: + /* ... the target is EL2 with HCR_EL2.{E2H,TGE} =3D=3D '11' ..= . */ + if ((arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) + !=3D (HCR_E2H | HCR_TGE)) { + break; + } + /* fall through */ + case 1: + /* ... the target is EL1 ... */ + /* ... and SCTLR_ELx.SPAN =3D=3D 0, then set to 1. */ + if ((env->cp15.sctlr_el[new_el] & SCTLR_SPAN) =3D=3D 0) { + new_mode |=3D PSTATE_PAN; + } + break; + } + } + if (cpu_isar_feature(aa64_mte, cpu)) { + new_mode |=3D PSTATE_TCO; + } + + pstate_write(env, PSTATE_DAIF | new_mode); + env->aarch64 =3D 1; + aarch64_restore_sp(env, new_el); +#ifdef CONFIG_TCG + arm_rebuild_hflags(env); +#endif /* CONFIG_TCG */ + + env->pc =3D addr; + + qemu_log_mask(CPU_LOG_INT, "...to EL%d PC 0x%" PRIx64 " PSTATE 0x%x\n", + new_el, env->pc, pstate_read(env)); +} + +void arm_log_exception(int idx) +{ + if (qemu_loglevel_mask(CPU_LOG_INT)) { + const char *exc =3D NULL; + static const char * const excnames[] =3D { + [EXCP_UDEF] =3D "Undefined Instruction", + [EXCP_SWI] =3D "SVC", + [EXCP_PREFETCH_ABORT] =3D "Prefetch Abort", + [EXCP_DATA_ABORT] =3D "Data Abort", + [EXCP_IRQ] =3D "IRQ", + [EXCP_FIQ] =3D "FIQ", + [EXCP_BKPT] =3D "Breakpoint", + [EXCP_EXCEPTION_EXIT] =3D "QEMU v7M exception exit", + [EXCP_KERNEL_TRAP] =3D "QEMU intercept of kernel commpage", + [EXCP_HVC] =3D "Hypervisor Call", + [EXCP_HYP_TRAP] =3D "Hypervisor Trap", + [EXCP_SMC] =3D "Secure Monitor Call", + [EXCP_VIRQ] =3D "Virtual IRQ", + [EXCP_VFIQ] =3D "Virtual FIQ", + [EXCP_SEMIHOST] =3D "Semihosting call", + [EXCP_NOCP] =3D "v7M NOCP UsageFault", + [EXCP_INVSTATE] =3D "v7M INVSTATE UsageFault", + [EXCP_STKOF] =3D "v8M STKOF UsageFault", + [EXCP_LAZYFP] =3D "v7M exception during lazy FP stacking", + [EXCP_LSERR] =3D "v8M LSERR UsageFault", + [EXCP_UNALIGNED] =3D "v7M UNALIGNED UsageFault", + }; + + if (idx >=3D 0 && idx < ARRAY_SIZE(excnames)) { + exc =3D excnames[idx]; + } + if (!exc) { + exc =3D "unknown"; + } + qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc); + } +} + +/* Handle a CPU exception for A and R profile CPUs. + * Do any appropriate logging, handle PSCI calls, and then hand off + * to the AArch64-entry or AArch32-entry function depending on the + * target exception level's register width. + * + * Note: this is used for both TCG (as the do_interrupt tcg op), + * and KVM to re-inject guest debug exceptions, and to + * inject a Synchronous-External-Abort. + */ +void arm_cpu_do_interrupt(CPUState *cs) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + unsigned int new_el =3D env->exception.target_el; + + assert(!arm_feature(env, ARM_FEATURE_M)); + + arm_log_exception(cs->exception_index); + qemu_log_mask(CPU_LOG_INT, "...from EL%d to EL%d\n", arm_current_el(en= v), + new_el); + if (qemu_loglevel_mask(CPU_LOG_INT) + && !excp_is_internal(cs->exception_index)) { + qemu_log_mask(CPU_LOG_INT, "...with ESR 0x%x/0x%" PRIx32 "\n", + syn_get_ec(env->exception.syndrome), + env->exception.syndrome); + } + +#ifdef CONFIG_TCG + if (tcg_enabled()) { + if (arm_is_psci_call(cpu, cs->exception_index)) { + arm_handle_psci_call(cpu); + qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n"); + return; + } + /* + * Semihosting semantics depend on the register width of the code + * that caused the exception, not the target exception level, so + * must be handled here. + */ + if (cs->exception_index =3D=3D EXCP_SEMIHOST) { + tcg_handle_semihosting(cs); + return; + } + } +#endif /* CONFIG_TCG */ + /* + * Hooks may change global state so BQL should be held, also the + * BQL needs to be held for any modification of + * cs->interrupt_request. + */ + g_assert(qemu_mutex_iothread_locked()); + arm_call_pre_el_change_hook(cpu); + + assert(!excp_is_internal(cs->exception_index)); + if (arm_el_is_aa64(env, new_el)) { + arm_cpu_do_interrupt_aarch64(cs); + } else { + arm_cpu_do_interrupt_aarch32(cs); + } + + arm_call_el_change_hook(cpu); + + if (tcg_enabled()) { + cs->interrupt_request |=3D CPU_INTERRUPT_EXITTB; + } +} diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 0f640a8b4e..1043551b9c 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -28,7 +28,7 @@ #include "cpu.h" #include "cpregs.h" #ifdef CONFIG_TCG -#include "hw/core/tcg-cpu-ops.h" +#include "tcg/tcg-cpu.h" #endif /* CONFIG_TCG */ #include "cpu32.h" #include "internals.h" @@ -60,25 +60,6 @@ static void arm_cpu_set_pc(CPUState *cs, vaddr value) } } =20 -#ifdef CONFIG_TCG -void arm_cpu_synchronize_from_tb(CPUState *cs, - const TranslationBlock *tb) -{ - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - - /* - * It's OK to look at env for the current mode here, because it's - * never possible for an AArch64 TB to chain to an AArch32 TB. - */ - if (is_a64(env)) { - env->pc =3D tb->pc; - } else { - env->regs[15] =3D tb->pc; - } -} -#endif /* CONFIG_TCG */ - static bool arm_cpu_has_work(CPUState *cs) { ARMCPU *cpu =3D ARM_CPU(cs); @@ -444,175 +425,6 @@ static void arm_cpu_reset(DeviceState *dev) } } =20 -static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, - unsigned int target_el, - unsigned int cur_el, bool secure, - uint64_t hcr_el2) -{ - CPUARMState *env =3D cs->env_ptr; - bool pstate_unmasked; - bool unmasked =3D false; - - /* - * Don't take exceptions if they target a lower EL. - * This check should catch any exceptions that would not be taken - * but left pending. - */ - if (cur_el > target_el) { - return false; - } - - switch (excp_idx) { - case EXCP_FIQ: - pstate_unmasked =3D !(env->daif & PSTATE_F); - break; - - case EXCP_IRQ: - pstate_unmasked =3D !(env->daif & PSTATE_I); - break; - - case EXCP_VFIQ: - if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { - /* VFIQs are only taken when hypervized. */ - return false; - } - return !(env->daif & PSTATE_F); - case EXCP_VIRQ: - if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { - /* VIRQs are only taken when hypervized. */ - return false; - } - return !(env->daif & PSTATE_I); - default: - g_assert_not_reached(); - } - - /* - * Use the target EL, current execution state and SCR/HCR settings to - * determine whether the corresponding CPSR bit is used to mask the - * interrupt. - */ - if ((target_el > cur_el) && (target_el !=3D 1)) { - /* Exceptions targeting a higher EL may not be maskable */ - if (arm_feature(env, ARM_FEATURE_AARCH64)) { - /* - * 64-bit masking rules are simple: exceptions to EL3 - * can't be masked, and exceptions to EL2 can only be - * masked from Secure state. The HCR and SCR settings - * don't affect the masking logic, only the interrupt routing. - */ - if (target_el =3D=3D 3 || !secure || (env->cp15.scr_el3 & SCR_= EEL2)) { - unmasked =3D true; - } - } else { - /* - * The old 32-bit-only environment has a more complicated - * masking setup. HCR and SCR bits not only affect interrupt - * routing but also change the behaviour of masking. - */ - bool hcr, scr; - - switch (excp_idx) { - case EXCP_FIQ: - /* - * If FIQs are routed to EL3 or EL2 then there are cases w= here - * we override the CPSR.F in determining if the exception = is - * masked or not. If neither of these are set then we fall= back - * to the CPSR.F setting otherwise we further assess the s= tate - * below. - */ - hcr =3D hcr_el2 & HCR_FMO; - scr =3D (env->cp15.scr_el3 & SCR_FIQ); - - /* - * When EL3 is 32-bit, the SCR.FW bit controls whether the - * CPSR.F bit masks FIQ interrupts when taken in non-secure - * state. If SCR.FW is set then FIQs can be masked by CPSR= .F - * when non-secure but only when FIQs are only routed to E= L3. - */ - scr =3D scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); - break; - case EXCP_IRQ: - /* - * When EL3 execution state is 32-bit, if HCR.IMO is set t= hen - * we may override the CPSR.I masking when in non-secure s= tate. - * The SCR.IRQ setting has already been taken into conside= ration - * when setting the target EL, so it does not have a furth= er - * affect here. - */ - hcr =3D hcr_el2 & HCR_IMO; - scr =3D false; - break; - default: - g_assert_not_reached(); - } - - if ((scr || hcr) && !secure) { - unmasked =3D true; - } - } - } - - /* - * The PSTATE bits only mask the interrupt if we have not overriden the - * ability above. - */ - return unmasked || pstate_unmasked; -} - -bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) -{ - CPUClass *cc =3D CPU_GET_CLASS(cs); - CPUARMState *env =3D cs->env_ptr; - uint32_t cur_el =3D arm_current_el(env); - bool secure =3D arm_is_secure(env); - uint64_t hcr_el2 =3D arm_hcr_el2_eff(env); - uint32_t target_el; - uint32_t excp_idx; - - /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */ - - if (interrupt_request & CPU_INTERRUPT_FIQ) { - excp_idx =3D EXCP_FIQ; - target_el =3D arm_phys_excp_target_el(cs, excp_idx, cur_el, secure= ); - if (arm_excp_unmasked(cs, excp_idx, target_el, - cur_el, secure, hcr_el2)) { - goto found; - } - } - if (interrupt_request & CPU_INTERRUPT_HARD) { - excp_idx =3D EXCP_IRQ; - target_el =3D arm_phys_excp_target_el(cs, excp_idx, cur_el, secure= ); - if (arm_excp_unmasked(cs, excp_idx, target_el, - cur_el, secure, hcr_el2)) { - goto found; - } - } - if (interrupt_request & CPU_INTERRUPT_VIRQ) { - excp_idx =3D EXCP_VIRQ; - target_el =3D 1; - if (arm_excp_unmasked(cs, excp_idx, target_el, - cur_el, secure, hcr_el2)) { - goto found; - } - } - if (interrupt_request & CPU_INTERRUPT_VFIQ) { - excp_idx =3D EXCP_VFIQ; - target_el =3D 1; - if (arm_excp_unmasked(cs, excp_idx, target_el, - cur_el, secure, hcr_el2)) { - goto found; - } - } - return false; - - found: - cs->exception_index =3D excp_idx; - env->exception.target_el =3D target_el; - cc->tcg_ops->do_interrupt(cs); - return true; -} - void arm_cpu_update_virq(ARMCPU *cpu) { /* @@ -1017,6 +829,7 @@ static void arm_cpu_finalizefn(Object *obj) QLIST_REMOVE(hook, node); g_free(hook); } + #ifndef CONFIG_USER_ONLY if (cpu->pmu_timer) { timer_free(cpu->pmu_timer); @@ -1632,24 +1445,6 @@ static Property arm_cpu_properties[] =3D { DEFINE_PROP_END_OF_LIST() }; =20 -#ifdef CONFIG_TCG -static struct TCGCPUOps arm_tcg_ops =3D { - .initialize =3D arm_translate_init, - .synchronize_from_tb =3D arm_cpu_synchronize_from_tb, - .cpu_exec_interrupt =3D arm_cpu_exec_interrupt, - .tlb_fill =3D arm_cpu_tlb_fill, - .debug_excp_handler =3D arm_debug_excp_handler, - -#if !defined(CONFIG_USER_ONLY) - .do_interrupt =3D arm_cpu_do_interrupt, - .do_transaction_failed =3D arm_cpu_do_transaction_failed, - .do_unaligned_access =3D arm_cpu_do_unaligned_access, - .adjust_watchpoint_address =3D arm_adjust_watchpoint_address, - .debug_check_watchpoint =3D arm_debug_check_watchpoint, -#endif /* !CONFIG_USER_ONLY */ -}; -#endif /* CONFIG_TCG */ - static void arm_cpu_class_init(ObjectClass *oc, void *data) { ARMCPUClass *acc =3D ARM_CPU_CLASS(oc); diff --git a/target/arm/tcg/helper.c b/target/arm/tcg/helper.c index 988ee1c49c..548c94e057 100644 --- a/target/arm/tcg/helper.c +++ b/target/arm/tcg/helper.c @@ -7,36 +7,16 @@ */ =20 #include "qemu/osdep.h" -#include "qemu/units.h" -#include "target/arm/idau.h" -#include "trace.h" #include "cpu.h" #include "internals.h" #include "exec/gdbstub.h" #include "exec/helper-proto.h" -#include "qemu/host-utils.h" -#include "qemu/main-loop.h" -#include "qemu/bitops.h" #include "qemu/crc32c.h" -#include "qemu/qemu-print.h" -#include "exec/exec-all.h" #include /* For crc32 */ -#include "hw/irq.h" -#include "semihosting/semihost.h" -#include "sysemu/cpus.h" -#include "sysemu/cpu-timers.h" -#include "sysemu/kvm.h" -#include "sysemu/tcg.h" -#include "qemu/range.h" -#include "qapi/error.h" -#include "qemu/guest-random.h" -#ifdef CONFIG_TCG #include "arm_ldst.h" -#include "exec/cpu_ldst.h" -#include "semihosting/common-semi.h" -#endif #include "cpu-mmu.h" #include "cpregs.h" +#include "tcg-cpu.h" =20 static int vfp_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg) { @@ -711,708 +691,6 @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32= _t excp_idx, return target_el; } =20 -void arm_log_exception(int idx) -{ - if (qemu_loglevel_mask(CPU_LOG_INT)) { - const char *exc =3D NULL; - static const char * const excnames[] =3D { - [EXCP_UDEF] =3D "Undefined Instruction", - [EXCP_SWI] =3D "SVC", - [EXCP_PREFETCH_ABORT] =3D "Prefetch Abort", - [EXCP_DATA_ABORT] =3D "Data Abort", - [EXCP_IRQ] =3D "IRQ", - [EXCP_FIQ] =3D "FIQ", - [EXCP_BKPT] =3D "Breakpoint", - [EXCP_EXCEPTION_EXIT] =3D "QEMU v7M exception exit", - [EXCP_KERNEL_TRAP] =3D "QEMU intercept of kernel commpage", - [EXCP_HVC] =3D "Hypervisor Call", - [EXCP_HYP_TRAP] =3D "Hypervisor Trap", - [EXCP_SMC] =3D "Secure Monitor Call", - [EXCP_VIRQ] =3D "Virtual IRQ", - [EXCP_VFIQ] =3D "Virtual FIQ", - [EXCP_SEMIHOST] =3D "Semihosting call", - [EXCP_NOCP] =3D "v7M NOCP UsageFault", - [EXCP_INVSTATE] =3D "v7M INVSTATE UsageFault", - [EXCP_STKOF] =3D "v8M STKOF UsageFault", - [EXCP_LAZYFP] =3D "v7M exception during lazy FP stacking", - [EXCP_LSERR] =3D "v8M LSERR UsageFault", - [EXCP_UNALIGNED] =3D "v7M UNALIGNED UsageFault", - }; - - if (idx >=3D 0 && idx < ARRAY_SIZE(excnames)) { - exc =3D excnames[idx]; - } - if (!exc) { - exc =3D "unknown"; - } - qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc); - } -} - -static void take_aarch32_exception(CPUARMState *env, int new_mode, - uint32_t mask, uint32_t offset, - uint32_t newpc) -{ - int new_el; - - /* Change the CPU state so as to actually take the exception. */ - switch_mode(env, new_mode); - - /* - * For exceptions taken to AArch32 we must clear the SS bit in both - * PSTATE and in the old-state value we save to SPSR_, so zero i= t now. - */ - env->pstate &=3D ~PSTATE_SS; - env->spsr =3D cpsr_read(env); - /* Clear IT bits. */ - env->condexec_bits =3D 0; - /* Switch to the new mode, and to the correct instruction set. */ - env->uncached_cpsr =3D (env->uncached_cpsr & ~CPSR_M) | new_mode; - - /* This must be after mode switching. */ - new_el =3D arm_current_el(env); - - /* Set new mode endianness */ - env->uncached_cpsr &=3D ~CPSR_E; - if (env->cp15.sctlr_el[new_el] & SCTLR_EE) { - env->uncached_cpsr |=3D CPSR_E; - } - /* J and IL must always be cleared for exception entry */ - env->uncached_cpsr &=3D ~(CPSR_IL | CPSR_J); - env->daif |=3D mask; - - if (cpu_isar_feature(aa32_ssbs, env_archcpu(env))) { - if (env->cp15.sctlr_el[new_el] & SCTLR_DSSBS_32) { - env->uncached_cpsr |=3D CPSR_SSBS; - } else { - env->uncached_cpsr &=3D ~CPSR_SSBS; - } - } - - if (new_mode =3D=3D ARM_CPU_MODE_HYP) { - env->thumb =3D (env->cp15.sctlr_el[2] & SCTLR_TE) !=3D 0; - env->elr_el[2] =3D env->regs[15]; - } else { - /* CPSR.PAN is normally preserved preserved unless... */ - if (cpu_isar_feature(aa32_pan, env_archcpu(env))) { - switch (new_el) { - case 3: - if (!arm_is_secure_below_el3(env)) { - /* ... the target is EL3, from non-secure state. */ - env->uncached_cpsr &=3D ~CPSR_PAN; - break; - } - /* ... the target is EL3, from secure state ... */ - /* fall through */ - case 1: - /* ... the target is EL1 and SCTLR.SPAN is 0. */ - if (!(env->cp15.sctlr_el[new_el] & SCTLR_SPAN)) { - env->uncached_cpsr |=3D CPSR_PAN; - } - break; - } - } - /* - * this is a lie, as there was no c1_sys on V4T/V5, but who cares - * and we should just guard the thumb mode on V4 - */ - if (arm_feature(env, ARM_FEATURE_V4T)) { - env->thumb =3D - (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_TE) !=3D 0; - } - env->regs[14] =3D env->regs[15] + offset; - } - env->regs[15] =3D newpc; - arm_rebuild_hflags(env); -} - -static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs) -{ - /* - * Handle exception entry to Hyp mode; this is sufficiently - * different to entry to other AArch32 modes that we handle it - * separately here. - * - * The vector table entry used is always the 0x14 Hyp mode entry point, - * unless this is an UNDEF/HVC/abort taken from Hyp to Hyp. - * The offset applied to the preferred return address is always zero - * (see DDI0487C.a section G1.12.3). - * PSTATE A/I/F masks are set based only on the SCR.EA/IRQ/FIQ values. - */ - uint32_t addr, mask; - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - - switch (cs->exception_index) { - case EXCP_UDEF: - addr =3D 0x04; - break; - case EXCP_SWI: - addr =3D 0x14; - break; - case EXCP_BKPT: - /* Fall through to prefetch abort. */ - case EXCP_PREFETCH_ABORT: - env->cp15.ifar_s =3D env->exception.vaddress; - qemu_log_mask(CPU_LOG_INT, "...with HIFAR 0x%x\n", - (uint32_t)env->exception.vaddress); - addr =3D 0x0c; - break; - case EXCP_DATA_ABORT: - env->cp15.dfar_s =3D env->exception.vaddress; - qemu_log_mask(CPU_LOG_INT, "...with HDFAR 0x%x\n", - (uint32_t)env->exception.vaddress); - addr =3D 0x10; - break; - case EXCP_IRQ: - addr =3D 0x18; - break; - case EXCP_FIQ: - addr =3D 0x1c; - break; - case EXCP_HVC: - addr =3D 0x08; - break; - case EXCP_HYP_TRAP: - addr =3D 0x14; - break; - default: - cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); - } - - if (cs->exception_index !=3D EXCP_IRQ && cs->exception_index !=3D EXCP= _FIQ) { - if (!arm_feature(env, ARM_FEATURE_V8)) { - /* - * QEMU syndrome values are v8-style. v7 has the IL bit - * UNK/SBZP for "field not valid" cases, where v8 uses RES1. - * If this is a v7 CPU, squash the IL bit in those cases. - */ - if (cs->exception_index =3D=3D EXCP_PREFETCH_ABORT || - (cs->exception_index =3D=3D EXCP_DATA_ABORT && - !(env->exception.syndrome & ARM_EL_ISV)) || - syn_get_ec(env->exception.syndrome) =3D=3D EC_UNCATEGORIZE= D) { - env->exception.syndrome &=3D ~ARM_EL_IL; - } - } - env->cp15.esr_el[2] =3D env->exception.syndrome; - } - - if (arm_current_el(env) !=3D 2 && addr < 0x14) { - addr =3D 0x14; - } - - mask =3D 0; - if (!(env->cp15.scr_el3 & SCR_EA)) { - mask |=3D CPSR_A; - } - if (!(env->cp15.scr_el3 & SCR_IRQ)) { - mask |=3D CPSR_I; - } - if (!(env->cp15.scr_el3 & SCR_FIQ)) { - mask |=3D CPSR_F; - } - - addr +=3D env->cp15.hvbar; - - take_aarch32_exception(env, ARM_CPU_MODE_HYP, mask, 0, addr); -} - -static void arm_cpu_do_interrupt_aarch32(CPUState *cs) -{ - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - uint32_t addr; - uint32_t mask; - int new_mode; - uint32_t offset; - uint32_t moe; - - /* If this is a debug exception we must update the DBGDSCR.MOE bits */ - switch (syn_get_ec(env->exception.syndrome)) { - case EC_BREAKPOINT: - case EC_BREAKPOINT_SAME_EL: - moe =3D 1; - break; - case EC_WATCHPOINT: - case EC_WATCHPOINT_SAME_EL: - moe =3D 10; - break; - case EC_AA32_BKPT: - moe =3D 3; - break; - case EC_VECTORCATCH: - moe =3D 5; - break; - default: - moe =3D 0; - break; - } - - if (moe) { - env->cp15.mdscr_el1 =3D deposit64(env->cp15.mdscr_el1, 2, 4, moe); - } - - if (env->exception.target_el =3D=3D 2) { - arm_cpu_do_interrupt_aarch32_hyp(cs); - return; - } - - switch (cs->exception_index) { - case EXCP_UDEF: - new_mode =3D ARM_CPU_MODE_UND; - addr =3D 0x04; - mask =3D CPSR_I; - if (env->thumb) - offset =3D 2; - else - offset =3D 4; - break; - case EXCP_SWI: - new_mode =3D ARM_CPU_MODE_SVC; - addr =3D 0x08; - mask =3D CPSR_I; - /* The PC already points to the next instruction. */ - offset =3D 0; - break; - case EXCP_BKPT: - /* Fall through to prefetch abort. */ - case EXCP_PREFETCH_ABORT: - A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr); - A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress); - qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n", - env->exception.fsr, (uint32_t)env->exception.vaddres= s); - new_mode =3D ARM_CPU_MODE_ABT; - addr =3D 0x0c; - mask =3D CPSR_A | CPSR_I; - offset =3D 4; - break; - case EXCP_DATA_ABORT: - A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); - A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress); - qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n", - env->exception.fsr, - (uint32_t)env->exception.vaddress); - new_mode =3D ARM_CPU_MODE_ABT; - addr =3D 0x10; - mask =3D CPSR_A | CPSR_I; - offset =3D 8; - break; - case EXCP_IRQ: - new_mode =3D ARM_CPU_MODE_IRQ; - addr =3D 0x18; - /* Disable IRQ and imprecise data aborts. */ - mask =3D CPSR_A | CPSR_I; - offset =3D 4; - if (env->cp15.scr_el3 & SCR_IRQ) { - /* IRQ routed to monitor mode */ - new_mode =3D ARM_CPU_MODE_MON; - mask |=3D CPSR_F; - } - break; - case EXCP_FIQ: - new_mode =3D ARM_CPU_MODE_FIQ; - addr =3D 0x1c; - /* Disable FIQ, IRQ and imprecise data aborts. */ - mask =3D CPSR_A | CPSR_I | CPSR_F; - if (env->cp15.scr_el3 & SCR_FIQ) { - /* FIQ routed to monitor mode */ - new_mode =3D ARM_CPU_MODE_MON; - } - offset =3D 4; - break; - case EXCP_VIRQ: - new_mode =3D ARM_CPU_MODE_IRQ; - addr =3D 0x18; - /* Disable IRQ and imprecise data aborts. */ - mask =3D CPSR_A | CPSR_I; - offset =3D 4; - break; - case EXCP_VFIQ: - new_mode =3D ARM_CPU_MODE_FIQ; - addr =3D 0x1c; - /* Disable FIQ, IRQ and imprecise data aborts. */ - mask =3D CPSR_A | CPSR_I | CPSR_F; - offset =3D 4; - break; - case EXCP_SMC: - new_mode =3D ARM_CPU_MODE_MON; - addr =3D 0x08; - mask =3D CPSR_A | CPSR_I | CPSR_F; - offset =3D 0; - break; - default: - cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); - return; /* Never happens. Keep compiler happy. */ - } - - if (new_mode =3D=3D ARM_CPU_MODE_MON) { - addr +=3D env->cp15.mvbar; - } else if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { - /* High vectors. When enabled, base address cannot be remapped. */ - addr +=3D 0xffff0000; - } else { - /* ARM v7 architectures provide a vector base address register to = remap - * the interrupt vector table. - * This register is only followed in non-monitor mode, and is bank= ed. - * Note: only bits 31:5 are valid. - */ - addr +=3D A32_BANKED_CURRENT_REG_GET(env, vbar); - } - - if ((env->uncached_cpsr & CPSR_M) =3D=3D ARM_CPU_MODE_MON) { - env->cp15.scr_el3 &=3D ~SCR_NS; - } - - take_aarch32_exception(env, new_mode, mask, offset, addr); -} - -static int aarch64_regnum(CPUARMState *env, int aarch32_reg) -{ - /* - * Return the register number of the AArch64 view of the AArch32 - * register @aarch32_reg. The CPUARMState CPSR is assumed to still - * be that of the AArch32 mode the exception came from. - */ - int mode =3D env->uncached_cpsr & CPSR_M; - - switch (aarch32_reg) { - case 0 ... 7: - return aarch32_reg; - case 8 ... 12: - return mode =3D=3D ARM_CPU_MODE_FIQ ? aarch32_reg + 16 : aarch32_r= eg; - case 13: - switch (mode) { - case ARM_CPU_MODE_USR: - case ARM_CPU_MODE_SYS: - return 13; - case ARM_CPU_MODE_HYP: - return 15; - case ARM_CPU_MODE_IRQ: - return 17; - case ARM_CPU_MODE_SVC: - return 19; - case ARM_CPU_MODE_ABT: - return 21; - case ARM_CPU_MODE_UND: - return 23; - case ARM_CPU_MODE_FIQ: - return 29; - default: - g_assert_not_reached(); - } - case 14: - switch (mode) { - case ARM_CPU_MODE_USR: - case ARM_CPU_MODE_SYS: - case ARM_CPU_MODE_HYP: - return 14; - case ARM_CPU_MODE_IRQ: - return 16; - case ARM_CPU_MODE_SVC: - return 18; - case ARM_CPU_MODE_ABT: - return 20; - case ARM_CPU_MODE_UND: - return 22; - case ARM_CPU_MODE_FIQ: - return 30; - default: - g_assert_not_reached(); - } - case 15: - return 31; - default: - g_assert_not_reached(); - } -} - -static uint32_t cpsr_read_for_spsr_elx(CPUARMState *env) -{ - uint32_t ret =3D cpsr_read(env); - - /* Move DIT to the correct location for SPSR_ELx */ - if (ret & CPSR_DIT) { - ret &=3D ~CPSR_DIT; - ret |=3D PSTATE_DIT; - } - /* Merge PSTATE.SS into SPSR_ELx */ - ret |=3D env->pstate & PSTATE_SS; - - return ret; -} - -/* Handle exception entry to a target EL which is using AArch64 */ -static void arm_cpu_do_interrupt_aarch64(CPUState *cs) -{ - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - unsigned int new_el =3D env->exception.target_el; - target_ulong addr =3D env->cp15.vbar_el[new_el]; - unsigned int new_mode =3D aarch64_pstate_mode(new_el, true); - unsigned int old_mode; - unsigned int cur_el =3D arm_current_el(env); - int rt; - - /* - * Note that new_el can never be 0. If cur_el is 0, then - * el0_a64 is is_a64(), else el0_a64 is ignored. - */ - aarch64_sve_change_el(env, cur_el, new_el, is_a64(env)); - - if (cur_el < new_el) { - /* Entry vector offset depends on whether the implemented EL - * immediately lower than the target level is using AArch32 or AAr= ch64 - */ - bool is_aa64; - uint64_t hcr; - - switch (new_el) { - case 3: - is_aa64 =3D (env->cp15.scr_el3 & SCR_RW) !=3D 0; - break; - case 2: - hcr =3D arm_hcr_el2_eff(env); - if ((hcr & (HCR_E2H | HCR_TGE)) !=3D (HCR_E2H | HCR_TGE)) { - is_aa64 =3D (hcr & HCR_RW) !=3D 0; - break; - } - /* fall through */ - case 1: - is_aa64 =3D is_a64(env); - break; - default: - g_assert_not_reached(); - } - - if (is_aa64) { - addr +=3D 0x400; - } else { - addr +=3D 0x600; - } - } else if (pstate_read(env) & PSTATE_SP) { - addr +=3D 0x200; - } - - switch (cs->exception_index) { - case EXCP_PREFETCH_ABORT: - case EXCP_DATA_ABORT: - env->cp15.far_el[new_el] =3D env->exception.vaddress; - qemu_log_mask(CPU_LOG_INT, "...with FAR 0x%" PRIx64 "\n", - env->cp15.far_el[new_el]); - /* fall through */ - case EXCP_BKPT: - case EXCP_UDEF: - case EXCP_SWI: - case EXCP_HVC: - case EXCP_HYP_TRAP: - case EXCP_SMC: - switch (syn_get_ec(env->exception.syndrome)) { - case EC_ADVSIMDFPACCESSTRAP: - /* - * QEMU internal FP/SIMD syndromes from AArch32 include the - * TA and coproc fields which are only exposed if the exception - * is taken to AArch32 Hyp mode. Mask them out to get a valid - * AArch64 format syndrome. - */ - env->exception.syndrome &=3D ~MAKE_64BIT_MASK(0, 20); - break; - case EC_CP14RTTRAP: - case EC_CP15RTTRAP: - case EC_CP14DTTRAP: - /* - * For a trap on AArch32 MRC/MCR/LDC/STC the Rt field is curre= ntly - * the raw register field from the insn; when taking this to - * AArch64 we must convert it to the AArch64 view of the regis= ter - * number. Notice that we read a 4-bit AArch32 register number= and - * write back a 5-bit AArch64 one. - */ - rt =3D extract32(env->exception.syndrome, 5, 4); - rt =3D aarch64_regnum(env, rt); - env->exception.syndrome =3D deposit32(env->exception.syndrome, - 5, 5, rt); - break; - case EC_CP15RRTTRAP: - case EC_CP14RRTTRAP: - /* Similarly for MRRC/MCRR traps for Rt and Rt2 fields */ - rt =3D extract32(env->exception.syndrome, 5, 4); - rt =3D aarch64_regnum(env, rt); - env->exception.syndrome =3D deposit32(env->exception.syndrome, - 5, 5, rt); - rt =3D extract32(env->exception.syndrome, 10, 4); - rt =3D aarch64_regnum(env, rt); - env->exception.syndrome =3D deposit32(env->exception.syndrome, - 10, 5, rt); - break; - } - env->cp15.esr_el[new_el] =3D env->exception.syndrome; - break; - case EXCP_IRQ: - case EXCP_VIRQ: - addr +=3D 0x80; - break; - case EXCP_FIQ: - case EXCP_VFIQ: - addr +=3D 0x100; - break; - default: - cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); - } - - if (is_a64(env)) { - old_mode =3D pstate_read(env); - aarch64_save_sp(env, arm_current_el(env)); - env->elr_el[new_el] =3D env->pc; - } else { - old_mode =3D cpsr_read_for_spsr_elx(env); - env->elr_el[new_el] =3D env->regs[15]; - - aarch64_sync_32_to_64(env); - - env->condexec_bits =3D 0; - } - env->banked_spsr[aarch64_banked_spsr_index(new_el)] =3D old_mode; - - qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n", - env->elr_el[new_el]); - - if (cpu_isar_feature(aa64_pan, cpu)) { - /* The value of PSTATE.PAN is normally preserved, except when ... = */ - new_mode |=3D old_mode & PSTATE_PAN; - switch (new_el) { - case 2: - /* ... the target is EL2 with HCR_EL2.{E2H,TGE} =3D=3D '11' ..= . */ - if ((arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) - !=3D (HCR_E2H | HCR_TGE)) { - break; - } - /* fall through */ - case 1: - /* ... the target is EL1 ... */ - /* ... and SCTLR_ELx.SPAN =3D=3D 0, then set to 1. */ - if ((env->cp15.sctlr_el[new_el] & SCTLR_SPAN) =3D=3D 0) { - new_mode |=3D PSTATE_PAN; - } - break; - } - } - if (cpu_isar_feature(aa64_mte, cpu)) { - new_mode |=3D PSTATE_TCO; - } - - if (cpu_isar_feature(aa64_ssbs, cpu)) { - if (env->cp15.sctlr_el[new_el] & SCTLR_DSSBS_64) { - new_mode |=3D PSTATE_SSBS; - } else { - new_mode &=3D ~PSTATE_SSBS; - } - } - - pstate_write(env, PSTATE_DAIF | new_mode); - env->aarch64 =3D 1; - aarch64_restore_sp(env, new_el); - helper_rebuild_hflags_a64(env, new_el); - - env->pc =3D addr; - - qemu_log_mask(CPU_LOG_INT, "...to EL%d PC 0x%" PRIx64 " PSTATE 0x%x\n", - new_el, env->pc, pstate_read(env)); -} - -/* - * Do semihosting call and set the appropriate return value. All the - * permission and validity checks have been done at translate time. - * - * We only see semihosting exceptions in TCG only as they are not - * trapped to the hypervisor in KVM. - */ -#ifdef CONFIG_TCG -static void handle_semihosting(CPUState *cs) -{ - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - - if (is_a64(env)) { - qemu_log_mask(CPU_LOG_INT, - "...handling as semihosting call 0x%" PRIx64 "\n", - env->xregs[0]); - env->xregs[0] =3D do_common_semihosting(cs); - env->pc +=3D 4; - } else { - qemu_log_mask(CPU_LOG_INT, - "...handling as semihosting call 0x%x\n", - env->regs[0]); - env->regs[0] =3D do_common_semihosting(cs); - env->regs[15] +=3D env->thumb ? 2 : 4; - } -} -#endif - -/* Handle a CPU exception for A and R profile CPUs. - * Do any appropriate logging, handle PSCI calls, and then hand off - * to the AArch64-entry or AArch32-entry function depending on the - * target exception level's register width. - * - * Note: this is used for both TCG (as the do_interrupt tcg op), - * and KVM to re-inject guest debug exceptions, and to - * inject a Synchronous-External-Abort. - */ -void arm_cpu_do_interrupt(CPUState *cs) -{ - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - unsigned int new_el =3D env->exception.target_el; - - assert(!arm_feature(env, ARM_FEATURE_M)); - - arm_log_exception(cs->exception_index); - qemu_log_mask(CPU_LOG_INT, "...from EL%d to EL%d\n", arm_current_el(en= v), - new_el); - if (qemu_loglevel_mask(CPU_LOG_INT) - && !excp_is_internal(cs->exception_index)) { - qemu_log_mask(CPU_LOG_INT, "...with ESR 0x%x/0x%" PRIx32 "\n", - syn_get_ec(env->exception.syndrome), - env->exception.syndrome); - } - - if (arm_is_psci_call(cpu, cs->exception_index)) { - arm_handle_psci_call(cpu); - qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n"); - return; - } - - /* - * Semihosting semantics depend on the register width of the code - * that caused the exception, not the target exception level, so - * must be handled here. - */ -#ifdef CONFIG_TCG - if (cs->exception_index =3D=3D EXCP_SEMIHOST) { - handle_semihosting(cs); - return; - } -#endif - - /* Hooks may change global state so BQL should be held, also the - * BQL needs to be held for any modification of - * cs->interrupt_request. - */ - g_assert(qemu_mutex_iothread_locked()); - - arm_call_pre_el_change_hook(cpu); - - assert(!excp_is_internal(cs->exception_index)); - if (arm_el_is_aa64(env, new_el)) { - arm_cpu_do_interrupt_aarch64(cs); - } else { - arm_cpu_do_interrupt_aarch32(cs); - } - - arm_call_el_change_hook(cpu); - - if (!kvm_enabled()) { - cs->interrupt_request |=3D CPU_INTERRUPT_EXITTB; - } -} #endif /* !CONFIG_USER_ONLY */ =20 /* Returns true if the stage 1 translation regime is using LPAE format page diff --git a/target/arm/tcg/sysemu/tcg-cpu.c b/target/arm/tcg/sysemu/tcg-cp= u.c new file mode 100644 index 0000000000..2c395f47e7 --- /dev/null +++ b/target/arm/tcg/sysemu/tcg-cpu.c @@ -0,0 +1,73 @@ +/* + * QEMU ARM TCG CPU (sysemu code) + * + * Copyright (c) 2012 SUSE LINUX Products GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see + * + */ + +#include "qemu/osdep.h" +#include "qemu/qemu-print.h" +#include "qemu-common.h" +#include "target/arm/idau.h" +#include "qemu/module.h" +#include "qapi/error.h" +#include "qapi/visitor.h" +#include "cpu.h" +#include "hw/core/tcg-cpu-ops.h" +#include "semihosting/common-semi.h" +#include "cpregs.h" +#include "internals.h" +#include "exec/exec-all.h" +#include "hw/qdev-properties.h" +#if !defined(CONFIG_USER_ONLY) +#include "hw/loader.h" +#include "hw/boards.h" +#endif +#include "sysemu/sysemu.h" +#include "sysemu/tcg.h" +#include "sysemu/hw_accel.h" +#include "kvm_arm.h" +#include "disas/capstone.h" +#include "fpu/softfloat.h" +#include "cpu-mmu.h" +#include "tcg/tcg-cpu.h" + +/* + * Do semihosting call and set the appropriate return value. All the + * permission and validity checks have been done at translate time. + * + * We only see semihosting exceptions in TCG only as they are not + * trapped to the hypervisor in KVM. + */ +void tcg_handle_semihosting(CPUState *cs) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + + if (is_a64(env)) { + qemu_log_mask(CPU_LOG_INT, + "...handling as semihosting call 0x%" PRIx64 "\n", + env->xregs[0]); + env->xregs[0] =3D do_common_semihosting(cs); + env->pc +=3D 4; + } else { + qemu_log_mask(CPU_LOG_INT, + "...handling as semihosting call 0x%x\n", + env->regs[0]); + env->regs[0] =3D do_common_semihosting(cs); + env->regs[15] +=3D env->thumb ? 2 : 4; + } +} diff --git a/target/arm/cpu_tcg.c b/target/arm/tcg/tcg-cpu-models.c similarity index 99% rename from target/arm/cpu_tcg.c rename to target/arm/tcg/tcg-cpu-models.c index d120250b18..f4eea544b3 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/tcg/tcg-cpu-models.c @@ -1,5 +1,5 @@ /* - * QEMU ARM TCG CPUs. + * QEMU ARM TCG-only CPUs. * * Copyright (c) 2012 SUSE LINUX Products GmbH * @@ -9,10 +9,8 @@ */ =20 #include "qemu/osdep.h" -#include "cpu.h" -#ifdef CONFIG_TCG -#include "hw/core/tcg-cpu-ops.h" -#endif /* CONFIG_TCG */ +#include "tcg-cpu.h" + #include "internals.h" #include "target/arm/idau.h" #if !defined(CONFIG_USER_ONLY) @@ -24,7 +22,6 @@ /* CPU models. These are not needed for the AArch64 linux-user build. */ #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) =20 -#ifdef CONFIG_TCG static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { CPUClass *cc =3D CPU_GET_CLASS(cs); @@ -48,7 +45,6 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int = interrupt_request) } return ret; } -#endif /* CONFIG_TCG */ =20 static void arm926_initfn(Object *obj) { @@ -833,7 +829,6 @@ static void pxa270c5_initfn(Object *obj) cpu->reset_sctlr =3D 0x00000078; } =20 -#ifdef CONFIG_TCG static struct TCGCPUOps arm_v7m_tcg_ops =3D { .initialize =3D arm_translate_init, .synchronize_from_tb =3D arm_cpu_synchronize_from_tb, @@ -849,7 +844,6 @@ static struct TCGCPUOps arm_v7m_tcg_ops =3D { .debug_check_watchpoint =3D arm_debug_check_watchpoint, #endif /* !CONFIG_USER_ONLY */ }; -#endif /* CONFIG_TCG */ =20 static void arm_v7m_class_init(ObjectClass *oc, void *data) { diff --git a/target/arm/tcg/tcg-cpu.c b/target/arm/tcg/tcg-cpu.c new file mode 100644 index 0000000000..9fd996d908 --- /dev/null +++ b/target/arm/tcg/tcg-cpu.c @@ -0,0 +1,229 @@ +/* + * QEMU ARM CPU + * + * Copyright (c) 2012 SUSE LINUX Products GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see + * + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "tcg-cpu.h" +#include "hw/core/tcg-cpu-ops.h" +#include "cpregs.h" +#include "internals.h" +#include "exec/exec-all.h" + +void arm_cpu_synchronize_from_tb(CPUState *cs, + const TranslationBlock *tb) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + + /* + * It's OK to look at env for the current mode here, because it's + * never possible for an AArch64 TB to chain to an AArch32 TB. + */ + if (is_a64(env)) { + env->pc =3D tb->pc; + } else { + env->regs[15] =3D tb->pc; + } +} + +static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, + unsigned int target_el, + unsigned int cur_el, bool secure, + uint64_t hcr_el2) +{ + CPUARMState *env =3D cs->env_ptr; + bool pstate_unmasked; + bool unmasked =3D false; + + /* + * Don't take exceptions if they target a lower EL. + * This check should catch any exceptions that would not be taken + * but left pending. + */ + if (cur_el > target_el) { + return false; + } + + switch (excp_idx) { + case EXCP_FIQ: + pstate_unmasked =3D !(env->daif & PSTATE_F); + break; + + case EXCP_IRQ: + pstate_unmasked =3D !(env->daif & PSTATE_I); + break; + + case EXCP_VFIQ: + if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { + /* VFIQs are only taken when hypervized. */ + return false; + } + return !(env->daif & PSTATE_F); + case EXCP_VIRQ: + if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { + /* VIRQs are only taken when hypervized. */ + return false; + } + return !(env->daif & PSTATE_I); + default: + g_assert_not_reached(); + } + + /* + * Use the target EL, current execution state and SCR/HCR settings to + * determine whether the corresponding CPSR bit is used to mask the + * interrupt. + */ + if ((target_el > cur_el) && (target_el !=3D 1)) { + /* Exceptions targeting a higher EL may not be maskable */ + if (arm_feature(env, ARM_FEATURE_AARCH64)) { + /* + * 64-bit masking rules are simple: exceptions to EL3 + * can't be masked, and exceptions to EL2 can only be + * masked from Secure state. The HCR and SCR settings + * don't affect the masking logic, only the interrupt routing. + */ + if (target_el =3D=3D 3 || !secure || (env->cp15.scr_el3 & SCR_= EEL2)) { + unmasked =3D true; + } + } else { + /* + * The old 32-bit-only environment has a more complicated + * masking setup. HCR and SCR bits not only affect interrupt + * routing but also change the behaviour of masking. + */ + bool hcr, scr; + + switch (excp_idx) { + case EXCP_FIQ: + /* + * If FIQs are routed to EL3 or EL2 then there are cases w= here + * we override the CPSR.F in determining if the exception = is + * masked or not. If neither of these are set then we fall= back + * to the CPSR.F setting otherwise we further assess the s= tate + * below. + */ + hcr =3D hcr_el2 & HCR_FMO; + scr =3D (env->cp15.scr_el3 & SCR_FIQ); + + /* + * When EL3 is 32-bit, the SCR.FW bit controls whether the + * CPSR.F bit masks FIQ interrupts when taken in non-secure + * state. If SCR.FW is set then FIQs can be masked by CPSR= .F + * when non-secure but only when FIQs are only routed to E= L3. + */ + scr =3D scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); + break; + case EXCP_IRQ: + /* + * When EL3 execution state is 32-bit, if HCR.IMO is set t= hen + * we may override the CPSR.I masking when in non-secure s= tate. + * The SCR.IRQ setting has already been taken into conside= ration + * when setting the target EL, so it does not have a furth= er + * affect here. + */ + hcr =3D hcr_el2 & HCR_IMO; + scr =3D false; + break; + default: + g_assert_not_reached(); + } + + if ((scr || hcr) && !secure) { + unmasked =3D true; + } + } + } + + /* + * The PSTATE bits only mask the interrupt if we have not overriden the + * ability above. + */ + return unmasked || pstate_unmasked; +} + +static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +{ + CPUClass *cc =3D CPU_GET_CLASS(cs); + CPUARMState *env =3D cs->env_ptr; + uint32_t cur_el =3D arm_current_el(env); + bool secure =3D arm_is_secure(env); + uint64_t hcr_el2 =3D arm_hcr_el2_eff(env); + uint32_t target_el; + uint32_t excp_idx; + + /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */ + + if (interrupt_request & CPU_INTERRUPT_FIQ) { + excp_idx =3D EXCP_FIQ; + target_el =3D arm_phys_excp_target_el(cs, excp_idx, cur_el, secure= ); + if (arm_excp_unmasked(cs, excp_idx, target_el, + cur_el, secure, hcr_el2)) { + goto found; + } + } + if (interrupt_request & CPU_INTERRUPT_HARD) { + excp_idx =3D EXCP_IRQ; + target_el =3D arm_phys_excp_target_el(cs, excp_idx, cur_el, secure= ); + if (arm_excp_unmasked(cs, excp_idx, target_el, + cur_el, secure, hcr_el2)) { + goto found; + } + } + if (interrupt_request & CPU_INTERRUPT_VIRQ) { + excp_idx =3D EXCP_VIRQ; + target_el =3D 1; + if (arm_excp_unmasked(cs, excp_idx, target_el, + cur_el, secure, hcr_el2)) { + goto found; + } + } + if (interrupt_request & CPU_INTERRUPT_VFIQ) { + excp_idx =3D EXCP_VFIQ; + target_el =3D 1; + if (arm_excp_unmasked(cs, excp_idx, target_el, + cur_el, secure, hcr_el2)) { + goto found; + } + } + return false; + + found: + cs->exception_index =3D excp_idx; + env->exception.target_el =3D target_el; + cc->tcg_ops->do_interrupt(cs); + return true; +} + +struct TCGCPUOps arm_tcg_ops =3D { + .initialize =3D arm_translate_init, + .synchronize_from_tb =3D arm_cpu_synchronize_from_tb, + .cpu_exec_interrupt =3D arm_cpu_exec_interrupt, + .tlb_fill =3D arm_cpu_tlb_fill, + .debug_excp_handler =3D arm_debug_excp_handler, + +#if !defined(CONFIG_USER_ONLY) + .do_interrupt =3D arm_cpu_do_interrupt, + .do_transaction_failed =3D arm_cpu_do_transaction_failed, + .do_unaligned_access =3D arm_cpu_do_unaligned_access, + .adjust_watchpoint_address =3D arm_adjust_watchpoint_address, + .debug_check_watchpoint =3D arm_debug_check_watchpoint, +#endif /* !CONFIG_USER_ONLY */ +}; diff --git a/target/arm/meson.build b/target/arm/meson.build index e4ff9a0534..3166e88c0d 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -3,7 +3,6 @@ arm_ss.add(files( 'cpu.c', 'cpu32.c', 'gdbstub.c', - 'cpu_tcg.c', 'cpu-mmu.c', 'cpregs.c', 'cpustate-list.c', @@ -19,10 +18,6 @@ arm_ss.add(when: 'TARGET_AARCH64', if_true: files( 'gdbstub64.c', )) =20 -arm_ss.add(when: 'CONFIG_TCG', if_true: files( - 'cpu_tcg.c', -)) - arm_softmmu_ss =3D ss.source_set() arm_softmmu_ss.add(files( 'arch_dump.c', diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index 6d372d44e6..d3d2f605d9 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -28,9 +28,11 @@ arm_ss.add(when: 'CONFIG_TCG', if_true: files( 'vfp_helper.c', 'crypto_helper.c', 'debug_helper.c', + 'tcg-cpu.c', + 'tcg-cpu-models.c', )) =20 -arm_ss.add(when: ['TARGET_AARCH64','CONFIG_TCG'], if_true: files( +arm_ss.add(when: ['TARGET_AARCH64', 'CONFIG_TCG'], if_true: files( 'translate-a64.c', 'translate-sve.c', 'helper-a64.c', diff --git a/target/arm/tcg/sysemu/meson.build b/target/arm/tcg/sysemu/meso= n.build index bc11678a0a..61dcacf593 100644 --- a/target/arm/tcg/sysemu/meson.build +++ b/target/arm/tcg/sysemu/meson.build @@ -1,3 +1,4 @@ =20 arm_softmmu_ss.add(when: ['CONFIG_TCG','CONFIG_SOFTMMU'], if_true: files( + 'tcg-cpu.c', )) --=20 2.26.2