From nobody Wed Nov 19 13:56:56 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1616006707; cv=none; d=zohomail.com; s=zohoarc; b=O957ouLN/T0tb2I9djHty+IgJTZsuFByF5/m/2CdFNpeTBhEkvz/+5qNk7Fcj09OUL9nPcZkVGYHlYviiwLtAhwHh8cWJVhZudGICeyEv9ntJEHTPsorkbiQ0PBcR+yoqXuT9GrpTfCV3eE8jbomzlVCePpO6IBEx3n/4F37nkc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1616006707; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=zvRL4eVObIsY0cQqtjV4P6brSV2DVuLNt6j4jMQD0sY=; b=E/AUM/lx7aGc/ZA45He0cocQB4fhy3Kswdc2sbkuQxHOHJK/XpvsLPTA9igQ8gvPns/fM2FVV95+POTZWu8SZiIlAAgxFeenQxumKVsLk2khx261vUGtLrdhAfHY+XkwZCMgqj1ubmgyGuB1Im7AbEDfBVeFMR3DL4U46cjSnVw= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 161600670753321.446894744304814; Wed, 17 Mar 2021 11:45:07 -0700 (PDT) Received: from localhost ([::1]:59580 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lMbAI-0001oY-7A for importer@patchew.org; Wed, 17 Mar 2021 14:45:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39480) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lMawf-00047i-49 for qemu-devel@nongnu.org; Wed, 17 Mar 2021 14:31:01 -0400 Received: from mx2.suse.de ([195.135.220.15]:48464) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lMawU-0007kl-BE for qemu-devel@nongnu.org; Wed, 17 Mar 2021 14:31:00 -0400 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id BA23CACA8; Wed, 17 Mar 2021 18:30:25 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [RFC v9 21/50] target/arm: move aarch64_sync_32_to_64 (and vv) to cpu code Date: Wed, 17 Mar 2021 19:29:44 +0100 Message-Id: <20210317183013.25772-22-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210317183013.25772-1-cfontana@suse.de> References: <20210317183013.25772-1-cfontana@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Roman Bolshakov , Claudio Fontana , Eduardo Habkost , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" and arm_phys_excp_target_el since it is tied up inside the same #ifdef block. aarch64_sync_32_to_64 and aarch64_sync_64_to_32 are mixed in with the TCG helpers, but they shouldn't, as they are needed for KVM too. kvm_arch_get_registers() { if (!is_a64(env)) { aarch64_sync_64_to_32(env); } write_kvmstate_to_list(cpu); write_list_to_cpustate(cpu); ... } kvm_arch_put_registers() { if (!is_a64(env)) { aarch64_sync_32_to_64(env); } write_cpustate_to_list(cpu, true); write_list_to_kvmstate(cpu, level) ... } Move to the cpu module. Signed-off-by: Claudio Fontana --- target/arm/cpu-sysemu.c | 217 +++++++++++++++++++++++++++++++++++++ target/arm/cpu-user.c | 11 ++ target/arm/tcg/helper.c | 232 +--------------------------------------- 3 files changed, 231 insertions(+), 229 deletions(-) diff --git a/target/arm/cpu-sysemu.c b/target/arm/cpu-sysemu.c index 3add2c2439..d510382742 100644 --- a/target/arm/cpu-sysemu.c +++ b/target/arm/cpu-sysemu.c @@ -133,3 +133,220 @@ void switch_mode(CPUARMState *env, int mode) env->banked_r14[r14_bank_number(old_mode)] =3D env->regs[14]; env->regs[14] =3D env->banked_r14[r14_bank_number(mode)]; } + + + +/* + * Function used to synchronize QEMU's AArch64 register set with AArch32 + * register set. This is necessary when switching between AArch32 and AAr= ch64 + * execution state. + */ +void aarch64_sync_32_to_64(CPUARMState *env) +{ + int i; + uint32_t mode =3D env->uncached_cpsr & CPSR_M; + + /* We can blanket copy R[0:7] to X[0:7] */ + for (i =3D 0; i < 8; i++) { + env->xregs[i] =3D env->regs[i]; + } + + /* + * Unless we are in FIQ mode, x8-x12 come from the user registers r8-r= 12. + * Otherwise, they come from the banked user regs. + */ + if (mode =3D=3D ARM_CPU_MODE_FIQ) { + for (i =3D 8; i < 13; i++) { + env->xregs[i] =3D env->usr_regs[i - 8]; + } + } else { + for (i =3D 8; i < 13; i++) { + env->xregs[i] =3D env->regs[i]; + } + } + + /* + * Registers x13-x23 are the various mode SP and FP registers. Registe= rs + * r13 and r14 are only copied if we are in that mode, otherwise we co= py + * from the mode banked register. + */ + if (mode =3D=3D ARM_CPU_MODE_USR || mode =3D=3D ARM_CPU_MODE_SYS) { + env->xregs[13] =3D env->regs[13]; + env->xregs[14] =3D env->regs[14]; + } else { + env->xregs[13] =3D env->banked_r13[bank_number(ARM_CPU_MODE_USR)]; + /* HYP is an exception in that it is copied from r14 */ + if (mode =3D=3D ARM_CPU_MODE_HYP) { + env->xregs[14] =3D env->regs[14]; + } else { + env->xregs[14] =3D env->banked_r14[r14_bank_number(ARM_CPU_MOD= E_USR)]; + } + } + + if (mode =3D=3D ARM_CPU_MODE_HYP) { + env->xregs[15] =3D env->regs[13]; + } else { + env->xregs[15] =3D env->banked_r13[bank_number(ARM_CPU_MODE_HYP)]; + } + + if (mode =3D=3D ARM_CPU_MODE_IRQ) { + env->xregs[16] =3D env->regs[14]; + env->xregs[17] =3D env->regs[13]; + } else { + env->xregs[16] =3D env->banked_r14[r14_bank_number(ARM_CPU_MODE_IR= Q)]; + env->xregs[17] =3D env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)]; + } + + if (mode =3D=3D ARM_CPU_MODE_SVC) { + env->xregs[18] =3D env->regs[14]; + env->xregs[19] =3D env->regs[13]; + } else { + env->xregs[18] =3D env->banked_r14[r14_bank_number(ARM_CPU_MODE_SV= C)]; + env->xregs[19] =3D env->banked_r13[bank_number(ARM_CPU_MODE_SVC)]; + } + + if (mode =3D=3D ARM_CPU_MODE_ABT) { + env->xregs[20] =3D env->regs[14]; + env->xregs[21] =3D env->regs[13]; + } else { + env->xregs[20] =3D env->banked_r14[r14_bank_number(ARM_CPU_MODE_AB= T)]; + env->xregs[21] =3D env->banked_r13[bank_number(ARM_CPU_MODE_ABT)]; + } + + if (mode =3D=3D ARM_CPU_MODE_UND) { + env->xregs[22] =3D env->regs[14]; + env->xregs[23] =3D env->regs[13]; + } else { + env->xregs[22] =3D env->banked_r14[r14_bank_number(ARM_CPU_MODE_UN= D)]; + env->xregs[23] =3D env->banked_r13[bank_number(ARM_CPU_MODE_UND)]; + } + + /* + * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in F= IQ + * mode, then we can copy from r8-r14. Otherwise, we copy from the + * FIQ bank for r8-r14. + */ + if (mode =3D=3D ARM_CPU_MODE_FIQ) { + for (i =3D 24; i < 31; i++) { + env->xregs[i] =3D env->regs[i - 16]; /* X[24:30] <- R[8:14] = */ + } + } else { + for (i =3D 24; i < 29; i++) { + env->xregs[i] =3D env->fiq_regs[i - 24]; + } + env->xregs[29] =3D env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)]; + env->xregs[30] =3D env->banked_r14[r14_bank_number(ARM_CPU_MODE_FI= Q)]; + } + + env->pc =3D env->regs[15]; +} + +/* + * Function used to synchronize QEMU's AArch32 register set with AArch64 + * register set. This is necessary when switching between AArch32 and AAr= ch64 + * execution state. + */ +void aarch64_sync_64_to_32(CPUARMState *env) +{ + int i; + uint32_t mode =3D env->uncached_cpsr & CPSR_M; + + /* We can blanket copy X[0:7] to R[0:7] */ + for (i =3D 0; i < 8; i++) { + env->regs[i] =3D env->xregs[i]; + } + + /* + * Unless we are in FIQ mode, r8-r12 come from the user registers x8-x= 12. + * Otherwise, we copy x8-x12 into the banked user regs. + */ + if (mode =3D=3D ARM_CPU_MODE_FIQ) { + for (i =3D 8; i < 13; i++) { + env->usr_regs[i - 8] =3D env->xregs[i]; + } + } else { + for (i =3D 8; i < 13; i++) { + env->regs[i] =3D env->xregs[i]; + } + } + + /* + * Registers r13 & r14 depend on the current mode. + * If we are in a given mode, we copy the corresponding x registers to= r13 + * and r14. Otherwise, we copy the x register to the banked r13 and r= 14 + * for the mode. + */ + if (mode =3D=3D ARM_CPU_MODE_USR || mode =3D=3D ARM_CPU_MODE_SYS) { + env->regs[13] =3D env->xregs[13]; + env->regs[14] =3D env->xregs[14]; + } else { + env->banked_r13[bank_number(ARM_CPU_MODE_USR)] =3D env->xregs[13]; + + /* + * HYP is an exception in that it does not have its own banked r14= but + * shares the USR r14 + */ + if (mode =3D=3D ARM_CPU_MODE_HYP) { + env->regs[14] =3D env->xregs[14]; + } else { + env->banked_r14[r14_bank_number(ARM_CPU_MODE_USR)] =3D env->xr= egs[14]; + } + } + + if (mode =3D=3D ARM_CPU_MODE_HYP) { + env->regs[13] =3D env->xregs[15]; + } else { + env->banked_r13[bank_number(ARM_CPU_MODE_HYP)] =3D env->xregs[15]; + } + + if (mode =3D=3D ARM_CPU_MODE_IRQ) { + env->regs[14] =3D env->xregs[16]; + env->regs[13] =3D env->xregs[17]; + } else { + env->banked_r14[r14_bank_number(ARM_CPU_MODE_IRQ)] =3D env->xregs[= 16]; + env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)] =3D env->xregs[17]; + } + + if (mode =3D=3D ARM_CPU_MODE_SVC) { + env->regs[14] =3D env->xregs[18]; + env->regs[13] =3D env->xregs[19]; + } else { + env->banked_r14[r14_bank_number(ARM_CPU_MODE_SVC)] =3D env->xregs[= 18]; + env->banked_r13[bank_number(ARM_CPU_MODE_SVC)] =3D env->xregs[19]; + } + + if (mode =3D=3D ARM_CPU_MODE_ABT) { + env->regs[14] =3D env->xregs[20]; + env->regs[13] =3D env->xregs[21]; + } else { + env->banked_r14[r14_bank_number(ARM_CPU_MODE_ABT)] =3D env->xregs[= 20]; + env->banked_r13[bank_number(ARM_CPU_MODE_ABT)] =3D env->xregs[21]; + } + + if (mode =3D=3D ARM_CPU_MODE_UND) { + env->regs[14] =3D env->xregs[22]; + env->regs[13] =3D env->xregs[23]; + } else { + env->banked_r14[r14_bank_number(ARM_CPU_MODE_UND)] =3D env->xregs[= 22]; + env->banked_r13[bank_number(ARM_CPU_MODE_UND)] =3D env->xregs[23]; + } + + /* + * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in F= IQ + * mode, then we can copy to r8-r14. Otherwise, we copy to the + * FIQ bank for r8-r14. + */ + if (mode =3D=3D ARM_CPU_MODE_FIQ) { + for (i =3D 24; i < 31; i++) { + env->regs[i - 16] =3D env->xregs[i]; /* X[24:30] -> R[8:14] = */ + } + } else { + for (i =3D 24; i < 29; i++) { + env->fiq_regs[i - 24] =3D env->xregs[i]; + } + env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)] =3D env->xregs[29]; + env->banked_r14[r14_bank_number(ARM_CPU_MODE_FIQ)] =3D env->xregs[= 30]; + } + + env->regs[15] =3D env->pc; +} diff --git a/target/arm/cpu-user.c b/target/arm/cpu-user.c index a72b7f5703..0225089e46 100644 --- a/target/arm/cpu-user.c +++ b/target/arm/cpu-user.c @@ -22,3 +22,14 @@ void switch_mode(CPUARMState *env, int mode) cpu_abort(CPU(cpu), "Tried to switch out of user mode\n"); } } + +void aarch64_sync_64_to_32(CPUARMState *env) +{ + g_assert_not_reached(); +} + +uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, + uint32_t cur_el, bool secure) +{ + return 1; +} diff --git a/target/arm/tcg/helper.c b/target/arm/tcg/helper.c index a93863152a..03dee5b447 100644 --- a/target/arm/tcg/helper.c +++ b/target/arm/tcg/helper.c @@ -658,22 +658,10 @@ uint32_t HELPER(rbit)(uint32_t x) return revbit32(x); } =20 -#ifdef CONFIG_USER_ONLY +#ifndef CONFIG_USER_ONLY =20 -uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, - uint32_t cur_el, bool secure) -{ - return 1; -} - -void aarch64_sync_64_to_32(CPUARMState *env) -{ - g_assert_not_reached(); -} - -#else - -/* Physical Interrupt Target EL Lookup Table +/* + * Physical Interrupt Target EL Lookup Table * * [ From ARM ARM section G1.13.4 (Table G1-15) ] * @@ -822,220 +810,6 @@ void arm_log_exception(int idx) } } =20 -/* - * Function used to synchronize QEMU's AArch64 register set with AArch32 - * register set. This is necessary when switching between AArch32 and AAr= ch64 - * execution state. - */ -void aarch64_sync_32_to_64(CPUARMState *env) -{ - int i; - uint32_t mode =3D env->uncached_cpsr & CPSR_M; - - /* We can blanket copy R[0:7] to X[0:7] */ - for (i =3D 0; i < 8; i++) { - env->xregs[i] =3D env->regs[i]; - } - - /* - * Unless we are in FIQ mode, x8-x12 come from the user registers r8-r= 12. - * Otherwise, they come from the banked user regs. - */ - if (mode =3D=3D ARM_CPU_MODE_FIQ) { - for (i =3D 8; i < 13; i++) { - env->xregs[i] =3D env->usr_regs[i - 8]; - } - } else { - for (i =3D 8; i < 13; i++) { - env->xregs[i] =3D env->regs[i]; - } - } - - /* - * Registers x13-x23 are the various mode SP and FP registers. Registe= rs - * r13 and r14 are only copied if we are in that mode, otherwise we co= py - * from the mode banked register. - */ - if (mode =3D=3D ARM_CPU_MODE_USR || mode =3D=3D ARM_CPU_MODE_SYS) { - env->xregs[13] =3D env->regs[13]; - env->xregs[14] =3D env->regs[14]; - } else { - env->xregs[13] =3D env->banked_r13[bank_number(ARM_CPU_MODE_USR)]; - /* HYP is an exception in that it is copied from r14 */ - if (mode =3D=3D ARM_CPU_MODE_HYP) { - env->xregs[14] =3D env->regs[14]; - } else { - env->xregs[14] =3D env->banked_r14[r14_bank_number(ARM_CPU_MOD= E_USR)]; - } - } - - if (mode =3D=3D ARM_CPU_MODE_HYP) { - env->xregs[15] =3D env->regs[13]; - } else { - env->xregs[15] =3D env->banked_r13[bank_number(ARM_CPU_MODE_HYP)]; - } - - if (mode =3D=3D ARM_CPU_MODE_IRQ) { - env->xregs[16] =3D env->regs[14]; - env->xregs[17] =3D env->regs[13]; - } else { - env->xregs[16] =3D env->banked_r14[r14_bank_number(ARM_CPU_MODE_IR= Q)]; - env->xregs[17] =3D env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)]; - } - - if (mode =3D=3D ARM_CPU_MODE_SVC) { - env->xregs[18] =3D env->regs[14]; - env->xregs[19] =3D env->regs[13]; - } else { - env->xregs[18] =3D env->banked_r14[r14_bank_number(ARM_CPU_MODE_SV= C)]; - env->xregs[19] =3D env->banked_r13[bank_number(ARM_CPU_MODE_SVC)]; - } - - if (mode =3D=3D ARM_CPU_MODE_ABT) { - env->xregs[20] =3D env->regs[14]; - env->xregs[21] =3D env->regs[13]; - } else { - env->xregs[20] =3D env->banked_r14[r14_bank_number(ARM_CPU_MODE_AB= T)]; - env->xregs[21] =3D env->banked_r13[bank_number(ARM_CPU_MODE_ABT)]; - } - - if (mode =3D=3D ARM_CPU_MODE_UND) { - env->xregs[22] =3D env->regs[14]; - env->xregs[23] =3D env->regs[13]; - } else { - env->xregs[22] =3D env->banked_r14[r14_bank_number(ARM_CPU_MODE_UN= D)]; - env->xregs[23] =3D env->banked_r13[bank_number(ARM_CPU_MODE_UND)]; - } - - /* - * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in F= IQ - * mode, then we can copy from r8-r14. Otherwise, we copy from the - * FIQ bank for r8-r14. - */ - if (mode =3D=3D ARM_CPU_MODE_FIQ) { - for (i =3D 24; i < 31; i++) { - env->xregs[i] =3D env->regs[i - 16]; /* X[24:30] <- R[8:14] = */ - } - } else { - for (i =3D 24; i < 29; i++) { - env->xregs[i] =3D env->fiq_regs[i - 24]; - } - env->xregs[29] =3D env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)]; - env->xregs[30] =3D env->banked_r14[r14_bank_number(ARM_CPU_MODE_FI= Q)]; - } - - env->pc =3D env->regs[15]; -} - -/* - * Function used to synchronize QEMU's AArch32 register set with AArch64 - * register set. This is necessary when switching between AArch32 and AAr= ch64 - * execution state. - */ -void aarch64_sync_64_to_32(CPUARMState *env) -{ - int i; - uint32_t mode =3D env->uncached_cpsr & CPSR_M; - - /* We can blanket copy X[0:7] to R[0:7] */ - for (i =3D 0; i < 8; i++) { - env->regs[i] =3D env->xregs[i]; - } - - /* - * Unless we are in FIQ mode, r8-r12 come from the user registers x8-x= 12. - * Otherwise, we copy x8-x12 into the banked user regs. - */ - if (mode =3D=3D ARM_CPU_MODE_FIQ) { - for (i =3D 8; i < 13; i++) { - env->usr_regs[i - 8] =3D env->xregs[i]; - } - } else { - for (i =3D 8; i < 13; i++) { - env->regs[i] =3D env->xregs[i]; - } - } - - /* - * Registers r13 & r14 depend on the current mode. - * If we are in a given mode, we copy the corresponding x registers to= r13 - * and r14. Otherwise, we copy the x register to the banked r13 and r= 14 - * for the mode. - */ - if (mode =3D=3D ARM_CPU_MODE_USR || mode =3D=3D ARM_CPU_MODE_SYS) { - env->regs[13] =3D env->xregs[13]; - env->regs[14] =3D env->xregs[14]; - } else { - env->banked_r13[bank_number(ARM_CPU_MODE_USR)] =3D env->xregs[13]; - - /* - * HYP is an exception in that it does not have its own banked r14= but - * shares the USR r14 - */ - if (mode =3D=3D ARM_CPU_MODE_HYP) { - env->regs[14] =3D env->xregs[14]; - } else { - env->banked_r14[r14_bank_number(ARM_CPU_MODE_USR)] =3D env->xr= egs[14]; - } - } - - if (mode =3D=3D ARM_CPU_MODE_HYP) { - env->regs[13] =3D env->xregs[15]; - } else { - env->banked_r13[bank_number(ARM_CPU_MODE_HYP)] =3D env->xregs[15]; - } - - if (mode =3D=3D ARM_CPU_MODE_IRQ) { - env->regs[14] =3D env->xregs[16]; - env->regs[13] =3D env->xregs[17]; - } else { - env->banked_r14[r14_bank_number(ARM_CPU_MODE_IRQ)] =3D env->xregs[= 16]; - env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)] =3D env->xregs[17]; - } - - if (mode =3D=3D ARM_CPU_MODE_SVC) { - env->regs[14] =3D env->xregs[18]; - env->regs[13] =3D env->xregs[19]; - } else { - env->banked_r14[r14_bank_number(ARM_CPU_MODE_SVC)] =3D env->xregs[= 18]; - env->banked_r13[bank_number(ARM_CPU_MODE_SVC)] =3D env->xregs[19]; - } - - if (mode =3D=3D ARM_CPU_MODE_ABT) { - env->regs[14] =3D env->xregs[20]; - env->regs[13] =3D env->xregs[21]; - } else { - env->banked_r14[r14_bank_number(ARM_CPU_MODE_ABT)] =3D env->xregs[= 20]; - env->banked_r13[bank_number(ARM_CPU_MODE_ABT)] =3D env->xregs[21]; - } - - if (mode =3D=3D ARM_CPU_MODE_UND) { - env->regs[14] =3D env->xregs[22]; - env->regs[13] =3D env->xregs[23]; - } else { - env->banked_r14[r14_bank_number(ARM_CPU_MODE_UND)] =3D env->xregs[= 22]; - env->banked_r13[bank_number(ARM_CPU_MODE_UND)] =3D env->xregs[23]; - } - - /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in F= IQ - * mode, then we can copy to r8-r14. Otherwise, we copy to the - * FIQ bank for r8-r14. - */ - if (mode =3D=3D ARM_CPU_MODE_FIQ) { - for (i =3D 24; i < 31; i++) { - env->regs[i - 16] =3D env->xregs[i]; /* X[24:30] -> R[8:14] = */ - } - } else { - for (i =3D 24; i < 29; i++) { - env->fiq_regs[i - 24] =3D env->xregs[i]; - } - env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)] =3D env->xregs[29]; - env->banked_r14[r14_bank_number(ARM_CPU_MODE_FIQ)] =3D env->xregs[= 30]; - } - - env->regs[15] =3D env->pc; -} - static void take_aarch32_exception(CPUARMState *env, int new_mode, uint32_t mask, uint32_t offset, uint32_t newpc) --=20 2.26.2