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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id i11sm8271154otp.76.2021.03.17.08.34.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Mar 2021 08:34:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QftnUci9yl2tdGuAjLKAsqWS6tnyLkghXArP9adcKcM=; b=oWhUA+GP6mq0YVf9cUigSurX/ccWlrdgxolQiezEK+Pv1qibsW833drhbuZ+fo5rLm ZsOT3S/9xA4XHgbs+XVm/n6BxoSkdRsX1XiWHnuniaene0WAikqBfJe2Guqxb8Sfw+7X Z0JoWcYOYcfarS38Iuew18lHX8cCvuPPHDvYK6Wojopu+DKYW9DSVuA4jiSPd0sUBGyc aKDhH9dLA1ls45RHhIYYKR/bRWSxfEOEhXOj7EUIvxq4Kw7F6U0TB2u1GhFiyDe1/RU2 /540vC9RPi/KJJc4ggYMFahx8ZeiNobdTJaLyF7jFSyfvyHELq9HPJIMgVPwnEspnpl3 r5lg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QftnUci9yl2tdGuAjLKAsqWS6tnyLkghXArP9adcKcM=; b=X/YV5xJd0xfIAN9+a4ex79haeecpOPoCHVHxjuuXd6+VzDV5KGJTIZW2uZ3/gaXIEC ml1SMbSV77FphzgfYWlddmhsVo7TvqlhLYqTckV0CUdPLT3hNGVvb2DPp7HuZhsTqu5g 656dmPU0S8XYEQ38rdEOBG4WFv/jeVOc21e11MuJhJUCIWIP0fQmcJiQ8UExfy+xbTn+ 74aLIbN21WXc57tZ8XZU3LzasQYkyAQqagN5r1eoNQPNAMXMWo0H3BgOjbGn6fjclDHW fEAXDwX0QNHeJGocIzsHQMFFDyVxluf0ZyWSJV3FvUyssBOSlvWE1mDpRa31l9px0fec W3AQ== X-Gm-Message-State: AOAM531o4L9ly5NMH3tUm/U8OJAIEU+Q0ofhGOsQJTJItfqT7+tPfgBD sV5d7tRD4Bkkh/BK3ZTFxbPViHUXk5qbKfNl X-Google-Smtp-Source: ABdhPJyM6XI0KG80ZM4EqwCkVONOpgJR5dxllyiNKHTMk58bNdp2E9TJt3jC68syU8QZWeznH5U+bg== X-Received: by 2002:a9d:6305:: with SMTP id q5mr3682009otk.10.1615995287036; Wed, 17 Mar 2021 08:34:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 01/38] tcg/tci: Remove ifdefs for TCG_TARGET_HAS_ext32[us]_i64 Date: Wed, 17 Mar 2021 09:34:07 -0600 Message-Id: <20210317153444.310566-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210317153444.310566-1-richard.henderson@linaro.org> References: <20210317153444.310566-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32a; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Stefan Weil Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" These operations are always available under different names: INDEX_op_ext_i32_i64 and INDEX_op_extu_i32_i64, so we remove no code with the ifdef. Reviewed-by: Stefan Weil Signed-off-by: Richard Henderson --- tcg/tci.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 3ccd30c39c..6a0bdf028b 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -774,17 +774,13 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, continue; } break; -#if TCG_TARGET_HAS_ext32s_i64 case INDEX_op_ext32s_i64: -#endif case INDEX_op_ext_i32_i64: t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (int32_t)t1); break; -#if TCG_TARGET_HAS_ext32u_i64 case INDEX_op_ext32u_i64: -#endif case INDEX_op_extu_i32_i64: t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); --=20 2.25.1 From nobody Wed Nov 19 12:23:30 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1615996423; cv=none; d=zohomail.com; s=zohoarc; b=JjBKtzw0hdPQwGOF+oP8bINIt8ZoNNi1/l+pIkjB0YvYvtLQhPHlgv3DnD2Bp7aJVvxj1Kx3ku37ex0YjvQf/Z+g3cDYu2oFsTscBXVZo0wer/BLGqYHztESH3gCoMUhPjvw+cA6Mdo+L3F9qpdWJoSrE5QvdnzFhEuRzykZKiI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615996423; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ruHlP0Os3wjw5VxiF3cEbfCQgqFVOBkfP7egc8QHYeI=; b=hKNS/vK47V9jlQwbS1pzQ5HxBWD6kW6ecK7DWbOrfuEAvjIrjQLscpMH81gCblQYLa/mIwpoK2uax1b06UHiMz0Wz1CX6m8A8EbdLFZRwu2qGle9Q5FRuO3IOp0tNZCLYI9eFJLZKRCuSRJ0sKCCOalKjxUgVXQkwgVLNmoSUHw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1615996423463937.147907807503; Wed, 17 Mar 2021 08:53:43 -0700 (PDT) Received: from localhost ([::1]:50562 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lMYUQ-0008VQ-5g for importer@patchew.org; Wed, 17 Mar 2021 11:53:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49780) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lMYCK-0004xY-56 for qemu-devel@nongnu.org; Wed, 17 Mar 2021 11:35:00 -0400 Received: from mail-ot1-x32d.google.com ([2607:f8b0:4864:20::32d]:45828) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lMYCA-00074Q-Cy for qemu-devel@nongnu.org; Wed, 17 Mar 2021 11:34:59 -0400 Received: by mail-ot1-x32d.google.com with SMTP id f73-20020a9d03cf0000b02901b4d889bce0so2145266otf.12 for ; Wed, 17 Mar 2021 08:34:48 -0700 (PDT) Received: from localhost.localdomain (fixed-187-189-51-144.totalplay.net. [187.189.51.144]) by smtp.gmail.com with ESMTPSA id i11sm8271154otp.76.2021.03.17.08.34.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Mar 2021 08:34:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ruHlP0Os3wjw5VxiF3cEbfCQgqFVOBkfP7egc8QHYeI=; b=v4u4BBvPyM/CdVwkq2Top/DdQhH5VzRtuToVLvAd1pRUC+oDX4SudHhEL9KcruJlb9 YhX6XkMNFWYiNlJBtvECw2acfWtmZeuSLc3nJJTBDbxsDjImqjQiPNOT4o8kENrudE4J Qr6bxii2VZ3m8s64K8mPGULRVHSW0eJLK/M3H9Cs/dFiQrMNi7e4a6nAeBCCQEORfcR2 aJtISqdhGlv7o68O7wvnKfAsaxz2+LdE543R8N5BhjVnGy6dE+CCNVSg+OKd2SDqch3/ Dcfr4lbc3kQ4CwH6H0pQ9rt1oRWxaajcB5xlW1CGegBQUCwxO2nt+tR/AQvFBIYk7bNr Y6zw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ruHlP0Os3wjw5VxiF3cEbfCQgqFVOBkfP7egc8QHYeI=; b=VemC/HFIza4wpPnO8m06gJmjOvnUIieUIQcD+wkWLP4zhOOMrQQg8wIgL5uUdzWld9 RZ27MILUNdw/VqGrU9CqzkBQXFlyTZSjj3fnMhSAUCfuHrCAwfoSbJMnRioCfSdJaGMN QtUt1Q6KcI2meWErGlh4a03Ufs/9Lg6zZCfm939Q6YD06I5sPGPQJ34OQ88qAPKBgrIB 5qZKqfsP/H3+oIyDwBTNu5kaPYwSKGOeTXdpaskPz7xqw7krTf98nz3pUnNxTsPHE5MV kf8TDTSNMbSPxDRl2+IZAOasNp22slSxdXijej3GmJyALrBQPpjCr+k/ixfSOa7meBCC prBQ== X-Gm-Message-State: AOAM531YqY/jNOyvLYUC8EGOE6oLwePxm2TNm52CRGAKDh9s70/S8dUD sC29tEUfnO4H3GxKjjEw1QLwb9Ip9QqTA+ZI X-Google-Smtp-Source: ABdhPJw/pbhnpr/YSYcJvqsOV/WUo8FWfX6tClRueuhW+TWpJhUfHBHUixmdF8FG9pClcb5CRwPkJw== X-Received: by 2002:a9d:6e87:: with SMTP id a7mr3735615otr.298.1615995288026; Wed, 17 Mar 2021 08:34:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 02/38] tcg/tci: Rename tci_read_r to tci_read_rval Date: Wed, 17 Mar 2021 09:34:08 -0600 Message-Id: <20210317153444.310566-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210317153444.310566-1-richard.henderson@linaro.org> References: <20210317153444.310566-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32d; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) In the next patches, we want to use tci_read_r to return the raw register number. So rename the existing function, which returns the register value, to tci_read_rval. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/tci.c | 192 +++++++++++++++++++++++++++--------------------------- 1 file changed, 96 insertions(+), 96 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 6a0bdf028b..6d6a5510da 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -119,7 +119,7 @@ static uint64_t tci_read_i64(const uint8_t **tb_ptr) =20 /* Read indexed register (native size) from bytecode. */ static tcg_target_ulong -tci_read_r(const tcg_target_ulong *regs, const uint8_t **tb_ptr) +tci_read_rval(const tcg_target_ulong *regs, const uint8_t **tb_ptr) { tcg_target_ulong value =3D tci_read_reg(regs, **tb_ptr); *tb_ptr +=3D 1; @@ -131,15 +131,15 @@ tci_read_r(const tcg_target_ulong *regs, const uint8_= t **tb_ptr) static uint64_t tci_read_r64(const tcg_target_ulong *regs, const uint8_t **tb_ptr) { - uint32_t low =3D tci_read_r(regs, tb_ptr); - return tci_uint64(tci_read_r(regs, tb_ptr), low); + uint32_t low =3D tci_read_rval(regs, tb_ptr); + return tci_uint64(tci_read_rval(regs, tb_ptr), low); } #elif TCG_TARGET_REG_BITS =3D=3D 64 /* Read indexed register (64 bit) from bytecode. */ static uint64_t tci_read_r64(const tcg_target_ulong *regs, const uint8_t **tb_ptr) { - return tci_read_r(regs, tb_ptr); + return tci_read_rval(regs, tb_ptr); } #endif =20 @@ -147,9 +147,9 @@ static uint64_t tci_read_r64(const tcg_target_ulong *re= gs, static target_ulong tci_read_ulong(const tcg_target_ulong *regs, const uint8_t **tb_ptr) { - target_ulong taddr =3D tci_read_r(regs, tb_ptr); + target_ulong taddr =3D tci_read_rval(regs, tb_ptr); #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS - taddr +=3D (uint64_t)tci_read_r(regs, tb_ptr) << 32; + taddr +=3D (uint64_t)tci_read_rval(regs, tb_ptr) << 32; #endif return taddr; } @@ -365,8 +365,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, continue; case INDEX_op_setcond_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); condition =3D *tb_ptr++; tci_write_reg(regs, t0, tci_compare32(t1, t2, condition)); break; @@ -381,15 +381,15 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, #elif TCG_TARGET_REG_BITS =3D=3D 64 case INDEX_op_setcond_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); condition =3D *tb_ptr++; tci_write_reg(regs, t0, tci_compare64(t1, t2, condition)); break; #endif CASE_32_64(mov) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, t1); break; case INDEX_op_tci_movi_i32: @@ -402,51 +402,51 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 CASE_32_64(ld8u) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); tci_write_reg(regs, t0, *(uint8_t *)(t1 + t2)); break; CASE_32_64(ld8s) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); tci_write_reg(regs, t0, *(int8_t *)(t1 + t2)); break; CASE_32_64(ld16u) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); tci_write_reg(regs, t0, *(uint16_t *)(t1 + t2)); break; CASE_32_64(ld16s) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); tci_write_reg(regs, t0, *(int16_t *)(t1 + t2)); break; case INDEX_op_ld_i32: CASE_64(ld32u) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); tci_write_reg(regs, t0, *(uint32_t *)(t1 + t2)); break; CASE_32_64(st8) - t0 =3D tci_read_r(regs, &tb_ptr); - t1 =3D tci_read_r(regs, &tb_ptr); + t0 =3D tci_read_rval(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); *(uint8_t *)(t1 + t2) =3D t0; break; CASE_32_64(st16) - t0 =3D tci_read_r(regs, &tb_ptr); - t1 =3D tci_read_r(regs, &tb_ptr); + t0 =3D tci_read_rval(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); *(uint16_t *)(t1 + t2) =3D t0; break; case INDEX_op_st_i32: CASE_64(st32) - t0 =3D tci_read_r(regs, &tb_ptr); - t1 =3D tci_read_r(regs, &tb_ptr); + t0 =3D tci_read_rval(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); *(uint32_t *)(t1 + t2) =3D t0; break; @@ -455,38 +455,38 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 CASE_32_64(add) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, t1 + t2); break; CASE_32_64(sub) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, t1 - t2); break; CASE_32_64(mul) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, t1 * t2); break; CASE_32_64(and) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, t1 & t2); break; CASE_32_64(or) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, t1 | t2); break; CASE_32_64(xor) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, t1 ^ t2); break; =20 @@ -494,26 +494,26 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 case INDEX_op_div_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (int32_t)t1 / (int32_t)t2); break; case INDEX_op_divu_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (uint32_t)t1 / (uint32_t)t2); break; case INDEX_op_rem_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (int32_t)t1 % (int32_t)t2); break; case INDEX_op_remu_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (uint32_t)t1 % (uint32_t)t2); break; =20 @@ -521,41 +521,41 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 case INDEX_op_shl_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (uint32_t)t1 << (t2 & 31)); break; case INDEX_op_shr_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (uint32_t)t1 >> (t2 & 31)); break; case INDEX_op_sar_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (int32_t)t1 >> (t2 & 31)); break; #if TCG_TARGET_HAS_rot_i32 case INDEX_op_rotl_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, rol32(t1, t2 & 31)); break; case INDEX_op_rotr_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, ror32(t1, t2 & 31)); break; #endif #if TCG_TARGET_HAS_deposit_i32 case INDEX_op_deposit_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tmp16 =3D *tb_ptr++; tmp8 =3D *tb_ptr++; tmp32 =3D (((1 << tmp8) - 1) << tmp16); @@ -563,8 +563,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, break; #endif case INDEX_op_brcond_i32: - t0 =3D tci_read_r(regs, &tb_ptr); - t1 =3D tci_read_r(regs, &tb_ptr); + t0 =3D tci_read_rval(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); condition =3D *tb_ptr++; label =3D tci_read_label(&tb_ptr); if (tci_compare32(t0, t1, condition)) { @@ -602,64 +602,64 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, case INDEX_op_mulu2_i32: t0 =3D *tb_ptr++; t1 =3D *tb_ptr++; - t2 =3D tci_read_r(regs, &tb_ptr); - tmp64 =3D (uint32_t)tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); + tmp64 =3D (uint32_t)tci_read_rval(regs, &tb_ptr); tci_write_reg64(regs, t1, t0, (uint32_t)t2 * tmp64); break; #endif /* TCG_TARGET_REG_BITS =3D=3D 32 */ #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 CASE_32_64(ext8s) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (int8_t)t1); break; #endif #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 CASE_32_64(ext16s) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (int16_t)t1); break; #endif #if TCG_TARGET_HAS_ext8u_i32 || TCG_TARGET_HAS_ext8u_i64 CASE_32_64(ext8u) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (uint8_t)t1); break; #endif #if TCG_TARGET_HAS_ext16u_i32 || TCG_TARGET_HAS_ext16u_i64 CASE_32_64(ext16u) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (uint16_t)t1); break; #endif #if TCG_TARGET_HAS_bswap16_i32 || TCG_TARGET_HAS_bswap16_i64 CASE_32_64(bswap16) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, bswap16(t1)); break; #endif #if TCG_TARGET_HAS_bswap32_i32 || TCG_TARGET_HAS_bswap32_i64 CASE_32_64(bswap32) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, bswap32(t1)); break; #endif #if TCG_TARGET_HAS_not_i32 || TCG_TARGET_HAS_not_i64 CASE_32_64(not) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, ~t1); break; #endif #if TCG_TARGET_HAS_neg_i32 || TCG_TARGET_HAS_neg_i64 CASE_32_64(neg) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, -t1); break; #endif @@ -674,19 +674,19 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 case INDEX_op_ld32s_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); tci_write_reg(regs, t0, *(int32_t *)(t1 + t2)); break; case INDEX_op_ld_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); tci_write_reg(regs, t0, *(uint64_t *)(t1 + t2)); break; case INDEX_op_st_i64: - t0 =3D tci_read_r(regs, &tb_ptr); - t1 =3D tci_read_r(regs, &tb_ptr); + t0 =3D tci_read_rval(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); *(uint64_t *)(t1 + t2) =3D t0; break; @@ -695,26 +695,26 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 case INDEX_op_div_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (int64_t)t1 / (int64_t)t2); break; case INDEX_op_divu_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (uint64_t)t1 / (uint64_t)t2); break; case INDEX_op_rem_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (int64_t)t1 % (int64_t)t2); break; case INDEX_op_remu_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (uint64_t)t1 % (uint64_t)t2); break; =20 @@ -722,41 +722,41 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 case INDEX_op_shl_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, t1 << (t2 & 63)); break; case INDEX_op_shr_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, t1 >> (t2 & 63)); break; case INDEX_op_sar_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, ((int64_t)t1 >> (t2 & 63))); break; #if TCG_TARGET_HAS_rot_i64 case INDEX_op_rotl_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, rol64(t1, t2 & 63)); break; case INDEX_op_rotr_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, ror64(t1, t2 & 63)); break; #endif #if TCG_TARGET_HAS_deposit_i64 case INDEX_op_deposit_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tmp16 =3D *tb_ptr++; tmp8 =3D *tb_ptr++; tmp64 =3D (((1ULL << tmp8) - 1) << tmp16); @@ -764,8 +764,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, break; #endif case INDEX_op_brcond_i64: - t0 =3D tci_read_r(regs, &tb_ptr); - t1 =3D tci_read_r(regs, &tb_ptr); + t0 =3D tci_read_rval(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); condition =3D *tb_ptr++; label =3D tci_read_label(&tb_ptr); if (tci_compare64(t0, t1, condition)) { @@ -777,19 +777,19 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, case INDEX_op_ext32s_i64: case INDEX_op_ext_i32_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (int32_t)t1); break; case INDEX_op_ext32u_i64: case INDEX_op_extu_i32_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (uint32_t)t1); break; #if TCG_TARGET_HAS_bswap64_i64 case INDEX_op_bswap64_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, bswap64(t1)); break; #endif @@ -896,7 +896,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, } break; case INDEX_op_qemu_st_i32: - t0 =3D tci_read_r(regs, &tb_ptr); + t0 =3D tci_read_rval(regs, &tb_ptr); taddr =3D tci_read_ulong(regs, &tb_ptr); oi =3D tci_read_i(&tb_ptr); switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) { --=20 2.25.1 From nobody Wed Nov 19 12:23:30 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id i11sm8271154otp.76.2021.03.17.08.34.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Mar 2021 08:34:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xde/dipL8afwqBBE42AhxwA5Vd3znbSEJPtj+mWbEUw=; b=us9o1VSMM5VlvFbh8OCtIDJJy1IWERVAHFHe+C/deBvpIJfLmPRHPKI3sB/cLF3HMV lOJiLBY2MlULnN+Zjn/T4eEK2yAykrt4+EfZX6czJFzum5E4qpnJIdgfZtrv/CyoJ2oR QcEizAG/w+xZpCkxyWZD2R4qR+rtWBHjQFUlgbcl98kYqG3h5MQIoQzkYdAN1aiRJoJl I3JW9Uq1IOZBJF60rPT3wfAPqW/CHs64eJF1yKolQd41ad0Sj79ghLeBuv6lzqHPUiAF QGY2z0tfGIK5ajVHouFiTexci2DGV/jsBWpJTiVbfQMnpp4EBrVAexb4HeThH3iZUBMt GHBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xde/dipL8afwqBBE42AhxwA5Vd3znbSEJPtj+mWbEUw=; b=uBV4iZk5mDhjcXnZACQ0gxKCEUvxfFRo0MTRIFgRaeBOklrhqppFJaOQUu9lbtIHpM hFVriAXEZGEz6Y6Y3m1WoxDCXTRDw2tEZrx/JJAYz6FPPZFxwaPzUa7utYGCvm66ERYk +5S+JMz5smoVB/DRDCSOAvmCXTvDe57BU5mpE9Ceio3MSah0MUhTiuAqQiffFI9cXhHi 70wP7YdlvUfmHOrktPEtigWRVN00WZcbR/dgTuqeABb8fN1rGxm+M6W9OfDftTcilDwY YvHKIOefcDnSOwYY0ydDKgBHSb35ajM7WyJL2qrFfo0LHSsVTRxpCTKJeAQD48PS6WGl S2HA== X-Gm-Message-State: AOAM531ktjGdsYQyO2bj8AZC8XuKQa1C9LryK2eceGM2MT08sDqV3k4b fJIv/SwSxrpgMs1JHAtr7fVJHAC+dG72rVxe X-Google-Smtp-Source: ABdhPJyau4TIjUcqYEDpH+Y6sDNEn+nqI0A5obmcQ+q+KzpWN80xT+b7Nc5wCwZt+rLI4BMKrWs6LQ== X-Received: by 2002:aca:4b03:: with SMTP id y3mr1795834oia.78.1615995289049; Wed, 17 Mar 2021 08:34:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 03/38] tcg/tci: Split out tci_args_rrs Date: Wed, 17 Mar 2021 09:34:09 -0600 Message-Id: <20210317153444.310566-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210317153444.310566-1-richard.henderson@linaro.org> References: <20210317153444.310566-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::232; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x232.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Begin splitting out functions that do pure argument decode, without actually loading values from the register set. This means that decoding need not concern itself between input and output registers. We can assert that the register number is in range during decode, so that it is safe to simply dereference from regs[] later. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/tci.c | 111 ++++++++++++++++++++++++++++++++---------------------- 1 file changed, 67 insertions(+), 44 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 6d6a5510da..5acf5c38c3 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -83,6 +83,20 @@ static uint64_t tci_uint64(uint32_t high, uint32_t low) } #endif =20 +/* Read constant byte from bytecode. */ +static uint8_t tci_read_b(const uint8_t **tb_ptr) +{ + return *(tb_ptr[0]++); +} + +/* Read register number from bytecode. */ +static TCGReg tci_read_r(const uint8_t **tb_ptr) +{ + uint8_t regno =3D tci_read_b(tb_ptr); + tci_assert(regno < TCG_TARGET_NB_REGS); + return regno; +} + /* Read constant (native size) from bytecode. */ static tcg_target_ulong tci_read_i(const uint8_t **tb_ptr) { @@ -161,6 +175,23 @@ static tcg_target_ulong tci_read_label(const uint8_t *= *tb_ptr) return label; } =20 +/* + * Load sets of arguments all at once. The naming convention is: + * tci_args_ + * where arguments is a sequence of + * + * r =3D register + * s =3D signed ldst offset + */ + +static void tci_args_rrs(const uint8_t **tb_ptr, + TCGReg *r0, TCGReg *r1, int32_t *i2) +{ + *r0 =3D tci_read_r(tb_ptr); + *r1 =3D tci_read_r(tb_ptr); + *i2 =3D tci_read_s32(tb_ptr); +} + static bool tci_compare32(uint32_t u0, uint32_t u1, TCGCond condition) { bool result =3D false; @@ -311,6 +342,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, uint8_t op_size =3D tb_ptr[1]; const uint8_t *old_code_ptr =3D tb_ptr; #endif + TCGReg r0, r1; tcg_target_ulong t0; tcg_target_ulong t1; tcg_target_ulong t2; @@ -325,6 +357,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, uint64_t v64; #endif TCGMemOpIdx oi; + int32_t ofs; + void *ptr; =20 /* Skip opcode and size entry. */ tb_ptr +=3D 2; @@ -401,54 +435,46 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, /* Load/store operations (32 bit). */ =20 CASE_32_64(ld8u) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg(regs, t0, *(uint8_t *)(t1 + t2)); + tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + ptr =3D (void *)(regs[r1] + ofs); + regs[r0] =3D *(uint8_t *)ptr; break; CASE_32_64(ld8s) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg(regs, t0, *(int8_t *)(t1 + t2)); + tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + ptr =3D (void *)(regs[r1] + ofs); + regs[r0] =3D *(int8_t *)ptr; break; CASE_32_64(ld16u) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg(regs, t0, *(uint16_t *)(t1 + t2)); + tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + ptr =3D (void *)(regs[r1] + ofs); + regs[r0] =3D *(uint16_t *)ptr; break; CASE_32_64(ld16s) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg(regs, t0, *(int16_t *)(t1 + t2)); + tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + ptr =3D (void *)(regs[r1] + ofs); + regs[r0] =3D *(int16_t *)ptr; break; case INDEX_op_ld_i32: CASE_64(ld32u) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg(regs, t0, *(uint32_t *)(t1 + t2)); + tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + ptr =3D (void *)(regs[r1] + ofs); + regs[r0] =3D *(uint32_t *)ptr; break; CASE_32_64(st8) - t0 =3D tci_read_rval(regs, &tb_ptr); - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_s32(&tb_ptr); - *(uint8_t *)(t1 + t2) =3D t0; + tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + ptr =3D (void *)(regs[r1] + ofs); + *(uint8_t *)ptr =3D regs[r0]; break; CASE_32_64(st16) - t0 =3D tci_read_rval(regs, &tb_ptr); - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_s32(&tb_ptr); - *(uint16_t *)(t1 + t2) =3D t0; + tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + ptr =3D (void *)(regs[r1] + ofs); + *(uint16_t *)ptr =3D regs[r0]; break; case INDEX_op_st_i32: CASE_64(st32) - t0 =3D tci_read_rval(regs, &tb_ptr); - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_s32(&tb_ptr); - *(uint32_t *)(t1 + t2) =3D t0; + tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + ptr =3D (void *)(regs[r1] + ofs); + *(uint32_t *)ptr =3D regs[r0]; break; =20 /* Arithmetic operations (mixed 32/64 bit). */ @@ -673,22 +699,19 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, /* Load/store operations (64 bit). */ =20 case INDEX_op_ld32s_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg(regs, t0, *(int32_t *)(t1 + t2)); + tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + ptr =3D (void *)(regs[r1] + ofs); + regs[r0] =3D *(int32_t *)ptr; break; case INDEX_op_ld_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg(regs, t0, *(uint64_t *)(t1 + t2)); + tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + ptr =3D (void *)(regs[r1] + ofs); + regs[r0] =3D *(uint64_t *)ptr; break; case INDEX_op_st_i64: - t0 =3D tci_read_rval(regs, &tb_ptr); - t1 =3D tci_read_rval(regs, &tb_ptr); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32c; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/tci.c | 67 +++++++++++++++++++++++++------------------------------ 1 file changed, 31 insertions(+), 36 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 5acf5c38c3..e5aba3a9fa 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -184,6 +184,13 @@ static tcg_target_ulong tci_read_label(const uint8_t *= *tb_ptr) * s =3D signed ldst offset */ =20 +static void tci_args_rr(const uint8_t **tb_ptr, + TCGReg *r0, TCGReg *r1) +{ + *r0 =3D tci_read_r(tb_ptr); + *r1 =3D tci_read_r(tb_ptr); +} + static void tci_args_rrs(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, int32_t *i2) { @@ -422,9 +429,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, break; #endif CASE_32_64(mov) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + tci_args_rr(&tb_ptr, &r0, &r1); + regs[r0] =3D regs[r1]; break; case INDEX_op_tci_movi_i32: t0 =3D *tb_ptr++; @@ -635,58 +641,50 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, #endif /* TCG_TARGET_REG_BITS =3D=3D 32 */ #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 CASE_32_64(ext8s) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (int8_t)t1); + tci_args_rr(&tb_ptr, &r0, &r1); + regs[r0] =3D (int8_t)regs[r1]; break; #endif #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 CASE_32_64(ext16s) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (int16_t)t1); + tci_args_rr(&tb_ptr, &r0, &r1); + regs[r0] =3D (int16_t)regs[r1]; break; #endif #if TCG_TARGET_HAS_ext8u_i32 || TCG_TARGET_HAS_ext8u_i64 CASE_32_64(ext8u) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (uint8_t)t1); + tci_args_rr(&tb_ptr, &r0, &r1); + regs[r0] =3D (uint8_t)regs[r1]; break; #endif #if TCG_TARGET_HAS_ext16u_i32 || TCG_TARGET_HAS_ext16u_i64 CASE_32_64(ext16u) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (uint16_t)t1); + tci_args_rr(&tb_ptr, &r0, &r1); + regs[r0] =3D (uint16_t)regs[r1]; break; #endif #if TCG_TARGET_HAS_bswap16_i32 || TCG_TARGET_HAS_bswap16_i64 CASE_32_64(bswap16) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, bswap16(t1)); + tci_args_rr(&tb_ptr, &r0, &r1); + regs[r0] =3D bswap16(regs[r1]); break; #endif #if TCG_TARGET_HAS_bswap32_i32 || TCG_TARGET_HAS_bswap32_i64 CASE_32_64(bswap32) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, bswap32(t1)); + tci_args_rr(&tb_ptr, &r0, &r1); + regs[r0] =3D bswap32(regs[r1]); break; #endif #if TCG_TARGET_HAS_not_i32 || TCG_TARGET_HAS_not_i64 CASE_32_64(not) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, ~t1); + tci_args_rr(&tb_ptr, &r0, &r1); + regs[r0] =3D ~regs[r1]; break; #endif #if TCG_TARGET_HAS_neg_i32 || TCG_TARGET_HAS_neg_i64 CASE_32_64(neg) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, -t1); + tci_args_rr(&tb_ptr, &r0, &r1); + regs[r0] =3D -regs[r1]; break; #endif #if TCG_TARGET_REG_BITS =3D=3D 64 @@ -799,21 +797,18 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, break; case INDEX_op_ext32s_i64: case INDEX_op_ext_i32_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (int32_t)t1); + tci_args_rr(&tb_ptr, &r0, &r1); + regs[r0] =3D (int32_t)regs[r1]; break; case INDEX_op_ext32u_i64: case INDEX_op_extu_i32_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (uint32_t)t1); + tci_args_rr(&tb_ptr, &r0, &r1); + regs[r0] =3D (uint32_t)regs[r1]; break; #if TCG_TARGET_HAS_bswap64_i64 case INDEX_op_bswap64_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, bswap64(t1)); + tci_args_rr(&tb_ptr, &r0, &r1); + regs[r0] =3D bswap64(regs[r1]); break; #endif #endif /* TCG_TARGET_REG_BITS =3D=3D 64 */ --=20 2.25.1 From nobody Wed Nov 19 12:23:30 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1615995489; cv=none; d=zohomail.com; s=zohoarc; b=YSdPI54+0Ei+eCJB0Oizg9StMUNYsWT66oaBi/ZUPw0q1I+WfvthtPcTWPoJtHqiQ7ZH7KCao+jn1uOuUpKHA1c0KUAP3+NNvamKOCXwsq2j3KUkqbRsY5mN2ALB2iz29k8goT29oe/nUK3OZOqRXYPdAoFlGRKiA/ZuqVcYP/4= ARC-Message-Signature: i=1; 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id i11sm8271154otp.76.2021.03.17.08.34.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Mar 2021 08:34:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Z/JpQCcUrKRnv9+kGh5cCSzc4dhrThbAR0CKm4hnpyM=; b=bH63AyUgNE6lZLEutsBwFaOaC0Mhoxugx8IJy65APxBt4jlnVNkrflqfGgWw5g9OEC sJeErsOo7ID7VHsJNDgGxJhwwDDP6kstymsvjBtuZ9Ce2icoL49Mx5QEgk0psXKJPwba DTTQiJS0XYEOjfXJifzbreO4ANF/OXf+KB5rw3QS2Iza/Wr0vFy6SycurW2kc4CmSfye gz7RNFHS95IUQPA82lX/om3vSLcM4xBc4wGAj6Spjdw740xyrFQVeusNJzNnsIZJL2pb 64wQLw+tgZ/L9ETlk+OAbZ6O46emsON0msuUKQFULi+RXE6u7mGfwi2nyQQ2he0SL24L eBVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Z/JpQCcUrKRnv9+kGh5cCSzc4dhrThbAR0CKm4hnpyM=; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::235; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x235.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/tci.c | 154 ++++++++++++++++++++---------------------------------- 1 file changed, 57 insertions(+), 97 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index e5aba3a9fa..1c879a2536 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -191,6 +191,14 @@ static void tci_args_rr(const uint8_t **tb_ptr, *r1 =3D tci_read_r(tb_ptr); } =20 +static void tci_args_rrr(const uint8_t **tb_ptr, + TCGReg *r0, TCGReg *r1, TCGReg *r2) +{ + *r0 =3D tci_read_r(tb_ptr); + *r1 =3D tci_read_r(tb_ptr); + *r2 =3D tci_read_r(tb_ptr); +} + static void tci_args_rrs(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, int32_t *i2) { @@ -349,7 +357,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, uint8_t op_size =3D tb_ptr[1]; const uint8_t *old_code_ptr =3D tb_ptr; #endif - TCGReg r0, r1; + TCGReg r0, r1, r2; tcg_target_ulong t0; tcg_target_ulong t1; tcg_target_ulong t2; @@ -486,101 +494,71 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchS= tate *env, /* Arithmetic operations (mixed 32/64 bit). */ =20 CASE_32_64(add) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 + t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D regs[r1] + regs[r2]; break; CASE_32_64(sub) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 - t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D regs[r1] - regs[r2]; break; CASE_32_64(mul) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 * t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D regs[r1] * regs[r2]; break; CASE_32_64(and) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 & t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D regs[r1] & regs[r2]; break; CASE_32_64(or) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 | t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D regs[r1] | regs[r2]; break; CASE_32_64(xor) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 ^ t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D regs[r1] ^ regs[r2]; break; =20 /* Arithmetic operations (32 bit). */ =20 case INDEX_op_div_i32: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (int32_t)t1 / (int32_t)t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D (int32_t)regs[r1] / (int32_t)regs[r2]; break; case INDEX_op_divu_i32: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (uint32_t)t1 / (uint32_t)t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D (uint32_t)regs[r1] / (uint32_t)regs[r2]; break; case INDEX_op_rem_i32: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (int32_t)t1 % (int32_t)t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D (int32_t)regs[r1] % (int32_t)regs[r2]; break; case INDEX_op_remu_i32: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (uint32_t)t1 % (uint32_t)t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D (uint32_t)regs[r1] % (uint32_t)regs[r2]; break; =20 /* Shift/rotate operations (32 bit). */ =20 case INDEX_op_shl_i32: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (uint32_t)t1 << (t2 & 31)); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D (uint32_t)regs[r1] << (regs[r2] & 31); break; case INDEX_op_shr_i32: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (uint32_t)t1 >> (t2 & 31)); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D (uint32_t)regs[r1] >> (regs[r2] & 31); break; case INDEX_op_sar_i32: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (int32_t)t1 >> (t2 & 31)); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D (int32_t)regs[r1] >> (regs[r2] & 31); break; #if TCG_TARGET_HAS_rot_i32 case INDEX_op_rotl_i32: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, rol32(t1, t2 & 31)); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D rol32(regs[r1], regs[r2] & 31); break; case INDEX_op_rotr_i32: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, ror32(t1, t2 & 31)); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D ror32(regs[r1], regs[r2] & 31); break; #endif #if TCG_TARGET_HAS_deposit_i32 @@ -715,62 +693,44 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, /* Arithmetic operations (64 bit). */ =20 case INDEX_op_div_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (int64_t)t1 / (int64_t)t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D (int64_t)regs[r1] / (int64_t)regs[r2]; break; case INDEX_op_divu_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (uint64_t)t1 / (uint64_t)t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D (uint64_t)regs[r1] / (uint64_t)regs[r2]; break; case INDEX_op_rem_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (int64_t)t1 % (int64_t)t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D (int64_t)regs[r1] % (int64_t)regs[r2]; break; case INDEX_op_remu_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (uint64_t)t1 % (uint64_t)t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D (uint64_t)regs[r1] % (uint64_t)regs[r2]; break; =20 /* Shift/rotate operations (64 bit). */ =20 case INDEX_op_shl_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 << (t2 & 63)); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D regs[r1] << (regs[r2] & 63); break; case INDEX_op_shr_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 >> (t2 & 63)); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D regs[r1] >> (regs[r2] & 63); break; case INDEX_op_sar_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, ((int64_t)t1 >> (t2 & 63))); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D (int64_t)regs[r1] >> (regs[r2] & 63); break; #if TCG_TARGET_HAS_rot_i64 case INDEX_op_rotl_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, rol64(t1, t2 & 63)); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D rol64(regs[r1], regs[r2] & 63); break; case INDEX_op_rotr_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, ror64(t1, t2 & 63)); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D ror64(regs[r1], regs[r2] & 63); break; #endif #if TCG_TARGET_HAS_deposit_i64 --=20 2.25.1 From nobody Wed Nov 19 12:23:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1615995497; cv=none; d=zohomail.com; s=zohoarc; b=FK29GYqov8rvKla2lLLS4je/6cjr/jcRFz3vrdq7WRwTX9Qy5Hjh+13Vnn80ZKl5hWccPhtWDzETd3km8qLhmNOV25Lrw0gIfZRBb1zykNNg7LoDOrNd/nJ4HgnUxieH7d3pgaz5N6sfI4Y1MQ83p8yqs3YIJeMeCiJWDUSTjYc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615995497; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::330; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/tci.c | 24 ++++++++++++++---------- 1 file changed, 14 insertions(+), 10 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 1c879a2536..dd9bcd74f3 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -180,6 +180,7 @@ static tcg_target_ulong tci_read_label(const uint8_t **= tb_ptr) * tci_args_ * where arguments is a sequence of * + * c =3D condition (TCGCond) * r =3D register * s =3D signed ldst offset */ @@ -207,6 +208,15 @@ static void tci_args_rrs(const uint8_t **tb_ptr, *i2 =3D tci_read_s32(tb_ptr); } =20 +static void tci_args_rrrc(const uint8_t **tb_ptr, + TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGCond *c3) +{ + *r0 =3D tci_read_r(tb_ptr); + *r1 =3D tci_read_r(tb_ptr); + *r2 =3D tci_read_r(tb_ptr); + *c3 =3D tci_read_b(tb_ptr); +} + static bool tci_compare32(uint32_t u0, uint32_t u1, TCGCond condition) { bool result =3D false; @@ -413,11 +423,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, tb_ptr =3D (uint8_t *)label; continue; case INDEX_op_setcond_i32: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - condition =3D *tb_ptr++; - tci_write_reg(regs, t0, tci_compare32(t1, t2, condition)); + tci_args_rrrc(&tb_ptr, &r0, &r1, &r2, &condition); + regs[r0] =3D tci_compare32(regs[r1], regs[r2], condition); break; #if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_setcond2_i32: @@ -429,11 +436,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, break; #elif TCG_TARGET_REG_BITS =3D=3D 64 case INDEX_op_setcond_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - condition =3D *tb_ptr++; - tci_write_reg(regs, t0, tci_compare64(t1, t2, condition)); + tci_args_rrrc(&tb_ptr, &r0, &r1, &r2, &condition); + regs[r0] =3D tci_compare64(regs[r1], regs[r2], condition); break; #endif CASE_32_64(mov) --=20 2.25.1 From nobody Wed Nov 19 12:23:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1615995726; cv=none; d=zohomail.com; s=zohoarc; b=AdAEVC1qEDUqzCdygDXbr9ppUas8TrVDfzSll9iBpOH56LthURncXVbr0mgm6hDUglWUjDUpnxzGUdwcZc8XZMqtopLhc2E9e2l6xKyPPhrrMJxlnDSL1o0W0RyD3eXndnmSMNRupCHZx1VtWVK0T5rnbrtHw+NveJCAgrsrNFM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615995726; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::230; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x230.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/tci.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index dd9bcd74f3..e323351b75 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -181,10 +181,16 @@ static tcg_target_ulong tci_read_label(const uint8_t = **tb_ptr) * where arguments is a sequence of * * c =3D condition (TCGCond) + * l =3D label or pointer * r =3D register * s =3D signed ldst offset */ =20 +static void tci_args_l(const uint8_t **tb_ptr, void **l0) +{ + *l0 =3D (void *)tci_read_label(tb_ptr); +} + static void tci_args_rr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1) { @@ -418,9 +424,9 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, #endif break; case INDEX_op_br: - label =3D tci_read_label(&tb_ptr); + tci_args_l(&tb_ptr, &ptr); tci_assert(tb_ptr =3D=3D old_code_ptr + op_size); - tb_ptr =3D (uint8_t *)label; + tb_ptr =3D ptr; continue; case INDEX_op_setcond_i32: tci_args_rrrc(&tb_ptr, &r0, &r1, &r2, &condition); --=20 2.25.1 From nobody Wed Nov 19 12:23:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1615995875; cv=none; d=zohomail.com; s=zohoarc; b=Wz3RfoVCl+OX4ZnXAqtl7ay06NAdK0EmKYB90nnARu3jRtUweaAG1W9sIVtWsONZ2n+DS1/6hmkfnAPhgTyvtJSpf5tWF5Uma5ZCWXAv9aATJQQ9c48S8UfOJBbLHar07/89jFJXXGvUhXJjqxOILrAgh7u8ZfPvqZGaFzzaiho= ARC-Message-Signature: i=1; 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id i11sm8271154otp.76.2021.03.17.08.34.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Mar 2021 08:34:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8xkAhhh9xDBGJqS4Ff/RQebFkN9aKkBl1/y4BfG2kuo=; b=Wmjjm++8DandsT2UBvqpcaRaI4PIJ0X0pgrGeQWpU7Pw2clJ0cgDpi1XnykljDul18 7jVl10C+R4SxHtlHPpD5A3zXR5QGhRUn1rsNfnwT7V5K90VuXpyV1uYrfaiYrfcUSjgB J7aiuwj46ZwGp+HILFeg6P25bThplysuPJrtuquyV54WPpg4Gk7k32yf03GZwEfoxnna jI1W6eV++t+R80oEq7eYcnflMtZ95AvivA5/3RbAveR1FFXJ+Mj5SsjsJSi8C9N2Pr9U DBSdLbsq0F3KHugkUKM89JSldidh0/TCleWtDcT7m/Nq+DcJkOT9Cmxda1wGdse4kfxd sIew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8xkAhhh9xDBGJqS4Ff/RQebFkN9aKkBl1/y4BfG2kuo=; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22a; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/tci.c | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index e323351b75..22ede4016d 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -223,6 +223,19 @@ static void tci_args_rrrc(const uint8_t **tb_ptr, *c3 =3D tci_read_b(tb_ptr); } =20 +#if TCG_TARGET_REG_BITS =3D=3D 32 +static void tci_args_rrrrrc(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, + TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGCond *c= 5) +{ + *r0 =3D tci_read_r(tb_ptr); + *r1 =3D tci_read_r(tb_ptr); + *r2 =3D tci_read_r(tb_ptr); + *r3 =3D tci_read_r(tb_ptr); + *r4 =3D tci_read_r(tb_ptr); + *c5 =3D tci_read_b(tb_ptr); +} +#endif + static bool tci_compare32(uint32_t u0, uint32_t u1, TCGCond condition) { bool result =3D false; @@ -385,7 +398,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, uint32_t tmp32; uint64_t tmp64; #if TCG_TARGET_REG_BITS =3D=3D 32 - uint64_t v64; + TCGReg r3, r4; + uint64_t v64, T1, T2; #endif TCGMemOpIdx oi; int32_t ofs; @@ -434,11 +448,10 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, break; #if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_setcond2_i32: - t0 =3D *tb_ptr++; - tmp64 =3D tci_read_r64(regs, &tb_ptr); - v64 =3D tci_read_r64(regs, &tb_ptr); - condition =3D *tb_ptr++; - tci_write_reg(regs, t0, tci_compare64(tmp64, v64, condition)); + tci_args_rrrrrc(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &condition); + T1 =3D tci_uint64(regs[r2], regs[r1]); + T2 =3D tci_uint64(regs[r4], regs[r3]); + regs[r0] =3D tci_compare64(T1, T2, condition); break; #elif TCG_TARGET_REG_BITS =3D=3D 64 case INDEX_op_setcond_i64: --=20 2.25.1 From nobody Wed Nov 19 12:23:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1615996071; cv=none; d=zohomail.com; s=zohoarc; b=b+QgleyiVfonwqDM6+TMvyJskr++9F09tFoEuv1LmXCeIJD+0Q2BwxQZiBm8lH+DCvBlCWYlukDZP6nfxSwqPzYIoXKxFBH2rMdolko1L13GbwcWMOZBTLiqEEem0bsCZT9CAjRKbpgpuzQyUuGNSgLrQA24AbyQj+I4h0DOaCU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615996071; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::236; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x236.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/tci.c | 52 ++++++++++++++++++++++++++++++++-------------------- 1 file changed, 32 insertions(+), 20 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 22ede4016d..854fc8df5d 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -214,6 +214,15 @@ static void tci_args_rrs(const uint8_t **tb_ptr, *i2 =3D tci_read_s32(tb_ptr); } =20 +static void tci_args_rrcl(const uint8_t **tb_ptr, + TCGReg *r0, TCGReg *r1, TCGCond *c2, void **l3) +{ + *r0 =3D tci_read_r(tb_ptr); + *r1 =3D tci_read_r(tb_ptr); + *c2 =3D tci_read_b(tb_ptr); + *l3 =3D (void *)tci_read_label(tb_ptr); +} + static void tci_args_rrrc(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGCond *c3) { @@ -224,6 +233,17 @@ static void tci_args_rrrc(const uint8_t **tb_ptr, } =20 #if TCG_TARGET_REG_BITS =3D=3D 32 +static void tci_args_rrrrcl(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, + TCGReg *r2, TCGReg *r3, TCGCond *c4, void **l5) +{ + *r0 =3D tci_read_r(tb_ptr); + *r1 =3D tci_read_r(tb_ptr); + *r2 =3D tci_read_r(tb_ptr); + *r3 =3D tci_read_r(tb_ptr); + *c4 =3D tci_read_b(tb_ptr); + *l5 =3D (void *)tci_read_label(tb_ptr); +} + static void tci_args_rrrrrc(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGCond *c= 5) { @@ -390,7 +410,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, tcg_target_ulong t0; tcg_target_ulong t1; tcg_target_ulong t2; - tcg_target_ulong label; TCGCond condition; target_ulong taddr; uint8_t tmp8; @@ -399,7 +418,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, uint64_t tmp64; #if TCG_TARGET_REG_BITS =3D=3D 32 TCGReg r3, r4; - uint64_t v64, T1, T2; + uint64_t T1, T2; #endif TCGMemOpIdx oi; int32_t ofs; @@ -596,13 +615,10 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, break; #endif case INDEX_op_brcond_i32: - t0 =3D tci_read_rval(regs, &tb_ptr); - t1 =3D tci_read_rval(regs, &tb_ptr); - condition =3D *tb_ptr++; - label =3D tci_read_label(&tb_ptr); - if (tci_compare32(t0, t1, condition)) { + tci_args_rrcl(&tb_ptr, &r0, &r1, &condition, &ptr); + if (tci_compare32(regs[r0], regs[r1], condition)) { tci_assert(tb_ptr =3D=3D old_code_ptr + op_size); - tb_ptr =3D (uint8_t *)label; + tb_ptr =3D ptr; continue; } break; @@ -622,13 +638,12 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, tci_write_reg64(regs, t1, t0, tmp64); break; case INDEX_op_brcond2_i32: - tmp64 =3D tci_read_r64(regs, &tb_ptr); - v64 =3D tci_read_r64(regs, &tb_ptr); - condition =3D *tb_ptr++; - label =3D tci_read_label(&tb_ptr); - if (tci_compare64(tmp64, v64, condition)) { + tci_args_rrrrcl(&tb_ptr, &r0, &r1, &r2, &r3, &condition, &ptr); + T1 =3D tci_uint64(regs[r1], regs[r0]); + T2 =3D tci_uint64(regs[r3], regs[r2]); + if (tci_compare64(T1, T2, condition)) { tci_assert(tb_ptr =3D=3D old_code_ptr + op_size); - tb_ptr =3D (uint8_t *)label; + tb_ptr =3D ptr; continue; } break; @@ -768,13 +783,10 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, break; #endif case INDEX_op_brcond_i64: - t0 =3D tci_read_rval(regs, &tb_ptr); - t1 =3D tci_read_rval(regs, &tb_ptr); - condition =3D *tb_ptr++; - label =3D tci_read_label(&tb_ptr); - if (tci_compare64(t0, t1, condition)) { + tci_args_rrcl(&tb_ptr, &r0, &r1, &condition, &ptr); + if (tci_compare64(regs[r0], regs[r1], condition)) { tci_assert(tb_ptr =3D=3D old_code_ptr + op_size); - tb_ptr =3D (uint8_t *)label; + tb_ptr =3D ptr; continue; } break; --=20 2.25.1 From nobody Wed Nov 19 12:23:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1615996759; cv=none; d=zohomail.com; s=zohoarc; b=FBS+wEMoHVNDhklH8q5KnNLWfTDO4zpkXoSS+0SO9wz1rTILUQBWmWFRPsXfarok4jh5ToLub2yDOuQqmOlCKaIZDBHuIWTygvUwsrPu2D1zhJkBov5kpRQT2VV66lNkh1wCpSn4XFHgdxwZAZgGoTD2v4h8vlPgCHLJayZ4eJ0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615996759; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=xFXP6U+4B29OsOJ+BmqhfwEMNTn92rQ42jQHvULubqM=; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::332; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/tci.c | 38 ++++++++++++++++++++++---------------- 1 file changed, 22 insertions(+), 16 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 854fc8df5d..9bb529c5ae 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -121,16 +121,6 @@ static int32_t tci_read_s32(const uint8_t **tb_ptr) return value; } =20 -#if TCG_TARGET_REG_BITS =3D=3D 64 -/* Read constant (64 bit) from bytecode. */ -static uint64_t tci_read_i64(const uint8_t **tb_ptr) -{ - uint64_t value =3D *(const uint64_t *)(*tb_ptr); - *tb_ptr +=3D sizeof(value); - return value; -} -#endif - /* Read indexed register (native size) from bytecode. */ static tcg_target_ulong tci_read_rval(const tcg_target_ulong *regs, const uint8_t **tb_ptr) @@ -181,6 +171,8 @@ static tcg_target_ulong tci_read_label(const uint8_t **= tb_ptr) * where arguments is a sequence of * * c =3D condition (TCGCond) + * i =3D immediate (uint32_t) + * I =3D immediate (tcg_target_ulong) * l =3D label or pointer * r =3D register * s =3D signed ldst offset @@ -198,6 +190,22 @@ static void tci_args_rr(const uint8_t **tb_ptr, *r1 =3D tci_read_r(tb_ptr); } =20 +static void tci_args_ri(const uint8_t **tb_ptr, + TCGReg *r0, tcg_target_ulong *i1) +{ + *r0 =3D tci_read_r(tb_ptr); + *i1 =3D tci_read_i32(tb_ptr); +} + +#if TCG_TARGET_REG_BITS =3D=3D 64 +static void tci_args_rI(const uint8_t **tb_ptr, + TCGReg *r0, tcg_target_ulong *i1) +{ + *r0 =3D tci_read_r(tb_ptr); + *i1 =3D tci_read_i(tb_ptr); +} +#endif + static void tci_args_rrr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2) { @@ -483,9 +491,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, regs[r0] =3D regs[r1]; break; case INDEX_op_tci_movi_i32: - t0 =3D *tb_ptr++; - t1 =3D tci_read_i32(&tb_ptr); - tci_write_reg(regs, t0, t1); + tci_args_ri(&tb_ptr, &r0, &t1); + regs[r0] =3D t1; break; =20 /* Load/store operations (32 bit). */ @@ -705,9 +712,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, #endif #if TCG_TARGET_REG_BITS =3D=3D 64 case INDEX_op_tci_movi_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_i64(&tb_ptr); - tci_write_reg(regs, t0, t1); + tci_args_rI(&tb_ptr, &r0, &t1); + regs[r0] =3D t1; break; =20 /* Load/store operations (64 bit). */ --=20 2.25.1 From nobody Wed Nov 19 12:23:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Date: Wed, 17 Mar 2021 09:34:17 -0600 Message-Id: <20210317153444.310566-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210317153444.310566-1-richard.henderson@linaro.org> References: <20210317153444.310566-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::234; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x234.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/tci.c | 38 +++++++++++++++++++------------------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 9bb529c5ae..0f8f606808 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -437,30 +437,30 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 switch (opc) { case INDEX_op_call: - t0 =3D tci_read_i(&tb_ptr); + tci_args_l(&tb_ptr, &ptr); tci_tb_ptr =3D (uintptr_t)tb_ptr; #if TCG_TARGET_REG_BITS =3D=3D 32 - tmp64 =3D ((helper_function)t0)(tci_read_reg(regs, TCG_REG_R0), - tci_read_reg(regs, TCG_REG_R1), - tci_read_reg(regs, TCG_REG_R2), - tci_read_reg(regs, TCG_REG_R3), - tci_read_reg(regs, TCG_REG_R4), - tci_read_reg(regs, TCG_REG_R5), - tci_read_reg(regs, TCG_REG_R6), - tci_read_reg(regs, TCG_REG_R7), - tci_read_reg(regs, TCG_REG_R8), - tci_read_reg(regs, TCG_REG_R9), - tci_read_reg(regs, TCG_REG_R10), - tci_read_reg(regs, TCG_REG_R11)); + tmp64 =3D ((helper_function)ptr)(tci_read_reg(regs, TCG_REG_R0= ), + tci_read_reg(regs, TCG_REG_R1), + tci_read_reg(regs, TCG_REG_R2), + tci_read_reg(regs, TCG_REG_R3), + tci_read_reg(regs, TCG_REG_R4), + tci_read_reg(regs, TCG_REG_R5), + tci_read_reg(regs, TCG_REG_R6), + tci_read_reg(regs, TCG_REG_R7), + tci_read_reg(regs, TCG_REG_R8), + tci_read_reg(regs, TCG_REG_R9), + tci_read_reg(regs, TCG_REG_R10), + tci_read_reg(regs, TCG_REG_R11)= ); tci_write_reg(regs, TCG_REG_R0, tmp64); tci_write_reg(regs, TCG_REG_R1, tmp64 >> 32); #else - tmp64 =3D ((helper_function)t0)(tci_read_reg(regs, TCG_REG_R0), - tci_read_reg(regs, TCG_REG_R1), - tci_read_reg(regs, TCG_REG_R2), - tci_read_reg(regs, TCG_REG_R3), - tci_read_reg(regs, TCG_REG_R4), - tci_read_reg(regs, TCG_REG_R5)); + tmp64 =3D ((helper_function)ptr)(tci_read_reg(regs, TCG_REG_R0= ), + tci_read_reg(regs, TCG_REG_R1), + tci_read_reg(regs, TCG_REG_R2), + tci_read_reg(regs, TCG_REG_R3), + tci_read_reg(regs, TCG_REG_R4), + tci_read_reg(regs, TCG_REG_R5)); tci_write_reg(regs, TCG_REG_R0, tmp64); #endif break; --=20 2.25.1 From nobody Wed Nov 19 12:23:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1615996425; cv=none; d=zohomail.com; s=zohoarc; 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id i11sm8271154otp.76.2021.03.17.08.34.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Mar 2021 08:34:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+MEWN9WQ0I4wojHOI5XK5Q12NZO/KQfmuWx2IIReuGY=; b=iAIpaRN9fzHJe6Zq/oNfk4C+KnVoniPee5dMnAIOi6D9eb0d54hhyh3PKaUSK41ix2 o/ikz4wynk5+599xz1xRV7XPJE3igC0I/z5gbgP+ykQesalbSTFu8Iz6aoMoEdcCcpV/ /cWEWFUjA/pjo1nlmnH6Hi8pK02aOZxM4hNH9NHV3mn/YfNGQ75+R0nfhjc6W02jABI1 Bq2s9XjaLt+h/k6T2iSRv6WO1No92C1kun5ouCZ0pgG0cEMwWZvkDbjIy4ed5cUXcEuS Zkx5GJEYXOFoWvEsM229Bdg3dt3t/3XthhaegwmUnq61uVmKotz1a0dIL9eTprtPa4o3 jmuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+MEWN9WQ0I4wojHOI5XK5Q12NZO/KQfmuWx2IIReuGY=; b=kQ8KSeNOfNuFHqTWHl7UzWfuI1/QfFgPlf24V02xwkdbk3sCboiPfgfS2UIIsWoukS XZE2G68K+8+CbaiSiBllYQugEQTgAfRIb6WcymJwbi1flj16XBcsddTTB5LaCE5d5hQ1 bcZ16x5CFbAafODihHV18yCDbwGpwiEsCsggUeW7o9XTcoiV2SyV/95nYvRJuXiSONkW /7ZrDOPqTnl6KOP1BN0R6eb9bfzQe5sQfHbgEFKHywy/wg9Q17RcaqhyzUplSYVd0fZd 77nfQpbDjhlARE5o5zblavX/fPzMb1rcsBlR5Vk4TBEJr26NlH2f305ph/IUTw8bBhSd PZAw== X-Gm-Message-State: AOAM5308BcGsXMC2Ln0LlnLdYZ4m3hoocTwaybJgHe0mJgoTjhkyewbH 6rmm4131jsDAMcJA4s6LywdrSsR89L4zjfP/ X-Google-Smtp-Source: ABdhPJw79/t56GsyEgGtR4fdKwenpK4v075IuH/RG34pmDoi8/a8UXu7lk3SrUqWrT+ur45LqBGX8Q== X-Received: by 2002:a05:6830:1282:: with SMTP id z2mr3887328otp.30.1615995298070; Wed, 17 Mar 2021 08:34:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 12/38] tcg/tci: Reuse tci_args_l for exit_tb Date: Wed, 17 Mar 2021 09:34:18 -0600 Message-Id: <20210317153444.310566-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210317153444.310566-1-richard.henderson@linaro.org> References: <20210317153444.310566-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::335; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Do not emit a uint64_t, but a tcg_target_ulong, aka uintptr_t. This reduces the size of the constant on 32-bit hosts. The assert for label !=3D NULL has to be removed because that is a valid value for exit_tb. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/tci.c | 13 ++++--------- tcg/tci/tcg-target.c.inc | 2 +- 2 files changed, 5 insertions(+), 10 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 0f8f606808..71d6720e22 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -160,9 +160,7 @@ tci_read_ulong(const tcg_target_ulong *regs, const uint= 8_t **tb_ptr) =20 static tcg_target_ulong tci_read_label(const uint8_t **tb_ptr) { - tcg_target_ulong label =3D tci_read_i(tb_ptr); - tci_assert(label !=3D 0); - return label; + return tci_read_i(tb_ptr); } =20 /* @@ -402,7 +400,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, tcg_target_ulong regs[TCG_TARGET_NB_REGS]; long tcg_temps[CPU_TEMP_BUF_NLONGS]; uintptr_t sp_value =3D (uintptr_t)(tcg_temps + CPU_TEMP_BUF_NLONGS); - uintptr_t ret =3D 0; =20 regs[TCG_AREG0] =3D (tcg_target_ulong)env; regs[TCG_REG_CALL_STACK] =3D sp_value; @@ -817,9 +814,9 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, /* QEMU specific operations. */ =20 case INDEX_op_exit_tb: - ret =3D *(uint64_t *)tb_ptr; - goto exit; - break; + tci_args_l(&tb_ptr, &ptr); + return (uintptr_t)ptr; + case INDEX_op_goto_tb: /* Jump address is aligned */ tb_ptr =3D QEMU_ALIGN_PTR_UP(tb_ptr, 4); @@ -977,6 +974,4 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, } tci_assert(tb_ptr =3D=3D old_code_ptr + op_size); } -exit: - return ret; } diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index c79f9c32d8..ff8040510f 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -401,7 +401,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, co= nst TCGArg *args, =20 switch (opc) { case INDEX_op_exit_tb: - tcg_out64(s, args[0]); + tcg_out_i(s, args[0]); break; =20 case INDEX_op_goto_tb: --=20 2.25.1 From nobody Wed Nov 19 12:23:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1615996300; cv=none; d=zohomail.com; s=zohoarc; b=A5v8hyUrOhdYyqjXS7akMBYIAqVAlGAal56q4SAjtjgdq/Jz7fVBgJpRmpS7e67rywks5uM69C6cD8F5PIeC2U7JqbVEjeA/b7dr7VT39+YvOTTf267RGyzsrMtWMa35dIHq6XqnQTGVv6QVGZYx1ZPeDnCLePo3aOUDkctnqgk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615996300; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=BZ0ZY1gI/xHAH0bHqFpAGpcK8xAM2Wgm2gqCXnQ6Hdw=; b=htMpV+1P9fYvgLJy+Clm5aeOKlxHEHKd4c6+48jhZmI1RGVrO3UBb4W6OcaADV5lzMB4c9kzRAAJ8QthXVTsndQu/KedQjqfkEdfpTdzcxHx/qSM1euRQkPZR+r1hRIctcAmQ4olx1hRrnFpfYjLOXLvwyeOFZ65M/n+6bpftVw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1615996300099542.7901257309558; Wed, 17 Mar 2021 08:51:40 -0700 (PDT) Received: from localhost ([::1]:42306 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lMYSR-000510-1Z for importer@patchew.org; Wed, 17 Mar 2021 11:51:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49896) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lMYCP-00058U-68 for qemu-devel@nongnu.org; Wed, 17 Mar 2021 11:35:05 -0400 Received: from mail-oi1-x231.google.com ([2607:f8b0:4864:20::231]:39516) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lMYCK-00078o-4a for qemu-devel@nongnu.org; Wed, 17 Mar 2021 11:35:04 -0400 Received: by mail-oi1-x231.google.com with SMTP id u62so26393512oib.6 for ; Wed, 17 Mar 2021 08:34:59 -0700 (PDT) Received: from localhost.localdomain (fixed-187-189-51-144.totalplay.net. [187.189.51.144]) by smtp.gmail.com with ESMTPSA id i11sm8271154otp.76.2021.03.17.08.34.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Mar 2021 08:34:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BZ0ZY1gI/xHAH0bHqFpAGpcK8xAM2Wgm2gqCXnQ6Hdw=; b=Inx22Ci9v08PALsSgnSYvnr66g/lOPJWtCkvLx2opKMhxrgPz+Y6wKXc5MTc7BwmMR ilTQaGAnd8Be7W+LCtDSBtvn2ljjPuRbBYDA9Pf5EOJ4HejJbjx7v/7UVwTcCOWDRI7k +4vq4Fu4/bcNzQB3uI+B2XqpB8eewWjgHnP9LO9YI5LUQSCVgRgK1yJ6jZe0RPohdS2z DjkzebPjBj8hHfD8U6HVaQEVNdOLaR1/9Ves0Mq7l31LOrpRmG1tleXIPBTf0oIr43Ii S/7Qv1SpUbbuubGn2dpHsrLjDE6T7oKnpUxmDtVDbY0hNXWMjnJEwOR5pOhFDFRadhgG NLVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BZ0ZY1gI/xHAH0bHqFpAGpcK8xAM2Wgm2gqCXnQ6Hdw=; b=o9CSmmp4Y9yb7LLOKZtyPAQtrUNm59t2td5RXCNftndpP0dNJ25qaUP/VckULtXxDj nciGka4hWVEbvqPQ6RTz8tBgYwKr0T+xmwSKXkokPWFkut82aYE3B7+kY2q+CO+61Kpe 5sYVd6MB5o8LCcstB6XlFk2yeQTzWm328NXbIeBEnJd3xcjzpckEt3+BGlA3Gc7/mOG3 MpMlHW+QH2SrwHIa7l4y5txkIe/YqWgfCI3xnuD4GxxP1Xsp4IkOBMyMpLQVTLBaS3Mi paVepF/+XSvWqj4o85b5EQzFmepCDYRVaBLybteyrG63tISZee/atWSl1Bi/s+smGVXz vx9g== X-Gm-Message-State: AOAM530AyoksD8S592HZlr4T5+YmdmDwC/keNRoKjHKFiCfZFJ5VSINL hff9bPPjUI0AlJPw/O4Z4bd1xiw3wLoGy3oO X-Google-Smtp-Source: ABdhPJyac+QiKMVO1ep81aapD9Z5463XIOtFK55ytypFpM7qxZCjakK4f0qjAV/jkAicH7I5UnVlDg== X-Received: by 2002:aca:4284:: with SMTP id p126mr3210031oia.123.1615995299108; Wed, 17 Mar 2021 08:34:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 13/38] tcg/tci: Reuse tci_args_l for goto_tb Date: Wed, 17 Mar 2021 09:34:19 -0600 Message-Id: <20210317153444.310566-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210317153444.310566-1-richard.henderson@linaro.org> References: <20210317153444.310566-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::231; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x231.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Convert to indirect jumps, as it's less complicated. Then we just have a pointer to the tb address at which the chain is stored, from which we read. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 11 +++-------- tcg/tci.c | 8 +++----- tcg/tci/tcg-target.c.inc | 13 +++---------- 3 files changed, 9 insertions(+), 23 deletions(-) diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 9c0021a26f..9285c930a2 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -87,7 +87,7 @@ #define TCG_TARGET_HAS_muluh_i32 0 #define TCG_TARGET_HAS_mulsh_i32 0 #define TCG_TARGET_HAS_goto_ptr 0 -#define TCG_TARGET_HAS_direct_jump 1 +#define TCG_TARGET_HAS_direct_jump 0 #define TCG_TARGET_HAS_qemu_st8_i32 0 =20 #if TCG_TARGET_REG_BITS =3D=3D 64 @@ -174,12 +174,7 @@ void tci_disas(uint8_t opc); =20 #define TCG_TARGET_HAS_MEMORY_BSWAP 1 =20 -static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jm= p_rx, - uintptr_t jmp_rw, uintptr_t ad= dr) -{ - /* patch the branch destination */ - qatomic_set((int32_t *)jmp_rw, addr - (jmp_rx + 4)); - /* no need to flush icache explicitly */ -} +/* not defined -- call should be eliminated at compile time */ +void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); =20 #endif /* TCG_TARGET_H */ diff --git a/tcg/tci.c b/tcg/tci.c index 71d6720e22..53e49ccf8e 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -818,13 +818,11 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, return (uintptr_t)ptr; =20 case INDEX_op_goto_tb: - /* Jump address is aligned */ - tb_ptr =3D QEMU_ALIGN_PTR_UP(tb_ptr, 4); - t0 =3D qatomic_read((int32_t *)tb_ptr); - tb_ptr +=3D sizeof(int32_t); + tci_args_l(&tb_ptr, &ptr); tci_assert(tb_ptr =3D=3D old_code_ptr + op_size); - tb_ptr +=3D (int32_t)t0; + tb_ptr =3D *(void **)ptr; continue; + case INDEX_op_qemu_ld_i32: t0 =3D *tb_ptr++; taddr =3D tci_read_ulong(regs, &tb_ptr); diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index ff8040510f..2c64b4f617 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -405,16 +405,9 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, break; =20 case INDEX_op_goto_tb: - if (s->tb_jmp_insn_offset) { - /* Direct jump method. */ - /* Align for atomic patching and thread safety */ - s->code_ptr =3D QEMU_ALIGN_PTR_UP(s->code_ptr, 4); - s->tb_jmp_insn_offset[args[0]] =3D tcg_current_code_size(s); - tcg_out32(s, 0); - } else { - /* Indirect jump method. */ - TODO(); - } + tcg_debug_assert(s->tb_jmp_insn_offset =3D=3D 0); + /* indirect jump method. */ + tcg_out_i(s, (uintptr_t)(s->tb_jmp_target_addr + args[0])); set_jmp_reset_offset(s, args[0]); break; =20 --=20 2.25.1 From nobody Wed Nov 19 12:23:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1615995698; cv=none; d=zohomail.com; s=zohoarc; b=HqqmKSebDQx4dhTNRyhiNMetNOCUVdw1PaXlJ6lkAG5uBVxibr+/qnUI0hpJvG7FScF4Rj94CM2k4WPuqEJAPQZ9SvLlBdh7F1/l261vzfgkeQL2TC74Pot82jESMSOd+UxC1DWltWzL+nj+PptwKwIPRSQJXJvNi6WhQIOhS0g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id i11sm8271154otp.76.2021.03.17.08.34.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Mar 2021 08:34:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kzxzzGavBk3earHX25KN1+PuYqdgRg5rKHqmB3mpxI0=; b=xqAZJQ6TKzfNS1jgV7fMGmH2grOK8n51cjzAAVInw7QKpMnFqEX63G2jyLemOO9tyS rJJB1bL7qUjYRE6OBkqvYfC6ivGDZznkni8B23fIIvXutqFFBwzzm+m2Y3ZvCMIj/M5D su3CU/3frB7fjs4Y0VTAg/bhyvYKo9EGm+6uaBjCBW60O7NRpcVMyzAUn1Lbe0EhKN1x GJXCSD64YKqJO2wck0JU/WpnQpIGkxlo9hXLlxp7ugXyfBOPoFqbzcJyvoPNSpKvJUzo h3K2ESW62y1gQM3tzp7F22ePbIIxUSKWUd7ruAejDr6/w++Zxn16tLz5ogsMh6YcqfHs SPUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kzxzzGavBk3earHX25KN1+PuYqdgRg5rKHqmB3mpxI0=; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32a; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/tci.c | 31 ++++++++++++++++++++----------- 1 file changed, 20 insertions(+), 11 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 53e49ccf8e..91c5f71065 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -260,6 +260,17 @@ static void tci_args_rrrrrc(const uint8_t **tb_ptr, TC= GReg *r0, TCGReg *r1, *r4 =3D tci_read_r(tb_ptr); *c5 =3D tci_read_b(tb_ptr); } + +static void tci_args_rrrrrr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, + TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGReg *r5) +{ + *r0 =3D tci_read_r(tb_ptr); + *r1 =3D tci_read_r(tb_ptr); + *r2 =3D tci_read_r(tb_ptr); + *r3 =3D tci_read_r(tb_ptr); + *r4 =3D tci_read_r(tb_ptr); + *r5 =3D tci_read_r(tb_ptr); +} #endif =20 static bool tci_compare32(uint32_t u0, uint32_t u1, TCGCond condition) @@ -422,7 +433,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, uint32_t tmp32; uint64_t tmp64; #if TCG_TARGET_REG_BITS =3D=3D 32 - TCGReg r3, r4; + TCGReg r3, r4, r5; uint64_t T1, T2; #endif TCGMemOpIdx oi; @@ -628,18 +639,16 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, break; #if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_add2_i32: - t0 =3D *tb_ptr++; - t1 =3D *tb_ptr++; - tmp64 =3D tci_read_r64(regs, &tb_ptr); - tmp64 +=3D tci_read_r64(regs, &tb_ptr); - tci_write_reg64(regs, t1, t0, tmp64); + tci_args_rrrrrr(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &r5); + T1 =3D tci_uint64(regs[r3], regs[r2]); + T2 =3D tci_uint64(regs[r5], regs[r4]); + tci_write_reg64(regs, r1, r0, T1 + T2); break; case INDEX_op_sub2_i32: - t0 =3D *tb_ptr++; - t1 =3D *tb_ptr++; - tmp64 =3D tci_read_r64(regs, &tb_ptr); - tmp64 -=3D tci_read_r64(regs, &tb_ptr); - tci_write_reg64(regs, t1, t0, tmp64); + tci_args_rrrrrr(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &r5); + T1 =3D tci_uint64(regs[r3], regs[r2]); + T2 =3D tci_uint64(regs[r5], regs[r4]); + tci_write_reg64(regs, r1, r0, T1 - T2); break; case INDEX_op_brcond2_i32: tci_args_rrrrcl(&tb_ptr, &r0, &r1, &r2, &r3, &condition, &ptr); --=20 2.25.1 From nobody Wed Nov 19 12:23:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1615996135; cv=none; d=zohomail.com; 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id i11sm8271154otp.76.2021.03.17.08.35.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Mar 2021 08:35:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=COmDyGzd2z7m4JzO4rKFadfntU5QXCdkJIoX0hERnXw=; b=hSO6/FObPXdAM/a5AP588K1vRxj+nI0/Dx5dlwezKlP7RCSn6UmKnCpB5XB9ucfeuM qM66zrIjVdexcETah9DNs1+Z/ZnD9AhOIEnRFYGBCs8YVzvvoZ8ubqq+DMm2Y1tUzNs7 Ay9FbEucptA7WBfx6f+ipwBPFkOhHJIOS+ESJG3tVAAwOmdqf6+QZoqLG10x+VErLpCe VOWtIR+4Oz0O3ByJW/0jKVFnwzYxGGU+ohGTs5TJB+g2VIuPTm11WDo1ytXo5oeb7Y+W iI9hJ8d2a5VINzpmgynQrH3OaFPa9hvMY45otujamT5E7vSrlPh3mZHZ3yn7WdHUSX0j jcPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=COmDyGzd2z7m4JzO4rKFadfntU5QXCdkJIoX0hERnXw=; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32e; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/tci.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 91c5f71065..2fcf5a2473 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -239,6 +239,15 @@ static void tci_args_rrrc(const uint8_t **tb_ptr, } =20 #if TCG_TARGET_REG_BITS =3D=3D 32 +static void tci_args_rrrr(const uint8_t **tb_ptr, + TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3) +{ + *r0 =3D tci_read_r(tb_ptr); + *r1 =3D tci_read_r(tb_ptr); + *r2 =3D tci_read_r(tb_ptr); + *r3 =3D tci_read_r(tb_ptr); +} + static void tci_args_rrrrcl(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGCond *c4, void **l5) { @@ -661,11 +670,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, } break; case INDEX_op_mulu2_i32: - t0 =3D *tb_ptr++; - t1 =3D *tb_ptr++; - t2 =3D tci_read_rval(regs, &tb_ptr); - tmp64 =3D (uint32_t)tci_read_rval(regs, &tb_ptr); - tci_write_reg64(regs, t1, t0, (uint32_t)t2 * tmp64); + tci_args_rrrr(&tb_ptr, &r0, &r1, &r2, &r3); + tci_write_reg64(regs, r1, r0, (uint64_t)regs[r2] * regs[r3]); break; #endif /* TCG_TARGET_REG_BITS =3D=3D 32 */ #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 --=20 2.25.1 From nobody Wed Nov 19 12:23:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id i11sm8271154otp.76.2021.03.17.08.35.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Mar 2021 08:35:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NmBZo7AXRGPv0b50PXBcgMx9DdtcXIoXUKSXEv41j2E=; b=YrDE5YoyQdpDau7WrKwMsvfPgvg1yS/rPssulrB9VlESBJAVMxx/tFPh93veIdPq4a rWZZA49KnLKqA28bwQslm8doU3Zu6x94fqBs0ElSx40sAd+qEDb5WknOToJmUTzB+Ut7 OS1IEWaQl6jDi06B+LILmsD8US27TJaaLCoYq7FTfm3BleGYl5leVeo93UD9MrFdlY+w bYBnWHTV9emDmTtRm7K2SXPYgD/V0m4t3oIUhg6Igo21MxbZSvEk6hpHwOsTtwrtCigP /mCM87XuaANdYZPFDFLu8ktV8Zsr83xwOujQB4AleHKuN9sl7RNz2tOChASTFobn9rbl Hyww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NmBZo7AXRGPv0b50PXBcgMx9DdtcXIoXUKSXEv41j2E=; b=DJdNSUa+kfq+6eV0NnTYAwH8TmRQsE/42Zwn+aAxQBHdg29LcAIXB1N9uTS2c3ndI8 JVA2FXkj8G91TufPvvpm2O+xMh8tNt6n7QJCIJdtQ5lpl6JhuFlX5DaBryx7s58ZNVuz 08ohjq70oI+1Rpndb0yFsgxf3PoKLBoUJcM4dWjJ4LXTSOmno1u6AzvTdKMBiVaILHMD s+ZbJCy4Rv2dQ+ROjjBjQhRetVDIOUcCNoST3/28E5JeeG/5+yETBSZtj0YBt05HwIaJ IS5xzb8TnlPqm6/avSvl3sxbB4N9LkVWQIUjxutvI2P6D+hQIgWcnVO9Voxe+nTUGY2+ P/Qg== X-Gm-Message-State: AOAM530l/iahhuikcsVeqzjXFNAy/cUWeeREExBZNelKTayC8Iz0G6Ad euTf0a6vAhd60scijL/aiY9fntIpkDImgi5m X-Google-Smtp-Source: ABdhPJxQNcitCdyUdWW3WeC0CDtZZoBweiFdkF0VuS3fY4juklDrlfTFB7a/Vm6Sg6cmxEP/L+wsHQ== X-Received: by 2002:a9d:12a4:: with SMTP id g33mr3803799otg.308.1615995302133; Wed, 17 Mar 2021 08:35:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 16/38] tcg/tci: Clean up deposit operations Date: Wed, 17 Mar 2021 09:34:22 -0600 Message-Id: <20210317153444.310566-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210317153444.310566-1-richard.henderson@linaro.org> References: <20210317153444.310566-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::332; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Use the correct set of asserts during code generation. We do not require the first input to overlap the output; the existing interpreter already supported that. Split out tci_args_rrrbb in the translator. Use the deposit32/64 functions rather than inline expansion. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/tci/tcg-target-con-set.h | 1 - tcg/tci.c | 33 ++++++++++++++++----------------- tcg/tci/tcg-target.c.inc | 24 ++++++++++++++---------- 3 files changed, 30 insertions(+), 28 deletions(-) diff --git a/tcg/tci/tcg-target-con-set.h b/tcg/tci/tcg-target-con-set.h index f51b7bcb13..316730f32c 100644 --- a/tcg/tci/tcg-target-con-set.h +++ b/tcg/tci/tcg-target-con-set.h @@ -13,7 +13,6 @@ C_O0_I2(r, r) C_O0_I3(r, r, r) C_O0_I4(r, r, r, r) C_O1_I1(r, r) -C_O1_I2(r, 0, r) C_O1_I2(r, r, r) C_O1_I4(r, r, r, r, r) C_O2_I1(r, r, r) diff --git a/tcg/tci.c b/tcg/tci.c index 2fcf5a2473..22a5832387 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -168,6 +168,7 @@ static tcg_target_ulong tci_read_label(const uint8_t **= tb_ptr) * tci_args_ * where arguments is a sequence of * + * b =3D immediate (bit position) * c =3D condition (TCGCond) * i =3D immediate (uint32_t) * I =3D immediate (tcg_target_ulong) @@ -238,6 +239,16 @@ static void tci_args_rrrc(const uint8_t **tb_ptr, *c3 =3D tci_read_b(tb_ptr); } =20 +static void tci_args_rrrbb(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, + TCGReg *r2, uint8_t *i3, uint8_t *i4) +{ + *r0 =3D tci_read_r(tb_ptr); + *r1 =3D tci_read_r(tb_ptr); + *r2 =3D tci_read_r(tb_ptr); + *i3 =3D tci_read_b(tb_ptr); + *i4 =3D tci_read_b(tb_ptr); +} + #if TCG_TARGET_REG_BITS =3D=3D 32 static void tci_args_rrrr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3) @@ -434,11 +445,9 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, TCGReg r0, r1, r2; tcg_target_ulong t0; tcg_target_ulong t1; - tcg_target_ulong t2; TCGCond condition; target_ulong taddr; - uint8_t tmp8; - uint16_t tmp16; + uint8_t pos, len; uint32_t tmp32; uint64_t tmp64; #if TCG_TARGET_REG_BITS =3D=3D 32 @@ -629,13 +638,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, #endif #if TCG_TARGET_HAS_deposit_i32 case INDEX_op_deposit_i32: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tmp16 =3D *tb_ptr++; - tmp8 =3D *tb_ptr++; - tmp32 =3D (((1 << tmp8) - 1) << tmp16); - tci_write_reg(regs, t0, (t1 & ~tmp32) | ((t2 << tmp16) & tmp32= )); + tci_args_rrrbb(&tb_ptr, &r0, &r1, &r2, &pos, &len); + regs[r0] =3D deposit32(regs[r1], pos, len, regs[r2]); break; #endif case INDEX_op_brcond_i32: @@ -791,13 +795,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, #endif #if TCG_TARGET_HAS_deposit_i64 case INDEX_op_deposit_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tmp16 =3D *tb_ptr++; - tmp8 =3D *tb_ptr++; - tmp64 =3D (((1ULL << tmp8) - 1) << tmp16); - tci_write_reg(regs, t0, (t1 & ~tmp64) | ((t2 << tmp16) & tmp64= )); + tci_args_rrrbb(&tb_ptr, &r0, &r1, &r2, &pos, &len); + regs[r0] =3D deposit64(regs[r1], pos, len, regs[r2]); break; #endif case INDEX_op_brcond_i64: diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 2c64b4f617..640407b4a8 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -126,11 +126,9 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpco= de op) case INDEX_op_rotr_i64: case INDEX_op_setcond_i32: case INDEX_op_setcond_i64: - return C_O1_I2(r, r, r); - case INDEX_op_deposit_i32: case INDEX_op_deposit_i64: - return C_O1_I2(r, 0, r); + return C_O1_I2(r, r, r); =20 case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: @@ -480,13 +478,19 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, break; =20 CASE_32_64(deposit) /* Optional (TCG_TARGET_HAS_deposit_*). */ - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - tcg_debug_assert(args[3] <=3D UINT8_MAX); - tcg_out8(s, args[3]); - tcg_debug_assert(args[4] <=3D UINT8_MAX); - tcg_out8(s, args[4]); + { + TCGArg pos =3D args[3], len =3D args[4]; + TCGArg max =3D opc =3D=3D INDEX_op_deposit_i32 ? 32 : 64; + + tcg_debug_assert(pos < max); + tcg_debug_assert(pos + len <=3D max); + + tcg_out_r(s, args[0]); + tcg_out_r(s, args[1]); + tcg_out_r(s, args[2]); + tcg_out8(s, pos); + tcg_out8(s, len); + } break; =20 CASE_32_64(brcond) --=20 2.25.1 From nobody Wed Nov 19 12:23:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1615997007; cv=none; d=zohomail.com; s=zohoarc; b=nXG3hRIlkf6I6NGGY3m/x57g3cP0FEh5Gl7M0aYpv2y9lomR6U124ibutzTbp6kL8holMxAr57v9uql4dfNluhXgO8VOQ3MyLvBS4MjrtFywZ7IxY8/tKRWk4ORnhJlQ/I77dsWDGWIeyPxR0q4sBLqU4qUtI87OsNzKXW7GpL4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615997007; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=JpDz6oY9vwUgYbUC8y1zTqK+NAlPHi554TXdiibHnyo=; b=VkzBAgAqpDd2z6bBxZW2aJfc9SyeOj2rBWzFIYqFzD1IaWaxO8dQbBk1OIIqW7GKJs8JSiMcpWgwf39/q7tOxXVPmMB1/sTLjFXaqkEZRYE2madqi8UJkKzOSLy+bK0LgQVyKMmbkec0A3zdl29c+uvW02wmUPAAN77Jp360nqI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1615997007388228.50574011934202; Wed, 17 Mar 2021 09:03:27 -0700 (PDT) Received: from localhost ([::1]:48728 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lMYdo-0002rw-Jp for importer@patchew.org; Wed, 17 Mar 2021 12:03:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50038) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lMYCV-0005Fo-7z for qemu-devel@nongnu.org; Wed, 17 Mar 2021 11:35:12 -0400 Received: from mail-ot1-x32c.google.com ([2607:f8b0:4864:20::32c]:39703) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lMYCO-0007CM-8R for qemu-devel@nongnu.org; Wed, 17 Mar 2021 11:35:10 -0400 Received: by mail-ot1-x32c.google.com with SMTP id h6-20020a0568300346b02901b71a850ab4so2179600ote.6 for ; Wed, 17 Mar 2021 08:35:03 -0700 (PDT) Received: from localhost.localdomain (fixed-187-189-51-144.totalplay.net. [187.189.51.144]) by smtp.gmail.com with ESMTPSA id i11sm8271154otp.76.2021.03.17.08.35.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Mar 2021 08:35:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JpDz6oY9vwUgYbUC8y1zTqK+NAlPHi554TXdiibHnyo=; b=AzkDADfY+I38lx0ypQxuuqn039tQpwq0q4L7iV1I2OOYJCKy/3lmCDsvHeEqW5RQWT ZMuMsP9b87803mjfsuX+hnOR9kAMd8MTmQ776Yi5sm7LdWO2lyynUElYjAqUT9uM4vDD EGfyGcOf29VLzkByqJJjT4VkZHzo3GehMvopa8B/UowEwLTrLUuvaaj0zpJxAP5+xmRX OWjqvvW9WnZvMfQWuO5swjIqBzGdq0+NngAlUkWCY5N9U9kaw7oX7p+gqE6XpawKE+up BXMc9nPgCi+6GedosYoe6rsLybu2OLohYMDwlwewxnLrr3MCy/UYFqiVUe60zu8u0PgQ qPfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JpDz6oY9vwUgYbUC8y1zTqK+NAlPHi554TXdiibHnyo=; b=R06FPc5rQxdk5l+Y5HiiciziBgAUdLtRVVilasTACHLzKfEjAVhqzGuPmxV835JRL+ Vig3SxWxel5D7ACS6LqAF1ArVqXJC3Ylfj1SDWzYh8PM9SI/4QaK4FWpwvipNNY/KL6m bVhsPGeksIpW1WASJUfKjQ93SFuvHulh0oxki3qcpWi924eJR1gIapuckqEEIKcO12zD VtHyDK5I3BLFfFpWsHJUPBCpPnGlUTa6JLmI7uoVhA74+Ich3uCjM6NFh6IMiO/HVaew yZ0uhmZHb0QopbkY9IVQp0Qol14U8CzUtLKeOahKTRtMzCih3ZpY3sziyH2w8QlXrfj4 0xOA== X-Gm-Message-State: AOAM532FBfGDvQ6et0b1qF9YwDjBVXPQhYABipzlcvsRqSOz/Yu9xOVZ cBE6WczqC6TM4/sXOVuvRUr1ni9B2BiqdvLb X-Google-Smtp-Source: ABdhPJyOSMNMyIcABwhaXSxeovy+Te/MpJdBw60EhX2YLVaLgvJj9PMMHeNwD40j/F9bPvQWyLdgUg== X-Received: by 2002:a05:6830:18c:: with SMTP id q12mr3802847ota.355.1615995303199; Wed, 17 Mar 2021 08:35:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 17/38] tcg/tci: Reduce qemu_ld/st TCGMemOpIdx operand to 32-bits Date: Wed, 17 Mar 2021 09:34:23 -0600 Message-Id: <20210317153444.310566-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210317153444.310566-1-richard.henderson@linaro.org> References: <20210317153444.310566-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32c; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) We are currently using the "natural" size routine, which uses 64-bits on a 64-bit host. The TCGMemOpIdx operand has 11 bits, so we can safely reduce to 32-bits. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/tci.c | 8 ++++---- tcg/tci/tcg-target.c.inc | 4 ++-- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 22a5832387..ebd4c74176 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -840,7 +840,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, case INDEX_op_qemu_ld_i32: t0 =3D *tb_ptr++; taddr =3D tci_read_ulong(regs, &tb_ptr); - oi =3D tci_read_i(&tb_ptr); + oi =3D tci_read_i32(&tb_ptr); switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) { case MO_UB: tmp32 =3D qemu_ld_ub; @@ -877,7 +877,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, t1 =3D *tb_ptr++; } taddr =3D tci_read_ulong(regs, &tb_ptr); - oi =3D tci_read_i(&tb_ptr); + oi =3D tci_read_i32(&tb_ptr); switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) { case MO_UB: tmp64 =3D qemu_ld_ub; @@ -926,7 +926,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, case INDEX_op_qemu_st_i32: t0 =3D tci_read_rval(regs, &tb_ptr); taddr =3D tci_read_ulong(regs, &tb_ptr); - oi =3D tci_read_i(&tb_ptr); + oi =3D tci_read_i32(&tb_ptr); switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) { case MO_UB: qemu_st_b(t0); @@ -950,7 +950,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, case INDEX_op_qemu_st_i64: tmp64 =3D tci_read_r64(regs, &tb_ptr); taddr =3D tci_read_ulong(regs, &tb_ptr); - oi =3D tci_read_i(&tb_ptr); + oi =3D tci_read_i32(&tb_ptr); switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) { case MO_UB: qemu_st_b(tmp64); diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 640407b4a8..6c187a25cc 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -550,7 +550,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, co= nst TCGArg *args, if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { tcg_out_r(s, *args++); } - tcg_out_i(s, *args++); + tcg_out32(s, *args++); break; =20 case INDEX_op_qemu_ld_i64: @@ -563,7 +563,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, co= nst TCGArg *args, if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { tcg_out_r(s, *args++); } - tcg_out_i(s, *args++); + tcg_out32(s, *args++); break; =20 case INDEX_op_mb: --=20 2.25.1 From nobody Wed Nov 19 12:23:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1615996353; cv=none; d=zohomail.com; s=zohoarc; b=ZQrNGe4X6FbawNdIcrWJOEuufwly6pmSXpIuxYd6TJPT5oyM5EYEOEtO2mAynp+jwH8jO9rG5XOkT3s96oS2li8/WLyiJDNTyV89l3Hj1K/T4e36iHwLQvC/U3AV+AE4T7wBXxEHnL5spzvOUW1QjDCYFc/5HsXhpjbSQS3r5eM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615996353; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=pMCNtzw8zxb7KEVYhmhe7WEY+ee7y9TjAKBvQCxei8U=; b=RIA0PTU7YYvvZAeyXpJ5uCYyDY0v1Lyq2KbH8uk8b5gpktpNl0hlgM0IJVWL5qOwxjepVNNIp+kUCy+QitUFb1b2TIzJic8u7sbhHFtOG0FjgPdzgnCQpRVugRKES0JTlsM2MK/982AcYGVrEuRcX53UbkamVtoZiIPlv1lcNxE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 161599635343973.59335276889044; Wed, 17 Mar 2021 08:52:33 -0700 (PDT) Received: from localhost ([::1]:45232 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lMYTI-0006L7-AT for importer@patchew.org; Wed, 17 Mar 2021 11:52:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49998) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lMYCS-0005EY-Nd for qemu-devel@nongnu.org; Wed, 17 Mar 2021 11:35:10 -0400 Received: from mail-ot1-x32b.google.com ([2607:f8b0:4864:20::32b]:46990) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lMYCP-0007Ch-EX for qemu-devel@nongnu.org; Wed, 17 Mar 2021 11:35:08 -0400 Received: by mail-ot1-x32b.google.com with SMTP id 68-20020a9d0f4a0000b02901b663e6258dso2149919ott.13 for ; Wed, 17 Mar 2021 08:35:04 -0700 (PDT) Received: from localhost.localdomain (fixed-187-189-51-144.totalplay.net. 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32b; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/tci.c | 147 ++++++++++++++++++++++++++++++------------------------ 1 file changed, 81 insertions(+), 66 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index ebd4c74176..1aa63fae4d 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -66,22 +66,18 @@ tci_write_reg(tcg_target_ulong *regs, TCGReg index, tcg= _target_ulong value) regs[index] =3D value; } =20 -#if TCG_TARGET_REG_BITS =3D=3D 32 static void tci_write_reg64(tcg_target_ulong *regs, uint32_t high_index, uint32_t low_index, uint64_t value) { tci_write_reg(regs, low_index, value); tci_write_reg(regs, high_index, value >> 32); } -#endif =20 -#if TCG_TARGET_REG_BITS =3D=3D 32 /* Create a 64 bit value from two 32 bit values. */ static uint64_t tci_uint64(uint32_t high, uint32_t low) { return ((uint64_t)high << 32) + low; } -#endif =20 /* Read constant byte from bytecode. */ static uint8_t tci_read_b(const uint8_t **tb_ptr) @@ -121,43 +117,6 @@ static int32_t tci_read_s32(const uint8_t **tb_ptr) return value; } =20 -/* Read indexed register (native size) from bytecode. */ -static tcg_target_ulong -tci_read_rval(const tcg_target_ulong *regs, const uint8_t **tb_ptr) -{ - tcg_target_ulong value =3D tci_read_reg(regs, **tb_ptr); - *tb_ptr +=3D 1; - return value; -} - -#if TCG_TARGET_REG_BITS =3D=3D 32 -/* Read two indexed registers (2 * 32 bit) from bytecode. */ -static uint64_t tci_read_r64(const tcg_target_ulong *regs, - const uint8_t **tb_ptr) -{ - uint32_t low =3D tci_read_rval(regs, tb_ptr); - return tci_uint64(tci_read_rval(regs, tb_ptr), low); -} -#elif TCG_TARGET_REG_BITS =3D=3D 64 -/* Read indexed register (64 bit) from bytecode. */ -static uint64_t tci_read_r64(const tcg_target_ulong *regs, - const uint8_t **tb_ptr) -{ - return tci_read_rval(regs, tb_ptr); -} -#endif - -/* Read indexed register(s) with target address from bytecode. */ -static target_ulong -tci_read_ulong(const tcg_target_ulong *regs, const uint8_t **tb_ptr) -{ - target_ulong taddr =3D tci_read_rval(regs, tb_ptr); -#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS - taddr +=3D (uint64_t)tci_read_rval(regs, tb_ptr) << 32; -#endif - return taddr; -} - static tcg_target_ulong tci_read_label(const uint8_t **tb_ptr) { return tci_read_i(tb_ptr); @@ -173,6 +132,7 @@ static tcg_target_ulong tci_read_label(const uint8_t **= tb_ptr) * i =3D immediate (uint32_t) * I =3D immediate (tcg_target_ulong) * l =3D label or pointer + * m =3D immediate (TCGMemOpIdx) * r =3D register * s =3D signed ldst offset */ @@ -205,6 +165,14 @@ static void tci_args_rI(const uint8_t **tb_ptr, } #endif =20 +static void tci_args_rrm(const uint8_t **tb_ptr, + TCGReg *r0, TCGReg *r1, TCGMemOpIdx *m2) +{ + *r0 =3D tci_read_r(tb_ptr); + *r1 =3D tci_read_r(tb_ptr); + *m2 =3D tci_read_i32(tb_ptr); +} + static void tci_args_rrr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2) { @@ -239,6 +207,15 @@ static void tci_args_rrrc(const uint8_t **tb_ptr, *c3 =3D tci_read_b(tb_ptr); } =20 +static void tci_args_rrrm(const uint8_t **tb_ptr, + TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGMemOpIdx = *m3) +{ + *r0 =3D tci_read_r(tb_ptr); + *r1 =3D tci_read_r(tb_ptr); + *r2 =3D tci_read_r(tb_ptr); + *m3 =3D tci_read_i32(tb_ptr); +} + static void tci_args_rrrbb(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, uint8_t *i3, uint8_t *i4) { @@ -249,6 +226,16 @@ static void tci_args_rrrbb(const uint8_t **tb_ptr, TCG= Reg *r0, TCGReg *r1, *i4 =3D tci_read_b(tb_ptr); } =20 +static void tci_args_rrrrm(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, + TCGReg *r2, TCGReg *r3, TCGMemOpIdx *m4) +{ + *r0 =3D tci_read_r(tb_ptr); + *r1 =3D tci_read_r(tb_ptr); + *r2 =3D tci_read_r(tb_ptr); + *r3 =3D tci_read_r(tb_ptr); + *m4 =3D tci_read_i32(tb_ptr); +} + #if TCG_TARGET_REG_BITS =3D=3D 32 static void tci_args_rrrr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3) @@ -442,8 +429,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, uint8_t op_size =3D tb_ptr[1]; const uint8_t *old_code_ptr =3D tb_ptr; #endif - TCGReg r0, r1, r2; - tcg_target_ulong t0; + TCGReg r0, r1, r2, r3; tcg_target_ulong t1; TCGCond condition; target_ulong taddr; @@ -451,7 +437,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, uint32_t tmp32; uint64_t tmp64; #if TCG_TARGET_REG_BITS =3D=3D 32 - TCGReg r3, r4, r5; + TCGReg r4, r5; uint64_t T1, T2; #endif TCGMemOpIdx oi; @@ -838,9 +824,13 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, continue; =20 case INDEX_op_qemu_ld_i32: - t0 =3D *tb_ptr++; - taddr =3D tci_read_ulong(regs, &tb_ptr); - oi =3D tci_read_i32(&tb_ptr); + if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { + tci_args_rrm(&tb_ptr, &r0, &r1, &oi); + taddr =3D regs[r1]; + } else { + tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi); + taddr =3D tci_uint64(regs[r2], regs[r1]); + } switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) { case MO_UB: tmp32 =3D qemu_ld_ub; @@ -869,15 +859,20 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, default: g_assert_not_reached(); } - tci_write_reg(regs, t0, tmp32); + regs[r0] =3D tmp32; break; + case INDEX_op_qemu_ld_i64: - t0 =3D *tb_ptr++; - if (TCG_TARGET_REG_BITS =3D=3D 32) { - t1 =3D *tb_ptr++; + if (TCG_TARGET_REG_BITS =3D=3D 64) { + tci_args_rrm(&tb_ptr, &r0, &r1, &oi); + taddr =3D regs[r1]; + } else if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { + tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi); + taddr =3D regs[r2]; + } else { + tci_args_rrrrm(&tb_ptr, &r0, &r1, &r2, &r3, &oi); + taddr =3D tci_uint64(regs[r3], regs[r2]); } - taddr =3D tci_read_ulong(regs, &tb_ptr); - oi =3D tci_read_i32(&tb_ptr); switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) { case MO_UB: tmp64 =3D qemu_ld_ub; @@ -918,39 +913,58 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, default: g_assert_not_reached(); } - tci_write_reg(regs, t0, tmp64); if (TCG_TARGET_REG_BITS =3D=3D 32) { - tci_write_reg(regs, t1, tmp64 >> 32); + tci_write_reg64(regs, r1, r0, tmp64); + } else { + regs[r0] =3D tmp64; } break; + case INDEX_op_qemu_st_i32: - t0 =3D tci_read_rval(regs, &tb_ptr); - taddr =3D tci_read_ulong(regs, &tb_ptr); - oi =3D tci_read_i32(&tb_ptr); + if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { + tci_args_rrm(&tb_ptr, &r0, &r1, &oi); + taddr =3D regs[r1]; + } else { + tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi); + taddr =3D tci_uint64(regs[r2], regs[r1]); + } + tmp32 =3D regs[r0]; switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) { case MO_UB: - qemu_st_b(t0); + qemu_st_b(tmp32); break; case MO_LEUW: - qemu_st_lew(t0); + qemu_st_lew(tmp32); break; case MO_LEUL: - qemu_st_lel(t0); + qemu_st_lel(tmp32); break; case MO_BEUW: - qemu_st_bew(t0); + qemu_st_bew(tmp32); break; case MO_BEUL: - qemu_st_bel(t0); + qemu_st_bel(tmp32); break; default: g_assert_not_reached(); } break; + case INDEX_op_qemu_st_i64: - tmp64 =3D tci_read_r64(regs, &tb_ptr); - taddr =3D tci_read_ulong(regs, &tb_ptr); - oi =3D tci_read_i32(&tb_ptr); + if (TCG_TARGET_REG_BITS =3D=3D 64) { + tci_args_rrm(&tb_ptr, &r0, &r1, &oi); + taddr =3D regs[r1]; + tmp64 =3D regs[r0]; + } else { + if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { + tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi); + taddr =3D regs[r2]; + } else { + tci_args_rrrrm(&tb_ptr, &r0, &r1, &r2, &r3, &oi); + taddr =3D tci_uint64(regs[r3], regs[r2]); + } + tmp64 =3D tci_uint64(regs[r1], regs[r0]); + } switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) { case MO_UB: qemu_st_b(tmp64); @@ -977,6 +991,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, g_assert_not_reached(); } break; + case INDEX_op_mb: /* Ensure ordering for all kinds */ smp_mb(); --=20 2.25.1 From nobody Wed Nov 19 12:23:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id i11sm8271154otp.76.2021.03.17.08.35.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Mar 2021 08:35:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TpmlYbNPO7F5/w02gLXULWpuaIOJTbsIcBvQlSSU3dc=; b=jMG9l2Zz8efmyFaYrutRjZONkWzG9uMcJ4YqOZzOOUwqWlkcU6evSj2dvyibJQXsHM 9wlPYGgoSkj0tsmQP8Iq7qnZFNZ2vaNVqvehlprhmWi47ecFRS+eoxZ0uZjXOf0CXt1i P7JaZnGClzdeoiYcKdKOp9wsmmeXZ34sYv84ybT5bOb0L/hgALjKhcz6hDV2KoOV5Dol M30tWAQS8tGzSm4gOlExb64kZ2rgVvbsVoNv+l6OVmmEcG4S6rT6d7dDAFRIx4pR6+aa ukiApoXcS5JVmqftQ8hdVPwEXs5SHCtTbtrTqeUWWfC+AeHiSLAr8wb0Bl8tNDuWRZcM tPiA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TpmlYbNPO7F5/w02gLXULWpuaIOJTbsIcBvQlSSU3dc=; b=SWHNBi9Zd9KO+B9j5B9DtOv1VRVfZwV6ly0uwqmyxmXJ4oB9EFKpFwqRFVEsif10Om Z4Qn6iDAjhABAMmpLn+ckLXl9Ar5vhEZK20yd4QDRcRJYs99FCCQ/ExIxYHpewtBJC82 RpRI7NtsamVMxoR2A1A3UmgJo7OyKSwFuLHWFUV7gceZRL6NeE0KnpKr5E/bAbaAiGXN QQjXosHBEIZC007eG3PSiP78+rCx0UPWLw0934l0+Iv/JBquvpFOUluqLJdaU9aDCslv zyX4FjDGpm6Tq2Ejgsxz9UvQFPSa8GmvAIF2OgEUB1Cq3rvFWm/tjxCWtj6XNKWqvvvD j0gw== X-Gm-Message-State: AOAM533cVdtuO6uZTTqgvXoj0MGQtzPmggmaS91+kPZ8aWJRCEtqaJ+r VR98hl0/ajWJV8l3wkQH/hyo6LZgNsv0FrG5 X-Google-Smtp-Source: ABdhPJx4RofRHT7HB7Lc6kMAEyI4uvGzjy5OEiJowy2OfOw+oLHya7qHMfaonLhKQ97YikokxcZCGg== X-Received: by 2002:a9d:6249:: with SMTP id i9mr3876797otk.166.1615995305203; Wed, 17 Mar 2021 08:35:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 19/38] tcg/tci: Hoist op_size checking into tci_args_* Date: Wed, 17 Mar 2021 09:34:25 -0600 Message-Id: <20210317153444.310566-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210317153444.310566-1-richard.henderson@linaro.org> References: <20210317153444.310566-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::333; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) This performs the size check while reading the arguments, which means that we don't have to arrange for it to be done after the operation. Which tidies all of the branches. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/tci.c | 87 ++++++++++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 73 insertions(+), 14 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 1aa63fae4d..b3e1c93ba8 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -24,7 +24,7 @@ #if defined(CONFIG_DEBUG_TCG) # define tci_assert(cond) assert(cond) #else -# define tci_assert(cond) ((void)0) +# define tci_assert(cond) ((void)(cond)) #endif =20 #include "qemu-common.h" @@ -137,146 +137,217 @@ static tcg_target_ulong tci_read_label(const uint8_= t **tb_ptr) * s =3D signed ldst offset */ =20 +static void check_size(const uint8_t *start, const uint8_t **tb_ptr) +{ + const uint8_t *old_code_ptr =3D start - 2; + uint8_t op_size =3D old_code_ptr[1]; + tci_assert(*tb_ptr =3D=3D old_code_ptr + op_size); +} + static void tci_args_l(const uint8_t **tb_ptr, void **l0) { + const uint8_t *start =3D *tb_ptr; + *l0 =3D (void *)tci_read_label(tb_ptr); + + check_size(start, tb_ptr); } =20 static void tci_args_rr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1) { + const uint8_t *start =3D *tb_ptr; + *r0 =3D tci_read_r(tb_ptr); *r1 =3D tci_read_r(tb_ptr); + + check_size(start, tb_ptr); } =20 static void tci_args_ri(const uint8_t **tb_ptr, TCGReg *r0, tcg_target_ulong *i1) { + const uint8_t *start =3D *tb_ptr; + *r0 =3D tci_read_r(tb_ptr); *i1 =3D tci_read_i32(tb_ptr); + + check_size(start, tb_ptr); } =20 #if TCG_TARGET_REG_BITS =3D=3D 64 static void tci_args_rI(const uint8_t **tb_ptr, TCGReg *r0, tcg_target_ulong *i1) { + const uint8_t *start =3D *tb_ptr; + *r0 =3D tci_read_r(tb_ptr); *i1 =3D tci_read_i(tb_ptr); + + check_size(start, tb_ptr); } #endif =20 static void tci_args_rrm(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGMemOpIdx *m2) { + const uint8_t *start =3D *tb_ptr; + *r0 =3D tci_read_r(tb_ptr); *r1 =3D tci_read_r(tb_ptr); *m2 =3D tci_read_i32(tb_ptr); + + check_size(start, tb_ptr); } =20 static void tci_args_rrr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2) { + const uint8_t *start =3D *tb_ptr; + *r0 =3D tci_read_r(tb_ptr); *r1 =3D tci_read_r(tb_ptr); *r2 =3D tci_read_r(tb_ptr); + + check_size(start, tb_ptr); } =20 static void tci_args_rrs(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, int32_t *i2) { + const uint8_t *start =3D *tb_ptr; + *r0 =3D tci_read_r(tb_ptr); *r1 =3D tci_read_r(tb_ptr); *i2 =3D tci_read_s32(tb_ptr); + + check_size(start, tb_ptr); } =20 static void tci_args_rrcl(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGCond *c2, void **l3) { + const uint8_t *start =3D *tb_ptr; + *r0 =3D tci_read_r(tb_ptr); *r1 =3D tci_read_r(tb_ptr); *c2 =3D tci_read_b(tb_ptr); *l3 =3D (void *)tci_read_label(tb_ptr); + + check_size(start, tb_ptr); } =20 static void tci_args_rrrc(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGCond *c3) { + const uint8_t *start =3D *tb_ptr; + *r0 =3D tci_read_r(tb_ptr); *r1 =3D tci_read_r(tb_ptr); *r2 =3D tci_read_r(tb_ptr); *c3 =3D tci_read_b(tb_ptr); + + check_size(start, tb_ptr); } =20 static void tci_args_rrrm(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGMemOpIdx = *m3) { + const uint8_t *start =3D *tb_ptr; + *r0 =3D tci_read_r(tb_ptr); *r1 =3D tci_read_r(tb_ptr); *r2 =3D tci_read_r(tb_ptr); *m3 =3D tci_read_i32(tb_ptr); + + check_size(start, tb_ptr); } =20 static void tci_args_rrrbb(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, uint8_t *i3, uint8_t *i4) { + const uint8_t *start =3D *tb_ptr; + *r0 =3D tci_read_r(tb_ptr); *r1 =3D tci_read_r(tb_ptr); *r2 =3D tci_read_r(tb_ptr); *i3 =3D tci_read_b(tb_ptr); *i4 =3D tci_read_b(tb_ptr); + + check_size(start, tb_ptr); } =20 static void tci_args_rrrrm(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGMemOpIdx *m4) { + const uint8_t *start =3D *tb_ptr; + *r0 =3D tci_read_r(tb_ptr); *r1 =3D tci_read_r(tb_ptr); *r2 =3D tci_read_r(tb_ptr); *r3 =3D tci_read_r(tb_ptr); *m4 =3D tci_read_i32(tb_ptr); + + check_size(start, tb_ptr); } =20 #if TCG_TARGET_REG_BITS =3D=3D 32 static void tci_args_rrrr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3) { + const uint8_t *start =3D *tb_ptr; + *r0 =3D tci_read_r(tb_ptr); *r1 =3D tci_read_r(tb_ptr); *r2 =3D tci_read_r(tb_ptr); *r3 =3D tci_read_r(tb_ptr); + + check_size(start, tb_ptr); } =20 static void tci_args_rrrrcl(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGCond *c4, void **l5) { + const uint8_t *start =3D *tb_ptr; + *r0 =3D tci_read_r(tb_ptr); *r1 =3D tci_read_r(tb_ptr); *r2 =3D tci_read_r(tb_ptr); *r3 =3D tci_read_r(tb_ptr); *c4 =3D tci_read_b(tb_ptr); *l5 =3D (void *)tci_read_label(tb_ptr); + + check_size(start, tb_ptr); } =20 static void tci_args_rrrrrc(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGCond *c= 5) { + const uint8_t *start =3D *tb_ptr; + *r0 =3D tci_read_r(tb_ptr); *r1 =3D tci_read_r(tb_ptr); *r2 =3D tci_read_r(tb_ptr); *r3 =3D tci_read_r(tb_ptr); *r4 =3D tci_read_r(tb_ptr); *c5 =3D tci_read_b(tb_ptr); + + check_size(start, tb_ptr); } =20 static void tci_args_rrrrrr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGReg *r5) { + const uint8_t *start =3D *tb_ptr; + *r0 =3D tci_read_r(tb_ptr); *r1 =3D tci_read_r(tb_ptr); *r2 =3D tci_read_r(tb_ptr); *r3 =3D tci_read_r(tb_ptr); *r4 =3D tci_read_r(tb_ptr); *r5 =3D tci_read_r(tb_ptr); + + check_size(start, tb_ptr); } #endif =20 @@ -425,10 +496,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, =20 for (;;) { TCGOpcode opc =3D tb_ptr[0]; -#if defined(CONFIG_DEBUG_TCG) && !defined(NDEBUG) - uint8_t op_size =3D tb_ptr[1]; - const uint8_t *old_code_ptr =3D tb_ptr; -#endif TCGReg r0, r1, r2, r3; tcg_target_ulong t1; TCGCond condition; @@ -478,7 +545,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, break; case INDEX_op_br: tci_args_l(&tb_ptr, &ptr); - tci_assert(tb_ptr =3D=3D old_code_ptr + op_size); tb_ptr =3D ptr; continue; case INDEX_op_setcond_i32: @@ -631,9 +697,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, case INDEX_op_brcond_i32: tci_args_rrcl(&tb_ptr, &r0, &r1, &condition, &ptr); if (tci_compare32(regs[r0], regs[r1], condition)) { - tci_assert(tb_ptr =3D=3D old_code_ptr + op_size); tb_ptr =3D ptr; - continue; } break; #if TCG_TARGET_REG_BITS =3D=3D 32 @@ -654,7 +718,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, T1 =3D tci_uint64(regs[r1], regs[r0]); T2 =3D tci_uint64(regs[r3], regs[r2]); if (tci_compare64(T1, T2, condition)) { - tci_assert(tb_ptr =3D=3D old_code_ptr + op_size); tb_ptr =3D ptr; continue; } @@ -788,9 +851,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, case INDEX_op_brcond_i64: tci_args_rrcl(&tb_ptr, &r0, &r1, &condition, &ptr); if (tci_compare64(regs[r0], regs[r1], condition)) { - tci_assert(tb_ptr =3D=3D old_code_ptr + op_size); tb_ptr =3D ptr; - continue; } break; case INDEX_op_ext32s_i64: @@ -819,9 +880,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, =20 case INDEX_op_goto_tb: tci_args_l(&tb_ptr, &ptr); - tci_assert(tb_ptr =3D=3D old_code_ptr + op_size); tb_ptr =3D *(void **)ptr; - continue; + break; =20 case INDEX_op_qemu_ld_i32: if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { @@ -999,6 +1059,5 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, default: g_assert_not_reached(); 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id i11sm8271154otp.76.2021.03.17.08.35.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Mar 2021 08:35:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8xPoOWc8JEXoubwWfAX3Ujreq35vzVqrQT2B+bRqWlk=; b=vPI+T4YICMZA92qvFhaXvYm9eRuv90PxJ6K6KYqrQ195tF7kDzwlZ8SzYhrbuW1V5r VmMmXtvPMg/ORFwBmEoB8eE8uD4NJUc4l9iwcbbHD5oTcqTs4FauEeVej2py6duSvHB6 /o8YJqSbPaqvBjTEgAsmuFIGl/7+Ncbs+jh0fGVrXwpHbe/c13oKeaeSg0sk72Wj5ra7 VzsYrsBQ9MxLnrEZn/gQUoN17veihOXh9fvFV1uk83jowobws2gXtK6SFccyI8+xlR4K xPcRrm8pYliBtdFRhxkGyk8YerWPonO4YuZjy1wmBL9nwxBGLg/lZ8sZaHvqXpRLyNsK rdYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8xPoOWc8JEXoubwWfAX3Ujreq35vzVqrQT2B+bRqWlk=; b=oz650xh7PbFdt6YR0PiwhmwoYfnb9fTn1hLH1ensz9RxVziAYJiOOHV6pYFAopLxjU t2SmFVG6HH5BCuXTdgMEVYZl7DLSow53xcpvmrfvS/yeoV+ljLVwvHG38B2GwTWEM98Q 788s9epzgTRUBc6EX+Ada3WoyFRvct7XIOKT8kjgBbcWz5VnSVrzuTfDBXbk0pmqzOlE hD/csE6HyWEY2ksc+k5hqvhj9TKYt+30PW01lpWO+pB8kgz5L0GFcbA3FH+NrWDIvaai +JaE7MUNlqQE9ICn+OM79KFufgHsCGQjfc+uIhNnF3TbrjmWpxW62+Mx8Uzhilr4GG6/ mExQ== X-Gm-Message-State: AOAM533c1JN0RATkadz4sskmuvifUQzEeseDOnoagvrEueKI/1LSx8CG suMA6kvohJ/kFKQoRINmtj4Yy8Z7+7JjDPk5 X-Google-Smtp-Source: ABdhPJw2Ty5vJQM9O8Eyuu6EH5QPhQXP9W8m1ovoQHimCmmSh7vwF27tUNTYsFDb2b9m1cRZlFJMWQ== X-Received: by 2002:a9d:65cf:: with SMTP id z15mr3727099oth.310.1615995306171; Wed, 17 Mar 2021 08:35:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 20/38] tcg/tci: Remove tci_disas Date: Wed, 17 Mar 2021 09:34:26 -0600 Message-Id: <20210317153444.310566-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210317153444.310566-1-richard.henderson@linaro.org> References: <20210317153444.310566-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32c; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FUZZY_BITCOIN=0.017, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) This function is unused. It's not even the disassembler, which is print_insn_tci, located in disas/tci.c. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 2 -- tcg/tci/tcg-target.c.inc | 10 ---------- 2 files changed, 12 deletions(-) diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 9285c930a2..52af6d8bc5 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -163,8 +163,6 @@ typedef enum { #define TCG_TARGET_CALL_STACK_OFFSET 0 #define TCG_TARGET_STACK_ALIGN 16 =20 -void tci_disas(uint8_t opc); - #define HAVE_TCG_QEMU_TB_EXEC =20 /* We could notice __i386__ or __s390x__ and reduce the barriers depending diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 6c187a25cc..7fb3b04eaf 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -253,16 +253,6 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int t= ype, return true; } =20 -#if defined(CONFIG_DEBUG_TCG_INTERPRETER) -/* Show current bytecode. Used by tcg interpreter. */ -void tci_disas(uint8_t opc) -{ - const TCGOpDef *def =3D &tcg_op_defs[opc]; - fprintf(stderr, "TCG %s %u, %u, %u\n", - def->name, def->nb_oargs, def->nb_iargs, def->nb_cargs); -} -#endif - /* Write value (native size). */ static void tcg_out_i(TCGContext *s, tcg_target_ulong v) { --=20 2.25.1 From nobody Wed Nov 19 12:23:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1615997228; cv=none; d=zohomail.com; s=zohoarc; b=mQbgmM87DP6vfMQYWdz1TvHb6nn3rRQQGZt/1lbBJdomXKl0aZg+o/XOtD3/jtwKlyYy/8WmPFtU8jbFgVtjozhNG5Qqhi9HwpDgaMHL47US8QKixFUIIKOhqe0xDJJsgS/54TneRwRU7nVGn1oA6rnyO865pktCPLCeaQ+IQ+I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615997228; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=q8TPNZDVr/5S20Kcc+tI61ZMTKujSdr9HThMmmaIzTU=; b=CB7kv32Demeq+E1UVvim7n4YdTvAmMBhF1BTDPInEqQTRIZyhozju5Qqaq8kqXEMEQx2rzk4x41YGJnI2zMpgvGcfdcDTZqJDQM67FbIlTo8WBthcph7Ytzx4P4LNMo5+Om7NiFDS2QljcCSzdWU+21BWDS4PrpTPuFO5UpvOJ4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1615997228289999.0977527288377; Wed, 17 Mar 2021 09:07:08 -0700 (PDT) Received: from localhost ([::1]:57414 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lMYhO-00076Z-RK for importer@patchew.org; Wed, 17 Mar 2021 12:07:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50118) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lMYCb-0005Id-AM for qemu-devel@nongnu.org; Wed, 17 Mar 2021 11:35:19 -0400 Received: from mail-ot1-x329.google.com ([2607:f8b0:4864:20::329]:34812) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lMYCS-0007EQ-D6 for qemu-devel@nongnu.org; Wed, 17 Mar 2021 11:35:16 -0400 Received: by mail-ot1-x329.google.com with SMTP id k14-20020a9d7dce0000b02901b866632f29so2183446otn.1 for ; Wed, 17 Mar 2021 08:35:07 -0700 (PDT) Received: from localhost.localdomain (fixed-187-189-51-144.totalplay.net. [187.189.51.144]) by smtp.gmail.com with ESMTPSA id i11sm8271154otp.76.2021.03.17.08.35.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Mar 2021 08:35:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=q8TPNZDVr/5S20Kcc+tI61ZMTKujSdr9HThMmmaIzTU=; b=dKLniXTNTsVYeMOZxVTQx4U5P1NXy5btSThvXtvvuoGYV9+RRFpYYwRb6HSqCrhBSQ 6JC9rnMkjI3E0v4yz6CXh9K7cV9NkEx/wUAkDTMx3kMNDo7CGROgG8gROOEldrYjfpn6 VjGXOfsSTzpG3TH0XlgImM4wKh5YRkackZtmuIvYUWdD3RsPPUM7Swxd6ve6eI1G4wsR MApyVzh2Zd9sMGs0wuHilBUjt2zzj9mPIZt1r+nALmRuq8/Z9U1eUVKGyz6cjq3+VtEL 0Qy8HfWaz12rYXniRC1Lc2zWvvx4gkEpmhHe4wA/ZNbMXH/uVgtrPg4TjjCXANxYOAT7 H/fA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=q8TPNZDVr/5S20Kcc+tI61ZMTKujSdr9HThMmmaIzTU=; b=GLHVFO+qq1sPw+4gsNxZXAYgQbDkzazVwXFXSleyXxibqxopoh/HBmwj75jKRESzEs 7gB8iew+hnYqz8Ufsb5/a58Nb0DUCz0jMbxK1oqaUyjK+WqeOnaFUNZG7SCrSWemriBD uQpql9s2NSRxkFpbN7RI2LMl7/OCmtlHZDyCVi0RC+DjInLMVB634ku+7JuK+39F/RUI QmunxXT2+yBoohMAGMRmmxfQivxeCgtQjUt0Bvth9wTSu9mHuIl1DG0psLWHXVkk5uA0 2s/EJYAXnkNk14UZcaBG7zdPG2jtN5nmfZxq4lGWvGtqSDK5FNuglY6i8+WBIcbYOjMp XqFw== X-Gm-Message-State: AOAM530L1tb1UcGuW8qWL/nSHZYgWwg1kPrRvJKsfsT3zxMTiVaskGOO /84IMqQgFeX8dv/nfLpdzSObWbhUZKM9H6DL X-Google-Smtp-Source: ABdhPJwLpivpVXSBcXI8WSu9TQ9itQk7B1vmexPBbvQTCEA3FIIOFf3iZuYBUHgdOfhdfdN5AOE8vw== X-Received: by 2002:a9d:3b86:: with SMTP id k6mr3905774otc.194.1615995307213; Wed, 17 Mar 2021 08:35:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 21/38] tcg/tci: Implement the disassembler properly Date: Wed, 17 Mar 2021 09:34:27 -0600 Message-Id: <20210317153444.310566-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210317153444.310566-1-richard.henderson@linaro.org> References: <20210317153444.310566-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::329; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Actually print arguments as opposed to simply the opcodes and, uselessly, the argument counts. Reuse all of the helpers developed as part of the interpreter. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- meson.build | 2 +- include/tcg/tcg-opc.h | 2 - disas/tci.c | 61 --------- tcg/tci.c | 283 ++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 284 insertions(+), 64 deletions(-) delete mode 100644 disas/tci.c diff --git a/meson.build b/meson.build index a7d2dd429d..5c85a15364 100644 --- a/meson.build +++ b/meson.build @@ -1943,7 +1943,7 @@ specific_ss.add(when: 'CONFIG_TCG', if_true: files( 'tcg/tcg-op.c', 'tcg/tcg.c', )) -specific_ss.add(when: 'CONFIG_TCG_INTERPRETER', if_true: files('disas/tci.= c', 'tcg/tci.c')) +specific_ss.add(when: 'CONFIG_TCG_INTERPRETER', if_true: files('tcg/tci.c'= )) =20 subdir('backends') subdir('disas') diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h index 900984c005..bbb0884af8 100644 --- a/include/tcg/tcg-opc.h +++ b/include/tcg/tcg-opc.h @@ -278,10 +278,8 @@ DEF(last_generic, 0, 0, 0, TCG_OPF_NOT_PRESENT) #ifdef TCG_TARGET_INTERPRETER /* These opcodes are only for use between the tci generator and interprete= r. */ DEF(tci_movi_i32, 1, 0, 1, TCG_OPF_NOT_PRESENT) -#if TCG_TARGET_REG_BITS =3D=3D 64 DEF(tci_movi_i64, 1, 0, 1, TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT) #endif -#endif =20 #undef TLADDR_ARGS #undef DATA64_ARGS diff --git a/disas/tci.c b/disas/tci.c deleted file mode 100644 index f1d6c6b469..0000000000 --- a/disas/tci.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Tiny Code Interpreter for QEMU - disassembler - * - * Copyright (c) 2011 Stefan Weil - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include "qemu/osdep.h" -#include "qemu-common.h" -#include "disas/dis-asm.h" -#include "tcg/tcg.h" - -/* Disassemble TCI bytecode. */ -int print_insn_tci(bfd_vma addr, disassemble_info *info) -{ - int length; - uint8_t byte; - int status; - TCGOpcode op; - - status =3D info->read_memory_func(addr, &byte, 1, info); - if (status !=3D 0) { - info->memory_error_func(status, addr, info); - return -1; - } - op =3D byte; - - addr++; - status =3D info->read_memory_func(addr, &byte, 1, info); - if (status !=3D 0) { - info->memory_error_func(status, addr, info); - return -1; - } - length =3D byte; - - if (op >=3D tcg_op_defs_max) { - info->fprintf_func(info->stream, "illegal opcode %d", op); - } else { - const TCGOpDef *def =3D &tcg_op_defs[op]; - int nb_oargs =3D def->nb_oargs; - int nb_iargs =3D def->nb_iargs; - int nb_cargs =3D def->nb_cargs; - /* TODO: Improve disassembler output. */ - info->fprintf_func(info->stream, "%s\to=3D%d i=3D%d c=3D%d", - def->name, nb_oargs, nb_iargs, nb_cargs); - } - - return length; -} diff --git a/tcg/tci.c b/tcg/tci.c index b3e1c93ba8..d68c5a4e55 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -1061,3 +1061,286 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArch= State *env, } } } + +/* + * Disassembler that matches the interpreter + */ + +static const char *str_r(TCGReg r) +{ + static const char regs[TCG_TARGET_NB_REGS][4] =3D { + "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", + "r8", "r9", "r10", "r11", "r12", "r13", "env", "sp" + }; + + QEMU_BUILD_BUG_ON(TCG_AREG0 !=3D TCG_REG_R14); + QEMU_BUILD_BUG_ON(TCG_REG_CALL_STACK !=3D TCG_REG_R15); + + assert((unsigned)r < TCG_TARGET_NB_REGS); + return regs[r]; +} + +static const char *str_c(TCGCond c) +{ + static const char cond[16][8] =3D { + [TCG_COND_NEVER] =3D "never", + [TCG_COND_ALWAYS] =3D "always", + [TCG_COND_EQ] =3D "eq", + [TCG_COND_NE] =3D "ne", + [TCG_COND_LT] =3D "lt", + [TCG_COND_GE] =3D "ge", + [TCG_COND_LE] =3D "le", + [TCG_COND_GT] =3D "gt", + [TCG_COND_LTU] =3D "ltu", + [TCG_COND_GEU] =3D "geu", + [TCG_COND_LEU] =3D "leu", + [TCG_COND_GTU] =3D "gtu", + }; + + assert((unsigned)c < ARRAY_SIZE(cond)); + assert(cond[c][0] !=3D 0); + return cond[c]; +} + +/* Disassemble TCI bytecode. */ +int print_insn_tci(bfd_vma addr, disassemble_info *info) +{ + uint8_t buf[256]; + int length, status; + const TCGOpDef *def; + const char *op_name; + TCGOpcode op; + TCGReg r0, r1, r2, r3; +#if TCG_TARGET_REG_BITS =3D=3D 32 + TCGReg r4, r5; +#endif + tcg_target_ulong i1; + int32_t s2; + TCGCond c; + TCGMemOpIdx oi; + uint8_t pos, len; + void *ptr; + const uint8_t *tb_ptr; + + status =3D info->read_memory_func(addr, buf, 2, info); + if (status !=3D 0) { + info->memory_error_func(status, addr, info); + return -1; + } + op =3D buf[0]; + length =3D buf[1]; + + if (length < 2) { + info->fprintf_func(info->stream, "invalid length %d", length); + return 1; + } + + status =3D info->read_memory_func(addr + 2, buf + 2, length - 2, info); + if (status !=3D 0) { + info->memory_error_func(status, addr + 2, info); + return -1; + } + + def =3D &tcg_op_defs[op]; + op_name =3D def->name; + tb_ptr =3D buf + 2; + + switch (op) { + case INDEX_op_br: + case INDEX_op_call: + case INDEX_op_exit_tb: + case INDEX_op_goto_tb: + tci_args_l(&tb_ptr, &ptr); + info->fprintf_func(info->stream, "%-12s %p", op_name, ptr); + break; + + case INDEX_op_brcond_i32: + case INDEX_op_brcond_i64: + tci_args_rrcl(&tb_ptr, &r0, &r1, &c, &ptr); + info->fprintf_func(info->stream, "%-12s %s, %s, %s, %p", + op_name, str_r(r0), str_r(r1), str_c(c), ptr); + break; + + case INDEX_op_setcond_i32: + case INDEX_op_setcond_i64: + tci_args_rrrc(&tb_ptr, &r0, &r1, &r2, &c); + info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s", + op_name, str_r(r0), str_r(r1), str_r(r2), str_c= (c)); + break; + + case INDEX_op_tci_movi_i32: + tci_args_ri(&tb_ptr, &r0, &i1); + info->fprintf_func(info->stream, "%-12s %s, 0x%" TCG_PRIlx, + op_name, str_r(r0), i1); + break; + +#if TCG_TARGET_REG_BITS =3D=3D 64 + case INDEX_op_tci_movi_i64: + tci_args_rI(&tb_ptr, &r0, &i1); + info->fprintf_func(info->stream, "%-12s %s, 0x%" TCG_PRIlx, + op_name, str_r(r0), i1); + break; +#endif + + case INDEX_op_ld8u_i32: + case INDEX_op_ld8u_i64: + case INDEX_op_ld8s_i32: + case INDEX_op_ld8s_i64: + case INDEX_op_ld16u_i32: + case INDEX_op_ld16u_i64: + case INDEX_op_ld16s_i32: + case INDEX_op_ld16s_i64: + case INDEX_op_ld32u_i64: + case INDEX_op_ld32s_i64: + case INDEX_op_ld_i32: + case INDEX_op_ld_i64: + case INDEX_op_st8_i32: + case INDEX_op_st8_i64: + case INDEX_op_st16_i32: + case INDEX_op_st16_i64: + case INDEX_op_st32_i64: + case INDEX_op_st_i32: + case INDEX_op_st_i64: + tci_args_rrs(&tb_ptr, &r0, &r1, &s2); + info->fprintf_func(info->stream, "%-12s %s, %s, %d", + op_name, str_r(r0), str_r(r1), s2); + break; + + case INDEX_op_mov_i32: + case INDEX_op_mov_i64: + case INDEX_op_ext8s_i32: + case INDEX_op_ext8s_i64: + case INDEX_op_ext8u_i32: + case INDEX_op_ext8u_i64: + case INDEX_op_ext16s_i32: + case INDEX_op_ext16s_i64: + case INDEX_op_ext16u_i32: + case INDEX_op_ext32s_i64: + case INDEX_op_ext32u_i64: + case INDEX_op_ext_i32_i64: + case INDEX_op_extu_i32_i64: + case INDEX_op_bswap16_i32: + case INDEX_op_bswap16_i64: + case INDEX_op_bswap32_i32: + case INDEX_op_bswap32_i64: + case INDEX_op_bswap64_i64: + case INDEX_op_not_i32: + case INDEX_op_not_i64: + case INDEX_op_neg_i32: + case INDEX_op_neg_i64: + tci_args_rr(&tb_ptr, &r0, &r1); + info->fprintf_func(info->stream, "%-12s %s, %s", + op_name, str_r(r0), str_r(r1)); + break; + + case INDEX_op_add_i32: + case INDEX_op_add_i64: + case INDEX_op_sub_i32: + case INDEX_op_sub_i64: + case INDEX_op_mul_i32: + case INDEX_op_mul_i64: + case INDEX_op_and_i32: + case INDEX_op_and_i64: + case INDEX_op_or_i32: + case INDEX_op_or_i64: + case INDEX_op_xor_i32: + case INDEX_op_xor_i64: + case INDEX_op_div_i32: + case INDEX_op_div_i64: + case INDEX_op_rem_i32: + case INDEX_op_rem_i64: + case INDEX_op_divu_i32: + case INDEX_op_divu_i64: + case INDEX_op_remu_i32: + case INDEX_op_remu_i64: + case INDEX_op_shl_i32: + case INDEX_op_shl_i64: + case INDEX_op_shr_i32: + case INDEX_op_shr_i64: + case INDEX_op_sar_i32: + case INDEX_op_sar_i64: + case INDEX_op_rotl_i32: + case INDEX_op_rotl_i64: + case INDEX_op_rotr_i32: + case INDEX_op_rotr_i64: + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + info->fprintf_func(info->stream, "%-12s %s, %s, %s", + op_name, str_r(r0), str_r(r1), str_r(r2)); + break; + + case INDEX_op_deposit_i32: + case INDEX_op_deposit_i64: + tci_args_rrrbb(&tb_ptr, &r0, &r1, &r2, &pos, &len); + info->fprintf_func(info->stream, "%-12s %s, %s, %s, %d, %d", + op_name, str_r(r0), str_r(r1), str_r(r2), pos, = len); + break; + +#if TCG_TARGET_REG_BITS =3D=3D 32 + case INDEX_op_setcond2_i32: + tci_args_rrrrrc(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &c); + info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s, %s, %s", + op_name, str_r(r0), str_r(r1), str_r(r2), + str_r(r3), str_r(r4), str_c(c)); + break; + + case INDEX_op_brcond2_i32: + tci_args_rrrrcl(&tb_ptr, &r0, &r1, &r2, &r3, &c, &ptr); + info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s, %s, %p", + op_name, str_r(r0), str_r(r1), + str_r(r2), str_r(r3), str_c(c), ptr); + break; + + case INDEX_op_mulu2_i32: + tci_args_rrrr(&tb_ptr, &r0, &r1, &r2, &r3); + info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s", + op_name, str_r(r0), str_r(r1), + str_r(r2), str_r(r3)); + break; + + case INDEX_op_add2_i32: + case INDEX_op_sub2_i32: + tci_args_rrrrrr(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &r5); + info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s, %s, %s", + op_name, str_r(r0), str_r(r1), str_r(r2), + str_r(r3), str_r(r4), str_r(r5)); + break; +#endif + + case INDEX_op_qemu_ld_i64: + case INDEX_op_qemu_st_i64: + len =3D DIV_ROUND_UP(64, TCG_TARGET_REG_BITS); + goto do_qemu_ldst; + case INDEX_op_qemu_ld_i32: + case INDEX_op_qemu_st_i32: + len =3D 1; + do_qemu_ldst: + len +=3D DIV_ROUND_UP(TARGET_LONG_BITS, TCG_TARGET_REG_BITS); + switch (len) { + case 2: + tci_args_rrm(&tb_ptr, &r0, &r1, &oi); + info->fprintf_func(info->stream, "%-12s %s, %s, %x", + op_name, str_r(r0), str_r(r1), oi); + break; + case 3: + tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi); + info->fprintf_func(info->stream, "%-12s %s, %s, %s, %x", + op_name, str_r(r0), str_r(r1), str_r(r2), o= i); + break; + case 4: + tci_args_rrrrm(&tb_ptr, &r0, &r1, &r2, &r3, &oi); + info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s, %x", + op_name, str_r(r0), str_r(r1), + str_r(r2), str_r(r3), oi); + break; + default: + g_assert_not_reached(); + } + break; + + default: + info->fprintf_func(info->stream, "illegal opcode %d", op); + break; + } + + return length; +} --=20 2.25.1 From nobody Wed Nov 19 12:23:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1615996065; cv=none; d=zohomail.com; s=zohoarc; b=PcCOFMkj2ugf2oNuqcd051AAMmWanx4+U3X+AveFjVC59EFp1l54UwKveJ9/oZg9r0BCGaMX6HkyMMWGIWxAKu/MakopAwU9iiOxwdTs+XpFJB92q9VjL+WJDDid8QKIzxqThHJcDRz/egN3mAIcHf6N6pND6m3tGzL3fXWgjfs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615996065; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id i11sm8271154otp.76.2021.03.17.08.35.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Mar 2021 08:35:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Jxlf9j4i3P6aWFIN0pGtiPy9SuEouipzz5x6uws4lSA=; b=mVw9aZ+AWtQP2M3KkbIzO8plZC4q8rMJ0AuAKOZIW3BEVnIyO0Emi1qnH+o8wRmb6n IkdbJc6nrVNm4Cw/SXkOt1MXJ5yQ4EB/GCnUzpzz8DiWpCpAFRzAyoHg2W5hlruKKFEe vlfvflQhlW6paLAa4p6aA4k1tSose36amezxf1GV/NGIvrkCcoMcjxmhuGvApzC+LjyR C8vxaORLskNAcFzz/3k/IrbJ3lWcFhJeY/jI5KU25r1Ejhr7lB+C1d5FLSv31sGZX9ez dTRk6VMtt1/b7VXJlUUyzfOjy0sXDZ+SpOWnWZmTe1nzmHjhGzQr3nLrIxtbYLFw0PCM 6d0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Jxlf9j4i3P6aWFIN0pGtiPy9SuEouipzz5x6uws4lSA=; b=WXFddFULoJIqgyNln35uwSFQ9QP9PyglZ4k7EqV5UmJYmWsFDJxo+HsDWJAk2/yrJE ebM+LVYpjJzrOYHqkeSNtMsHpFSp7z9RaIq8DK5a8vAv51KQhWpbQx7Oyag2tRG5CvPh a6Em+BqaPsudi3swxnpurlZSJwuozChBVwu5cEkv7GaUWBnPL5ZlcKvNnV7hmw/Qafh/ WhW5Os8dSyyNpyrU2CYXLeqsxiwS9pOx72rCmB+nxHZORSgY+PC8m2xcS4zN1754Z9dV 6J0GgH2oXrXHfZBSTFmwAqyqVSOLjY9HnuzsUFTwp6S6cQ1o/mcWkqqskZ6mJyhBqRjC cbig== X-Gm-Message-State: AOAM531JpLhpZXyLkQnr4ezIVIyS28/fszHjU4GmuOSLyBmAxhatO6dC TAqXTTizYhtm5Ncl4X7tuTXJm45wa0C3A4s/ X-Google-Smtp-Source: ABdhPJw9qbSNSIIBUuIceUz8umhlwz3ogKSDwzFZmypJFjmzgsIaBJ1ekzHGnTXuuHS8AySruvMVYQ== X-Received: by 2002:a9d:24c7:: with SMTP id z65mr3856678ota.243.1615995308213; Wed, 17 Mar 2021 08:35:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 22/38] tcg/tci: Push opcode emit into each case Date: Wed, 17 Mar 2021 09:34:28 -0600 Message-Id: <20210317153444.310566-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210317153444.310566-1-richard.henderson@linaro.org> References: <20210317153444.310566-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32e; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) We're about to split out bytecode output into helpers, but we can't do that one at a time if tcg_out_op_t is being done outside of the switch. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 35 ++++++++++++++++++++++++++++++++--- 1 file changed, 32 insertions(+), 3 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 7fb3b04eaf..c5b061fe76 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -385,40 +385,48 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, { uint8_t *old_code_ptr =3D s->code_ptr; =20 - tcg_out_op_t(s, opc); - switch (opc) { case INDEX_op_exit_tb: + tcg_out_op_t(s, opc); tcg_out_i(s, args[0]); + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; =20 case INDEX_op_goto_tb: tcg_debug_assert(s->tb_jmp_insn_offset =3D=3D 0); /* indirect jump method. */ + tcg_out_op_t(s, opc); tcg_out_i(s, (uintptr_t)(s->tb_jmp_target_addr + args[0])); + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; set_jmp_reset_offset(s, args[0]); break; =20 case INDEX_op_br: + tcg_out_op_t(s, opc); tci_out_label(s, arg_label(args[0])); + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; =20 CASE_32_64(setcond) + tcg_out_op_t(s, opc); tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_out_r(s, args[2]); tcg_out8(s, args[3]); /* condition */ + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; =20 #if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_setcond2_i32: /* setcond2_i32 cond, t0, t1_low, t1_high, t2_low, t2_high */ + tcg_out_op_t(s, opc); tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_out_r(s, args[2]); tcg_out_r(s, args[3]); tcg_out_r(s, args[4]); tcg_out8(s, args[5]); /* condition */ + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; #endif =20 @@ -436,10 +444,12 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, CASE_64(st32) CASE_64(st) stack_bounds_check(args[1], args[2]); + tcg_out_op_t(s, opc); tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_debug_assert(args[2] =3D=3D (int32_t)args[2]); tcg_out32(s, args[2]); + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; =20 CASE_32_64(add) @@ -462,12 +472,15 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, CASE_32_64(divu) /* Optional (TCG_TARGET_HAS_div_*). */ CASE_32_64(rem) /* Optional (TCG_TARGET_HAS_div_*). */ CASE_32_64(remu) /* Optional (TCG_TARGET_HAS_div_*). */ + tcg_out_op_t(s, opc); tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_out_r(s, args[2]); + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; =20 CASE_32_64(deposit) /* Optional (TCG_TARGET_HAS_deposit_*). */ + tcg_out_op_t(s, opc); { TCGArg pos =3D args[3], len =3D args[4]; TCGArg max =3D opc =3D=3D INDEX_op_deposit_i32 ? 32 : 64; @@ -481,13 +494,16 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, tcg_out8(s, pos); tcg_out8(s, len); } + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; =20 CASE_32_64(brcond) + tcg_out_op_t(s, opc); tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_out8(s, args[2]); /* condition */ tci_out_label(s, arg_label(args[3])); + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; =20 CASE_32_64(neg) /* Optional (TCG_TARGET_HAS_neg_*). */ @@ -503,48 +519,59 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, CASE_32_64(bswap16) /* Optional (TCG_TARGET_HAS_bswap16_*). */ CASE_32_64(bswap32) /* Optional (TCG_TARGET_HAS_bswap32_*). */ CASE_64(bswap64) /* Optional (TCG_TARGET_HAS_bswap64_i64). */ + tcg_out_op_t(s, opc); tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; =20 #if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_add2_i32: case INDEX_op_sub2_i32: + tcg_out_op_t(s, opc); tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_out_r(s, args[2]); tcg_out_r(s, args[3]); tcg_out_r(s, args[4]); tcg_out_r(s, args[5]); + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; case INDEX_op_brcond2_i32: + tcg_out_op_t(s, opc); tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_out_r(s, args[2]); tcg_out_r(s, args[3]); tcg_out8(s, args[4]); /* condition */ tci_out_label(s, arg_label(args[5])); + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; case INDEX_op_mulu2_i32: + tcg_out_op_t(s, opc); tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_out_r(s, args[2]); tcg_out_r(s, args[3]); + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; #endif =20 case INDEX_op_qemu_ld_i32: case INDEX_op_qemu_st_i32: + tcg_out_op_t(s, opc); tcg_out_r(s, *args++); tcg_out_r(s, *args++); if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { tcg_out_r(s, *args++); } tcg_out32(s, *args++); + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; =20 case INDEX_op_qemu_ld_i64: case INDEX_op_qemu_st_i64: + tcg_out_op_t(s, opc); tcg_out_r(s, *args++); if (TCG_TARGET_REG_BITS =3D=3D 32) { tcg_out_r(s, *args++); @@ -554,9 +581,12 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, tcg_out_r(s, *args++); } tcg_out32(s, *args++); + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; =20 case INDEX_op_mb: + tcg_out_op_t(s, opc); + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::333; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 84 +++++++++++++++++++--------------------- 1 file changed, 39 insertions(+), 45 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index c5b061fe76..bb4dd76211 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -297,32 +297,38 @@ static void stack_bounds_check(TCGReg base, target_lo= ng offset) } } =20 -static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg= 1, - intptr_t arg2) +static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op, + TCGReg r0, TCGReg r1, intptr_t i2) { uint8_t *old_code_ptr =3D s->code_ptr; =20 - stack_bounds_check(arg1, arg2); - if (type =3D=3D TCG_TYPE_I32) { - tcg_out_op_t(s, INDEX_op_ld_i32); - tcg_out_r(s, ret); - tcg_out_r(s, arg1); - tcg_out32(s, arg2); - } else { - tcg_debug_assert(type =3D=3D TCG_TYPE_I64); -#if TCG_TARGET_REG_BITS =3D=3D 64 - tcg_out_op_t(s, INDEX_op_ld_i64); - tcg_out_r(s, ret); - tcg_out_r(s, arg1); - tcg_debug_assert(arg2 =3D=3D (int32_t)arg2); - tcg_out32(s, arg2); -#else - TODO(); -#endif - } + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_debug_assert(i2 =3D=3D (int32_t)i2); + tcg_out32(s, i2); + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg val, TCGReg bas= e, + intptr_t offset) +{ + stack_bounds_check(base, offset); + switch (type) { + case TCG_TYPE_I32: + tcg_out_op_rrs(s, INDEX_op_ld_i32, val, base, offset); + break; +#if TCG_TARGET_REG_BITS =3D=3D 64 + case TCG_TYPE_I64: + tcg_out_op_rrs(s, INDEX_op_ld_i64, val, base, offset); + break; +#endif + default: + g_assert_not_reached(); + } +} + static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g) { uint8_t *old_code_ptr =3D s->code_ptr; @@ -444,12 +450,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, CASE_64(st32) CASE_64(st) stack_bounds_check(args[1], args[2]); - tcg_out_op_t(s, opc); - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_debug_assert(args[2] =3D=3D (int32_t)args[2]); - tcg_out32(s, args[2]); - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out_op_rrs(s, opc, args[0], args[1], args[2]); break; =20 CASE_32_64(add) @@ -597,29 +598,22 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, } } =20 -static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg= 1, - intptr_t arg2) +static void tcg_out_st(TCGContext *s, TCGType type, TCGReg val, TCGReg bas= e, + intptr_t offset) { - uint8_t *old_code_ptr =3D s->code_ptr; - - stack_bounds_check(arg1, arg2); - if (type =3D=3D TCG_TYPE_I32) { - tcg_out_op_t(s, INDEX_op_st_i32); - tcg_out_r(s, arg); - tcg_out_r(s, arg1); - tcg_out32(s, arg2); - } else { - tcg_debug_assert(type =3D=3D TCG_TYPE_I64); + stack_bounds_check(base, offset); + switch (type) { + case TCG_TYPE_I32: + tcg_out_op_rrs(s, INDEX_op_st_i32, val, base, offset); + break; #if TCG_TARGET_REG_BITS =3D=3D 64 - tcg_out_op_t(s, INDEX_op_st_i64); - tcg_out_r(s, arg); - tcg_out_r(s, arg1); - tcg_out32(s, arg2); -#else - TODO(); + case TCG_TYPE_I64: + tcg_out_op_rrs(s, INDEX_op_st_i64, val, base, offset); + break; #endif + default: + g_assert_not_reached(); } - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, --=20 2.25.1 From nobody Wed Nov 19 12:23:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::335; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index bb4dd76211..bf2733d42b 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -297,6 +297,16 @@ static void stack_bounds_check(TCGReg base, target_lon= g offset) } } =20 +static void tcg_out_op_l(TCGContext *s, TCGOpcode op, TCGLabel *l0) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tci_out_label(s, l0); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, intptr_t i2) { @@ -408,9 +418,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, co= nst TCGArg *args, break; =20 case INDEX_op_br: - tcg_out_op_t(s, opc); - tci_out_label(s, arg_label(args[0])); - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out_op_l(s, opc, arg_label(args[0])); break; =20 CASE_32_64(setcond) --=20 2.25.1 From nobody Wed Nov 19 12:23:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1615997433; cv=none; d=zohomail.com; s=zohoarc; b=U1DGKxjfY+hzr9TbkOE4R0IK5l1d19ejyqiv5K252kcrx4rKtRK7dQzkDpw3tpuSm+3BMrcP2R2/AVCJSFVi8Wi6l7c9bgM1aa6H4ixvL1CO2BiKymj/dnIuNrntD4V1no6CNoEhxXbJMb/B4GUiKEQpinkQvx7IgObFowJmUPI= ARC-Message-Signature: i=1; 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id i11sm8271154otp.76.2021.03.17.08.35.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Mar 2021 08:35:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9gOc+vBqXpfUn2Q8eNd5OOU1iZ9hXi0uS626WbgV7Zk=; b=zGPUcW4C+D3jLTbjKQcxrpUkmWrZAOkXAd/xgMjxQXZISUISPNSOdm6EIF4SwA3be8 BShzd8KdUrQXL55mMCEFtPsiuXspOT/67k8LS4ObjaCL54rk7PlssExyJ3UlMtqrQVqp DsjlhnB3SV4HbFuULrqBJuiFi7BjOOMG+EqAjwaItZ4fYn8VXVPkRgymZ8zdG1mIOJ8R rmEetQo/eTz+1qjbT/6gHHIuPHl3an451nkP4s9OgqqhICPehqqRN10+57vN6qjtxj6E VdOSguYF8FlrFfT0/rq6M0Jx0og5keVCWq1x2TuvdQSXF21W/ak7dV7OdH/d3m9QSWQh Xykg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9gOc+vBqXpfUn2Q8eNd5OOU1iZ9hXi0uS626WbgV7Zk=; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::332; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index bf2733d42b..85c5ab5a08 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -307,6 +307,16 @@ static void tcg_out_op_l(TCGContext *s, TCGOpcode op, = TCGLabel *l0) old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +static void tcg_out_op_p(TCGContext *s, TCGOpcode op, void *p0) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_i(s, (uintptr_t)p0); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, intptr_t i2) { @@ -403,17 +413,13 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, =20 switch (opc) { case INDEX_op_exit_tb: - tcg_out_op_t(s, opc); - tcg_out_i(s, args[0]); - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out_op_p(s, opc, (void *)args[0]); break; =20 case INDEX_op_goto_tb: tcg_debug_assert(s->tb_jmp_insn_offset =3D=3D 0); /* indirect jump method. */ - tcg_out_op_t(s, opc); - tcg_out_i(s, (uintptr_t)(s->tb_jmp_target_addr + args[0])); - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out_op_p(s, opc, s->tb_jmp_target_addr + args[0]); set_jmp_reset_offset(s, args[0]); break; =20 --=20 2.25.1 From nobody Wed Nov 19 12:23:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id i11sm8271154otp.76.2021.03.17.08.35.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Mar 2021 08:35:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kaB/usyGMCTopUHUsqMJlKWSU0ljEaKqjVTihcu+D7c=; b=PoVBWjkgUukh7r4zYlruwVUzuT19JEDuT6fklEW0T4Ti7zGuYcA36BLvV9tvbZcdRI GC4k6Hph27F2YEaHBnvbSt9SpaUBKcsgBkhW5HYeMrGWu17jcATW17eC+LvaLpwmrhTO A9uamqp7YNnUhn1RDjFCvbp5uF0rZhIBEbo9J7sEJJoduGQazmErG91kVNLSXJQSbjhg dX+tCcDB/+pWtuuCgGBAy/mF7bbeomxP8oI30B81oIGd28M2rQR3qGlqDfYIL0En8Dc1 0FJ7IYLlOdKF3rlociECfiKmTFFjrw5oG1kTm0mj5iHebaMEOkXmZ/pzkoUBv2dQbXlx 1OXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kaB/usyGMCTopUHUsqMJlKWSU0ljEaKqjVTihcu+D7c=; b=ewlwXZROx2TDHH1Uo9XiJgaKgdy1RHUfWtUxrEme/+jmIZj/Km3C0AhaPAr09cNwMx RNS7ZklFfMF9U9g1SJ4pmDt22dUVqZavFsrugql/4sNgCgEzurPJL7G6q8+gd6NH93lk HpZjO98PoQSdHOhnAcwPnHSV4t0qyO9tzZyrxRmNbo2KJzhO5unGj6tzNHj+Bae4f/3o FX/5qB7IITKEjG4PhAEHxY6fonqoXW3RDfMnp9LFt9/7oGsbU5a+yuvR+YtE2hT73l0d e6T0v9cx/gxaYCQOy87l7895O3fTE6K9hlEsOmpANLfGt8jiFNpYhXoF5Rxq/2LIEHc0 ebSg== X-Gm-Message-State: AOAM533iWCgLeyFUnSjpRylehrukUsX27j0SoXqfiMBBZxQGQjWRZBM4 J66eXf68hRi8kIZ4ZMkjHYpgRmZcVB6CUtT7 X-Google-Smtp-Source: ABdhPJw4EHOvc/BDmTCvLqM2eY4jZrB/+sPtebrW4U0kD+PWH6KNQQsw4boXDC9GSfYYZdH00YYTuQ== X-Received: by 2002:a9d:6013:: with SMTP id h19mr3805134otj.72.1615995312501; Wed, 17 Mar 2021 08:35:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 26/38] tcg/tci: Split out tcg_out_op_rr Date: Wed, 17 Mar 2021 09:34:32 -0600 Message-Id: <20210317153444.310566-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210317153444.310566-1-richard.henderson@linaro.org> References: <20210317153444.310566-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32e; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) At the same time, validate the type argument in tcg_out_mov. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 36 +++++++++++++++++++++++------------- 1 file changed, 23 insertions(+), 13 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 85c5ab5a08..322627811b 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -317,6 +317,17 @@ static void tcg_out_op_p(TCGContext *s, TCGOpcode op, = void *p0) old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +static void tcg_out_op_rr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r= 1) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, intptr_t i2) { @@ -351,16 +362,18 @@ static void tcg_out_ld(TCGContext *s, TCGType type, T= CGReg val, TCGReg base, =20 static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g) { - uint8_t *old_code_ptr =3D s->code_ptr; - tcg_debug_assert(ret !=3D arg); -#if TCG_TARGET_REG_BITS =3D=3D 32 - tcg_out_op_t(s, INDEX_op_mov_i32); -#else - tcg_out_op_t(s, INDEX_op_mov_i64); + switch (type) { + case TCG_TYPE_I32: + tcg_out_op_rr(s, INDEX_op_mov_i32, ret, arg); + break; +#if TCG_TARGET_REG_BITS =3D=3D 64 + case TCG_TYPE_I64: + tcg_out_op_rr(s, INDEX_op_mov_i64, ret, arg); + break; #endif - tcg_out_r(s, ret); - tcg_out_r(s, arg); - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + default: + g_assert_not_reached(); + } return true; } =20 @@ -534,10 +547,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, CASE_32_64(bswap16) /* Optional (TCG_TARGET_HAS_bswap16_*). */ CASE_32_64(bswap32) /* Optional (TCG_TARGET_HAS_bswap32_*). */ CASE_64(bswap64) /* Optional (TCG_TARGET_HAS_bswap64_i64). */ - tcg_out_op_t(s, opc); - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out_op_rr(s, opc, args[0], args[1]); break; =20 #if TCG_TARGET_REG_BITS =3D=3D 32 --=20 2.25.1 From nobody Wed Nov 19 12:23:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1615996643; cv=none; d=zohomail.com; s=zohoarc; b=YaXhscsyFAZ26WcCSKNlAVpVBSQv/nW7fbcLXxVSBfWOHJuhZfkWK8bf7/+4sR2lHn+FDakOZYm7xCNi6FkD2Kh2CTSgrd37L1NqZerLMJGA9wgwBmubd5lIJaEY/j2dsOSVKW1/lAY2cRd3SWEbatj2elJWpeJ9WWwVOSKDH0U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615996643; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=HAdnSjQxf3T1WyRq+twwvQ5ZT+qjDq3vtJ+I7ES6tCM=; b=fUBCm0U/vg8DklIsNgXwSSiYccABl02EtAb88WAbfdg78ewnD/1pzeJXRE+ojHvvu0A0033bwemTltFqhSorgLodAS94q5L4FQ6YNL6EVjFCUpeBM6sjHr72cavG+t4LR9qephkA8amrD1A3HiFCFb3jBI8e0GjmarMHpVYwCds= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1615996643258141.5443059866965; Wed, 17 Mar 2021 08:57:23 -0700 (PDT) Received: from localhost ([::1]:34072 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lMYXy-00052J-1B for importer@patchew.org; Wed, 17 Mar 2021 11:57:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50184) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lMYCh-0005JG-7s for qemu-devel@nongnu.org; Wed, 17 Mar 2021 11:35:24 -0400 Received: from mail-ot1-x32d.google.com ([2607:f8b0:4864:20::32d]:33284) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lMYCY-0007GL-HQ for qemu-devel@nongnu.org; Wed, 17 Mar 2021 11:35:22 -0400 Received: by mail-ot1-x32d.google.com with SMTP id o19-20020a9d22130000b02901bfa5b79e18so2197383ota.0 for ; Wed, 17 Mar 2021 08:35:14 -0700 (PDT) Received: from localhost.localdomain (fixed-187-189-51-144.totalplay.net. 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32d; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 322627811b..3320ec1088 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -328,6 +328,19 @@ static void tcg_out_op_rr(TCGContext *s, TCGOpcode op,= TCGReg r0, TCGReg r1) old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +static void tcg_out_op_rrr(TCGContext *s, TCGOpcode op, + TCGReg r0, TCGReg r1, TCGReg r2) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_out_r(s, r2); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, intptr_t i2) { @@ -500,11 +513,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, CASE_32_64(divu) /* Optional (TCG_TARGET_HAS_div_*). */ CASE_32_64(rem) /* Optional (TCG_TARGET_HAS_div_*). */ CASE_32_64(remu) /* Optional (TCG_TARGET_HAS_div_*). */ - tcg_out_op_t(s, opc); - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out_op_rrr(s, opc, args[0], args[1], args[2]); break; =20 CASE_32_64(deposit) /* Optional (TCG_TARGET_HAS_deposit_*). */ --=20 2.25.1 From nobody Wed Nov 19 12:23:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::335; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 3320ec1088..d4207818cf 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -355,6 +355,20 @@ static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op, old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +static void tcg_out_op_rrrc(TCGContext *s, TCGOpcode op, + TCGReg r0, TCGReg r1, TCGReg r2, TCGCond c3) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_out_r(s, r2); + tcg_out8(s, c3); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg val, TCGReg bas= e, intptr_t offset) { @@ -454,12 +468,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, break; =20 CASE_32_64(setcond) - tcg_out_op_t(s, opc); - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - tcg_out8(s, args[3]); /* condition */ - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out_op_rrrc(s, opc, args[0], args[1], args[2], args[3]); break; =20 #if TCG_TARGET_REG_BITS =3D=3D 32 --=20 2.25.1 From nobody Wed Nov 19 12:23:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::230; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x230.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 30 +++++++++++++++++++++--------- 1 file changed, 21 insertions(+), 9 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index d4207818cf..8504e82e95 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -369,6 +369,25 @@ static void tcg_out_op_rrrc(TCGContext *s, TCGOpcode o= p, old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +#if TCG_TARGET_REG_BITS =3D=3D 32 +static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op, + TCGReg r0, TCGReg r1, TCGReg r2, + TCGReg r3, TCGReg r4, TCGCond c5) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_out_r(s, r2); + tcg_out_r(s, r3); + tcg_out_r(s, r4); + tcg_out8(s, c5); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} +#endif + static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg val, TCGReg bas= e, intptr_t offset) { @@ -473,15 +492,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, =20 #if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_setcond2_i32: - /* setcond2_i32 cond, t0, t1_low, t1_high, t2_low, t2_high */ - tcg_out_op_t(s, opc); - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - tcg_out_r(s, args[3]); - tcg_out_r(s, args[4]); - tcg_out8(s, args[5]); /* condition */ - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out_op_rrrrrc(s, opc, args[0], args[1], args[2], + args[3], args[4], args[5]); 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id i11sm8271154otp.76.2021.03.17.08.35.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Mar 2021 08:35:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=q8I1YCSoWNXxPVW6fLoHCz2kYQaXyDJJKMZjEFQ+AKY=; b=POpz4bqHnU5KMw4PyfEoYttsa+Bq6eTR/UvNRsGkD9mU71UtArGIbrw2FBDn/hB83Q Iz0CfAklbi3HQhPZ4xhXJEu8jVNgV0B5qvT+WzFmZMHugwYeITDi4pKPtuZiaEt9Hm0d fkR4K1YvNZy1UOc84QYPjTscaKzuQmbwT57zdSP+C2Zz/H3NlgJRW9ISBPbaLxWlki9z /a1/55DvY44SMjNkgVzlU2vGzZ02mKSNRpnCcwVzxHnMGIQ70d227bhUkko59pv6Tiq/ Wr6tP19HNNpeg5zIbrKA/12ug+yr4ulhj8UzgUTfwd7FuvsUomLjWllzzMFyzX3ghhpZ Y1JA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=q8I1YCSoWNXxPVW6fLoHCz2kYQaXyDJJKMZjEFQ+AKY=; b=UUIaXXxQ6uqP+siakSA6zWHmV9D/LjUQNqGDR/M30Ikt0ISuSTjcoqk71wpLgwYN77 oXhczYePS7aDx6NgFRfqV3SBcT2UOwtzZlBsIulrLHDcwj779WwgbfNLck2BvjLdCF3b 8N7MucW7YlWcj2cTGLgOqrsSVMcSvi+S+S3wFdWVTaM3Z85R6um+dVItqMWHN7w551cn /eoIPqla+IKrrQfd8dw8dMBAJm+uAjXLz36K1uge9yceK+uFjSiTJ++qlsj52epDLaaR ja8xkH+9lupvnwnrY6EMHghdyXtiM9zKgq9aqpYZ9al1wDc+wZ2ZaQDY3bX7luA/oheD E4ow== X-Gm-Message-State: AOAM530XBHNp6M1a8lBtSFSK8AZbdCEWDMY9lflHHiNm2K4H9hbGwxMh rwS3vr/deIfi8mttrykGqR20LRsrDoi5XMLE X-Google-Smtp-Source: ABdhPJygihfYRwaKH83tztE9JDadaFCHiLZ71aBkArRVuspNyuyrqZZBZ40nA+zDLg9U8cphGnQFsw== X-Received: by 2002:a05:6808:313:: with SMTP id i19mr3070662oie.67.1615995316393; Wed, 17 Mar 2021 08:35:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 30/38] tcg/tci: Split out tcg_out_op_rrrbb Date: Wed, 17 Mar 2021 09:34:36 -0600 Message-Id: <20210317153444.310566-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210317153444.310566-1-richard.henderson@linaro.org> References: <20210317153444.310566-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22b; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 8504e82e95..b153334dfb 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -369,6 +369,21 @@ static void tcg_out_op_rrrc(TCGContext *s, TCGOpcode o= p, old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +static void tcg_out_op_rrrbb(TCGContext *s, TCGOpcode op, TCGReg r0, + TCGReg r1, TCGReg r2, uint8_t b3, uint8_t b4) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_out_r(s, r2); + tcg_out8(s, b3); + tcg_out8(s, b4); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + #if TCG_TARGET_REG_BITS =3D=3D 32 static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, @@ -538,7 +553,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, co= nst TCGArg *args, break; =20 CASE_32_64(deposit) /* Optional (TCG_TARGET_HAS_deposit_*). */ - tcg_out_op_t(s, opc); { TCGArg pos =3D args[3], len =3D args[4]; TCGArg max =3D opc =3D=3D INDEX_op_deposit_i32 ? 32 : 64; @@ -546,13 +560,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, tcg_debug_assert(pos < max); tcg_debug_assert(pos + len <=3D max); =20 - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - tcg_out8(s, pos); - tcg_out8(s, len); + tcg_out_op_rrrbb(s, opc, args[0], args[1], args[2], pos, len); } - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; =20 CASE_32_64(brcond) --=20 2.25.1 From nobody Wed Nov 19 12:23:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1615997636; cv=none; d=zohomail.com; s=zohoarc; b=G6VKqeULbJczSaT6QACUj74ndmUEGHQdnr4x6/h+P19nQd0kBD+oOJWxyoylVkMSFuZ3ZpNhh38n67qYcis3F2e57KQQQ6WwCVjafc911dNFZh67Nfw6G9RjI8hU6YAVrRQZLo8eA37Qde59s0Lp3thH4IWzm6yao9WtiD95xYE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615997636; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=N/QfbjLf5co+LZFn6W3l+/yR9yA2JEjJarf6EF+7jdc=; b=GRxCByE7tXTFzS+0Cd+yf+s/xEY1Ozu3+R022AJ26WYirAGnxp0TikmaIShLvzizkYVrdej62QPbaRqKGijtdtDxlrOJ3oc0luY53OcSQtUKRXOnpX2KAkmZAML5gKaFJvLsao+AWKoCy8aBC4Ab3sA53MMekDBQ8W9wp/nAJnY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1615997636549899.8711032337792; Wed, 17 Mar 2021 09:13:56 -0700 (PDT) Received: from localhost ([::1]:47532 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lMYny-00074E-4z for importer@patchew.org; Wed, 17 Mar 2021 12:13:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50256) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lMYCn-0005Jp-T5 for qemu-devel@nongnu.org; Wed, 17 Mar 2021 11:35:29 -0400 Received: from mail-oi1-x234.google.com ([2607:f8b0:4864:20::234]:37854) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lMYCc-0007I6-St for qemu-devel@nongnu.org; Wed, 17 Mar 2021 11:35:29 -0400 Received: by mail-oi1-x234.google.com with SMTP id u198so37226533oia.4 for ; Wed, 17 Mar 2021 08:35:17 -0700 (PDT) Received: from localhost.localdomain (fixed-187-189-51-144.totalplay.net. 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::234; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x234.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index b153334dfb..d0036c9519 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -355,6 +355,20 @@ static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op, old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +static void tcg_out_op_rrcl(TCGContext *s, TCGOpcode op, + TCGReg r0, TCGReg r1, TCGCond c2, TCGLabel *l3) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_out8(s, c2); + tci_out_label(s, l3); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rrrc(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGCond c3) { @@ -565,12 +579,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, break; =20 CASE_32_64(brcond) - tcg_out_op_t(s, opc); - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out8(s, args[2]); /* condition */ - tci_out_label(s, arg_label(args[3])); - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out_op_rrcl(s, opc, args[0], args[1], args[2], arg_label(args[= 3])); break; =20 CASE_32_64(neg) /* Optional (TCG_TARGET_HAS_neg_*). */ --=20 2.25.1 From nobody Wed Nov 19 12:23:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::336; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 27 +++++++++++++++++++-------- 1 file changed, 19 insertions(+), 8 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index d0036c9519..20dd186b84 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -415,6 +415,23 @@ static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode= op, =20 old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } + +static void tcg_out_op_rrrrrr(TCGContext *s, TCGOpcode op, + TCGReg r0, TCGReg r1, TCGReg r2, + TCGReg r3, TCGReg r4, TCGReg r5) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_out_r(s, r2); + tcg_out_r(s, r3); + tcg_out_r(s, r4); + tcg_out_r(s, r5); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} #endif =20 static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg val, TCGReg bas= e, @@ -601,14 +618,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, #if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_add2_i32: case INDEX_op_sub2_i32: - tcg_out_op_t(s, opc); - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - tcg_out_r(s, args[3]); - tcg_out_r(s, args[4]); - tcg_out_r(s, args[5]); - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out_op_rrrrrr(s, opc, args[0], args[1], args[2], + args[3], args[4], args[5]); break; case INDEX_op_brcond2_i32: tcg_out_op_t(s, opc); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::233; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x233.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 20dd186b84..1e98c73417 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -399,6 +399,20 @@ static void tcg_out_op_rrrbb(TCGContext *s, TCGOpcode = op, TCGReg r0, } =20 #if TCG_TARGET_REG_BITS =3D=3D 32 +static void tcg_out_op_rrrr(TCGContext *s, TCGOpcode op, + TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_out_r(s, r2); + tcg_out_r(s, r3); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3, TCGReg r4, TCGCond c5) @@ -632,12 +646,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; case INDEX_op_mulu2_i32: - tcg_out_op_t(s, opc); - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - tcg_out_r(s, args[3]); - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out_op_rrrr(s, opc, args[0], args[1], args[2], args[3]); break; #endif =20 --=20 2.25.1 From nobody Wed Nov 19 12:23:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id i11sm8271154otp.76.2021.03.17.08.35.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Mar 2021 08:35:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ACE1sMT8wY4iUN+EqRzW5k07GACFzZCdY0lH0VS72yo=; b=fUEvKG6aAEMjtm9GaEPWzq9fpbo/JJKWgrX301eFWv9n8h9SSnkcywja4V76ElfnJp gjiI1az1tGunOArtxVCnPZQM7eo8kj6o1WncgX03AAeWHb0JXbNmVRvKx3+Qe1VoXgiv BdvH1wjx8uGL1aOIurIjCHNremP6HTdapwAFqA3RtoGD8jwGCi7ZX09BlE2nX6jKkHy/ MSMu3ZzztEJNq+Ah/SD7Csey1t6/DV+WdJXAmkddxC/yEbeWIw0+z6xA0tPYsMQBZl7N sR0Frezvs+L15lNNI0WjHu8wvsJuNeDrkyIOUAJJOFTGhkrPjcluzNwLlFLvMJCoZqzP whHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ACE1sMT8wY4iUN+EqRzW5k07GACFzZCdY0lH0VS72yo=; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22f; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 27 +++++++++++++++++++-------- 1 file changed, 19 insertions(+), 8 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 1e98c73417..86b59179bb 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -413,6 +413,23 @@ static void tcg_out_op_rrrr(TCGContext *s, TCGOpcode o= p, old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +static void tcg_out_op_rrrrcl(TCGContext *s, TCGOpcode op, + TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3, + TCGCond c4, TCGLabel *l5) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_out_r(s, r2); + tcg_out_r(s, r3); + tcg_out8(s, c4); + tci_out_label(s, l5); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3, TCGReg r4, TCGCond c5) @@ -636,14 +653,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, args[3], args[4], args[5]); break; case INDEX_op_brcond2_i32: - tcg_out_op_t(s, opc); - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - tcg_out_r(s, args[3]); - tcg_out8(s, args[4]); /* condition */ - tci_out_label(s, arg_label(args[5])); - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out_op_rrrrcl(s, opc, args[0], args[1], args[2], + args[3], args[4], arg_label(args[5])); break; case INDEX_op_mulu2_i32: tcg_out_op_rrrr(s, opc, args[0], args[1], args[2], args[3]); --=20 2.25.1 From nobody Wed Nov 19 12:23:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1615996721; cv=none; d=zohomail.com; s=zohoarc; b=UU3JGOs9+/iT8eCoMexrm9Ain29zsYbXEI2NG+DEhws7uo+2e3+NsCDEDuUJzy9kXYYkqjIQ7n4jvC2FHVfUaSoJ4QhEvSMCZh2zIAG5NzMAdS8fwfbeEbirTMkTurrzHGAmk2b6lqmw1AgpXlx8zs54Vz3lFRJH3+BmL7Ptv0w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615996721; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=kmnDEWcNjBI0CV2v+4la8ocEzwYbaD/h2AKvp5PoRaQ=; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::235; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x235.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 70 ++++++++++++++++++++++++++++++---------- 1 file changed, 53 insertions(+), 17 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 86b59179bb..2aa0997ae9 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -328,6 +328,19 @@ static void tcg_out_op_rr(TCGContext *s, TCGOpcode op,= TCGReg r0, TCGReg r1) old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +static void tcg_out_op_rrm(TCGContext *s, TCGOpcode op, + TCGReg r0, TCGReg r1, TCGArg m2) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_out32(s, m2); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rrr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2) { @@ -383,6 +396,20 @@ static void tcg_out_op_rrrc(TCGContext *s, TCGOpcode o= p, old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +static void tcg_out_op_rrrm(TCGContext *s, TCGOpcode op, + TCGReg r0, TCGReg r1, TCGReg r2, TCGArg m3) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_out_r(s, r2); + tcg_out32(s, m3); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rrrbb(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, uint8_t b3, uint8_t b4) { @@ -398,6 +425,21 @@ static void tcg_out_op_rrrbb(TCGContext *s, TCGOpcode = op, TCGReg r0, old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +static void tcg_out_op_rrrrm(TCGContext *s, TCGOpcode op, TCGReg r0, + TCGReg r1, TCGReg r2, TCGReg r3, TCGArg m4) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_out_r(s, r2); + tcg_out_r(s, r3); + tcg_out32(s, m4); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + #if TCG_TARGET_REG_BITS =3D=3D 32 static void tcg_out_op_rrrr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3) @@ -663,29 +705,23 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, =20 case INDEX_op_qemu_ld_i32: case INDEX_op_qemu_st_i32: - tcg_out_op_t(s, opc); - tcg_out_r(s, *args++); - tcg_out_r(s, *args++); - if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { - tcg_out_r(s, *args++); + if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { + tcg_out_op_rrm(s, opc, args[0], args[1], args[2]); + } else { + tcg_out_op_rrrm(s, opc, args[0], args[1], args[2], args[3]); } - tcg_out32(s, *args++); - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; =20 case INDEX_op_qemu_ld_i64: case INDEX_op_qemu_st_i64: - tcg_out_op_t(s, opc); - tcg_out_r(s, *args++); - if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_out_r(s, *args++); + if (TCG_TARGET_REG_BITS =3D=3D 64) { + tcg_out_op_rrm(s, opc, args[0], args[1], args[2]); + } else if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { + tcg_out_op_rrrm(s, opc, args[0], args[1], args[2], args[3]); + } else { + tcg_out_op_rrrrm(s, opc, args[0], args[1], + args[2], args[3], args[4]); } - tcg_out_r(s, *args++); - if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { - tcg_out_r(s, *args++); - } - tcg_out32(s, *args++); - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; =20 case INDEX_op_mb: --=20 2.25.1 From nobody Wed Nov 19 12:23:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id i11sm8271154otp.76.2021.03.17.08.35.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Mar 2021 08:35:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1jqdZoMkwFIBCGSsjtnW2H3IsZVrYebU0beixQQ3ds4=; b=isBpwSquSBoAr1jvkxnzsTUuIu3H4I3fcuL9R13x0/3jEofkfYt5QvfyME/nmu5+EY wUQ1RRx6qXr0/ZZqEsDWe0QatpH8fky/5iMAv30VmppvuYYkbRxtpUYTVWUDminWc0mB d5ViyEIjxPOuExGo5KocU4Fwxrw2mh2X/uHFrPPBlYDIZ9qAA4FyHpnVKaG3ERxfxv+A dHdD7go51ptR0DzsNtwpkkPazgbcCYi/Wkdnb6PKYCB2eIV/lfK3jf51fQVyriwVuaX+ v2jy4ttMP6F6mYdHxcQ7dDh2ndx3T0CuHH8Q2gesIriaYz7q+AgVpo5V1VNgGHWdS45B 1TOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1jqdZoMkwFIBCGSsjtnW2H3IsZVrYebU0beixQQ3ds4=; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22e; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 2aa0997ae9..f93d587493 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -317,6 +317,15 @@ static void tcg_out_op_p(TCGContext *s, TCGOpcode op, = void *p0) old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +static void tcg_out_op_v(TCGContext *s, TCGOpcode op) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r= 1) { uint8_t *old_code_ptr =3D s->code_ptr; @@ -587,8 +596,6 @@ static inline void tcg_out_call(TCGContext *s, const tc= g_insn_unit *arg) static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, const int *const_args) { - uint8_t *old_code_ptr =3D s->code_ptr; - switch (opc) { case INDEX_op_exit_tb: tcg_out_op_p(s, opc, (void *)args[0]); @@ -725,8 +732,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, co= nst TCGArg *args, break; =20 case INDEX_op_mb: - tcg_out_op_t(s, opc); - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out_op_v(s, opc); break; =20 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ --=20 2.25.1 From nobody Wed Nov 19 12:23:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id i11sm8271154otp.76.2021.03.17.08.35.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Mar 2021 08:35:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fgoAkYC9IFNWuPeH+z6aBzUcnRdada5Ms22SlWibiTM=; b=PUSYzYJ98uDRacH5AZgsCz37yxlVZZlCXjwyM1WNYaCUlwM6CPFHMmARXTRErvu+tz 8RGgyAtSQhDDlCRx7y04hGPooloSqGVu0TV8ttHxkg/fRZ3jmNANXIDeJk28ilhTT1CM YEe852Q0FNPHtRSLeudivRrcf3jHTTlMdqA6nmbLGMQIYSpHr9C6fX1pGupqmscUMMTw k4fRpBkAgjnEFSuM5560/xFwErm7VHCgHGACy5NQBWnePLJyBh6HE8u+7x/klf/DKQR9 7z9AvPuzRDywFrSfzbUh15Kp8nyXlJn8HYuvb2BnbcWbrRBI/RKcqHhW8GQ6lSLLNqYl 2C3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fgoAkYC9IFNWuPeH+z6aBzUcnRdada5Ms22SlWibiTM=; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22c; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 50 ++++++++++++++++++++++++++++------------ 1 file changed, 35 insertions(+), 15 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index f93d587493..7e7b9fed44 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -326,6 +326,31 @@ static void tcg_out_op_v(TCGContext *s, TCGOpcode op) old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +static void tcg_out_op_ri(TCGContext *s, TCGOpcode op, TCGReg r0, int32_t = i1) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out32(s, i1); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + +#if TCG_TARGET_REG_BITS =3D=3D 64 +static void tcg_out_op_rI(TCGContext *s, TCGOpcode op, + TCGReg r0, uint64_t i1) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out64(s, i1); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} +#endif + static void tcg_out_op_rr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r= 1) { uint8_t *old_code_ptr =3D s->code_ptr; @@ -552,25 +577,20 @@ static bool tcg_out_mov(TCGContext *s, TCGType type, = TCGReg ret, TCGReg arg) } =20 static void tcg_out_movi(TCGContext *s, TCGType type, - TCGReg t0, tcg_target_long arg) + TCGReg ret, tcg_target_long arg) { - uint8_t *old_code_ptr =3D s->code_ptr; - uint32_t arg32 =3D arg; - if (type =3D=3D TCG_TYPE_I32 || arg =3D=3D arg32) { - tcg_out_op_t(s, INDEX_op_tci_movi_i32); - tcg_out_r(s, t0); - tcg_out32(s, arg32); - } else { - tcg_debug_assert(type =3D=3D TCG_TYPE_I64); + switch (type) { + case TCG_TYPE_I32: + tcg_out_op_ri(s, INDEX_op_tci_movi_i32, ret, arg); + break; #if TCG_TARGET_REG_BITS =3D=3D 64 - tcg_out_op_t(s, INDEX_op_tci_movi_i64); - tcg_out_r(s, t0); - tcg_out64(s, arg); -#else - TODO(); + case TCG_TYPE_I64: + tcg_out_op_rI(s, INDEX_op_tci_movi_i64, ret, arg); + break; #endif + default: + g_assert_not_reached(); } - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 static inline void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg) --=20 2.25.1 From nobody Wed Nov 19 12:23:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1615997943; cv=none; d=zohomail.com; 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id i11sm8271154otp.76.2021.03.17.08.35.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Mar 2021 08:35:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=eMGXmrjjBijTVozb/SNcJosQWc4OplVY9EwbvL5eB0U=; b=bkKIBKuUedhLcTT96Th/DToy5Jm/Zd1d6i6ooOGgRajkXLoZyEacwMLWR6Xlt8Jmc5 n6DC7Td/4wwqELayE9CAI6d80aXfSz+lleiFjYS7YbrztBTWVU29aMCYxvWNhyNaueGh fbsn3VfNIP5AiHUpWIEQpLlKkKWMr0Naq7ByBMScsvyJvLOVcu1tMmcQ5aFxDV09qgbL QSxS6k6IMMSTLOceRBD+naCZAJFoz0DFV+ZpkBbK/sqLmLz0mVaf60l1Y0+dqznqoTRF U69qczkrRyU14AYw8NKycxtbm9L04al5waadNGiMpqMMn95bQtd/rXqfklPxZWpPz4hN 5QoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eMGXmrjjBijTVozb/SNcJosQWc4OplVY9EwbvL5eB0U=; b=c37IkJiDsDZvJdQuxJplG/XMSak5E09Zr59HWVkNBghZpLR1LKrxNnFb1rSn8OVXyc Io+mafc1+uzu7vZDXril5WicCKXLjuGPJbZgKiZ7eiBo/CpeK7havYmc777ui9hjseWT 4OGb61dwbrZHb+jNd/X5INOsoZjzzy7p3UHZHJkj2Qh8sfc6bdUQbcW3aBtV52x3c2K8 BjC8IFV02R2eoFMK4RgoNXPTEGrmIzT00JeGlpwxmT31D8bOTNNja3Gbkhkjc8hINXlE kPXLTXAr5tlvCyvgunTw6Gog4hGA2CKVU0vj9KWDfDxxA/ZC/WP+pASSkKZSBsCUXbWK pSSg== X-Gm-Message-State: AOAM530aiGGPrZpc+YZVHHY9Mojmi5UHbFdxfKITFo7p3LEdsNGCSD9g AZI9RGQh+7ESNngj/4cMgG8UU9vITkvt4FtK X-Google-Smtp-Source: ABdhPJzqX3UPGkovYFkOxP9RbPsQPH0bnHyLO8ArbqOOS703vvVeZfnx4GEK6h4bT7KXgh+f+hvqCg== X-Received: by 2002:aca:ad57:: with SMTP id w84mr3266618oie.100.1615995324373; Wed, 17 Mar 2021 08:35:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 38/38] tcg: Fix prototypes for tcg_out_vec_op and tcg_out_op Date: Wed, 17 Mar 2021 09:34:44 -0600 Message-Id: <20210317153444.310566-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210317153444.310566-1-richard.henderson@linaro.org> References: <20210317153444.310566-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22a; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Miroslav Rezanina Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Miroslav Rezanina There are two different versions of prototype for tcg_out_op and tcg_out_vec_op functions: 1) using const TCGArg *args and const int *const_args arguments 2) using const TCGArg args[TCG_MAX_OP_ARGS] and const int const_args[TCG_MAX_OP_ARGS] aguments. This duality causes warnings on GCC 11 and prevents build using --enable-werror. As second version provides more information, unify functions prototypes to this variant. Signed-off-by: Miroslav Rezanina Message-Id: <20210312121418.139093-1-mrezanin@redhat.com> Signed-off-by: Richard Henderson --- tcg/tcg.c | 19 +++++++++++-------- tcg/aarch64/tcg-target.c.inc | 3 ++- tcg/i386/tcg-target.c.inc | 6 ++++-- tcg/mips/tcg-target.c.inc | 3 ++- tcg/ppc/tcg-target.c.inc | 8 +++++--- tcg/riscv/tcg-target.c.inc | 3 ++- tcg/s390/tcg-target.c.inc | 3 ++- tcg/tci/tcg-target.c.inc | 5 +++-- 8 files changed, 31 insertions(+), 19 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 2991112829..de91bb6e9e 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -107,8 +107,9 @@ static void tcg_out_ld(TCGContext *s, TCGType type, TCG= Reg ret, TCGReg arg1, static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g); static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, tcg_target_long arg); -static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, - const int *const_args); +static void tcg_out_op(TCGContext *s, TCGOpcode opc, + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]); #if TCG_TARGET_MAYBE_vec static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, TCGReg dst, TCGReg src); @@ -116,9 +117,10 @@ static bool tcg_out_dupm_vec(TCGContext *s, TCGType ty= pe, unsigned vece, TCGReg dst, TCGReg base, intptr_t offset); static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, TCGReg dst, int64_t arg); -static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl, - unsigned vece, const TCGArg *args, - const int *const_args); +static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, + unsigned vecl, unsigned vece, + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]); #else static inline bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned v= ece, TCGReg dst, TCGReg src) @@ -135,9 +137,10 @@ static inline void tcg_out_dupi_vec(TCGContext *s, TCG= Type type, unsigned vece, { g_assert_not_reached(); } -static inline void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned v= ecl, - unsigned vece, const TCGArg *args, - const int *const_args) +static inline void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, + unsigned vecl, unsigned vece, + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]) { g_assert_not_reached(); } diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index fcaa5aface..f07ba98aa4 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -2286,7 +2286,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, =20 static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl, unsigned vece, - const TCGArg *args, const int *const_args) + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]) { static const AArch64Insn cmp_vec_insn[16] =3D { [TCG_COND_EQ] =3D I3616_CMEQ, diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 40326c2806..415c5c0796 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -2177,7 +2177,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is64) } =20 static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, - const TCGArg *args, const int *const_args) + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]) { TCGArg a0, a1, a2; int c, const_a2, vexop, rexw =3D 0; @@ -2613,7 +2614,8 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, =20 static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl, unsigned vece, - const TCGArg *args, const int *const_args) + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]) { static int const add_insn[4] =3D { OPC_PADDB, OPC_PADDW, OPC_PADDD, OPC_PADDQ diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index ab55f3109b..8738a3a581 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -1651,7 +1651,8 @@ static void tcg_out_clz(TCGContext *s, MIPSInsn opcv2= , MIPSInsn opcv6, } =20 static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, - const TCGArg *args, const int *const_args) + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]) { MIPSInsn i1, i2; TCGArg a0, a1, a2; diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 4377d15d62..838ccfa42d 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -2319,8 +2319,9 @@ static void tcg_target_qemu_prologue(TCGContext *s) tcg_out32(s, BCLR | BO_ALWAYS); } =20 -static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, - const int *const_args) +static void tcg_out_op(TCGContext *s, TCGOpcode opc, + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]) { TCGArg a0, a1, a2; int c; @@ -3115,7 +3116,8 @@ static bool tcg_out_dupm_vec(TCGContext *s, TCGType t= ype, unsigned vece, =20 static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl, unsigned vece, - const TCGArg *args, const int *const_args) + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]) { static const uint32_t add_op[4] =3D { VADDUBM, VADDUHM, VADDUWM, VADDUDM }, diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index e700c52067..ef43147040 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -1212,7 +1212,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is_64) static const tcg_insn_unit *tb_ret_addr; =20 static void tcg_out_op(TCGContext *s, TCGOpcode opc, - const TCGArg *args, const int *const_args) + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]) { TCGArg a0 =3D args[0]; TCGArg a1 =3D args[1]; diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc index 695d7ee652..af8dfe81ac 100644 --- a/tcg/s390/tcg-target.c.inc +++ b/tcg/s390/tcg-target.c.inc @@ -1705,7 +1705,8 @@ static void tcg_out_qemu_st(TCGContext* s, TCGReg dat= a_reg, TCGReg addr_reg, case glue(glue(INDEX_op_,x),_i64) =20 static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, - const TCGArg *args, const int *const_args) + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]) { S390Opcode op, op2; TCGArg a0, a1, a2; diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 7e7b9fed44..ee6cdfec71 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -613,8 +613,9 @@ static inline void tcg_out_call(TCGContext *s, const tc= g_insn_unit *arg) # define CASE_64(x) #endif =20 -static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, - const int *const_args) +static void tcg_out_op(TCGContext *s, TCGOpcode opc, + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]) { switch (opc) { case INDEX_op_exit_tb: --=20 2.25.1