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[88.21.201.17]) by smtp.gmail.com with ESMTPSA id v18sm14511057wrf.41.2021.03.13.11.48.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Mar 2021 11:48:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NdWkTYFq4CcNFJEVWCc6s/+3/xKpysVoHg6G3a/oBtM=; b=dFvUMEYf1j1/Wrw/e6nUs3LozpmXPldk8DDVFe93AoggoMniod8Z1lopJ87uSQShxv UnQtExh650xd7SEiPX1Cn3AKRFkBR0lBTxPdZfnFbh0onty6v99Afm6Izz9yuTBMnFn+ KiszKVqoNYSg5qPsiCDSfgPI8HOSBCH0iOefSHGx+rX0oja10Jgz0jRMeqAqGAYDmMte TKADyjfjTlZqxqwATQUHNfT8Hrc//vPFnXODKFNqfizeNFse5HMObVWE2Z8+gQbBe2p7 uoehjXx486IdFM3PFsHevtelwV5UM72vN2fB23CxGPJ/p5xyQUGmhQwcvNSnKPzxkjQh k7+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=NdWkTYFq4CcNFJEVWCc6s/+3/xKpysVoHg6G3a/oBtM=; b=NjBGODeoIYyuwZJPH0MZ9InlLnU/YJdVr9a74ZHHFRLzd57+szqcMQJTTTIHJwTc9+ zM8hHUUvmdAfWIZcvXkgFIajlWCQQZxJn63K5oGiGln7htSym9OrS1pGkTDjb97SC092 y0BiBLobuuRNNKGI8blZd9Ot7e+hBJRdgFVa4z8c9Ye6WIrbHD54XY35rv/JWvNtCfBt SU7v/WYpKOANtxx3QJkX3BnRrBFZppBIQCjGd32K8Gw8AmJJyt4Us4AHUfZGhmk3Fdhj C6UQ8YFZcs67KLXuPS0q7h91mznQUQRUg3TELKqJrQf1vIMow9NyIj9JGQH+KkK1OOOX yJZQ== X-Gm-Message-State: AOAM530H8cINQwQqCDc3Qu8yskoKHZx2l66Bv4hN8jileaBOeYkSNnBb LByK37FJncL0bp8hjH+KZv0= X-Google-Smtp-Source: ABdhPJxQAeIvP1o92Kti5erMo9ukbM96BO1lIRiTQLdJLcWjWuYzb//x0xKRFFI6cE+zyrLaubzSCQ== X-Received: by 2002:a5d:5256:: with SMTP id k22mr20684883wrc.162.1615664916929; Sat, 13 Mar 2021 11:48:36 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , BALATON Zoltan Subject: [PULL 01/27] hw/mips/gt64xxx: Initialize ISD I/O memory region in DeviceRealize() Date: Sat, 13 Mar 2021 20:48:03 +0100 Message-Id: <20210313194829.2193621-2-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210313194829.2193621-1-f4bug@amsat.org> References: <20210313194829.2193621-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) The ISD I/O region belongs to the TYPE_GT64120_PCI_HOST_BRIDGE, so initialize it before it is realized, not after. Rename the region as 'gt64120-isd' so it is clearer to realize it belongs to the GT64120 in the memory tree view. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: BALATON Zoltan Message-Id: <20210309142630.728014-2-f4bug@amsat.org> --- hw/mips/gt64xxx_pci.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index 588e6f99301..6eb73e77057 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -1196,6 +1196,14 @@ static void gt64120_reset(DeviceState *dev) gt64120_pci_mapping(s); } =20 +static void gt64120_realize(DeviceState *dev, Error **errp) +{ + GT64120State *s =3D GT64120_PCI_HOST_BRIDGE(dev); + + memory_region_init_io(&s->ISD_mem, OBJECT(dev), &isd_mem_ops, s, + "gt64120-isd", 0x1000); +} + PCIBus *gt64120_register(qemu_irq *pic) { GT64120State *d; @@ -1214,8 +1222,6 @@ PCIBus *gt64120_register(qemu_irq *pic) get_system_io(), PCI_DEVFN(18, 0), 4, TYPE_PCI_BUS); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); - memory_region_init_io(&d->ISD_mem, OBJECT(dev), &isd_mem_ops, d, - "isd-mem", 0x1000); =20 pci_create_simple(phb->bus, PCI_DEVFN(0, 0), "gt64120_pci"); return phb->bus; @@ -1270,6 +1276,7 @@ static void gt64120_class_init(ObjectClass *klass, vo= id *data) DeviceClass *dc =3D DEVICE_CLASS(klass); =20 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); + dc->realize =3D gt64120_realize; dc->reset =3D gt64120_reset; dc->vmsd =3D &vmstate_gt64120; } --=20 2.26.2 From nobody Sat May 18 21:45:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.42 as permitted sender) client-ip=209.85.128.42; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f42.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.42 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1615664923; cv=none; d=zohomail.com; s=zohoarc; b=d5uAP1hNmCoEa5OBlEY0dVxfoGohZyYPrH38aVLG0XYIkANUYKgXDH6YgI+90sqxixpMY8sx9ZcYlEDPEsDGmmZ0DG7da54zAnli50Vn7a/UxPX4n9zOxsdCqzaboIn6UcgR/zwSSSAMIHx2/Zc660Qfys5JpZSK5cpA3y27mas= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615664923; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=1fsEr4CTL/3Iyvv1LF8p7dPgqU+b0Kxc61FnxzTyzZo=; b=MGBau9kJYNl9RSsi2kG+xauzZ2sOjG/hezLuDzLeA2VnZRPHURL4nBarayFZIcm7SAQYq0PCARCEfmf3iiIgpuLm2WI5CdzdyVt8dKOfY58dYg8tSxG6tj1/ljvxTtg5Dje0r3bW11OmtQake6gLbRzDnzUeVhXd0fpEra8qAoo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.42 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) by mx.zohomail.com with SMTPS id 1615664923633594.5682666756102; Sat, 13 Mar 2021 11:48:43 -0800 (PST) Received: by mail-wm1-f42.google.com with SMTP id l19so5751333wmh.1 for ; Sat, 13 Mar 2021 11:48:43 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (17.red-88-21-201.staticip.rima-tde.net. [88.21.201.17]) by smtp.gmail.com with ESMTPSA id k4sm17401976wrd.9.2021.03.13.11.48.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Mar 2021 11:48:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1fsEr4CTL/3Iyvv1LF8p7dPgqU+b0Kxc61FnxzTyzZo=; b=EZ7GmQY7U/HQ9eDiGIVMIbZLPERrpkhPBckiZsoThCoKhEm66iPx/8mYPqJdWdU43K voDl0EMLElunDWoEiIOA8ulGfqadf8uJdd6d+Ze1+CugdwveYs37Iw+mlOoqdQG7l35U K9PFFMrZLJnc1j0CCd7TXpljcgMW9XZViDt1u6ufMEkcjPSjqU16v1JjQb62Dzdg/bVx QMa0IzdtsEds+dyrbsBYQHuUZkQWfT2r7cIo8Ri8o7ymuik7o4/OWa694mHGAOqlPhXu HNiZqVUFDdj8N2uCuRjlpanZ6hZ3LO/IhbH2xuU5O/HEqZYHa/c1puabPHMaeEc2BVTC ENyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=1fsEr4CTL/3Iyvv1LF8p7dPgqU+b0Kxc61FnxzTyzZo=; b=sy2OaZOtjmIfYTfmK8bBdMydffS/Yua6/cD0WuiK2X5tTsOIFmBPqbUCVPQR85ShFf zD/HzQitD+r6Z97Fb4hAtmOoFSTtE/Zgh+vTleve0/0DSo2roqlj7fiMQ+kf6C1TqSjn zPv6ZzssfcYquEUZ05ouWM/mMZTrR+W3h6FUB2uMPzul6Z64WtV3rREJ1Rd7/QAQTSCK tCkkw/RRunTyYcvwvp5F5Z4ezs08LPtGa2i4O3ZHuFGKe/10hg4Fxw48ig3F0ukV1nZz IaofhYBWas5ib3BkMKJCqK+GhsHKc1WRCvqVvJyzjrr/19bzLAI/j5znaTn85E5rlj5E 33Fg== X-Gm-Message-State: AOAM533bZ5UpctTQrd+7c5p1ItORBWT1FU3+oE01t8wAXN1xtuSqSGjd 6aqiMxwqGjhwYeTuJbRuwrxdCX2Td4PY7A== X-Google-Smtp-Source: ABdhPJyyaxqxk3q9+A1Yfht+mO2oHYqMOYMtAExibwW7qG3mxMLuO4IiNgcUHMtehKJVZIsDuzvZnQ== X-Received: by 2002:a05:600c:4f4f:: with SMTP id m15mr18877187wmq.29.1615664921904; Sat, 13 Mar 2021 11:48:41 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , BALATON Zoltan Subject: [PULL 02/27] hw/mips/gt64xxx: Simplify ISD MemoryRegion read/write handlers Date: Sat, 13 Mar 2021 20:48:04 +0100 Message-Id: <20210313194829.2193621-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210313194829.2193621-1-f4bug@amsat.org> References: <20210313194829.2193621-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) The ISD MemoryRegion is implemented for 32-bit accesses. Simplify it by setting the MemoryRegionOps::impl min/max access size fields. Since the region is registered with a size of 0x1000 bytes, we can remove the hwaddr mask. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: BALATON Zoltan Message-Id: <20210309142630.728014-3-f4bug@amsat.org> --- hw/mips/gt64xxx_pci.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index 6eb73e77057..99b1690af19 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -385,13 +385,12 @@ static void gt64120_writel(void *opaque, hwaddr addr, { GT64120State *s =3D opaque; PCIHostState *phb =3D PCI_HOST_BRIDGE(s); - uint32_t saddr; + uint32_t saddr =3D addr >> 2; =20 if (!(s->regs[GT_CPU] & 0x00001000)) { val =3D bswap32(val); } =20 - saddr =3D (addr & 0xfff) >> 2; switch (saddr) { =20 /* CPU Configuration */ @@ -695,9 +694,8 @@ static uint64_t gt64120_readl(void *opaque, GT64120State *s =3D opaque; PCIHostState *phb =3D PCI_HOST_BRIDGE(s); uint32_t val; - uint32_t saddr; + uint32_t saddr =3D addr >> 2; =20 - saddr =3D (addr & 0xfff) >> 2; switch (saddr) { =20 /* CPU Configuration */ @@ -976,6 +974,10 @@ static const MemoryRegionOps isd_mem_ops =3D { .read =3D gt64120_readl, .write =3D gt64120_writel, .endianness =3D DEVICE_NATIVE_ENDIAN, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, }; =20 static int gt64120_pci_map_irq(PCIDevice *pci_dev, int irq_num) --=20 2.26.2 From nobody Sat May 18 21:45:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.41 as permitted sender) client-ip=209.85.221.41; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f41.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.41 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1615664928; cv=none; d=zohomail.com; s=zohoarc; b=MeoZMVxsbEZT+slaetrSG3tLe4fmWT48vNGl6njkiTUbR5+VzGZ5hRUVFXiJ5rYdDeUNU4889e6KDABBMGFlsnPAaJJNf5A5ZBc9iBB5OewBBZAYiWj+vUtpzjofO+vQm2lIj/SmtwKCg6UsL+RHaZ6vG55JgjJCMQ3GbMNXU2g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615664928; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=2Vu9O6tCMWZUmivFcqYztsy3+MmYDuWhmuiNrezQaCQ=; b=G6KU466KyuUmHtZtjbA+QUjJcnRYyC9bibLDr+xhT31uRPmk+9fmntj53UUVIsNntYsjt53USaj+zfBgV7LJTvbW4pSyOsCQJPmWWDz4Coyeuzqh+HXXzuZw7eFYjSjavYW6nPgdB8PM9z9OJsfZP+urc83RqwqmFpnIK6Fuq+4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.41 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-wr1-f41.google.com (mail-wr1-f41.google.com [209.85.221.41]) by mx.zohomail.com with SMTPS id 1615664928515797.1620696665706; Sat, 13 Mar 2021 11:48:48 -0800 (PST) Received: by mail-wr1-f41.google.com with SMTP id e10so6605033wro.12 for ; Sat, 13 Mar 2021 11:48:47 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (17.red-88-21-201.staticip.rima-tde.net. [88.21.201.17]) by smtp.gmail.com with ESMTPSA id y10sm13577848wrl.19.2021.03.13.11.48.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Mar 2021 11:48:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2Vu9O6tCMWZUmivFcqYztsy3+MmYDuWhmuiNrezQaCQ=; b=ItpAcowJUxqDZkRJYCJ78V9RkDTQg50M7S6RgIokygkfvLQAmN8+oTAUBAJIO+Pl4m VBJqibro09vTJDxhRAF9YBtNF655cEMq1p2CYILYDIvOAnJ040M/eye1oNAB9yFVminE +M47LM1sRuUccWwbJw2mkAAoJPV7KZ9Fw5vIIkeuvAYRj+tu/MULAGjrQZYlUCCMYBHh G2M5r2N4iZgrOC/LKiMp9t3Am/mowozMPsLS3txuffSmlZbgfPWqQIZa+hyuTpQFgR1R AplX9rKfQ+L552jMCocpB1kBKpPtT6tvt5a68MT6+CT9f1eCKK2suo/ic/GjJmxEKnhW 6vGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=2Vu9O6tCMWZUmivFcqYztsy3+MmYDuWhmuiNrezQaCQ=; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Fix the following typos: - GT_PCI1_CFGDATA is not a timer register but a PCI one, - zero-padding flag is out of the format Fixes: 641ca2bfcd5 ("hw/mips/gt64xxx_pci: Use qemu_log_mask() instead of de= bug printf()") Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: BALATON Zoltan Message-Id: <20210309142630.728014-4-f4bug@amsat.org> --- hw/mips/gt64xxx_pci.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index 99b1690af19..8ff31380d74 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -463,7 +463,7 @@ static void gt64120_writel(void *opaque, hwaddr addr, /* Read-only registers, do nothing */ qemu_log_mask(LOG_GUEST_ERROR, "gt64120: Read-only register write " - "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", + "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n", saddr << 2, size, size << 1, val); break; =20 @@ -473,7 +473,7 @@ static void gt64120_writel(void *opaque, hwaddr addr, /* Read-only registers, do nothing */ qemu_log_mask(LOG_GUEST_ERROR, "gt64120: Read-only register write " - "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", + "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n", saddr << 2, size, size << 1, val); break; =20 @@ -515,7 +515,7 @@ static void gt64120_writel(void *opaque, hwaddr addr, /* Not implemented */ qemu_log_mask(LOG_UNIMP, "gt64120: Unimplemented device register write " - "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", + "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n", saddr << 2, size, size << 1, val); break; =20 @@ -528,7 +528,7 @@ static void gt64120_writel(void *opaque, hwaddr addr, /* Read-only registers, do nothing */ qemu_log_mask(LOG_GUEST_ERROR, "gt64120: Read-only register write " - "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", + "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n", saddr << 2, size, size << 1, val); break; =20 @@ -565,7 +565,7 @@ static void gt64120_writel(void *opaque, hwaddr addr, /* Not implemented */ qemu_log_mask(LOG_UNIMP, "gt64120: Unimplemented DMA register write " - "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", + "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n", saddr << 2, size, size << 1, val); break; =20 @@ -578,7 +578,7 @@ static void gt64120_writel(void *opaque, hwaddr addr, /* Not implemented */ qemu_log_mask(LOG_UNIMP, "gt64120: Unimplemented timer register write " - "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", + "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n", saddr << 2, size, size << 1, val); break; =20 @@ -621,8 +621,8 @@ static void gt64120_writel(void *opaque, hwaddr addr, case GT_PCI1_CFGDATA: /* not implemented */ qemu_log_mask(LOG_UNIMP, - "gt64120: Unimplemented timer register write " - "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", + "gt64120: Unimplemented PCI register write " + "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n", saddr << 2, size, size << 1, val); break; case GT_PCI0_CFGADDR: @@ -682,7 +682,7 @@ static void gt64120_writel(void *opaque, hwaddr addr, default: qemu_log_mask(LOG_GUEST_ERROR, "gt64120: Illegal register write " - "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", + "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n", saddr << 2, size, size << 1, val); break; } @@ -958,7 +958,7 @@ static uint64_t gt64120_readl(void *opaque, val =3D s->regs[saddr]; qemu_log_mask(LOG_GUEST_ERROR, "gt64120: Illegal register read " - "reg:0x03%x size:%u value:0x%0*x\n", + "reg:0x%03x size:%u value:0x%0*x\n", saddr << 2, size, size << 1, val); break; } --=20 2.26.2 From nobody Sat May 18 21:45:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.52 as permitted sender) client-ip=209.85.221.52; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f52.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.52 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1615664933; cv=none; d=zohomail.com; s=zohoarc; b=V2ofwuOmhe3NJyZgd6e2B5xvYqxSEw5wuUjvsoEN2XLIAqEI4hhyHWM9bd23VIizQHTRZakRCL9Dwpif/P5xC+7SnuOlMzD+zGzeln0Q9LtkwaDnfsiuHpelpXRsW6hIM/BkpJR6fK/nk4r/yUv91GXRrm/RqEF3mHUxfn04S+I= ARC-Message-Signature: i=1; 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[88.21.201.17]) by smtp.gmail.com with ESMTPSA id g202sm7402468wme.20.2021.03.13.11.48.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Mar 2021 11:48:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=IjSXtEma9Ce1RqOZdI2+7Q74pg1NHqIsfhqlfuqbobI=; b=eFlae2YUbIpYxH+Kcj7lN5xm9Yl/sFvzpL6v3Nw0DkrIp1snhkH1aaFyJwyh4Je2y3 ivORJabTwi7QK9Fw9KoLmBfiD6pZLnhRg256Q6YBRo07v9Oh9UOjqyuCRyTTZK19LX50 yeGGk2WqoUHoB2IyW5EN7h6pkbj2iXDhmP3FQRnXtpilSGoz9/9sSEk5OPM+z/oHyFOt GRO0VSg8h1Sn0Uum3tkgMcfEoOgXa7/6UzZYTLzfztpJfIiI7QYvKHHdJGCoEHy9wbzz 2oq0cAZhsiIBWNZM1BfGtxBINzZz3uPmMUJAGzdhQtHHz2EGTB8wy4Vn60TWpc5Rvlka Jffw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=IjSXtEma9Ce1RqOZdI2+7Q74pg1NHqIsfhqlfuqbobI=; b=lZXPsAe5JoCOLQbw0jwrexuqsnvB3FnLYHKO9tmbQGxoEGXlk95mvRiaWPON4eYrcJ o8dXnvOiZNvHyEMan5UZ+L8tgTekjEtj8p0TyiUeTN3jeoeV1geo57yZ4ErvE+x9o2V8 +C3bt6pCAzNOrU1n35J6DtBJhpL7lVHpHqWMVWKamjqWC5YZyTV3jWAGF5myjK5hQ5T8 EwycfFOVR2RM94nxl29wbD2oVVTlTSQCaKcIpaFDpaGvg/gwAGSwQ7nwvdA8ShW4mmAB X0eR+YP8xW51QXH6Nlte1aFmqjs/sWR+NL2hPVy/eqtsdLeZdN/1A4IBHQyc99aHMsGQ dZBQ== X-Gm-Message-State: AOAM532YMjmCz7C3Xcob/FuLrd4k8Y4F2NQ+uqFk8x8P44grR2KwShrU V0PQc+x0kIz+lOTAKj4Z2pI= X-Google-Smtp-Source: ABdhPJy0Qx92uHR4wXK9fF6N6suGUXi3lKnHHO1BOM8BvEUlaN3L9e4ze556B4U3kGVVMGqJ2UdN1A== X-Received: by 2002:adf:ea8b:: with SMTP id s11mr20813334wrm.413.1615664931780; Sat, 13 Mar 2021 11:48:51 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , BALATON Zoltan Subject: [PULL 04/27] hw/mips/gt64xxx: Rename trace events related to interrupt registers Date: Sat, 13 Mar 2021 20:48:06 +0100 Message-Id: <20210313194829.2193621-5-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210313194829.2193621-1-f4bug@amsat.org> References: <20210313194829.2193621-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) We want to trace all register accesses. First rename the current gt64120_read / gt64120_write events with '_intreg' suffix, as they are restricted to interrupt registers. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: BALATON Zoltan Message-Id: <20210309142630.728014-5-f4bug@amsat.org> --- hw/mips/gt64xxx_pci.c | 16 ++++++++-------- hw/mips/trace-events | 4 ++-- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index 8ff31380d74..9a12d00d1e1 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -642,19 +642,19 @@ static void gt64120_writel(void *opaque, hwaddr addr, /* not really implemented */ s->regs[saddr] =3D ~(~(s->regs[saddr]) | ~(val & 0xfffffffe)); s->regs[saddr] |=3D !!(s->regs[saddr] & 0xfffffffe); - trace_gt64120_write("INTRCAUSE", size, val); + trace_gt64120_write_intreg("INTRCAUSE", size, val); break; case GT_INTRMASK: s->regs[saddr] =3D val & 0x3c3ffffe; - trace_gt64120_write("INTRMASK", size, val); + trace_gt64120_write_intreg("INTRMASK", size, val); break; case GT_PCI0_ICMASK: s->regs[saddr] =3D val & 0x03fffffe; - trace_gt64120_write("ICMASK", size, val); + trace_gt64120_write_intreg("ICMASK", size, val); break; case GT_PCI0_SERR0MASK: s->regs[saddr] =3D val & 0x0000003f; - trace_gt64120_write("SERR0MASK", size, val); + trace_gt64120_write_intreg("SERR0MASK", size, val); break; =20 /* Reserved when only PCI_0 is configured. */ @@ -929,19 +929,19 @@ static uint64_t gt64120_readl(void *opaque, /* Interrupts */ case GT_INTRCAUSE: val =3D s->regs[saddr]; - trace_gt64120_read("INTRCAUSE", size, val); + trace_gt64120_read_intreg("INTRCAUSE", size, val); break; case GT_INTRMASK: val =3D s->regs[saddr]; - trace_gt64120_read("INTRMASK", size, val); + trace_gt64120_read_intreg("INTRMASK", size, val); break; case GT_PCI0_ICMASK: val =3D s->regs[saddr]; - trace_gt64120_read("ICMASK", size, val); + trace_gt64120_read_intreg("ICMASK", size, val); break; case GT_PCI0_SERR0MASK: val =3D s->regs[saddr]; - trace_gt64120_read("SERR0MASK", size, val); + trace_gt64120_read_intreg("SERR0MASK", size, val); break; =20 /* Reserved when only PCI_0 is configured. */ diff --git a/hw/mips/trace-events b/hw/mips/trace-events index 915139d9811..b7e934c3933 100644 --- a/hw/mips/trace-events +++ b/hw/mips/trace-events @@ -1,4 +1,4 @@ # gt64xxx_pci.c -gt64120_read(const char *regname, unsigned size, uint64_t value) "gt64120 = read %s size:%u value:0x%08" PRIx64 -gt64120_write(const char *regname, unsigned size, uint64_t value) "gt64120= write %s size:%u value:0x%08" PRIx64 +gt64120_read_intreg(const char *regname, unsigned size, uint64_t value) "g= t64120 read %s size:%u value:0x%08" PRIx64 +gt64120_write_intreg(const char *regname, unsigned size, uint64_t value) "= gt64120 write %s size:%u value:0x%08" PRIx64 gt64120_isd_remap(uint64_t from_length, uint64_t from_addr, uint64_t to_le= ngth, uint64_t to_addr) "ISD: 0x%08" PRIx64 "@0x%08" PRIx64 " -> 0x%08" PRI= x64 "@0x%08" PRIx64 --=20 2.26.2 From nobody Sat May 18 21:45:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.54 as permitted sender) client-ip=209.85.221.54; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f54.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.54 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1615664938; cv=none; d=zohomail.com; s=zohoarc; b=NB4M4XHp+fYacmooeN51FM38n6wqNW3cHcSjaQodQ+RnONFW2yeImHnqk6lzfu0RfXq5tY928A8YwbyAEdwxTJlYsi5XRQ8YutCbqGfVT0lNZGHVM9wvbe7nYsaYqzU2kyi0nPclP6o7ZjVsBkCczrEDlzB/DUBTCOevFW/nJU0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615664938; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=vo/wOkAEHZzISR8kxsy1npD6PBbaQKYO5QfdkGe+lII=; b=dl2ZCpUxVgCjsg15IBUUAVDzSbJvk5pjGGfqQ1sj7dcb0JYgFtcC5WZTsSD3oaOmYyjoEozhi38Psk3eGOMITuxV+S3lhs3Zr5mar+o71ChBUZKS6mDPNxuw295Q6b4todloXgsskum8XOOt8sBZ0hcZHDstk4gVmaCvmx/z3Fg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.54 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f54.google.com (mail-wr1-f54.google.com [209.85.221.54]) by mx.zohomail.com with SMTPS id 1615664938751244.50382742663032; Sat, 13 Mar 2021 11:48:58 -0800 (PST) Received: by mail-wr1-f54.google.com with SMTP id z2so3619589wrl.5 for ; Sat, 13 Mar 2021 11:48:58 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (17.red-88-21-201.staticip.rima-tde.net. [88.21.201.17]) by smtp.gmail.com with ESMTPSA id f7sm14929492wrm.36.2021.03.13.11.48.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Mar 2021 11:48:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vo/wOkAEHZzISR8kxsy1npD6PBbaQKYO5QfdkGe+lII=; b=gVOwDkbrQhjSdJesfoNLlEMzD5mfub8PqpLT90DOeJ8Iz4pfkLwHdXUalKEGRPJKus C445CDad+T9ljHQ9Ljyui3M+4eecndmOz1uB8S/NkF7hH5q3HEOcyyaMUrRsC+vV8n6A wvSzyPJgbCUPvaWHyo9L1iUFAclt0crk50ebTSHdm9P7IwWMxaxShgb/x7ggEk1QDLnq shbVszJLYSh2Hxsg9FWfP3vDkYOmQc8dTIt1k148I9W1f2tDuZx6fYmoJcJHXfKfe+gQ UnCsdDLGzEQc/vFcgZ35jCFrKRvW4FpwG0tbUxjgi9NuBjNE10Lo9jsEEU08Uo8Xw++t nI4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=vo/wOkAEHZzISR8kxsy1npD6PBbaQKYO5QfdkGe+lII=; b=W6zDRMp/aGvrVRMbN7uNY0hZi3z5FOjNtfk1AdnZpN8l5du0270mdcERGf3zg9z/0M +QBqjamMlLAm1Vbb1/RpaYL7VV/MFDVfJoO7wVYabnJ0JzRkApzvgdC3nRDbqpTKXPp+ a0TGBu2ejyzw4SW+kqz6Rdz/TNr9vH/AvSnr2o19W/iUlULuwRUYz38oU/g3nbJfyh3g hEsb8B3wgoZ0LK6SzPNEYuL98oGmroAJe+94VT31qz5cOlU7R9/C8LXr8nWtc9UR1oDJ VOyFCmvFK5dQbzulnF7qauu2z2oygdlNYd94ZqP7WHmUJKXQne/v6kgNpydaY/LX4gjs fQhg== X-Gm-Message-State: AOAM531Uh8wn6cBVS2hfkvbIuyY5uvQG/cV5/nvUnJkHGx/Z51JHJ7+9 wTGYxmlO2ub+bYbFQPAx2ts= X-Google-Smtp-Source: ABdhPJyrv3KsWsn8pC3Kx81vGfT2EWR2AhOJXbmXJupfFfJ0AXgQ+lGOAbe5vTnKoIcR1l4FzVCmWg== X-Received: by 2002:a5d:4d01:: with SMTP id z1mr20134733wrt.133.1615664937014; Sat, 13 Mar 2021 11:48:57 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , BALATON Zoltan Subject: [PULL 05/27] hw/mips/gt64xxx: Trace accesses to ISD registers Date: Sat, 13 Mar 2021 20:48:07 +0100 Message-Id: <20210313194829.2193621-6-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210313194829.2193621-1-f4bug@amsat.org> References: <20210313194829.2193621-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Trace all accesses to Internal Space Decode (ISD) registers. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: BALATON Zoltan Message-Id: <20210309142630.728014-6-f4bug@amsat.org> --- hw/mips/gt64xxx_pci.c | 2 ++ hw/mips/trace-events | 2 ++ 2 files changed, 4 insertions(+) diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index 9a12d00d1e1..43349d6837d 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -387,6 +387,7 @@ static void gt64120_writel(void *opaque, hwaddr addr, PCIHostState *phb =3D PCI_HOST_BRIDGE(s); uint32_t saddr =3D addr >> 2; =20 + trace_gt64120_write(addr, val); if (!(s->regs[GT_CPU] & 0x00001000)) { val =3D bswap32(val); } @@ -966,6 +967,7 @@ static uint64_t gt64120_readl(void *opaque, if (!(s->regs[GT_CPU] & 0x00001000)) { val =3D bswap32(val); } + trace_gt64120_read(addr, val); =20 return val; } diff --git a/hw/mips/trace-events b/hw/mips/trace-events index b7e934c3933..13ee731a488 100644 --- a/hw/mips/trace-events +++ b/hw/mips/trace-events @@ -1,4 +1,6 @@ # gt64xxx_pci.c +gt64120_read(uint64_t addr, uint64_t value) "gt64120 read 0x%03"PRIx64" va= lue:0x%08" PRIx64 +gt64120_write(uint64_t addr, uint64_t value) "gt64120 write 0x%03"PRIx64" = value:0x%08" PRIx64 gt64120_read_intreg(const char *regname, unsigned size, uint64_t value) "g= t64120 read %s size:%u value:0x%08" PRIx64 gt64120_write_intreg(const char *regname, unsigned size, uint64_t value) "= gt64120 write %s size:%u value:0x%08" PRIx64 gt64120_isd_remap(uint64_t from_length, uint64_t from_addr, uint64_t to_le= ngth, uint64_t to_addr) "ISD: 0x%08" PRIx64 "@0x%08" PRIx64 " -> 0x%08" PRI= x64 "@0x%08" PRIx64 --=20 2.26.2 From nobody Sat May 18 21:45:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.44 as permitted sender) client-ip=209.85.128.44; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f44.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.44 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1615664943; cv=none; d=zohomail.com; s=zohoarc; b=JeTxOaW4p0BWgzVY/PF/uhyDtc+0BLc6gGTRXq/J/+npC8hocwbOZ+F/LcCZpNgZPJqJejCNW5PSoWdNoiAjjauDb/bkD27EfHtdBwK9iHGLa/mkjYSmcelQuw/8/yy5r8vMzGtI6FuAHMs3hN1i5MPUoxbAcuLeF+Ub2zpfOMs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615664943; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=p3rJSXI8AKLVIYnCtIJWOvToJLkr6ghkaSVEvpGX+18=; b=c8zLLr1fSWRhTBDcn9FKv1L1r/pWZkAvFhom3jKXFnSw42crPG3DAS4miiS7g72sZnU9pmkzii6hAA2Di5tqKflpteTvFqnYG/VSItsN5E3NQJw/9M+lL2Uk9IqtembX+qoqFtjGfhj9NMItix3+Vj5hwur2riMd7C115Oa11Ng= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.44 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) by mx.zohomail.com with SMTPS id 1615664943448144.13573908142234; Sat, 13 Mar 2021 11:49:03 -0800 (PST) Received: by mail-wm1-f44.google.com with SMTP id y124-20020a1c32820000b029010c93864955so17800598wmy.5 for ; Sat, 13 Mar 2021 11:49:02 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (17.red-88-21-201.staticip.rima-tde.net. [88.21.201.17]) by smtp.gmail.com with ESMTPSA id x13sm12900544wrt.75.2021.03.13.11.49.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Mar 2021 11:49:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=p3rJSXI8AKLVIYnCtIJWOvToJLkr6ghkaSVEvpGX+18=; b=B1YpgeO7wcHMKXyr858QrYYX8Ou0S6TSFOUYm5PiLxc89hO0tuRRwtlAVg1ZEDksbC z134Hv3Sun6+NpjJVlhA7VFg/fE63gpxnR+U/jdi9Gy87c2296iK9lIYXYgVcardPqFR 5v8YRyRRh2I18t/3SEL4b7dztK4Y51im/qygFAKB1RSXNzqARX7Jx2d/T+3Ahl5BTDBv L7I+WyVMxzXl589n9/M3zj8VFNqfr+7qIB6k6WXA+95rkw3GbvO1y5Bp/FyRFKEeDsAX afSog01cQs8k51vXlV0HPaNspfytcY8GDeLl83O2c94TzK3qD3NbRQ3zLuoqIlu4Zy5I i0Yw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=p3rJSXI8AKLVIYnCtIJWOvToJLkr6ghkaSVEvpGX+18=; b=sCb6uFWyHSKfDO186D2vpz3CSSO5DLwdrHFlkJ7sc6MQ8L+VoBHw18QzaZE3egfg3V b2qumpPU5OISqVAEmEX8MRWrskztCI8MwFs3i3khvXKl54VadFBjCT4ivUnGUGYE/BrS cNatV4dkJhgStfQ2Ac1k/tneRxuM5VmBBE6b69gWoWHKzWcCagtW6yJvU3gMGO/e8Jiu 4ir/QWPIw8EP8hq1s/aWTIGkCJeKtUnc8xynMh7jHL1ZVwyQzzc1LQ4Zb0SLDJmEVH5U S4QjvDgOhOe9/6ZW4tSdGcYEbBl4pUfeODh0AcqnE8EqTy7sz31p9RhSCMRDOj6fCffJ IE+Q== X-Gm-Message-State: AOAM530p2zJK939LBWYU4gy+aoyYE5nLyOs1BzWdGnOdNqzvYM60S/NB fiEQKEYZIR1uKtuB/lEqwlM= X-Google-Smtp-Source: ABdhPJwdKxsPhx/htLlNPAagCk7+vMiojx0KvyB+2CCnYircVoh801TIoTgdFyWNFG+K34qngD4pQg== X-Received: by 2002:a05:600c:2197:: with SMTP id e23mr18590577wme.39.1615664941799; Sat, 13 Mar 2021 11:49:01 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 06/27] target/mips/meson: Introduce mips_tcg source set Date: Sat, 13 Mar 2021 20:48:08 +0100 Message-Id: <20210313194829.2193621-7-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210313194829.2193621-1-f4bug@amsat.org> References: <20210313194829.2193621-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Introduce the 'mips_tcg' source set to collect TCG specific files. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/meson.build | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/target/mips/meson.build b/target/mips/meson.build index 9741545440c..75c16524606 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -6,12 +6,13 @@ ] =20 mips_ss =3D ss.source_set() -mips_ss.add(gen) mips_ss.add(files( 'cpu.c', 'gdbstub.c', )) -mips_ss.add(when: 'CONFIG_TCG', if_true: files( +mips_tcg_ss =3D ss.source_set() +mips_tcg_ss.add(gen) +mips_tcg_ss.add(files( 'dsp_helper.c', 'fpu_helper.c', 'lmmi_helper.c', @@ -36,5 +37,7 @@ 'cp0_helper.c', )) =20 +mips_ss.add_all(when: 'CONFIG_TCG', if_true: [mips_tcg_ss]) + target_arch +=3D {'mips': mips_ss} target_softmmu_arch +=3D {'mips': mips_softmmu_ss} --=20 2.26.2 From nobody Sat May 18 21:45:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.54 as permitted sender) client-ip=209.85.221.54; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f54.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.54 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1615664948; cv=none; d=zohomail.com; s=zohoarc; b=Cgt2GfUEHroljq+Y5aMzLo2ZVShV5QVsc8Hn7ayaiepqcXAA3CoKygDvP1mhHcficuvl6dzUnVwRDHSgzk/sTgMXXyyrGWvAjM64PQVF1SbmZpmEsq0u6w1BBPl+aZs3ZPEkaUbUzrpf4luDkSNtdSXEbvWfNi8Qve7bNviDuco= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615664948; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=moYUnA443ZNCun6tItxZiGo6Z2/jYTaF1F6gDoL/yFY=; b=n94MZdzj8+sVU6O8gRELbsIWETCQ3DKejhjXK24304NiMPwYhX7YahUUoEOXyl7YERX5saL3RyMFUhGPenKzMKfIsz7W1IyRGSzoubfZyZMsIfteIMRM1IdmeLquscNtdjC7EDyLF3mG+fCCusmtWduuhSOdqUd3659noepRf/8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.54 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f54.google.com (mail-wr1-f54.google.com [209.85.221.54]) by mx.zohomail.com with SMTPS id 1615664948216184.1018476970031; Sat, 13 Mar 2021 11:49:08 -0800 (PST) Received: by mail-wr1-f54.google.com with SMTP id y16so6634041wrw.3 for ; Sat, 13 Mar 2021 11:49:07 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (17.red-88-21-201.staticip.rima-tde.net. [88.21.201.17]) by smtp.gmail.com with ESMTPSA id x11sm8409427wme.9.2021.03.13.11.49.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Mar 2021 11:49:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=moYUnA443ZNCun6tItxZiGo6Z2/jYTaF1F6gDoL/yFY=; b=Nod/YtpbQgu+foFOgTk7lBE9RhDfhwsvUVlAGmZEn7kuf6sfLQM2DZGsDZlElCJBpL Ymb4p8wCU8FXS+IUpDXiOUiP2o3UntsnVmOZd7I1mYGDo5IFM/0kgueNvL+a03OcdXUQ bJ84t8BaCJGh6J3TH3r2KuZCL0Kn/N39Z70EDEmScHgP4vQUG/DCoiv9ZH5Jr2r0YSpP wRTrWgN1bkSeSo6fXAtWhQPBip2DVaAJuohfaEyfI7Nh5NzthOOy0WAziCMsXbXzsZnm XsUUtlH3xqX1SJgK6riBnTzCTmzK6AmLZ6bjfJaZ21MlAW0yfpcKCDEDSfj75rwYDJJZ hsoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=moYUnA443ZNCun6tItxZiGo6Z2/jYTaF1F6gDoL/yFY=; b=cwNmwir2ODQOW5Fd5Jh7ZQKKHpIgInmDzQssQsxHUtU9+gtSA2GhgIbF0S6BvcbGki u2zD2SqK/ubeoVQ8oWrx1aSE3v6X2HlrCevAJ1NLH+4GQ3YZb9VopLFwF1Gmfm24UUlC 7I5xTDBF6eP0gBpJKyhQIB4e+o4Ub5k21B/JHZUxlha/V6BwN5OvrycljSLecQ38BgDP E0EoJc6DEdXtTbt1S54t54090BNPOt8u3A+3aqbWpst1M2kSqbIcWhKpDETiYUop/2Nc bVQihJTP67lp49xU9v/kgJ3gSgtkuflQEgnDOy5W3VXvOKzGRTOBMP45BzdC2j1T0Nt1 7kLQ== X-Gm-Message-State: AOAM533uQQHRF4Qzq0i3Tq3IvIiBXNbMhqwHf61awt/70tFKfL3WFWdH uzH8dqgcH5RD4RY8l7+jk+U= X-Google-Smtp-Source: ABdhPJy5Qw4u13qlDQgYECb2wC0AGYi4zMGUjrb8whmCebbufRG9enPN/mOL26/Yu4kyYcccDRUrZA== X-Received: by 2002:adf:f587:: with SMTP id f7mr20196758wro.147.1615664946594; Sat, 13 Mar 2021 11:49:06 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 07/27] target/mips/meson: Restrict mips-semi.c to TCG Date: Sat, 13 Mar 2021 20:48:09 +0100 Message-Id: <20210313194829.2193621-8-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210313194829.2193621-1-f4bug@amsat.org> References: <20210313194829.2193621-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/mips/meson.build b/target/mips/meson.build index 75c16524606..53580633ce0 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -31,10 +31,10 @@ 'addr.c', 'cp0_timer.c', 'machine.c', - 'mips-semi.c', )) mips_softmmu_ss.add(when: 'CONFIG_TCG', if_true: files( 'cp0_helper.c', + 'mips-semi.c', )) =20 mips_ss.add_all(when: 'CONFIG_TCG', if_true: [mips_tcg_ss]) --=20 2.26.2 From nobody Sat May 18 21:45:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.50 as permitted sender) client-ip=209.85.221.50; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f50.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.50 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1615664953; cv=none; d=zohomail.com; s=zohoarc; b=WApeIvadg8f/EiMAvabwnTCkG5lA5dQOr5wXccitH6fc+/qrhdBc+ufXlMy28xneLn1XwWLWpsK5WYXKRURFIg+N673vx2GOh22ysAegKkLHe357G9Bn5Z0EZGhhgOlV/XhTsP082FkPLJwdBDyc0XsDvV+rbQwkF4NQOo0aims= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615664953; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=QT135G9+ZflxNaE9JXFsl2Girh95rzMzYvPq1Qqa2Qk=; b=mj4J4Ww/MM3pMc0N+FwSL6Yj/7GLLETufHZ5zRLVIYiFvDTtPAXqCTJmgnuaGFZ5HLdJJBnzisPiYVhSyqBkc1nurnUgJ8uiWb+TFzKxwJhBjSIIUndivSEK1CtR6KSp1IY8kSEQGnNVTAqLXPnbz+xj3AlpfPpGzQtn6ZAZPLY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.50 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f50.google.com (mail-wr1-f50.google.com [209.85.221.50]) by mx.zohomail.com with SMTPS id 1615664953122238.08297478614088; Sat, 13 Mar 2021 11:49:13 -0800 (PST) Received: by mail-wr1-f50.google.com with SMTP id o14so2817631wrm.11 for ; Sat, 13 Mar 2021 11:49:12 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (17.red-88-21-201.staticip.rima-tde.net. [88.21.201.17]) by smtp.gmail.com with ESMTPSA id x11sm8409619wme.9.2021.03.13.11.49.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Mar 2021 11:49:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QT135G9+ZflxNaE9JXFsl2Girh95rzMzYvPq1Qqa2Qk=; b=MmuGRmy8UhezppiyA4ChcDyh8ZlcDuabjxgQ5ugaWA3gBqJAUIrYBNFpgF2zCvYW8I ERM8xhsF2SA4cysQQETsNhBgfnKcrqqUCo4u13EQXxq0Da0Xf3bq/CXBhGEiO5iBYguG hrvrROm/qQYsNQzqueDmhC2okfj4nBve6uKz7PyKN37t/jX3IWIB8vW9FodOdxhJyNad T9nD88cpnAIl66cE8dF7YQ7xoho4KL1q40RVUWk1ezWB1CvKjwRmo90/YaSXAVBXRmcH AflXAGQqid+KmOkDINo5HFOLtsskNsbg/v9sNcwhihPd7NcPJU5SC5rQziIDrCGe64Uj QBFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=QT135G9+ZflxNaE9JXFsl2Girh95rzMzYvPq1Qqa2Qk=; b=IRBrN9JxeeNrWHBAPCiwliy07TktfxOGKUPa3Gii2jHMYt98iR2sOYkesJU2Ovu7jC eidMcFs2oiI9OFWq25y8HN8HMV0ZKFOB15Twca4MoCVRMFgc9eDDkI4HaITkqRll1Att PHOQNbV9vGH1jBjh04YzxKn7jAnqGXbDkqGfALKucTdsSvP0EgLY1wXq2FyQqlNBRmEK ZYuDKXOBEXVhoe8KJWBNZm8ktUe/uK2EWNW/efpXzluK6jB7/5Ky2lwKrhDuVCPvA5gX XXDTlB0m5YJIwAx2a0wX0u1vjgONco2iuIG5eEkk80FbznQr9gfOuAxlfH3hO1zipVFm +t5A== X-Gm-Message-State: AOAM532eio+tonu5F74EoCD7YWxP5gRSMdKu9WCJmmf6meROYblZ+kJV RreXuVAvSZvZpChcSYp+gYw= X-Google-Smtp-Source: ABdhPJx6cfM6335gPZTv6t+xPo0V2/oMCq6Ub2BmeIqV1vo6y/LXbm7j5FFmQ82sTp8Qyt7CvmY9jw== X-Received: by 2002:adf:d1ce:: with SMTP id b14mr19987184wrd.126.1615664951444; Sat, 13 Mar 2021 11:49:11 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 08/27] target/mips: Rewrite complex ifdef'ry Date: Sat, 13 Mar 2021 20:48:10 +0100 Message-Id: <20210313194829.2193621-9-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210313194829.2193621-1-f4bug@amsat.org> References: <20210313194829.2193621-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) No need for this obfuscated ifdef'ry, KISS. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/translate.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 0b6d82d228e..ceb77a3a7ca 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28276,13 +28276,16 @@ static bool decode_opc_legacy(CPUMIPSState *env, = DisasContext *ctx) #if defined(TARGET_MIPS64) if ((ctx->insn_flags & INSN_R5900) && (ctx->insn_flags & ASE_MMI))= { decode_mmi(env, ctx); -#else + break; + } +#endif +#if !defined(TARGET_MIPS64) if (ctx->insn_flags & ASE_MXU) { decode_opc_mxu(env, ctx); -#endif - } else { - decode_opc_special2_legacy(env, ctx); + break; } +#endif + decode_opc_special2_legacy(env, ctx); break; case OPC_SPECIAL3: #if defined(TARGET_MIPS64) --=20 2.26.2 From nobody Sat May 18 21:45:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.52 as permitted sender) client-ip=209.85.128.52; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f52.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.52 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1615664959; cv=none; d=zohomail.com; s=zohoarc; b=ME28z03ouXzfAoEEvwdZHCItMZ8vHigqhZ4yqyF8X2X6qb7Yi9KVqyMlgKRQ7wZQDNoN43At1PqW0ln7mxhlNvowkhRSeYhgLMPZpTgCWX5Rg4pcIA26R2Wi4UoEKI0Hmsga23LS3b5UJs3RIV9g3jrCBkLLutSLl6f42GOQr60= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615664959; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Qv+ek4gJlon/VRjqa0yiW9aP8XMNZk3Sab+R6Xka1F0=; b=Rmak7Nlvk7GwpYBRGU2LvdIFdTK8qZq9vrGnJFab+WqtmJxharqoAIFmy8fabM9SZewUAWDuT7WSJ9ephdyXdPgBfkfPDNxQjmmgh5Qp41MqN4AX7VKrUqv/M80HbbfON2g7R+ZOZbh7WylENtKmSEPmnA/+qP9YBQ6TXhKhHcY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.52 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) by mx.zohomail.com with SMTPS id 1615664959420345.7998511620359; Sat, 13 Mar 2021 11:49:19 -0800 (PST) Received: by mail-wm1-f52.google.com with SMTP id m20-20020a7bcb940000b029010cab7e5a9fso17790976wmi.3 for ; Sat, 13 Mar 2021 11:49:18 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (17.red-88-21-201.staticip.rima-tde.net. [88.21.201.17]) by smtp.gmail.com with ESMTPSA id s18sm14943414wrr.27.2021.03.13.11.49.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Mar 2021 11:49:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Qv+ek4gJlon/VRjqa0yiW9aP8XMNZk3Sab+R6Xka1F0=; b=e0XtMkB/HxclQG0of4s1kJrR1H8/Tlld3yWUsRKQO//BxgVMU1JhTgD7+pHNn6EV0X RC4c/JDZ3cqjVebRyQ13Qi/CUUB9wnKeXFBXScWpnDVgrltn1yxNwXkemfxBG0DB55fY gGknNDZ+w2zZ2cYE1aCmT+NS+YkhH/MEXfZOqcAI+6g+7xXkp/5Lv8YsoO2ebXRTPjVc ypZsN8iCUWUvL68ktlB68hIQYL7r8rVdJd17WACKtLQ+34RyADI7DxirV4OnxF3SYJ04 5OrtmwjgWmB/O7JXqPFDtpY6006A63kjfemXWa6D6eHhsb3UKhFb80nwYJ20SCht31wK d3ow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=Qv+ek4gJlon/VRjqa0yiW9aP8XMNZk3Sab+R6Xka1F0=; b=WHlvB6Xm+4p2AY4X42k22ZIaYcV3hpNmVXcDMpVdcfjuYVjawvbTlaktsU4p+Psnf5 I2Pv80KXgTMQayWIEjaNoMe7vRmqXoZ+O7rap+oSwuSDjJEOWR5a8Hzfx31GBnqZ1rO9 DPs38XUQrJ6GoxTXTIPIud8xxcL3mbteF5lZh32Tzm10X23NRN4XilawG4EKZkV7eMcR ABkCPPVbcgpPHPFjPiiizhCXPU3nJllOVTDNJFzjWNuECcQw/LQQPF3vpxhgrWXKt3WY /8u0BSpWD/sk9plkaDuAWQjhW18wjZ0JNC5avWZ8DxtaS2JnNDos8e1oG/+DiyysprHh iVaA== X-Gm-Message-State: AOAM533dG2lQTsX8lE16TZWHECHTCX6Xd/wyrcfQkQiubwOBd0iGuadm XvXCOziH7w4Lc0BLzH+KFNs= X-Google-Smtp-Source: ABdhPJw8WcLDKdYRSjwEawn2Nzzg8f82foOfvLkHptBHIx9xzBwfimqbG+Vi0P8M0MWIpmyhKRj1ig== X-Received: by 2002:a1c:43c6:: with SMTP id q189mr19072923wma.80.1615664956976; Sat, 13 Mar 2021 11:49:16 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 09/27] target/mips: Remove XBurst Media eXtension Unit dead code Date: Sat, 13 Mar 2021 20:48:11 +0100 Message-Id: <20210313194829.2193621-10-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210313194829.2193621-1-f4bug@amsat.org> References: <20210313194829.2193621-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) All these unimplemented MXU opcodes end up calling gen_reserved_instruction() which is the default switch case in decode_opc_mxu(). The translate.c file is already big enough and hard to maintain, remove 1300 lines of unnecessary code and /* TODO */ comments. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/translate.c | 1286 --------------------------------------- 1 file changed, 1286 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index ceb77a3a7ca..2b9438eaff2 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1464,70 +1464,16 @@ enum { */ =20 enum { - OPC_MXU_S32MADD =3D 0x00, - OPC_MXU_S32MADDU =3D 0x01, OPC__MXU_MUL =3D 0x02, OPC_MXU__POOL00 =3D 0x03, - OPC_MXU_S32MSUB =3D 0x04, - OPC_MXU_S32MSUBU =3D 0x05, - OPC_MXU__POOL01 =3D 0x06, - OPC_MXU__POOL02 =3D 0x07, OPC_MXU_D16MUL =3D 0x08, - OPC_MXU__POOL03 =3D 0x09, OPC_MXU_D16MAC =3D 0x0A, - OPC_MXU_D16MACF =3D 0x0B, - OPC_MXU_D16MADL =3D 0x0C, - OPC_MXU_S16MAD =3D 0x0D, - OPC_MXU_Q16ADD =3D 0x0E, - OPC_MXU_D16MACE =3D 0x0F, OPC_MXU__POOL04 =3D 0x10, - OPC_MXU__POOL05 =3D 0x11, - OPC_MXU__POOL06 =3D 0x12, - OPC_MXU__POOL07 =3D 0x13, - OPC_MXU__POOL08 =3D 0x14, - OPC_MXU__POOL09 =3D 0x15, - OPC_MXU__POOL10 =3D 0x16, - OPC_MXU__POOL11 =3D 0x17, - OPC_MXU_D32ADD =3D 0x18, - OPC_MXU__POOL12 =3D 0x19, - /* not assigned 0x1A */ - OPC_MXU__POOL13 =3D 0x1B, - OPC_MXU__POOL14 =3D 0x1C, - OPC_MXU_Q8ACCE =3D 0x1D, - /* not assigned 0x1E */ - /* not assigned 0x1F */ - /* not assigned 0x20 */ - /* not assigned 0x21 */ OPC_MXU_S8LDD =3D 0x22, - OPC_MXU_S8STD =3D 0x23, - OPC_MXU_S8LDI =3D 0x24, - OPC_MXU_S8SDI =3D 0x25, - OPC_MXU__POOL15 =3D 0x26, OPC_MXU__POOL16 =3D 0x27, - OPC_MXU__POOL17 =3D 0x28, - /* not assigned 0x29 */ - OPC_MXU_S16LDD =3D 0x2A, - OPC_MXU_S16STD =3D 0x2B, - OPC_MXU_S16LDI =3D 0x2C, - OPC_MXU_S16SDI =3D 0x2D, OPC_MXU_S32M2I =3D 0x2E, OPC_MXU_S32I2M =3D 0x2F, - OPC_MXU_D32SLL =3D 0x30, - OPC_MXU_D32SLR =3D 0x31, - OPC_MXU_D32SARL =3D 0x32, - OPC_MXU_D32SAR =3D 0x33, - OPC_MXU_Q16SLL =3D 0x34, - OPC_MXU_Q16SLR =3D 0x35, - OPC_MXU__POOL18 =3D 0x36, - OPC_MXU_Q16SAR =3D 0x37, OPC_MXU__POOL19 =3D 0x38, - OPC_MXU__POOL20 =3D 0x39, - OPC_MXU__POOL21 =3D 0x3A, - OPC_MXU_Q16SCOP =3D 0x3B, - OPC_MXU_Q8MADL =3D 0x3C, - OPC_MXU_S32SFL =3D 0x3D, - OPC_MXU_Q8SAD =3D 0x3E, - /* not assigned 0x3F */ }; =20 =20 @@ -1541,39 +1487,6 @@ enum { OPC_MXU_D16MIN =3D 0x03, OPC_MXU_Q8MAX =3D 0x04, OPC_MXU_Q8MIN =3D 0x05, - OPC_MXU_Q8SLT =3D 0x06, - OPC_MXU_Q8SLTU =3D 0x07, -}; - -/* - * MXU pool 01 - */ -enum { - OPC_MXU_S32SLT =3D 0x00, - OPC_MXU_D16SLT =3D 0x01, - OPC_MXU_D16AVG =3D 0x02, - OPC_MXU_D16AVGR =3D 0x03, - OPC_MXU_Q8AVG =3D 0x04, - OPC_MXU_Q8AVGR =3D 0x05, - OPC_MXU_Q8ADD =3D 0x07, -}; - -/* - * MXU pool 02 - */ -enum { - OPC_MXU_S32CPS =3D 0x00, - OPC_MXU_D16CPS =3D 0x02, - OPC_MXU_Q8ABD =3D 0x04, - OPC_MXU_Q16SAT =3D 0x06, -}; - -/* - * MXU pool 03 - */ -enum { - OPC_MXU_D16MULF =3D 0x00, - OPC_MXU_D16MULE =3D 0x01, }; =20 /* @@ -1584,136 +1497,17 @@ enum { OPC_MXU_S32LDDR =3D 0x01, }; =20 -/* - * MXU pool 05 - */ -enum { - OPC_MXU_S32STD =3D 0x00, - OPC_MXU_S32STDR =3D 0x01, -}; - -/* - * MXU pool 06 - */ -enum { - OPC_MXU_S32LDDV =3D 0x00, - OPC_MXU_S32LDDVR =3D 0x01, -}; - -/* - * MXU pool 07 - */ -enum { - OPC_MXU_S32STDV =3D 0x00, - OPC_MXU_S32STDVR =3D 0x01, -}; - -/* - * MXU pool 08 - */ -enum { - OPC_MXU_S32LDI =3D 0x00, - OPC_MXU_S32LDIR =3D 0x01, -}; - -/* - * MXU pool 09 - */ -enum { - OPC_MXU_S32SDI =3D 0x00, - OPC_MXU_S32SDIR =3D 0x01, -}; - -/* - * MXU pool 10 - */ -enum { - OPC_MXU_S32LDIV =3D 0x00, - OPC_MXU_S32LDIVR =3D 0x01, -}; - -/* - * MXU pool 11 - */ -enum { - OPC_MXU_S32SDIV =3D 0x00, - OPC_MXU_S32SDIVR =3D 0x01, -}; - -/* - * MXU pool 12 - */ -enum { - OPC_MXU_D32ACC =3D 0x00, - OPC_MXU_D32ACCM =3D 0x01, - OPC_MXU_D32ASUM =3D 0x02, -}; - -/* - * MXU pool 13 - */ -enum { - OPC_MXU_Q16ACC =3D 0x00, - OPC_MXU_Q16ACCM =3D 0x01, - OPC_MXU_Q16ASUM =3D 0x02, -}; - -/* - * MXU pool 14 - */ -enum { - OPC_MXU_Q8ADDE =3D 0x00, - OPC_MXU_D8SUM =3D 0x01, - OPC_MXU_D8SUMC =3D 0x02, -}; - -/* - * MXU pool 15 - */ -enum { - OPC_MXU_S32MUL =3D 0x00, - OPC_MXU_S32MULU =3D 0x01, - OPC_MXU_S32EXTR =3D 0x02, - OPC_MXU_S32EXTRV =3D 0x03, -}; - /* * MXU pool 16 */ enum { - OPC_MXU_D32SARW =3D 0x00, - OPC_MXU_S32ALN =3D 0x01, OPC_MXU_S32ALNI =3D 0x02, - OPC_MXU_S32LUI =3D 0x03, OPC_MXU_S32NOR =3D 0x04, OPC_MXU_S32AND =3D 0x05, OPC_MXU_S32OR =3D 0x06, OPC_MXU_S32XOR =3D 0x07, }; =20 -/* - * MXU pool 17 - */ -enum { - OPC_MXU_LXB =3D 0x00, - OPC_MXU_LXH =3D 0x01, - OPC_MXU_LXW =3D 0x03, - OPC_MXU_LXBU =3D 0x04, - OPC_MXU_LXHU =3D 0x05, -}; - -/* - * MXU pool 18 - */ -enum { - OPC_MXU_D32SLLV =3D 0x00, - OPC_MXU_D32SLRV =3D 0x01, - OPC_MXU_D32SARV =3D 0x03, - OPC_MXU_Q16SLLV =3D 0x04, - OPC_MXU_Q16SLRV =3D 0x05, - OPC_MXU_Q16SARV =3D 0x07, -}; - /* * MXU pool 19 */ @@ -1722,26 +1516,6 @@ enum { OPC_MXU_Q8MULSU =3D 0x01, }; =20 -/* - * MXU pool 20 - */ -enum { - OPC_MXU_Q8MOVZ =3D 0x00, - OPC_MXU_Q8MOVN =3D 0x01, - OPC_MXU_D16MOVZ =3D 0x02, - OPC_MXU_D16MOVN =3D 0x03, - OPC_MXU_S32MOVZ =3D 0x04, - OPC_MXU_S32MOVN =3D 0x05, -}; - -/* - * MXU pool 21 - */ -enum { - OPC_MXU_Q8MAC =3D 0x00, - OPC_MXU_Q8MACSU =3D 0x01, -}; - /* * Overview of the TX79-specific instruction set * =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D @@ -25332,11 +25106,6 @@ static void gen_mxu_s32ldd_s32lddr(DisasContext *c= tx) * S32NOR XRa, XRb, XRc * Update XRa with the result of logical bitwise 'nor' operation * applied to the content of XRb and XRc. - * - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+-----+-------+-------+-------+-----------+ - * | SPECIAL2 |0 0 0 0 0| opc | XRc | XRb | XRa |MXU__POOL16| - * +-----------+---------+-----+-------+-------+-------+-----------+ */ static void gen_mxu_S32NOR(DisasContext *ctx) { @@ -25373,11 +25142,6 @@ static void gen_mxu_S32NOR(DisasContext *ctx) * S32AND XRa, XRb, XRc * Update XRa with the result of logical bitwise 'and' operation * applied to the content of XRb and XRc. - * - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+-----+-------+-------+-------+-----------+ - * | SPECIAL2 |0 0 0 0 0| opc | XRc | XRb | XRa |MXU__POOL16| - * +-----------+---------+-----+-------+-------+-------+-----------+ */ static void gen_mxu_S32AND(DisasContext *ctx) { @@ -25408,11 +25172,6 @@ static void gen_mxu_S32AND(DisasContext *ctx) * S32OR XRa, XRb, XRc * Update XRa with the result of logical bitwise 'or' operation * applied to the content of XRb and XRc. - * - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+-----+-------+-------+-------+-----------+ - * | SPECIAL2 |0 0 0 0 0| opc | XRc | XRb | XRa |MXU__POOL16| - * +-----------+---------+-----+-------+-------+-------+-----------+ */ static void gen_mxu_S32OR(DisasContext *ctx) { @@ -25449,11 +25208,6 @@ static void gen_mxu_S32OR(DisasContext *ctx) * S32XOR XRa, XRb, XRc * Update XRa with the result of logical bitwise 'xor' operation * applied to the content of XRb and XRc. - * - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+-----+-------+-------+-------+-----------+ - * | SPECIAL2 |0 0 0 0 0| opc | XRc | XRb | XRa |MXU__POOL16| - * +-----------+---------+-----+-------+-------+-------+-----------+ */ static void gen_mxu_S32XOR(DisasContext *ctx) { @@ -25503,11 +25257,6 @@ static void gen_mxu_S32XOR(DisasContext *ctx) * S32MIN XRa, XRb, XRc * Update XRa with the minimum of signed 32-bit integers contained * in XRb and XRc. - * - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+-----+-------+-------+-------+-----------+ - * | SPECIAL2 |0 0 0 0 0| opc | XRc | XRb | XRa |MXU__POOL00| - * +-----------+---------+-----+-------+-------+-------+-----------+ */ static void gen_mxu_S32MAX_S32MIN(DisasContext *ctx) { @@ -25558,11 +25307,6 @@ static void gen_mxu_S32MAX_S32MIN(DisasContext *ct= x) * D16MIN * Update XRa with the 16-bit-wise minimums of signed integers * contained in XRb and XRc. - * - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+-----+-------+-------+-------+-----------+ - * | SPECIAL2 |0 0 0 0 0| opc | XRc | XRb | XRa |MXU__POOL00| - * +-----------+---------+-----+-------+-------+-------+-----------+ */ static void gen_mxu_D16MAX_D16MIN(DisasContext *ctx) { @@ -25660,11 +25404,6 @@ static void gen_mxu_D16MAX_D16MIN(DisasContext *ct= x) * Q8MIN * Update XRa with the 8-bit-wise minimums of signed integers * contained in XRb and XRc. - * - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+-----+-------+-------+-------+-----------+ - * | SPECIAL2 |0 0 0 0 0| opc | XRc | XRb | XRa |MXU__POOL00| - * +-----------+---------+-----+-------+-------+-------+-----------+ */ static void gen_mxu_Q8MAX_Q8MIN(DisasContext *ctx) { @@ -25774,12 +25513,6 @@ static void gen_mxu_Q8MAX_Q8MIN(DisasContext *ctx) * S32ALNI XRc, XRb, XRa, optn3 * Arrange bytes from XRb and XRc according to one of five sets of * rules determined by optn3, and place the result in XRa. - * - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+-----+---+-----+-------+-------+-------+-----------+ - * | SPECIAL2 |optn3|0 0|x x x| XRc | XRb | XRa |MXU__POOL16| - * +-----------+-----+---+-----+-------+-------+-------+-----------+ - * */ static void gen_mxu_S32ALNI(DisasContext *ctx) { @@ -25961,16 +25694,6 @@ static void gen_mxu_S32ALNI(DisasContext *ctx) * =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D */ =20 -/* - * - * Decode MXU pool00 - * - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+-----+-------+-------+-------+-----------+ - * | SPECIAL2 |0 0 0 0 0|x x x| XRc | XRb | XRa |MXU__POOL00| - * +-----------+---------+-----+-------+-------+-------+-----------+ - * - */ static void decode_opc_mxu__pool00(CPUMIPSState *env, DisasContext *ctx) { uint32_t opcode =3D extract32(ctx->opcode, 18, 3); @@ -25988,16 +25711,6 @@ static void decode_opc_mxu__pool00(CPUMIPSState *e= nv, DisasContext *ctx) case OPC_MXU_Q8MIN: gen_mxu_Q8MAX_Q8MIN(ctx); break; - case OPC_MXU_Q8SLT: - /* TODO: Implement emulation of Q8SLT instruction. */ - MIPS_INVAL("OPC_MXU_Q8SLT"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_Q8SLTU: - /* TODO: Implement emulation of Q8SLTU instruction. */ - MIPS_INVAL("OPC_MXU_Q8SLTU"); - gen_reserved_instruction(ctx); - break; default: MIPS_INVAL("decode_opc_mxu"); gen_reserved_instruction(ctx); @@ -26005,161 +25718,6 @@ static void decode_opc_mxu__pool00(CPUMIPSState *= env, DisasContext *ctx) } } =20 -/* - * - * Decode MXU pool01 - * - * S32SLT, D16SLT, D16AVG, D16AVGR, Q8AVG, Q8AVGR: - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+-----+-------+-------+-------+-----------+ - * | SPECIAL2 |0 0 0 0 0|x x x| XRc | XRb | XRa |MXU__POOL01| - * +-----------+---------+-----+-------+-------+-------+-----------+ - * - * Q8ADD: - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---+-----+-----+-------+-------+-------+-----------+ - * | SPECIAL2 |en2|0 0 0|x x x| XRc | XRb | XRa |MXU__POOL01| - * +-----------+---+-----+-----+-------+-------+-------+-----------+ - * - */ -static void decode_opc_mxu__pool01(CPUMIPSState *env, DisasContext *ctx) -{ - uint32_t opcode =3D extract32(ctx->opcode, 18, 3); - - switch (opcode) { - case OPC_MXU_S32SLT: - /* TODO: Implement emulation of S32SLT instruction. */ - MIPS_INVAL("OPC_MXU_S32SLT"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_D16SLT: - /* TODO: Implement emulation of D16SLT instruction. */ - MIPS_INVAL("OPC_MXU_D16SLT"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_D16AVG: - /* TODO: Implement emulation of D16AVG instruction. */ - MIPS_INVAL("OPC_MXU_D16AVG"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_D16AVGR: - /* TODO: Implement emulation of D16AVGR instruction. */ - MIPS_INVAL("OPC_MXU_D16AVGR"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_Q8AVG: - /* TODO: Implement emulation of Q8AVG instruction. */ - MIPS_INVAL("OPC_MXU_Q8AVG"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_Q8AVGR: - /* TODO: Implement emulation of Q8AVGR instruction. */ - MIPS_INVAL("OPC_MXU_Q8AVGR"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_Q8ADD: - /* TODO: Implement emulation of Q8ADD instruction. */ - MIPS_INVAL("OPC_MXU_Q8ADD"); - gen_reserved_instruction(ctx); - break; - default: - MIPS_INVAL("decode_opc_mxu"); - gen_reserved_instruction(ctx); - break; - } -} - -/* - * - * Decode MXU pool02 - * - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+-----+-------+-------+-------+-----------+ - * | SPECIAL2 |0 0 0 0 0|x x x| XRc | XRb | XRa |MXU__POOL02| - * +-----------+---------+-----+-------+-------+-------+-----------+ - * - */ -static void decode_opc_mxu__pool02(CPUMIPSState *env, DisasContext *ctx) -{ - uint32_t opcode =3D extract32(ctx->opcode, 18, 3); - - switch (opcode) { - case OPC_MXU_S32CPS: - /* TODO: Implement emulation of S32CPS instruction. */ - MIPS_INVAL("OPC_MXU_S32CPS"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_D16CPS: - /* TODO: Implement emulation of D16CPS instruction. */ - MIPS_INVAL("OPC_MXU_D16CPS"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_Q8ABD: - /* TODO: Implement emulation of Q8ABD instruction. */ - MIPS_INVAL("OPC_MXU_Q8ABD"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_Q16SAT: - /* TODO: Implement emulation of Q16SAT instruction. */ - MIPS_INVAL("OPC_MXU_Q16SAT"); - gen_reserved_instruction(ctx); - break; - default: - MIPS_INVAL("decode_opc_mxu"); - gen_reserved_instruction(ctx); - break; - } -} - -/* - * - * Decode MXU pool03 - * - * D16MULF: - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---+---+-------+-------+-------+-------+-----------+ - * | SPECIAL2 |x x|on2|0 0 0 0| XRc | XRb | XRa |MXU__POOL03| - * +-----------+---+---+-------+-------+-------+-------+-----------+ - * - * D16MULE: - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---+---+-------+-------+-------+-------+-----------+ - * | SPECIAL2 |x x|on2| Xd | XRc | XRb | XRa |MXU__POOL03| - * +-----------+---+---+-------+-------+-------+-------+-----------+ - * - */ -static void decode_opc_mxu__pool03(CPUMIPSState *env, DisasContext *ctx) -{ - uint32_t opcode =3D extract32(ctx->opcode, 24, 2); - - switch (opcode) { - case OPC_MXU_D16MULF: - /* TODO: Implement emulation of D16MULF instruction. */ - MIPS_INVAL("OPC_MXU_D16MULF"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_D16MULE: - /* TODO: Implement emulation of D16MULE instruction. */ - MIPS_INVAL("OPC_MXU_D16MULE"); - gen_reserved_instruction(ctx); - break; - default: - MIPS_INVAL("decode_opc_mxu"); - gen_reserved_instruction(ctx); - break; - } -} - -/* - * - * Decode MXU pool04 - * - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+-+-------------------+-------+-----------+ - * | SPECIAL2 | rb |x| s12 | XRa |MXU__POOL04| - * +-----------+---------+-+-------------------+-------+-----------+ - * - */ static void decode_opc_mxu__pool04(CPUMIPSState *env, DisasContext *ctx) { uint32_t opcode =3D extract32(ctx->opcode, 20, 1); @@ -26176,455 +25734,14 @@ static void decode_opc_mxu__pool04(CPUMIPSState = *env, DisasContext *ctx) } } =20 -/* - * - * Decode MXU pool05 - * - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+-+-------------------+-------+-----------+ - * | SPECIAL2 | rb |x| s12 | XRa |MXU__POOL05| - * +-----------+---------+-+-------------------+-------+-----------+ - * - */ -static void decode_opc_mxu__pool05(CPUMIPSState *env, DisasContext *ctx) -{ - uint32_t opcode =3D extract32(ctx->opcode, 20, 1); - - switch (opcode) { - case OPC_MXU_S32STD: - /* TODO: Implement emulation of S32STD instruction. */ - MIPS_INVAL("OPC_MXU_S32STD"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_S32STDR: - /* TODO: Implement emulation of S32STDR instruction. */ - MIPS_INVAL("OPC_MXU_S32STDR"); - gen_reserved_instruction(ctx); - break; - default: - MIPS_INVAL("decode_opc_mxu"); - gen_reserved_instruction(ctx); - break; - } -} - -/* - * - * Decode MXU pool06 - * - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+---------+---+-------+-------+-----------+ - * | SPECIAL2 | rb | rc |st2|x x x x| XRa |MXU__POOL06| - * +-----------+---------+---------+---+-------+-------+-----------+ - * - */ -static void decode_opc_mxu__pool06(CPUMIPSState *env, DisasContext *ctx) -{ - uint32_t opcode =3D extract32(ctx->opcode, 10, 4); - - switch (opcode) { - case OPC_MXU_S32LDDV: - /* TODO: Implement emulation of S32LDDV instruction. */ - MIPS_INVAL("OPC_MXU_S32LDDV"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_S32LDDVR: - /* TODO: Implement emulation of S32LDDVR instruction. */ - MIPS_INVAL("OPC_MXU_S32LDDVR"); - gen_reserved_instruction(ctx); - break; - default: - MIPS_INVAL("decode_opc_mxu"); - gen_reserved_instruction(ctx); - break; - } -} - -/* - * - * Decode MXU pool07 - * - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+---------+---+-------+-------+-----------+ - * | SPECIAL2 | rb | rc |st2|x x x x| XRa |MXU__POOL07| - * +-----------+---------+---------+---+-------+-------+-----------+ - * - */ -static void decode_opc_mxu__pool07(CPUMIPSState *env, DisasContext *ctx) -{ - uint32_t opcode =3D extract32(ctx->opcode, 10, 4); - - switch (opcode) { - case OPC_MXU_S32STDV: - /* TODO: Implement emulation of S32TDV instruction. */ - MIPS_INVAL("OPC_MXU_S32TDV"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_S32STDVR: - /* TODO: Implement emulation of S32TDVR instruction. */ - MIPS_INVAL("OPC_MXU_S32TDVR"); - gen_reserved_instruction(ctx); - break; - default: - MIPS_INVAL("decode_opc_mxu"); - gen_reserved_instruction(ctx); - break; - } -} - -/* - * - * Decode MXU pool08 - * - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+-+-------------------+-------+-----------+ - * | SPECIAL2 | rb |x| s12 | XRa |MXU__POOL08| - * +-----------+---------+-+-------------------+-------+-----------+ - * - */ -static void decode_opc_mxu__pool08(CPUMIPSState *env, DisasContext *ctx) -{ - uint32_t opcode =3D extract32(ctx->opcode, 20, 1); - - switch (opcode) { - case OPC_MXU_S32LDI: - /* TODO: Implement emulation of S32LDI instruction. */ - MIPS_INVAL("OPC_MXU_S32LDI"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_S32LDIR: - /* TODO: Implement emulation of S32LDIR instruction. */ - MIPS_INVAL("OPC_MXU_S32LDIR"); - gen_reserved_instruction(ctx); - break; - default: - MIPS_INVAL("decode_opc_mxu"); - gen_reserved_instruction(ctx); - break; - } -} - -/* - * - * Decode MXU pool09 - * - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+-+-------------------+-------+-----------+ - * | SPECIAL2 | rb |x| s12 | XRa |MXU__POOL09| - * +-----------+---------+-+-------------------+-------+-----------+ - * - */ -static void decode_opc_mxu__pool09(CPUMIPSState *env, DisasContext *ctx) -{ - uint32_t opcode =3D extract32(ctx->opcode, 5, 0); - - switch (opcode) { - case OPC_MXU_S32SDI: - /* TODO: Implement emulation of S32SDI instruction. */ - MIPS_INVAL("OPC_MXU_S32SDI"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_S32SDIR: - /* TODO: Implement emulation of S32SDIR instruction. */ - MIPS_INVAL("OPC_MXU_S32SDIR"); - gen_reserved_instruction(ctx); - break; - default: - MIPS_INVAL("decode_opc_mxu"); - gen_reserved_instruction(ctx); - break; - } -} - -/* - * - * Decode MXU pool10 - * - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+---------+---+-------+-------+-----------+ - * | SPECIAL2 | rb | rc |st2|x x x x| XRa |MXU__POOL10| - * +-----------+---------+---------+---+-------+-------+-----------+ - * - */ -static void decode_opc_mxu__pool10(CPUMIPSState *env, DisasContext *ctx) -{ - uint32_t opcode =3D extract32(ctx->opcode, 5, 0); - - switch (opcode) { - case OPC_MXU_S32LDIV: - /* TODO: Implement emulation of S32LDIV instruction. */ - MIPS_INVAL("OPC_MXU_S32LDIV"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_S32LDIVR: - /* TODO: Implement emulation of S32LDIVR instruction. */ - MIPS_INVAL("OPC_MXU_S32LDIVR"); - gen_reserved_instruction(ctx); - break; - default: - MIPS_INVAL("decode_opc_mxu"); - gen_reserved_instruction(ctx); - break; - } -} - -/* - * - * Decode MXU pool11 - * - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+---------+---+-------+-------+-----------+ - * | SPECIAL2 | rb | rc |st2|x x x x| XRa |MXU__POOL11| - * +-----------+---------+---------+---+-------+-------+-----------+ - * - */ -static void decode_opc_mxu__pool11(CPUMIPSState *env, DisasContext *ctx) -{ - uint32_t opcode =3D extract32(ctx->opcode, 10, 4); - - switch (opcode) { - case OPC_MXU_S32SDIV: - /* TODO: Implement emulation of S32SDIV instruction. */ - MIPS_INVAL("OPC_MXU_S32SDIV"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_S32SDIVR: - /* TODO: Implement emulation of S32SDIVR instruction. */ - MIPS_INVAL("OPC_MXU_S32SDIVR"); - gen_reserved_instruction(ctx); - break; - default: - MIPS_INVAL("decode_opc_mxu"); - gen_reserved_instruction(ctx); - break; - } -} - -/* - * - * Decode MXU pool12 - * - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---+---+-------+-------+-------+-------+-----------+ - * | SPECIAL2 |an2|x x| Xd | XRc | XRb | XRa |MXU__POOL12| - * +-----------+---+---+-------+-------+-------+-------+-----------+ - * - */ -static void decode_opc_mxu__pool12(CPUMIPSState *env, DisasContext *ctx) -{ - uint32_t opcode =3D extract32(ctx->opcode, 22, 2); - - switch (opcode) { - case OPC_MXU_D32ACC: - /* TODO: Implement emulation of D32ACC instruction. */ - MIPS_INVAL("OPC_MXU_D32ACC"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_D32ACCM: - /* TODO: Implement emulation of D32ACCM instruction. */ - MIPS_INVAL("OPC_MXU_D32ACCM"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_D32ASUM: - /* TODO: Implement emulation of D32ASUM instruction. */ - MIPS_INVAL("OPC_MXU_D32ASUM"); - gen_reserved_instruction(ctx); - break; - default: - MIPS_INVAL("decode_opc_mxu"); - gen_reserved_instruction(ctx); - break; - } -} - -/* - * - * Decode MXU pool13 - * - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---+---+-------+-------+-------+-------+-----------+ - * | SPECIAL2 |en2|x x|0 0 0 0| XRc | XRb | XRa |MXU__POOL13| - * +-----------+---+---+-------+-------+-------+-------+-----------+ - * - */ -static void decode_opc_mxu__pool13(CPUMIPSState *env, DisasContext *ctx) -{ - uint32_t opcode =3D extract32(ctx->opcode, 22, 2); - - switch (opcode) { - case OPC_MXU_Q16ACC: - /* TODO: Implement emulation of Q16ACC instruction. */ - MIPS_INVAL("OPC_MXU_Q16ACC"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_Q16ACCM: - /* TODO: Implement emulation of Q16ACCM instruction. */ - MIPS_INVAL("OPC_MXU_Q16ACCM"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_Q16ASUM: - /* TODO: Implement emulation of Q16ASUM instruction. */ - MIPS_INVAL("OPC_MXU_Q16ASUM"); - gen_reserved_instruction(ctx); - break; - default: - MIPS_INVAL("decode_opc_mxu"); - gen_reserved_instruction(ctx); - break; - } -} - -/* - * - * Decode MXU pool14 - * - * Q8ADDE, Q8ACCE: - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---+---+-------+-------+-------+-------+-----------+ - * | SPECIAL2 |0 0|x x| XRd | XRc | XRb | XRa |MXU__POOL14| - * +-----------+---+---+-------+-------+-------+-------+-----------+ - * - * D8SUM, D8SUMC: - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---+---+-------+-------+-------+-------+-----------+ - * | SPECIAL2 |en2|x x|0 0 0 0| XRc | XRb | XRa |MXU__POOL14| - * +-----------+---+---+-------+-------+-------+-------+-----------+ - * - */ -static void decode_opc_mxu__pool14(CPUMIPSState *env, DisasContext *ctx) -{ - uint32_t opcode =3D extract32(ctx->opcode, 22, 2); - - switch (opcode) { - case OPC_MXU_Q8ADDE: - /* TODO: Implement emulation of Q8ADDE instruction. */ - MIPS_INVAL("OPC_MXU_Q8ADDE"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_D8SUM: - /* TODO: Implement emulation of D8SUM instruction. */ - MIPS_INVAL("OPC_MXU_D8SUM"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_D8SUMC: - /* TODO: Implement emulation of D8SUMC instruction. */ - MIPS_INVAL("OPC_MXU_D8SUMC"); - gen_reserved_instruction(ctx); - break; - default: - MIPS_INVAL("decode_opc_mxu"); - gen_reserved_instruction(ctx); - break; - } -} - -/* - * - * Decode MXU pool15 - * - * S32MUL, S32MULU, S32EXTRV: - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+---------+---+-------+-------+-----------+ - * | SPECIAL2 | rs | rt |x x| XRd | XRa |MXU__POOL15| - * +-----------+---------+---------+---+-------+-------+-----------+ - * - * S32EXTR: - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+---------+---+-------+-------+-----------+ - * | SPECIAL2 | rb | sft5 |x x| XRd | XRa |MXU__POOL15| - * +-----------+---------+---------+---+-------+-------+-----------+ - * - */ -static void decode_opc_mxu__pool15(CPUMIPSState *env, DisasContext *ctx) -{ - uint32_t opcode =3D extract32(ctx->opcode, 14, 2); - - switch (opcode) { - case OPC_MXU_S32MUL: - /* TODO: Implement emulation of S32MUL instruction. */ - MIPS_INVAL("OPC_MXU_S32MUL"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_S32MULU: - /* TODO: Implement emulation of S32MULU instruction. */ - MIPS_INVAL("OPC_MXU_S32MULU"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_S32EXTR: - /* TODO: Implement emulation of S32EXTR instruction. */ - MIPS_INVAL("OPC_MXU_S32EXTR"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_S32EXTRV: - /* TODO: Implement emulation of S32EXTRV instruction. */ - MIPS_INVAL("OPC_MXU_S32EXTRV"); - gen_reserved_instruction(ctx); - break; - default: - MIPS_INVAL("decode_opc_mxu"); - gen_reserved_instruction(ctx); - break; - } -} - -/* - * - * Decode MXU pool16 - * - * D32SARW: - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+-----+-------+-------+-------+-----------+ - * | SPECIAL2 | rb |x x x| XRc | XRb | XRa |MXU__POOL16| - * +-----------+---------+-----+-------+-------+-------+-----------+ - * - * S32ALN: - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+-----+-------+-------+-------+-----------+ - * | SPECIAL2 | rs |x x x| XRc | XRb | XRa |MXU__POOL16| - * +-----------+---------+-----+-------+-------+-------+-----------+ - * - * S32ALNI: - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+-----+---+-----+-------+-------+-------+-----------+ - * | SPECIAL2 | s3 |0 0|x x x| XRc | XRb | XRa |MXU__POOL16| - * +-----------+-----+---+-----+-------+-------+-------+-----------+ - * - * S32LUI: - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+-----+---+-----+-------+---------------+-----------+ - * | SPECIAL2 |optn3|0 0|x x x| XRc | s8 |MXU__POOL16| - * +-----------+-----+---+-----+-------+---------------+-----------+ - * - * S32NOR, S32AND, S32OR, S32XOR: - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+-----+-------+-------+-------+-----------+ - * | SPECIAL2 |0 0 0 0 0|x x x| XRc | XRb | XRa |MXU__POOL16| - * +-----------+---------+-----+-------+-------+-------+-----------+ - * - */ static void decode_opc_mxu__pool16(CPUMIPSState *env, DisasContext *ctx) { uint32_t opcode =3D extract32(ctx->opcode, 18, 3); =20 switch (opcode) { - case OPC_MXU_D32SARW: - /* TODO: Implement emulation of D32SARW instruction. */ - MIPS_INVAL("OPC_MXU_D32SARW"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_S32ALN: - /* TODO: Implement emulation of S32ALN instruction. */ - MIPS_INVAL("OPC_MXU_S32ALN"); - gen_reserved_instruction(ctx); - break; case OPC_MXU_S32ALNI: gen_mxu_S32ALNI(ctx); break; - case OPC_MXU_S32LUI: - /* TODO: Implement emulation of S32LUI instruction. */ - MIPS_INVAL("OPC_MXU_S32LUI"); - gen_reserved_instruction(ctx); - break; case OPC_MXU_S32NOR: gen_mxu_S32NOR(ctx); break; @@ -26644,114 +25761,6 @@ static void decode_opc_mxu__pool16(CPUMIPSState *= env, DisasContext *ctx) } } =20 -/* - * - * Decode MXU pool17 - * - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+---------+---+---------+-----+-----------+ - * | SPECIAL2 | rs | rt |0 0| rd |x x x|MXU__POOL15| - * +-----------+---------+---------+---+---------+-----+-----------+ - * - */ -static void decode_opc_mxu__pool17(CPUMIPSState *env, DisasContext *ctx) -{ - uint32_t opcode =3D extract32(ctx->opcode, 6, 2); - - switch (opcode) { - case OPC_MXU_LXW: - /* TODO: Implement emulation of LXW instruction. */ - MIPS_INVAL("OPC_MXU_LXW"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_LXH: - /* TODO: Implement emulation of LXH instruction. */ - MIPS_INVAL("OPC_MXU_LXH"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_LXHU: - /* TODO: Implement emulation of LXHU instruction. */ - MIPS_INVAL("OPC_MXU_LXHU"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_LXB: - /* TODO: Implement emulation of LXB instruction. */ - MIPS_INVAL("OPC_MXU_LXB"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_LXBU: - /* TODO: Implement emulation of LXBU instruction. */ - MIPS_INVAL("OPC_MXU_LXBU"); - gen_reserved_instruction(ctx); - break; - default: - MIPS_INVAL("decode_opc_mxu"); - gen_reserved_instruction(ctx); - break; - } -} -/* - * - * Decode MXU pool18 - * - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+-----+-------+-------+-------+-----------+ - * | SPECIAL2 | rb |x x x| XRd | XRa |0 0 0 0|MXU__POOL18| - * +-----------+---------+-----+-------+-------+-------+-----------+ - * - */ -static void decode_opc_mxu__pool18(CPUMIPSState *env, DisasContext *ctx) -{ - uint32_t opcode =3D extract32(ctx->opcode, 18, 3); - - switch (opcode) { - case OPC_MXU_D32SLLV: - /* TODO: Implement emulation of D32SLLV instruction. */ - MIPS_INVAL("OPC_MXU_D32SLLV"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_D32SLRV: - /* TODO: Implement emulation of D32SLRV instruction. */ - MIPS_INVAL("OPC_MXU_D32SLRV"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_D32SARV: - /* TODO: Implement emulation of D32SARV instruction. */ - MIPS_INVAL("OPC_MXU_D32SARV"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_Q16SLLV: - /* TODO: Implement emulation of Q16SLLV instruction. */ - MIPS_INVAL("OPC_MXU_Q16SLLV"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_Q16SLRV: - /* TODO: Implement emulation of Q16SLRV instruction. */ - MIPS_INVAL("OPC_MXU_Q16SLRV"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_Q16SARV: - /* TODO: Implement emulation of Q16SARV instruction. */ - MIPS_INVAL("OPC_MXU_Q16SARV"); - gen_reserved_instruction(ctx); - break; - default: - MIPS_INVAL("decode_opc_mxu"); - gen_reserved_instruction(ctx); - break; - } -} - -/* - * - * Decode MXU pool19 - * - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---+---+-------+-------+-------+-------+-----------+ - * | SPECIAL2 |0 0|x x| XRd | XRc | XRb | XRa |MXU__POOL19| - * +-----------+---+---+-------+-------+-------+-------+-----------+ - * - */ static void decode_opc_mxu__pool19(CPUMIPSState *env, DisasContext *ctx) { uint32_t opcode =3D extract32(ctx->opcode, 22, 2); @@ -26768,107 +25777,11 @@ static void decode_opc_mxu__pool19(CPUMIPSState = *env, DisasContext *ctx) } } =20 -/* - * - * Decode MXU pool20 - * - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+-----+-------+-------+-------+-----------+ - * | SPECIAL2 |0 0 0 0 0|x x x| XRc | XRb | XRa |MXU__POOL20| - * +-----------+---------+-----+-------+-------+-------+-----------+ - * - */ -static void decode_opc_mxu__pool20(CPUMIPSState *env, DisasContext *ctx) -{ - uint32_t opcode =3D extract32(ctx->opcode, 18, 3); - - switch (opcode) { - case OPC_MXU_Q8MOVZ: - /* TODO: Implement emulation of Q8MOVZ instruction. */ - MIPS_INVAL("OPC_MXU_Q8MOVZ"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_Q8MOVN: - /* TODO: Implement emulation of Q8MOVN instruction. */ - MIPS_INVAL("OPC_MXU_Q8MOVN"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_D16MOVZ: - /* TODO: Implement emulation of D16MOVZ instruction. */ - MIPS_INVAL("OPC_MXU_D16MOVZ"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_D16MOVN: - /* TODO: Implement emulation of D16MOVN instruction. */ - MIPS_INVAL("OPC_MXU_D16MOVN"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_S32MOVZ: - /* TODO: Implement emulation of S32MOVZ instruction. */ - MIPS_INVAL("OPC_MXU_S32MOVZ"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_S32MOVN: - /* TODO: Implement emulation of S32MOVN instruction. */ - MIPS_INVAL("OPC_MXU_S32MOVN"); - gen_reserved_instruction(ctx); - break; - default: - MIPS_INVAL("decode_opc_mxu"); - gen_reserved_instruction(ctx); - break; - } -} - -/* - * - * Decode MXU pool21 - * - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---+---+-------+-------+-------+-------+-----------+ - * | SPECIAL2 |an2|x x| XRd | XRc | XRb | XRa |MXU__POOL21| - * +-----------+---+---+-------+-------+-------+-------+-----------+ - * - */ -static void decode_opc_mxu__pool21(CPUMIPSState *env, DisasContext *ctx) -{ - uint32_t opcode =3D extract32(ctx->opcode, 22, 2); - - switch (opcode) { - case OPC_MXU_Q8MAC: - /* TODO: Implement emulation of Q8MAC instruction. */ - MIPS_INVAL("OPC_MXU_Q8MAC"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_Q8MACSU: - /* TODO: Implement emulation of Q8MACSU instruction. */ - MIPS_INVAL("OPC_MXU_Q8MACSU"); - gen_reserved_instruction(ctx); - break; - default: - MIPS_INVAL("decode_opc_mxu"); - gen_reserved_instruction(ctx); - break; - } -} - - /* * Main MXU decoding function - * - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------------------------------------+-----------+ - * | SPECIAL2 | |x x x x x x| - * +-----------+---------------------------------------+-----------+ - * */ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx) { - /* - * TODO: Investigate necessity of including handling of - * CLZ, CLO, SDBB in this function, as they belong to - * SPECIAL2 opcode space for regular pre-R6 MIPS ISAs. - */ uint32_t opcode =3D extract32(ctx->opcode, 0, 6); =20 if (opcode =3D=3D OPC__MXU_MUL) { @@ -26903,226 +25816,27 @@ static void decode_opc_mxu(CPUMIPSState *env, Di= sasContext *ctx) tcg_gen_brcondi_tl(TCG_COND_NE, t_mxu_cr, MXU_CR_MXU_EN, l_exit); =20 switch (opcode) { - case OPC_MXU_S32MADD: - /* TODO: Implement emulation of S32MADD instruction. */ - MIPS_INVAL("OPC_MXU_S32MADD"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_S32MADDU: - /* TODO: Implement emulation of S32MADDU instruction. */ - MIPS_INVAL("OPC_MXU_S32MADDU"); - gen_reserved_instruction(ctx); - break; case OPC_MXU__POOL00: decode_opc_mxu__pool00(env, ctx); break; - case OPC_MXU_S32MSUB: - /* TODO: Implement emulation of S32MSUB instruction. */ - MIPS_INVAL("OPC_MXU_S32MSUB"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_S32MSUBU: - /* TODO: Implement emulation of S32MSUBU instruction. */ - MIPS_INVAL("OPC_MXU_S32MSUBU"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU__POOL01: - decode_opc_mxu__pool01(env, ctx); - break; - case OPC_MXU__POOL02: - decode_opc_mxu__pool02(env, ctx); - break; case OPC_MXU_D16MUL: gen_mxu_d16mul(ctx); break; - case OPC_MXU__POOL03: - decode_opc_mxu__pool03(env, ctx); - break; case OPC_MXU_D16MAC: gen_mxu_d16mac(ctx); break; - case OPC_MXU_D16MACF: - /* TODO: Implement emulation of D16MACF instruction. */ - MIPS_INVAL("OPC_MXU_D16MACF"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_D16MADL: - /* TODO: Implement emulation of D16MADL instruction. */ - MIPS_INVAL("OPC_MXU_D16MADL"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_S16MAD: - /* TODO: Implement emulation of S16MAD instruction. */ - MIPS_INVAL("OPC_MXU_S16MAD"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_Q16ADD: - /* TODO: Implement emulation of Q16ADD instruction. */ - MIPS_INVAL("OPC_MXU_Q16ADD"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_D16MACE: - /* TODO: Implement emulation of D16MACE instruction. */ - MIPS_INVAL("OPC_MXU_D16MACE"); - gen_reserved_instruction(ctx); - break; case OPC_MXU__POOL04: decode_opc_mxu__pool04(env, ctx); break; - case OPC_MXU__POOL05: - decode_opc_mxu__pool05(env, ctx); - break; - case OPC_MXU__POOL06: - decode_opc_mxu__pool06(env, ctx); - break; - case OPC_MXU__POOL07: - decode_opc_mxu__pool07(env, ctx); - break; - case OPC_MXU__POOL08: - decode_opc_mxu__pool08(env, ctx); - break; - case OPC_MXU__POOL09: - decode_opc_mxu__pool09(env, ctx); - break; - case OPC_MXU__POOL10: - decode_opc_mxu__pool10(env, ctx); - break; - case OPC_MXU__POOL11: - decode_opc_mxu__pool11(env, ctx); - break; - case OPC_MXU_D32ADD: - /* TODO: Implement emulation of D32ADD instruction. */ - MIPS_INVAL("OPC_MXU_D32ADD"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU__POOL12: - decode_opc_mxu__pool12(env, ctx); - break; - case OPC_MXU__POOL13: - decode_opc_mxu__pool13(env, ctx); - break; - case OPC_MXU__POOL14: - decode_opc_mxu__pool14(env, ctx); - break; - case OPC_MXU_Q8ACCE: - /* TODO: Implement emulation of Q8ACCE instruction. */ - MIPS_INVAL("OPC_MXU_Q8ACCE"); - gen_reserved_instruction(ctx); - break; case OPC_MXU_S8LDD: gen_mxu_s8ldd(ctx); break; - case OPC_MXU_S8STD: - /* TODO: Implement emulation of S8STD instruction. */ - MIPS_INVAL("OPC_MXU_S8STD"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_S8LDI: - /* TODO: Implement emulation of S8LDI instruction. */ - MIPS_INVAL("OPC_MXU_S8LDI"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_S8SDI: - /* TODO: Implement emulation of S8SDI instruction. */ - MIPS_INVAL("OPC_MXU_S8SDI"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU__POOL15: - decode_opc_mxu__pool15(env, ctx); - break; case OPC_MXU__POOL16: decode_opc_mxu__pool16(env, ctx); break; - case OPC_MXU__POOL17: - decode_opc_mxu__pool17(env, ctx); - break; - case OPC_MXU_S16LDD: - /* TODO: Implement emulation of S16LDD instruction. */ - MIPS_INVAL("OPC_MXU_S16LDD"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_S16STD: - /* TODO: Implement emulation of S16STD instruction. */ - MIPS_INVAL("OPC_MXU_S16STD"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_S16LDI: - /* TODO: Implement emulation of S16LDI instruction. */ - MIPS_INVAL("OPC_MXU_S16LDI"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_S16SDI: - /* TODO: Implement emulation of S16SDI instruction. */ - MIPS_INVAL("OPC_MXU_S16SDI"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_D32SLL: - /* TODO: Implement emulation of D32SLL instruction. */ - MIPS_INVAL("OPC_MXU_D32SLL"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_D32SLR: - /* TODO: Implement emulation of D32SLR instruction. */ - MIPS_INVAL("OPC_MXU_D32SLR"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_D32SARL: - /* TODO: Implement emulation of D32SARL instruction. */ - MIPS_INVAL("OPC_MXU_D32SARL"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_D32SAR: - /* TODO: Implement emulation of D32SAR instruction. */ - MIPS_INVAL("OPC_MXU_D32SAR"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_Q16SLL: - /* TODO: Implement emulation of Q16SLL instruction. */ - MIPS_INVAL("OPC_MXU_Q16SLL"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_Q16SLR: - /* TODO: Implement emulation of Q16SLR instruction. */ - MIPS_INVAL("OPC_MXU_Q16SLR"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU__POOL18: - decode_opc_mxu__pool18(env, ctx); - break; - case OPC_MXU_Q16SAR: - /* TODO: Implement emulation of Q16SAR instruction. */ - MIPS_INVAL("OPC_MXU_Q16SAR"); - gen_reserved_instruction(ctx); - break; case OPC_MXU__POOL19: decode_opc_mxu__pool19(env, ctx); break; - case OPC_MXU__POOL20: - decode_opc_mxu__pool20(env, ctx); - break; - case OPC_MXU__POOL21: - decode_opc_mxu__pool21(env, ctx); - break; - case OPC_MXU_Q16SCOP: - /* TODO: Implement emulation of Q16SCOP instruction. */ - MIPS_INVAL("OPC_MXU_Q16SCOP"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_Q8MADL: - /* TODO: Implement emulation of Q8MADL instruction. */ - MIPS_INVAL("OPC_MXU_Q8MADL"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_S32SFL: - /* TODO: Implement emulation of S32SFL instruction. */ - MIPS_INVAL("OPC_MXU_S32SFL"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_Q8SAD: - /* TODO: Implement emulation of Q8SAD instruction. */ - MIPS_INVAL("OPC_MXU_Q8SAD"); - gen_reserved_instruction(ctx); - break; default: MIPS_INVAL("decode_opc_mxu"); gen_reserved_instruction(ctx); --=20 2.26.2 From nobody Sat May 18 21:45:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.49 as permitted sender) client-ip=209.85.221.49; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f49.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.49 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1615664963; cv=none; d=zohomail.com; s=zohoarc; b=OTCkDL5i1rNkwTe+cwKcC2BCvsax/nIjE2MjcN1VD3NvT4JtKnTTHm2woWMSX9glHwhgKsQLG9eIMsf/61n/HVAh6buRMUNiz9i30HxoBHaMGLheek2j5DsB4kQmHISX4VAjdL/j5HKFEfM5+hQEJpnirCu7BdaiVGO91X8tay4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615664963; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=7sfsMyoeWthmDEq+zoogz2A6903r3yzybeu6ACTL9Tk=; b=dGM9z/fNHAuFMfzv/sRP43KSmsdunD0TaK4YmGsa46dOsWkwUJxD1W0ISYDcz34/7cDhsOiAsly1mIapXGk+r/A3Jkuh1TE/ZC8CmNjIKHj/COuh5igsecVxHsFmIERUKChBPqxU5W4yO75w0eJ7NKClhipAmEvQhDRXqTjegfo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.49 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f49.google.com (mail-wr1-f49.google.com [209.85.221.49]) by mx.zohomail.com with SMTPS id 1615664963653499.17712311154594; Sat, 13 Mar 2021 11:49:23 -0800 (PST) Received: by mail-wr1-f49.google.com with SMTP id e9so3609416wrw.10 for ; Sat, 13 Mar 2021 11:49:23 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (17.red-88-21-201.staticip.rima-tde.net. [88.21.201.17]) by smtp.gmail.com with ESMTPSA id q15sm13223790wrr.58.2021.03.13.11.49.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Mar 2021 11:49:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7sfsMyoeWthmDEq+zoogz2A6903r3yzybeu6ACTL9Tk=; b=gEUeiU9sJAFrOHXHeiydkvdn00KXpr7lUxtndc4whQ8JHxknr7yAvnhgZJs89N5m84 6UFvodk4ZySVwR9z4MkyjRK2KT0S9K9mxt0/GyDiCmOE5asGLecX0piJ0C/LcjMx7+oy W/rtsSwB7awCK5oVix88pG6i+wbx89luHhKCEyLAB32w0afd7jBr6sA/yjLo+g7lPomx oy3V3Fhel/hsRtZKUkWhjRMHY30mq3QxZOVQNv9bsJtIarutgV8OiBHimng845CB3AZV 8Ku0Ve2+5Y+GI1W2+gSFNiZodqhfhiCEZMMw+rLgnipmcs4Vatri/sN83+iDNN+a59pB 4MMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=7sfsMyoeWthmDEq+zoogz2A6903r3yzybeu6ACTL9Tk=; b=iRWwfR6cNCJbHCukAbNGKM3UM1sBFUCcJY5n4h6KCBN+TFYB49mqpVGZ13prgRDwI7 y/Q3+P2FpZu0kQ1I2/ltJ8Sq4VxZOWBSqtQ9wn05ps9oS27bW7uuXHk4zys0wJTwVZDP MhRLoJP+ePVuzSthhTc/3q6PFTLXoyWB2cd6qLjAQEGzijxuO48g4zrxU8M7LSmgmxc4 fnH9eG2PeDxWICW5gr6Ap/la+Nlb6IU1QjZ6nxl0DHD2PSUg7I1hfsfxeEbwEs07EzOp ayCTDTKkx3AzyadqtsJuvty+RBJGC9L4OUHjgqAWXYVHePVdP4uqO25sF/glwqHAxu54 PrcQ== X-Gm-Message-State: AOAM5337Ms5rjbRHGfwJQ+l56sxEOHZMMHprf5+rAEQQMu+obp2hGASZ 9HUkmnFqHe8wg5wueXTFPg4= X-Google-Smtp-Source: ABdhPJxphDNCy+60QLr0KZMdjpxfsHb0veARUQLz812qKoewVpSp6gV53Npo0fTKHlDPm0u2j3DzdA== X-Received: by 2002:a5d:6b50:: with SMTP id x16mr4367193wrw.379.1615664961932; Sat, 13 Mar 2021 11:49:21 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 10/27] target/mips: Remove unused CPUMIPSState* from MXU functions Date: Sat, 13 Mar 2021 20:48:12 +0100 Message-Id: <20210313194829.2193621-11-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210313194829.2193621-1-f4bug@amsat.org> References: <20210313194829.2193621-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) None of these MXU functions use their CPUMIPSState* env argument, remove it. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/translate.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 2b9438eaff2..9c06a0df814 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -25694,7 +25694,7 @@ static void gen_mxu_S32ALNI(DisasContext *ctx) * =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D */ =20 -static void decode_opc_mxu__pool00(CPUMIPSState *env, DisasContext *ctx) +static void decode_opc_mxu__pool00(DisasContext *ctx) { uint32_t opcode =3D extract32(ctx->opcode, 18, 3); =20 @@ -25718,7 +25718,7 @@ static void decode_opc_mxu__pool00(CPUMIPSState *en= v, DisasContext *ctx) } } =20 -static void decode_opc_mxu__pool04(CPUMIPSState *env, DisasContext *ctx) +static void decode_opc_mxu__pool04(DisasContext *ctx) { uint32_t opcode =3D extract32(ctx->opcode, 20, 1); =20 @@ -25734,7 +25734,7 @@ static void decode_opc_mxu__pool04(CPUMIPSState *en= v, DisasContext *ctx) } } =20 -static void decode_opc_mxu__pool16(CPUMIPSState *env, DisasContext *ctx) +static void decode_opc_mxu__pool16(DisasContext *ctx) { uint32_t opcode =3D extract32(ctx->opcode, 18, 3); =20 @@ -25761,7 +25761,7 @@ static void decode_opc_mxu__pool16(CPUMIPSState *en= v, DisasContext *ctx) } } =20 -static void decode_opc_mxu__pool19(CPUMIPSState *env, DisasContext *ctx) +static void decode_opc_mxu__pool19(DisasContext *ctx) { uint32_t opcode =3D extract32(ctx->opcode, 22, 2); =20 @@ -25780,7 +25780,7 @@ static void decode_opc_mxu__pool19(CPUMIPSState *en= v, DisasContext *ctx) /* * Main MXU decoding function */ -static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx) +static void decode_opc_mxu(DisasContext *ctx) { uint32_t opcode =3D extract32(ctx->opcode, 0, 6); =20 @@ -25817,7 +25817,7 @@ static void decode_opc_mxu(CPUMIPSState *env, Disas= Context *ctx) =20 switch (opcode) { case OPC_MXU__POOL00: - decode_opc_mxu__pool00(env, ctx); + decode_opc_mxu__pool00(ctx); break; case OPC_MXU_D16MUL: gen_mxu_d16mul(ctx); @@ -25826,16 +25826,16 @@ static void decode_opc_mxu(CPUMIPSState *env, Dis= asContext *ctx) gen_mxu_d16mac(ctx); break; case OPC_MXU__POOL04: - decode_opc_mxu__pool04(env, ctx); + decode_opc_mxu__pool04(ctx); break; case OPC_MXU_S8LDD: gen_mxu_s8ldd(ctx); break; case OPC_MXU__POOL16: - decode_opc_mxu__pool16(env, ctx); + decode_opc_mxu__pool16(ctx); break; case OPC_MXU__POOL19: - decode_opc_mxu__pool19(env, ctx); + decode_opc_mxu__pool19(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); @@ -26995,7 +26995,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, Di= sasContext *ctx) #endif #if !defined(TARGET_MIPS64) if (ctx->insn_flags & ASE_MXU) { - decode_opc_mxu(env, ctx); + decode_opc_mxu(ctx); break; } #endif --=20 2.26.2 From nobody Sat May 18 21:45:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) client-ip=209.85.221.53; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f53.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1615664969; cv=none; d=zohomail.com; s=zohoarc; b=Fm0qE0WAwLphjyE8xYh0oMgberj4ZldqvgSxdzVuzFWnQwT0rPsodw7EETcKrUSCUd4eGiIoY64fTCMevR9yjG21pqE3gPEmkmso8SMyD+uOv5kNY9nJPQeZgifr/jBsb97uLLcZyvnHUpPPaqTKo0dioryNUTcg0dM+6Xkn3EM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615664969; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=jh52farOo7vXC67krWWYD5jALBg5ls6JEjcKoXwmteI=; b=i9aQTY7iw941YiydVkvgpoPucCc5UOn78omvnm4VZpNmjihtt41e8AOPy3a3e9E97X0MGkfuuVwjhgzhhrhnrOjRnbI9Zk0ro9u2cF42MYbbijPWneTQCsnwNGXi3xYXEhDfGlWtTqxjEVHgEM8M2CbolGqX0sq5MQ8NKdVL/R0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f53.google.com (mail-wr1-f53.google.com [209.85.221.53]) by mx.zohomail.com with SMTPS id 1615664969495261.48171486889066; Sat, 13 Mar 2021 11:49:29 -0800 (PST) Received: by mail-wr1-f53.google.com with SMTP id a18so6591048wrc.13 for ; Sat, 13 Mar 2021 11:49:27 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (17.red-88-21-201.staticip.rima-tde.net. [88.21.201.17]) by smtp.gmail.com with ESMTPSA id y18sm12911296wrq.61.2021.03.13.11.49.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Mar 2021 11:49:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jh52farOo7vXC67krWWYD5jALBg5ls6JEjcKoXwmteI=; b=WG0cyiHoYNv5aVEpSxlP4biXWUrdFxvh51PmWCeTd7EZ7+h+wDFkoCWfnwvDuBRTsa 00rOKm65CsECQOy3b9AvarYnqskKi2IX/drAJNddaiVNUUW0gShI181OLkkTr+heV0Ne XdqgHarRH9vAo+Q0WDheaa7LXdPCYisoYh+895KbbeOpGK8s8In1tTwxqennCPFExx5n x4JltAHStWh3ks4C3TBC9M+aaSGqreIpYewIgr/LxBQPRkqEGNQBhDEZsM5+5YOR+pFH l1h/dwaGsDAXQ5w6M3Odv1hq8HgdoSHLivCqkvdKZzDIwYlKayCDJs5quHCJ/gvWQ0VJ UQKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=jh52farOo7vXC67krWWYD5jALBg5ls6JEjcKoXwmteI=; b=PGtGt/iabWAgho42IrqnrcGoNUEU6WreS9EFyNgoLl8glU11SXEsN80/YZ+u/2FQDB BvBnotzHUFMu+BCZY1BZqHQ0tstiQqenJZM6bOsUZLDCsD27b//4e18imFwJfPcoFf2+ Fcaaj7IdjXHtgOEqLTRr4bwMvCOMBiyHsIeuhemaKKGmTiMfTw+UU0B28O11qge9AM7D uM+O91c2AeqrWoQtAx+if4P1NAd/g5zT8Uy/VpBOKTckpuRK5nSlgc1hhG7w8hx1ihLX mMaWr6j7X6jBW9uaxL5ZQkAljOEIHS0xwSErKtt/08QpiHgMif9NBLo/awhjNU7p2/H9 MsnA== X-Gm-Message-State: AOAM5323L8uEqyDtIfUejyCgjd8Ro/iX7FZ1LD2mORDwULrcTdunLdDR 4HL7v3WaaQ4EClE6Kdg1roI= X-Google-Smtp-Source: ABdhPJzD9UEEiK9GJE4qEYPKZW4vxL8gN+aondpgmxo8U8aDEJZ6z9+e+nElJRpXHQxBvcq9YAj8gg== X-Received: by 2002:adf:a2c7:: with SMTP id t7mr20288862wra.42.1615664966858; Sat, 13 Mar 2021 11:49:26 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 11/27] target/mips: Pass instruction opcode to decode_opc_mxu() Date: Sat, 13 Mar 2021 20:48:13 +0100 Message-Id: <20210313194829.2193621-12-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210313194829.2193621-1-f4bug@amsat.org> References: <20210313194829.2193621-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) In the next commit we'll make decode_opc_mxu() match decodetree prototype by returning a boolean. First pass ctx->opcode as an argument. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/translate.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 9c06a0df814..8ab0a96a340 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -25780,17 +25780,17 @@ static void decode_opc_mxu__pool19(DisasContext *= ctx) /* * Main MXU decoding function */ -static void decode_opc_mxu(DisasContext *ctx) +static void decode_opc_mxu(DisasContext *ctx, uint32_t insn) { - uint32_t opcode =3D extract32(ctx->opcode, 0, 6); + uint32_t opcode =3D extract32(insn, 0, 6); =20 if (opcode =3D=3D OPC__MXU_MUL) { uint32_t rs, rt, rd, op1; =20 - rs =3D extract32(ctx->opcode, 21, 5); - rt =3D extract32(ctx->opcode, 16, 5); - rd =3D extract32(ctx->opcode, 11, 5); - op1 =3D MASK_SPECIAL2(ctx->opcode); + rs =3D extract32(insn, 21, 5); + rt =3D extract32(insn, 16, 5); + rd =3D extract32(insn, 11, 5); + op1 =3D MASK_SPECIAL2(insn); =20 gen_arith(ctx, op1, rd, rs, rt); =20 @@ -26995,7 +26995,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, Di= sasContext *ctx) #endif #if !defined(TARGET_MIPS64) if (ctx->insn_flags & ASE_MXU) { - decode_opc_mxu(ctx); + decode_opc_mxu(ctx, ctx->opcode); break; } #endif --=20 2.26.2 From nobody Sat May 18 21:45:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.51 as permitted sender) client-ip=209.85.221.51; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f51.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.51 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1615664973; cv=none; d=zohomail.com; s=zohoarc; b=g9TxwjBWR0+AstYXlsYUh7pbRarEQnAgoc57LjkD0SRssmlEoCAYFq4vkZOE3FWrHoypqQngXN/EZfBKCHW5N99k6DT9QkHC9A7ZMxrVhCCLzRtLHAKIoXE2G4blZ0OdLydvcKmB05XyRIDPB21J1+MLT02FeD1689YBero3RZk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615664973; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=OaH7pKdhqoFCV1aTXDa0qp3I1qn/JzU2ueenlLqzFCY=; b=k3GZwIAobdHMS/P2TEMnr02aV3vLTF19/VywDhRhd2GilVQnDdWvf/sKLSE6nHY38S4+DVyaC4Rf0UebmnuqUVKjNX7sHg8AzEW9hPGS3K67JeJl/a1B5qcHbp90kaWrKqyxK7488cq/9T32IVYdaeiEDhMMxVJpIlaCbtwQIV0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.51 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f51.google.com (mail-wr1-f51.google.com [209.85.221.51]) by mx.zohomail.com with SMTPS id 1615664973403640.2033737571226; Sat, 13 Mar 2021 11:49:33 -0800 (PST) Received: by mail-wr1-f51.google.com with SMTP id w11so6591902wrr.10 for ; Sat, 13 Mar 2021 11:49:32 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (17.red-88-21-201.staticip.rima-tde.net. [88.21.201.17]) by smtp.gmail.com with ESMTPSA id a3sm12857254wrt.68.2021.03.13.11.49.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Mar 2021 11:49:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OaH7pKdhqoFCV1aTXDa0qp3I1qn/JzU2ueenlLqzFCY=; b=EJ1CUFRQlz4+J0g2ReOci1DtoJ1OWpsYHYcrZiKraacJmLLiCwos6xRn3evp8+07s2 pImiwaVrRdHchteDkqTg2LMm0wuPC2VVvoiTgtPfgDhDYWPQjthJNdY1bXHudpdpTuf6 03RB4SOsHClRtEnv2SteQCANbZYze/1WNngetxdu6wJA8AKzUveiOWIssg4UvKrw/961 FS/xtSNgGi+UkmjDpNooAVmTMO54u+6qTbnzmLsSXnI9xohRIV+HbQNTGtOa7pCJ2bIt tLECwdUQCZZelzVUCCti/9kRObATVNOzHER9GhdafvCPSWf/bKQZISindot5LDfvkMOC YAXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=OaH7pKdhqoFCV1aTXDa0qp3I1qn/JzU2ueenlLqzFCY=; b=MJrID2PXvRkfy2id0fNo1dooPJGI4G6NBxFamS9uK98q3ncjySIgf9DHiDzXxrd6AF NHP0ozkFHKhLUjoUWvMpTSTvKC+mJ670hLUGTSxu+0A7I16Ckw5ZNplgoxBrMF06fs70 I9Xt9mdGtEpMsFNabhAkv/nGDzw/ttEYhgeoIFxR/W7GQB187UZRo9gtUsPBNrzM97CP N3cEi8UxnnoacxQnnFeJbmq+lh6/ehALCXYRF/W7a0cUxa06BvWoP0J+yTUTxKl+Tvvi 2w8IWnNwliZrs5oeWZZqPJpSzMDvSxNGGeKmo6GkPnM+VZLYaKYcRtSrzZUJ1yeRYQ0H ZMtQ== X-Gm-Message-State: AOAM530xQBCEMhpg6RjKAKMEoquJcj8lc+Wm03/4f98zA58UzH1Yq/kp izALUVY2IJCHq3MzBe2Zauw= X-Google-Smtp-Source: ABdhPJxNiSCfuPPVqXdTaKvR+Tw42z2NUNFvwHgcjrXINBNTMVHKGFi4rkIjib/sGlr/SwNVOT2TIw== X-Received: by 2002:a5d:4286:: with SMTP id k6mr19692221wrq.278.1615664971757; Sat, 13 Mar 2021 11:49:31 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 12/27] target/mips: Use OPC_MUL instead of OPC__MXU_MUL Date: Sat, 13 Mar 2021 20:48:14 +0100 Message-Id: <20210313194829.2193621-13-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210313194829.2193621-1-f4bug@amsat.org> References: <20210313194829.2193621-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) We already have a macro and definition to extract / check the Special2 MUL opcode. Use it instead of the unnecessary OPC__MXU_MUL macro. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/translate.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 8ab0a96a340..ad09321de84 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1464,7 +1464,6 @@ enum { */ =20 enum { - OPC__MXU_MUL =3D 0x02, OPC_MXU__POOL00 =3D 0x03, OPC_MXU_D16MUL =3D 0x08, OPC_MXU_D16MAC =3D 0x0A, @@ -25784,7 +25783,7 @@ static void decode_opc_mxu(DisasContext *ctx, uint3= 2_t insn) { uint32_t opcode =3D extract32(insn, 0, 6); =20 - if (opcode =3D=3D OPC__MXU_MUL) { + if (MASK_SPECIAL2(insn) =3D=3D OPC_MUL) { uint32_t rs, rt, rd, op1; =20 rs =3D extract32(insn, 21, 5); --=20 2.26.2 From nobody Sat May 18 21:45:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.43 as permitted sender) client-ip=209.85.128.43; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f43.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.43 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1615664978; cv=none; d=zohomail.com; s=zohoarc; b=AsnIf9vHmp8l6MfvSkDgMBF2mASpOzs/7XOyJdlah/C1+jt0FftlkJ6YUSi66rd4Dxo4wSwxwPcaxEQJ+UDDXAxCtiCKYodVgQwJdTLwGDetOaE3/YPx/XkKaWm34vle5kQFGv0pGq4gU3sGHqSGBTa3hagq56Q8AvIofhTK3WE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615664978; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=4tbqQvnoVK3lZGspNq95Zwb17LCzzHK2/0Y4sp/YjBI=; b=HRU9c3xVzbNTnaGq1RXbs+L6fDS9K9k0HqpiSOuYECJn3GqtSP3Y66QQhZPYV24w4Y96VFbTluYMFPNUmF3kHGvCQFAcQxmsZA0s3CWoFtivXr8PCYpSaGAhYk7IdjYvRIXdLGB8EGkl+XnMDnTYX2HTh10Qud7lKnY+Ge/2fyU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.43 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) by mx.zohomail.com with SMTPS id 1615664978358104.78796779834352; Sat, 13 Mar 2021 11:49:38 -0800 (PST) Received: by mail-wm1-f43.google.com with SMTP id y124-20020a1c32820000b029010c93864955so17801012wmy.5 for ; Sat, 13 Mar 2021 11:49:37 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (17.red-88-21-201.staticip.rima-tde.net. [88.21.201.17]) by smtp.gmail.com with ESMTPSA id s8sm13823193wrn.97.2021.03.13.11.49.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Mar 2021 11:49:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4tbqQvnoVK3lZGspNq95Zwb17LCzzHK2/0Y4sp/YjBI=; b=HT/a0geU2rb7M0JmAJ/0nozYbNgVZxfxOWrJDO7rNvkRo2wXWReZ+1Jip5f29msVi4 2zLkyYNgDSe36wwVX2czaF2GGnsJExzcOvNWxPa0TGENq/hZQdCESzal3ci79IMN3fJM 0kwVcsH/5srYuOm7p01dEHkAv0Jvnsm4qc0sqJBwX1tHs43JxFxBlBsTwPnSu1q7A3c7 jwFs8di2ohvSdoacQ8qibMFMIxKt99pDfBvV9ZRQT+MNgZarJpbhMslzCEAiLRjDNok9 ITou/Op1AFYm/XSHlGNT5f31AMW0MjFhVBdpuAyrVzxbvy9sM2qcG7Xl4R0KGCgx4vGX dVmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=4tbqQvnoVK3lZGspNq95Zwb17LCzzHK2/0Y4sp/YjBI=; b=EeGTq5VTdrzeXmf73lwTFqGEuxkis5UGO13q+i6pz8lP9/3H6/BiasVwC1n8WEs4tw BLV3HZKodFWpU8/ePcCx4Zm7WunRyXOkLXNrgZWSb5v16q3gXQT5itWpuPVaYMAYdSBr 0+j62xaRndX1geaqlT88jtuzT34WQIczP/3cWAfDpYzaS4I/6v4QbIwFX5iJBeK/zytz r2MYXJSoJc1RSGGx4At6vX/Xj6QAWf3NrUeSU8NQlD/U+gUSB+7DTpq7kvNFhwJtw1+C 7BKy+d8TyoO+qaLbw3xBf5h9BDjkVdSxAuaoGIeEbg40IbQ3KNAffEuIHNQTCB1kg/hZ HWGw== X-Gm-Message-State: AOAM531t69+zIOvrqIIuTtkaTcFNjpAEGGTcrtUb3EZgxBjhoLLtfBly zyOd0jTY6Z3PuyPAkQDCgBs= X-Google-Smtp-Source: ABdhPJyQZUAas6RUOIB8vshTChzZdGoNqb1Gelo/lyEmtha9ucoN5lbZQ/MjXFkBsjF+RsnsIL+QXA== X-Received: by 2002:a05:600c:19ce:: with SMTP id u14mr18195273wmq.109.1615664976587; Sat, 13 Mar 2021 11:49:36 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 13/27] target/mips: Move MUL opcode check from decode_mxu() to decode_legacy() Date: Sat, 13 Mar 2021 20:48:15 +0100 Message-Id: <20210313194829.2193621-14-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210313194829.2193621-1-f4bug@amsat.org> References: <20210313194829.2193621-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Move the check for MUL opcode from decode_opc_mxu() callee to decode_opc_legacy() caller, so we can simplify the ifdef'ry and elide the call in few commits. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/translate.c | 19 +++++-------------- 1 file changed, 5 insertions(+), 14 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index ad09321de84..17cf608d0bd 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -25783,19 +25783,6 @@ static void decode_opc_mxu(DisasContext *ctx, uint= 32_t insn) { uint32_t opcode =3D extract32(insn, 0, 6); =20 - if (MASK_SPECIAL2(insn) =3D=3D OPC_MUL) { - uint32_t rs, rt, rd, op1; - - rs =3D extract32(insn, 21, 5); - rt =3D extract32(insn, 16, 5); - rd =3D extract32(insn, 11, 5); - op1 =3D MASK_SPECIAL2(insn); - - gen_arith(ctx, op1, rd, rs, rt); - - return; - } - if (opcode =3D=3D OPC_MXU_S32M2I) { gen_mxu_s32m2i(ctx); return; @@ -26994,7 +26981,11 @@ static bool decode_opc_legacy(CPUMIPSState *env, D= isasContext *ctx) #endif #if !defined(TARGET_MIPS64) if (ctx->insn_flags & ASE_MXU) { - decode_opc_mxu(ctx, ctx->opcode); + if (MASK_SPECIAL2(ctx->opcode) =3D=3D OPC_MUL) { + gen_arith(ctx, OPC_MUL, rd, rs, rt); + } else { + decode_opc_mxu(ctx, ctx->opcode); + } break; } #endif --=20 2.26.2 From nobody Sat May 18 21:45:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.52 as permitted sender) client-ip=209.85.221.52; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f52.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.52 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1615664983; cv=none; d=zohomail.com; s=zohoarc; b=n67ff9l/ZMrB3BVrC85aGYJiUG36GC8diEAsZPkAaBwX5QfAp0Ggn26IK3QhwtjNCRiqp8fi68ZbrC2VwYFLyC9vEooUx6za6bN2xjSw+yIZUiB80mZRuRfwBjKCh51FYijy4q2DGOVjbqJbdnEEEZaUtDTspu4A8IIEn59HuFU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615664983; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=b5JSmOY5tI24VF6HR0/6YEBu9VRNCCc/o2zwYA8b8zI=; b=ZQsizP9Eih+fWyb2WRrAZhGG+7S1X0/ZflwP2sfyzTqFtHu+yG9bxwVLelxj3gKqqjtB7QQfTuFPm2MY6lKJ/UBccekTTNRn/EjWEtEyrvYl1m6nVFvqtUtTV7Z7nhfR6878cLWCAcURu7EOwjhgNCikC4Tq+pnoliovvX/wi4E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.52 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f52.google.com (mail-wr1-f52.google.com [209.85.221.52]) by mx.zohomail.com with SMTPS id 1615664983519655.6814335131014; Sat, 13 Mar 2021 11:49:43 -0800 (PST) Received: by mail-wr1-f52.google.com with SMTP id 61so3611785wrm.12 for ; Sat, 13 Mar 2021 11:49:42 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (17.red-88-21-201.staticip.rima-tde.net. [88.21.201.17]) by smtp.gmail.com with ESMTPSA id s12sm7355839wmj.28.2021.03.13.11.49.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Mar 2021 11:49:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=b5JSmOY5tI24VF6HR0/6YEBu9VRNCCc/o2zwYA8b8zI=; b=o+Am7oaxBRaMTHeJqxAcZIEsYhJckbWVsQA6WX+PDWD0uGuov7AbolP3Xc/3sb9qld Qwuxtx3ovCaz4PrAoNmB3QcB9vWAvkXR0AE8zMGf28FBiV8/bYvsdmqS5Gw17rB8s0JK 9/uF5d13OpDRKiFaZt6OXBivKKfP+g7+0yDUGakAyGHGTk4dzi6fyezVX6yksMzO6S3f os4dsQnAO/L4lLPPEIZUoVdKm1KFXrGoF6La8N8IhmSa8M+2w0N+OWutZJy2t160mmI0 5TtevOa5nisET1MqcQ/ORCiZbwS+EpbGShiRzb/TJaoD2aPk08qtu4U0nkXWakxwq4lk eYRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=b5JSmOY5tI24VF6HR0/6YEBu9VRNCCc/o2zwYA8b8zI=; b=X55WC6+35oBZQ/1StkmAoMH0oIGQW28kq9DqPPbQh3wr3uiFciRK3kTExxS971b5We P724stT5vbRKDLbvjjYNZvpPLIN8XSV4nLI05UwSmGna4FecKJLCVLQppl52b7VpRfcx xCc5+T9aJveUxDEcxFTkH3biaH05iu0jHJc9B2WIpl4k5PUSaQdvc7B6t+wuYtiSeAPu DM2guTM1Kkn3eZ1mf1YCLLgVYjFaESzcdQWs33VPyY4MSI6eqL9nMYbThSNY1UipQFhV UitidLdI1NK04syixWsNzqLMpDmQYW6d5P2FaS0Kc2MdIPcVmQK0mQ45C/aOXbv73F/c oyeg== X-Gm-Message-State: AOAM533pAy7nKmWM3uhy5iUfYBbsGPTz+yGulwclFtTHAYTjg+S7RGVY wq+INPb0VGtBvT1STIKnQ9F0JLv6+qgLtg== X-Google-Smtp-Source: ABdhPJyX3bzAkhgm4xpFD08nCqIXMupgt7IeSPaCcvD5lsrvu/UlhG+qLy9uV5V5rIa/Y8Q2PcDkFQ== X-Received: by 2002:a05:6000:221:: with SMTP id l1mr19931613wrz.370.1615664981881; Sat, 13 Mar 2021 11:49:41 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 14/27] target/mips: Rename decode_opc_mxu() as decode_ase_mxu() Date: Sat, 13 Mar 2021 20:48:16 +0100 Message-Id: <20210313194829.2193621-15-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210313194829.2193621-1-f4bug@amsat.org> References: <20210313194829.2193621-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Use "decode_{isa,ase,ext}_$name()" function name pattern for public decodetree entrypoints. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 17cf608d0bd..5c1909f0ba4 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -25779,7 +25779,7 @@ static void decode_opc_mxu__pool19(DisasContext *ct= x) /* * Main MXU decoding function */ -static void decode_opc_mxu(DisasContext *ctx, uint32_t insn) +static void decode_ase_mxu(DisasContext *ctx, uint32_t insn) { uint32_t opcode =3D extract32(insn, 0, 6); =20 @@ -26984,7 +26984,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, Di= sasContext *ctx) if (MASK_SPECIAL2(ctx->opcode) =3D=3D OPC_MUL) { gen_arith(ctx, OPC_MUL, rd, rs, rt); } else { - decode_opc_mxu(ctx, ctx->opcode); + decode_ase_mxu(ctx, ctx->opcode); } break; } --=20 2.26.2 From nobody Sat May 18 21:45:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.52 as permitted sender) client-ip=209.85.221.52; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f52.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.52 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1615664988; cv=none; d=zohomail.com; s=zohoarc; b=D3xu5/wPVDgMwlc3MQE+eAEL3uD29PySMX2OC3P1AsnzEe8jYnGP24VwhjHyYxxMRbKNPjBVJyf8Fs0LQeZhPBJ5IxfIgBCJNwleWL6Dsker8ZTx40NsDYgwmWTcqyhAHH+OZjNoREupYac2jWHEgtNJvMSmZYq5XobmTMZ9MtU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615664988; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=E2Z0O0pMji5sPBGCo+tbE5Tls7XBWXUfioYeWCs//1A=; b=eSSaAcDYvqoTQ36qduT7F2GJADhx5Jnj1CWDsb1m73inEhuqyRz4Oeb5g1EYNdjHKethdl1otIcEA3+F6eqjnNqlH/fDRrzyvAVrXPjXP12SjY23FuwGwOzLLp7niJMg+BPSy1iunN9S2x8Vpjdnpb7xXEJa045m5CTf6zmcrFs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.52 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f52.google.com (mail-wr1-f52.google.com [209.85.221.52]) by mx.zohomail.com with SMTPS id 1615664988439184.34782088508996; Sat, 13 Mar 2021 11:49:48 -0800 (PST) Received: by mail-wr1-f52.google.com with SMTP id v15so6629287wrx.4 for ; Sat, 13 Mar 2021 11:49:47 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (17.red-88-21-201.staticip.rima-tde.net. [88.21.201.17]) by smtp.gmail.com with ESMTPSA id q19sm13924141wrg.80.2021.03.13.11.49.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Mar 2021 11:49:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=E2Z0O0pMji5sPBGCo+tbE5Tls7XBWXUfioYeWCs//1A=; b=R685hd6x/p1qzSK0VJiGHHCflDztVaqPf0jZrQHAb5sUCZ4vYsnb1PZ7Wp0+5z+MXT WvKUx5yK1z5v2FDePVhSiVYzYLoQeLAngq2D5YC87ZUj3wA+/dFooi62prSn8dO6fuhv i2Bz6Nr5WGyx7We8pcWxzGDoefHLGYwYc2s7MiFNle3XuaKBQ6O3QfDGJb9FWwHPJmEu FEYNiRKP/10UhEIbduw5nVM9+yrLROWGxVZtrtnUOCvLYJNhSQP7+fTxsNpmOeeLikKm /QLD0sRBeybRxuA3fBvRnAjsWxdPZ4kwbdPm9zf+e6Nj/KF+UXnclqp4MxbL4a53Wd+i ihIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=E2Z0O0pMji5sPBGCo+tbE5Tls7XBWXUfioYeWCs//1A=; b=h5pljDUenJ+zObM1YFK48wgxlibOyD2NK37w0UryfT0VIimmYBb9My5WSqySaN4KwC HwIKvHFTKht8z9sQMqb1CXbSrtIwWrGPh4uXvitGNpK3ZmPJZHHlLRhI2vwcbQo2rYaX q4sdcRC7mNTdTY5VUD8Hcu5Sf0In1ICI59xcV5VWK/QifBDuGid3/Vm+3A2TiJNrQoBi /SXqmr/UuWkXosd+Eu4ktFIWCCEYRyuHOETyhOgoNGaBIavcDRCw/2jmI7p7TYJa6wPL oHQTNY7G+F2Pz/fpdP6CH0l/2djy5Fc71bdj2yvef5phPXJoMCGB+ziCzt0mx7SsF+66 he6w== X-Gm-Message-State: AOAM533nCTfOJBZzg9L75Jogjb5Tq7h8WhHsAFxoO1nOIGWk39QGjZkB o3zITOCQiTKBvrEzu0W3+MM= X-Google-Smtp-Source: ABdhPJxtKtcWK7vbBO+SZV0W+2fma3rZ6WGCJNiax5MFC+8dumDQ8L7TIzHcUOxkLMS75u3xRPd8Gw== X-Received: by 2002:a05:6000:1ca:: with SMTP id t10mr20290464wrx.45.1615664986674; Sat, 13 Mar 2021 11:49:46 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 15/27] target/mips: Convert decode_ase_mxu() to decodetree prototype Date: Sat, 13 Mar 2021 20:48:17 +0100 Message-Id: <20210313194829.2193621-16-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210313194829.2193621-1-f4bug@amsat.org> References: <20210313194829.2193621-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) To easily convert MXU code to decodetree, making it return a boolean. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/translate.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 5c1909f0ba4..99269cd6691 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -25779,18 +25779,18 @@ static void decode_opc_mxu__pool19(DisasContext *= ctx) /* * Main MXU decoding function */ -static void decode_ase_mxu(DisasContext *ctx, uint32_t insn) +static bool decode_ase_mxu(DisasContext *ctx, uint32_t insn) { uint32_t opcode =3D extract32(insn, 0, 6); =20 if (opcode =3D=3D OPC_MXU_S32M2I) { gen_mxu_s32m2i(ctx); - return; + return true; } =20 if (opcode =3D=3D OPC_MXU_S32I2M) { gen_mxu_s32i2m(ctx); - return; + return true; } =20 { @@ -25831,6 +25831,8 @@ static void decode_ase_mxu(DisasContext *ctx, uint3= 2_t insn) gen_set_label(l_exit); tcg_temp_free(t_mxu_cr); } + + return true; } =20 #endif /* !defined(TARGET_MIPS64) */ --=20 2.26.2 From nobody Sat May 18 21:45:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.47 as permitted sender) client-ip=209.85.128.47; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f47.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.47 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1615664993; cv=none; d=zohomail.com; s=zohoarc; b=Mgf4v6Tsb5nA8SV5dt6NvyDq9fmNDvLXWOenwtrWeJA86BR3IO9LygktmF+4jKFXLcZkVCihHlt4LZU3f3r7l7Uhdbqf5WM/b5OsbRs3C+uUtZCbMBJWU4ua6S3eyGP8df4qL3bT5MVe2MrqxzLgVWOzNX20Wgh0JAnm/KlTnyI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615664993; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=BIVV/9uuQ0QDB8mjniywDP78vHWVrFUcutHKOjxeu00=; b=SK9CAxVvLY4MeczpgWwJQtwwRcC0vFqhwF7SUCzTwUtpggwZo2Laq4PKOffmCh17i18XYqWI1g9cB7tF8ZYNVkVrfiN20aPiCWDrrH7Fl1vFcYqXUE1o7HVBjz9h7tx50TI0cfiKQwIrV4tCAh7viMrsoMimfIKdaOw/0kXEIDQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.47 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) by mx.zohomail.com with SMTPS id 1615664993401451.36228982393493; Sat, 13 Mar 2021 11:49:53 -0800 (PST) Received: by mail-wm1-f47.google.com with SMTP id g8so5764797wmd.4 for ; Sat, 13 Mar 2021 11:49:52 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (17.red-88-21-201.staticip.rima-tde.net. [88.21.201.17]) by smtp.gmail.com with ESMTPSA id g5sm13252034wrq.30.2021.03.13.11.49.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Mar 2021 11:49:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BIVV/9uuQ0QDB8mjniywDP78vHWVrFUcutHKOjxeu00=; b=LCmvFkC5tfFJAC515wRtBmMaZqV0sswkiI3xzUpxRLBdUXaS/aiSvsdNEGm3ooPsCJ mZQISBglgfIKn94sw/o0JCEQFdjSqDMcXXDLs2BWv6L6ezbzOBrcwa/lf5Y2W79uxuI4 4PWtJ83CNAd6rlEeX89qcolTHMHX6gv52dRHWcI5qghSQjZgELvHsKiDhxo9fj4BSFWO ZjTQwt8Xps19SvT0DfWMBfurczDwur6Ygp1hX2mN96fB/rnxBNmlLhRYa8OSAlhe6Odg AFBBT+W0bnjAUHDuvb7U6cYOedXepRsK9c2ALIlu/EsGUppNbWHPK86exr4hDSUhbcWJ WZfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=BIVV/9uuQ0QDB8mjniywDP78vHWVrFUcutHKOjxeu00=; b=BFG1sxzsWmKb1C5NKSuJoLfbvnU9YKkCUSw7fcwTpMmPMF5XL3vkwY4ur2MZtBjt8z R3NTyqGEgcu9jQosRwUNgg+u8JtFdhw1avcGF/yFDp7LOiHKDGBMkNHOrYGIeTA+iPlS G7LWprdwfh9E272ko7Xd0Uvb3sVaQBKGoVRFMfS8HkZisxx26gEWGmEC1hokQyVerS/B hQlzpo0OOehpm/Lm3dLFp+itUtDDC98LnWCov3Ey7iFTLEprssGjbolxfBIc+8bqJeao uk3Ozh2LI24cf6Epv5HWLZMgrLE9AjG26Q5oiGlcWx68y6v36SHKD0wC04XAdpvovbJR ebsQ== X-Gm-Message-State: AOAM5321gZi2TJ8zxk3GU0eyaPBS6svH4I2JBNKO9NqtnEqM0iEI5Km3 yvgnZs/QjpUiFOiQkhGOF28= X-Google-Smtp-Source: ABdhPJxOGzliazRG960/8mmm9Bd9kFkUKDJkoAKRkSyE1ePh7TBU2XO6bZl/2PFy+33BHmfICs+hJw== X-Received: by 2002:a1c:cc08:: with SMTP id h8mr19170450wmb.188.1615664991693; Sat, 13 Mar 2021 11:49:51 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 16/27] target/mips: Simplify decode_opc_mxu() ifdef'ry Date: Sat, 13 Mar 2021 20:48:18 +0100 Message-Id: <20210313194829.2193621-17-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210313194829.2193621-1-f4bug@amsat.org> References: <20210313194829.2193621-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) By making the prototype public and checking 'TARGET_LONG_BITS =3D=3D 32' we let the compiler elide the decode_opc_mxu() call. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/translate.h | 3 +++ target/mips/translate.c | 6 ++---- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/target/mips/translate.h b/target/mips/translate.h index 468e29d7578..a5c49f1ee22 100644 --- a/target/mips/translate.h +++ b/target/mips/translate.h @@ -178,6 +178,9 @@ extern TCGv bcond; /* MSA */ void msa_translate_init(void); =20 +/* MXU */ +bool decode_ase_mxu(DisasContext *ctx, uint32_t insn); + /* decodetree generated */ bool decode_isa_rel6(DisasContext *ctx, uint32_t insn); bool decode_ase_msa(DisasContext *ctx, uint32_t insn); diff --git a/target/mips/translate.c b/target/mips/translate.c index 99269cd6691..2139109744f 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -25779,7 +25779,7 @@ static void decode_opc_mxu__pool19(DisasContext *ct= x) /* * Main MXU decoding function */ -static bool decode_ase_mxu(DisasContext *ctx, uint32_t insn) +bool decode_ase_mxu(DisasContext *ctx, uint32_t insn) { uint32_t opcode =3D extract32(insn, 0, 6); =20 @@ -26981,8 +26981,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, Di= sasContext *ctx) break; } #endif -#if !defined(TARGET_MIPS64) - if (ctx->insn_flags & ASE_MXU) { + if (TARGET_LONG_BITS =3D=3D 32 && (ctx->insn_flags & ASE_MXU)) { if (MASK_SPECIAL2(ctx->opcode) =3D=3D OPC_MUL) { gen_arith(ctx, OPC_MUL, rd, rs, rt); } else { @@ -26990,7 +26989,6 @@ static bool decode_opc_legacy(CPUMIPSState *env, Di= sasContext *ctx) } break; } -#endif decode_opc_special2_legacy(env, ctx); break; case OPC_SPECIAL3: --=20 2.26.2 From nobody Sat May 18 21:45:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) client-ip=209.85.221.53; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f53.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1615664998; cv=none; d=zohomail.com; s=zohoarc; b=WniRAtk4sH3QOikMEsPVIHqztEOSZiNVxYPhDpSVKifZyi1kCAHOtaWTjGbg7dqxoJCGF27RYQlgD5FMi4WLePIO0VHEVSTz350wXnQRXMO5GWQpYMxLNPxXomKwviV5bxLKZQasU2Da/LGdDjyR9HGV8UHWSQpTd2XLl/5Why4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615664998; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=E92VnqLwuF8/5Gj1qGvWBeROavRT6+04OcSXoUXN6bc=; b=ekKRbMzwR3IH53qwdtL9P9cZy78PDdSug/x2g0vhpLUZMrFGfNdfGk4m3tYOh/54kO02+eABADEOKKfj1FTOF6dWo3DQxZzF/SwSB0NYqsKFEjJoI2kF9H35R40H8amBAtnz6FZFwEtmZAfI4jenIqK1vSUelLRvTXss7M/2wiE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f53.google.com (mail-wr1-f53.google.com [209.85.221.53]) by mx.zohomail.com with SMTPS id 1615664998327904.2495905924328; Sat, 13 Mar 2021 11:49:58 -0800 (PST) Received: by mail-wr1-f53.google.com with SMTP id b9so3617795wrt.8 for ; Sat, 13 Mar 2021 11:49:57 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (17.red-88-21-201.staticip.rima-tde.net. [88.21.201.17]) by smtp.gmail.com with ESMTPSA id l9sm7030024wmq.2.2021.03.13.11.49.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Mar 2021 11:49:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=E92VnqLwuF8/5Gj1qGvWBeROavRT6+04OcSXoUXN6bc=; b=Mq6OYJEtS1fTrb1NxhNkapBm0jb85tzUOvWAE65fJr1rpPWaQf6gIxcfbWWDe84e56 swwwZvN8TRnUinci4GoBmNtOMWZy4iHFIypsNP8O4rzs3TvCjoWx/EYqN+F7bSHtbaNN QAYRcWVjd4EpxJ5mPZvkpXyDzqZmOb8H/lmvFQGEZCQSa/+VVtngn9L1s725IZV3NJtr IqOkZ17ddnHlsoJWGY7XhBsPTgRY888CIpaJtRoumhYJ2xqmrO9Q/MrJoH/T3a3wuPg5 fWiMhQWq4n77bV0/0FhsXuCaWve1cfe7GMDGvXTQZoy+9GqiXbCmdS7s1tCQdkIFGl3h t6bg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=E92VnqLwuF8/5Gj1qGvWBeROavRT6+04OcSXoUXN6bc=; b=kdkkq2BNAzNNYPCT3GJKAieglSFN8c3H2N6zNfM/uOSlNlPXfTfLZgMTbCB2xfURaw JLtIKtePnZbW4kSA/KSJoQN3O9U/0c424A+DkF1Mt5e+wHHXJrTe36zuRLQXAVViKOGH LHbI+jcD0UxDDLTUAHu4SDwKfu1+GqXQspNCDczC2MAVESWsPdJzAP6qjAr6cuosXqUG ok9cqxQ6VPgx2XNEgQY7Uc51j1SOtCdIpHoESnkPA2QtDrvHZs51EwwWUJSaAcZZYedk Jo3ma5O2zUPonQwIAybVblpDTmrqyevP1lFTHYpysPPtgwB2eohunFsooY2GVOZ2TZBS cnKA== X-Gm-Message-State: AOAM531oVBSZz6W8WN46fm4eE3smPVuE1s8DCR0A/P/U+foVR6VZ6FWe SJ8KHvIxRHFX6qtAp4+FNao= X-Google-Smtp-Source: ABdhPJzs5XunLyNb/OJSLmUXQC9l7Pb6jf6NC7iVSDE4AAiRTiqhhqpk0wzSh1rv7uagp3YxUz/YAA== X-Received: by 2002:a5d:6807:: with SMTP id w7mr19883830wru.103.1615664996641; Sat, 13 Mar 2021 11:49:56 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 17/27] target/mips: Introduce mxu_translate_init() helper Date: Sat, 13 Mar 2021 20:48:19 +0100 Message-Id: <20210313194829.2193621-18-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210313194829.2193621-1-f4bug@amsat.org> References: <20210313194829.2193621-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Extract the MXU register initialization code from mips_tcg_init() as a new mxu_translate_init() helper. Make it public and replace !TARGET_MIPS64 ifdef'ry by the 'TARGET_LONG_BITS =3D=3D 32' check to elide this code at preprocessing time. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/translate.h | 1 + target/mips/translate.c | 28 ++++++++++++++++------------ 2 files changed, 17 insertions(+), 12 deletions(-) diff --git a/target/mips/translate.h b/target/mips/translate.h index a5c49f1ee22..a807b3d2566 100644 --- a/target/mips/translate.h +++ b/target/mips/translate.h @@ -179,6 +179,7 @@ extern TCGv bcond; void msa_translate_init(void); =20 /* MXU */ +void mxu_translate_init(void); bool decode_ase_mxu(DisasContext *ctx, uint32_t insn); =20 /* decodetree generated */ diff --git a/target/mips/translate.c b/target/mips/translate.c index 2139109744f..a1a9a850085 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -2045,7 +2045,20 @@ static const char * const mxuregnames[] =3D { "XR1", "XR2", "XR3", "XR4", "XR5", "XR6", "XR7", "XR8", "XR9", "XR10", "XR11", "XR12", "XR13", "XR14", "XR15", "MXU_CR", }; -#endif + +void mxu_translate_init(void) +{ + for (unsigned i =3D 0; i < NUMBER_OF_MXU_REGISTERS - 1; i++) { + mxu_gpr[i] =3D tcg_global_mem_new(cpu_env, + offsetof(CPUMIPSState, active_tc.m= xu_gpr[i]), + mxuregnames[i]); + } + + mxu_CR =3D tcg_global_mem_new(cpu_env, + offsetof(CPUMIPSState, active_tc.mxu_cr), + mxuregnames[NUMBER_OF_MXU_REGISTERS - 1]); +} +#endif /* !TARGET_MIPS64 */ =20 /* General purpose registers moves. */ void gen_load_gpr(TCGv t, int reg) @@ -28047,18 +28060,9 @@ void mips_tcg_init(void) cpu_llval =3D tcg_global_mem_new(cpu_env, offsetof(CPUMIPSState, llval= ), "llval"); =20 -#if !defined(TARGET_MIPS64) - for (i =3D 0; i < NUMBER_OF_MXU_REGISTERS - 1; i++) { - mxu_gpr[i] =3D tcg_global_mem_new(cpu_env, - offsetof(CPUMIPSState, - active_tc.mxu_gpr[i]), - mxuregnames[i]); + if (TARGET_LONG_BITS =3D=3D 32) { + mxu_translate_init(); } - - mxu_CR =3D tcg_global_mem_new(cpu_env, - offsetof(CPUMIPSState, active_tc.mxu_cr), - mxuregnames[NUMBER_OF_MXU_REGISTERS - 1]); -#endif /* !TARGET_MIPS64 */ } =20 void restore_state_to_opc(CPUMIPSState *env, TranslationBlock *tb, --=20 2.26.2 From nobody Sat May 18 21:45:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.42 as permitted sender) client-ip=209.85.128.42; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f42.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.42 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1615665004; cv=none; d=zohomail.com; s=zohoarc; b=axQxwKdmwzWOgdCE8BoDvVYETwaKaoUVRv2pR7i6wS5sa88SC9I6kkJA6JA0HwxwnS4/eXznZpXPOT7qmyH8P1wBx0aJu0o5F3jK/wB4Xj6W+UlvTKNl08/jHkHtf/4yxSh28ZS6+XmPnklM/9fRyL4V4ILWpn/26g/4mV1juqw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615665004; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=mwVHnsKh24fRwrqLm2RB8FpYWM0m7y86Wl1VRaM4YsU=; b=PQlrSCWFfeXRhcNkjLH6eikFq0VDC16hBo6pWyyhp4lb9Qvha1kNBUTdyIgZTPR6JkCBs6RMEu/ekPTLYiad4obadE3Zn5TrjZWvLgB6oNOLY03I+mAtud6xZ7sWHotldqP4Nd+3d1lhWy5d7yLRABJ8CcEH9/ZQ3xqGWdEKsqg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.42 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) by mx.zohomail.com with SMTPS id 161566500488198.99491334840775; Sat, 13 Mar 2021 11:50:04 -0800 (PST) Received: by mail-wm1-f42.google.com with SMTP id u5-20020a7bcb050000b029010e9316b9d5so14164449wmj.2 for ; Sat, 13 Mar 2021 11:50:03 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (17.red-88-21-201.staticip.rima-tde.net. [88.21.201.17]) by smtp.gmail.com with ESMTPSA id e18sm366411wru.73.2021.03.13.11.50.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Mar 2021 11:50:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mwVHnsKh24fRwrqLm2RB8FpYWM0m7y86Wl1VRaM4YsU=; b=uBr6ATdAKXrTn1cgFlRCp/5HQ8WEMpZeWKX8m5+gJdY/TPFlDWcecXq1NQqE2OWNM8 H4LRnFxAKzW+PyFGm8c5TDB7WR6/hDdQCZirJGpPbAnpIZNmupreQDS/JO99ChmXenj9 JhlNPArzL6Aa3RpTcI41WWQmJ/jV7gCqMPc0Yk25mNO9BfpZr6/YETIeFEjSOPX3DKyn toIhny/ogfmGYabfJFpRzepaSPePgGY9XFYLCRD87idS0C4xGc52bQvq/oZjHuQ8Su3w gA9EaFjUXSFlc7XX93Ocm6sMv7h2frih+62tYyjQY6ieLwPzknORYK3F8yV7VRdAi95q FRRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=mwVHnsKh24fRwrqLm2RB8FpYWM0m7y86Wl1VRaM4YsU=; b=DLOJ3djbjcnymyHMfazXibrwq5XvkrofSjOVvrCuJ4JJAuwS8ZLw2y30VFmbxV389Z IWma0Eu+sUAlSMKRzhIZGVg7QhpNFQXoG61i0BDalvHEnGHDxGbxpwRedyvEGpEF49sU Fgdt1+0lOytKiikLbk3H0PfBCUoTzF8wIZmUH8LdnM5cCugssyCzQiPDWECXFCFu3zK8 J4Q6xBHWMuVBtigHRBfxDysjTK5sfRCWyzoG9606EvsDxWwQfrsbJLiuBqpJqJdcZmWf 0emsmram9fMtG7kkhZ6gYxtLgHRaJyU0vl3CI0JYGUDcLDDyPRWXUa8yQO4UFtrInsLx RlJw== X-Gm-Message-State: AOAM530A7erftKJFK0b84DjpfpeGFtdclKNf10x6zn3gfjd9S1FUiul4 R2hY0BSU4anYlLr2irgjXTM= X-Google-Smtp-Source: ABdhPJw9Nngd2DB01Lxg+xxHImSKdjBlIX994o/uhN4kp41tLIO6yjzIdJrlWbEOHQoOumNCyoZxCQ== X-Received: by 2002:a7b:c010:: with SMTP id c16mr19432638wmb.46.1615665002139; Sat, 13 Mar 2021 11:50:02 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 18/27] target/mips: Extract MXU code to new mxu_translate.c file Date: Sat, 13 Mar 2021 20:48:20 +0100 Message-Id: <20210313194829.2193621-19-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210313194829.2193621-1-f4bug@amsat.org> References: <20210313194829.2193621-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Extract 1600+ lines from the big translate.c into a new file. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/mxu_translate.c | 1609 +++++++++++++++++++++++++++++++++++ target/mips/translate.c | 1605 ---------------------------------- target/mips/meson.build | 4 + 3 files changed, 1613 insertions(+), 1605 deletions(-) create mode 100644 target/mips/mxu_translate.c diff --git a/target/mips/mxu_translate.c b/target/mips/mxu_translate.c new file mode 100644 index 00000000000..afc008eeeef --- /dev/null +++ b/target/mips/mxu_translate.c @@ -0,0 +1,1609 @@ +/* + * Ingenic XBurst Media eXtension Unit (MXU) translation routines. + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * Copyright (c) 2006 Marius Groeger (FPU operations) + * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support) + * Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support) + * Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support) + * + * SPDX-License-Identifier: LGPL-2.1-or-later + * + * Datasheet: + * + * "XBurst=C2=AE Instruction Set Architecture MIPS eXtension/enhanced Un= it + * Programming Manual", Ingenic Semiconductor Co, Ltd., revision June 2,= 2017 + */ + +#include "qemu/osdep.h" +#include "tcg/tcg-op.h" +#include "exec/helper-gen.h" +#include "translate.h" + +/* + * + * AN OVERVIEW OF MXU EXTENSION INSTRUCTION SET + * =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + * + * + * MXU (full name: MIPS eXtension/enhanced Unit) is a SIMD extension of MI= PS32 + * instructions set. It is designed to fit the needs of signal, graphical = and + * video processing applications. MXU instruction set is used in Xburst fa= mily + * of microprocessors by Ingenic. + * + * MXU unit contains 17 registers called X0-X16. X0 is always zero, and X1= 6 is + * the control register. + * + * + * The notation used in MXU assembler mnemonics + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + * + * Register operands: + * + * XRa, XRb, XRc, XRd - MXU registers + * Rb, Rc, Rd, Rs, Rt - general purpose MIPS registers + * + * Non-register operands: + * + * aptn1 - 1-bit accumulate add/subtract pattern + * aptn2 - 2-bit accumulate add/subtract pattern + * eptn2 - 2-bit execute add/subtract pattern + * optn2 - 2-bit operand pattern + * optn3 - 3-bit operand pattern + * sft4 - 4-bit shift amount + * strd2 - 2-bit stride amount + * + * Prefixes: + * + * Level of parallelism: Operand size: + * S - single operation at a time 32 - word + * D - two operations in parallel 16 - half word + * Q - four operations in parallel 8 - byte + * + * Operations: + * + * ADD - Add or subtract + * ADDC - Add with carry-in + * ACC - Accumulate + * ASUM - Sum together then accumulate (add or subtract) + * ASUMC - Sum together then accumulate (add or subtract) with carry-in + * AVG - Average between 2 operands + * ABD - Absolute difference + * ALN - Align data + * AND - Logical bitwise 'and' operation + * CPS - Copy sign + * EXTR - Extract bits + * I2M - Move from GPR register to MXU register + * LDD - Load data from memory to XRF + * LDI - Load data from memory to XRF (and increase the address base) + * LUI - Load unsigned immediate + * MUL - Multiply + * MULU - Unsigned multiply + * MADD - 64-bit operand add 32x32 product + * MSUB - 64-bit operand subtract 32x32 product + * MAC - Multiply and accumulate (add or subtract) + * MAD - Multiply and add or subtract + * MAX - Maximum between 2 operands + * MIN - Minimum between 2 operands + * M2I - Move from MXU register to GPR register + * MOVZ - Move if zero + * MOVN - Move if non-zero + * NOR - Logical bitwise 'nor' operation + * OR - Logical bitwise 'or' operation + * STD - Store data from XRF to memory + * SDI - Store data from XRF to memory (and increase the address base) + * SLT - Set of less than comparison + * SAD - Sum of absolute differences + * SLL - Logical shift left + * SLR - Logical shift right + * SAR - Arithmetic shift right + * SAT - Saturation + * SFL - Shuffle + * SCOP - Calculate x=E2=80=99s scope (-1, means x<0; 0, means x=3D=3D0= ; 1, means x>0) + * XOR - Logical bitwise 'exclusive or' operation + * + * Suffixes: + * + * E - Expand results + * F - Fixed point multiplication + * L - Low part result + * R - Doing rounding + * V - Variable instead of immediate + * W - Combine above L and V + * + * + * The list of MXU instructions grouped by functionality + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + * + * Load/Store instructions Multiplication instructions + * ----------------------- --------------------------- + * + * S32LDD XRa, Rb, s12 S32MADD XRa, XRd, Rs, Rt + * S32STD XRa, Rb, s12 S32MADDU XRa, XRd, Rs, Rt + * S32LDDV XRa, Rb, rc, strd2 S32MSUB XRa, XRd, Rs, Rt + * S32STDV XRa, Rb, rc, strd2 S32MSUBU XRa, XRd, Rs, Rt + * S32LDI XRa, Rb, s12 S32MUL XRa, XRd, Rs, Rt + * S32SDI XRa, Rb, s12 S32MULU XRa, XRd, Rs, Rt + * S32LDIV XRa, Rb, rc, strd2 D16MUL XRa, XRb, XRc, XRd, optn2 + * S32SDIV XRa, Rb, rc, strd2 D16MULE XRa, XRb, XRc, optn2 + * S32LDDR XRa, Rb, s12 D16MULF XRa, XRb, XRc, optn2 + * S32STDR XRa, Rb, s12 D16MAC XRa, XRb, XRc, XRd, aptn2, op= tn2 + * S32LDDVR XRa, Rb, rc, strd2 D16MACE XRa, XRb, XRc, XRd, aptn2, o= ptn2 + * S32STDVR XRa, Rb, rc, strd2 D16MACF XRa, XRb, XRc, XRd, aptn2, o= ptn2 + * S32LDIR XRa, Rb, s12 D16MADL XRa, XRb, XRc, XRd, aptn2, o= ptn2 + * S32SDIR XRa, Rb, s12 S16MAD XRa, XRb, XRc, XRd, aptn1, op= tn2 + * S32LDIVR XRa, Rb, rc, strd2 Q8MUL XRa, XRb, XRc, XRd + * S32SDIVR XRa, Rb, rc, strd2 Q8MULSU XRa, XRb, XRc, XRd + * S16LDD XRa, Rb, s10, eptn2 Q8MAC XRa, XRb, XRc, XRd, aptn2 + * S16STD XRa, Rb, s10, eptn2 Q8MACSU XRa, XRb, XRc, XRd, aptn2 + * S16LDI XRa, Rb, s10, eptn2 Q8MADL XRa, XRb, XRc, XRd, aptn2 + * S16SDI XRa, Rb, s10, eptn2 + * S8LDD XRa, Rb, s8, eptn3 + * S8STD XRa, Rb, s8, eptn3 Addition and subtraction instructions + * S8LDI XRa, Rb, s8, eptn3 ------------------------------------- + * S8SDI XRa, Rb, s8, eptn3 + * LXW Rd, Rs, Rt, strd2 D32ADD XRa, XRb, XRc, XRd, eptn2 + * LXH Rd, Rs, Rt, strd2 D32ADDC XRa, XRb, XRc, XRd + * LXHU Rd, Rs, Rt, strd2 D32ACC XRa, XRb, XRc, XRd, eptn2 + * LXB Rd, Rs, Rt, strd2 D32ACCM XRa, XRb, XRc, XRd, eptn2 + * LXBU Rd, Rs, Rt, strd2 D32ASUM XRa, XRb, XRc, XRd, eptn2 + * S32CPS XRa, XRb, XRc + * Q16ADD XRa, XRb, XRc, XRd, eptn2, op= tn2 + * Comparison instructions Q16ACC XRa, XRb, XRc, XRd, eptn2 + * ----------------------- Q16ACCM XRa, XRb, XRc, XRd, eptn2 + * D16ASUM XRa, XRb, XRc, XRd, eptn2 + * S32MAX XRa, XRb, XRc D16CPS XRa, XRb, + * S32MIN XRa, XRb, XRc D16AVG XRa, XRb, XRc + * S32SLT XRa, XRb, XRc D16AVGR XRa, XRb, XRc + * S32MOVZ XRa, XRb, XRc Q8ADD XRa, XRb, XRc, eptn2 + * S32MOVN XRa, XRb, XRc Q8ADDE XRa, XRb, XRc, XRd, eptn2 + * D16MAX XRa, XRb, XRc Q8ACCE XRa, XRb, XRc, XRd, eptn2 + * D16MIN XRa, XRb, XRc Q8ABD XRa, XRb, XRc + * D16SLT XRa, XRb, XRc Q8SAD XRa, XRb, XRc, XRd + * D16MOVZ XRa, XRb, XRc Q8AVG XRa, XRb, XRc + * D16MOVN XRa, XRb, XRc Q8AVGR XRa, XRb, XRc + * Q8MAX XRa, XRb, XRc D8SUM XRa, XRb, XRc, XRd + * Q8MIN XRa, XRb, XRc D8SUMC XRa, XRb, XRc, XRd + * Q8SLT XRa, XRb, XRc + * Q8SLTU XRa, XRb, XRc + * Q8MOVZ XRa, XRb, XRc Shift instructions + * Q8MOVN XRa, XRb, XRc ------------------ + * + * D32SLL XRa, XRb, XRc, XRd, sft4 + * Bitwise instructions D32SLR XRa, XRb, XRc, XRd, sft4 + * -------------------- D32SAR XRa, XRb, XRc, XRd, sft4 + * D32SARL XRa, XRb, XRc, sft4 + * S32NOR XRa, XRb, XRc D32SLLV XRa, XRb, Rb + * S32AND XRa, XRb, XRc D32SLRV XRa, XRb, Rb + * S32XOR XRa, XRb, XRc D32SARV XRa, XRb, Rb + * S32OR XRa, XRb, XRc D32SARW XRa, XRb, XRc, Rb + * Q16SLL XRa, XRb, XRc, XRd, sft4 + * Q16SLR XRa, XRb, XRc, XRd, sft4 + * Miscellaneous instructions Q16SAR XRa, XRb, XRc, XRd, sft4 + * ------------------------- Q16SLLV XRa, XRb, Rb + * Q16SLRV XRa, XRb, Rb + * S32SFL XRa, XRb, XRc, XRd, optn2 Q16SARV XRa, XRb, Rb + * S32ALN XRa, XRb, XRc, Rb + * S32ALNI XRa, XRb, XRc, s3 + * S32LUI XRa, s8, optn3 Move instructions + * S32EXTR XRa, XRb, Rb, bits5 ----------------- + * S32EXTRV XRa, XRb, Rs, Rt + * Q16SCOP XRa, XRb, XRc, XRd S32M2I XRa, Rb + * Q16SAT XRa, XRb, XRc S32I2M XRa, Rb + * + * + * The opcode organization of MXU instructions + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + * + * The bits 31..26 of all MXU instructions are equal to 0x1C (also referred + * as opcode SPECIAL2 in the base MIPS ISA). The organization and meaning = of + * other bits up to the instruction level is as follows: + * + * bits + * 05..00 + * + * =E2=94=8C=E2=94=80 000000 =E2=94=80 OPC_MXU_S32MADD + * =E2=94=9C=E2=94=80 000001 =E2=94=80 OPC_MXU_S32MADDU + * =E2=94=9C=E2=94=80 000010 =E2=94=80 (non-MXU = OPC_MUL) + * =E2=94=82 + * =E2=94=82 20..18 + * =E2=94=9C=E2=94=80 000011 =E2=94=80 OPC_MXU__POOL00 =E2=94=80= =E2=94=AC=E2=94=80 000 =E2=94=80 OPC_MXU_S32MAX + * =E2=94=82 =E2=94=9C=E2=94=80 001 = =E2=94=80 OPC_MXU_S32MIN + * =E2=94=82 =E2=94=9C=E2=94=80 010 = =E2=94=80 OPC_MXU_D16MAX + * =E2=94=82 =E2=94=9C=E2=94=80 011 = =E2=94=80 OPC_MXU_D16MIN + * =E2=94=82 =E2=94=9C=E2=94=80 100 = =E2=94=80 OPC_MXU_Q8MAX + * =E2=94=82 =E2=94=9C=E2=94=80 101 = =E2=94=80 OPC_MXU_Q8MIN + * =E2=94=82 =E2=94=9C=E2=94=80 110 = =E2=94=80 OPC_MXU_Q8SLT + * =E2=94=82 =E2=94=94=E2=94=80 111 = =E2=94=80 OPC_MXU_Q8SLTU + * =E2=94=9C=E2=94=80 000100 =E2=94=80 OPC_MXU_S32MSUB + * =E2=94=9C=E2=94=80 000101 =E2=94=80 OPC_MXU_S32MSUBU 20..18 + * =E2=94=9C=E2=94=80 000110 =E2=94=80 OPC_MXU__POOL01 =E2=94=80= =E2=94=AC=E2=94=80 000 =E2=94=80 OPC_MXU_S32SLT + * =E2=94=82 =E2=94=9C=E2=94=80 001 = =E2=94=80 OPC_MXU_D16SLT + * =E2=94=82 =E2=94=9C=E2=94=80 010 = =E2=94=80 OPC_MXU_D16AVG + * =E2=94=82 =E2=94=9C=E2=94=80 011 = =E2=94=80 OPC_MXU_D16AVGR + * =E2=94=82 =E2=94=9C=E2=94=80 100 = =E2=94=80 OPC_MXU_Q8AVG + * =E2=94=82 =E2=94=9C=E2=94=80 101 = =E2=94=80 OPC_MXU_Q8AVGR + * =E2=94=82 =E2=94=94=E2=94=80 111 = =E2=94=80 OPC_MXU_Q8ADD + * =E2=94=82 + * =E2=94=82 20..18 + * =E2=94=9C=E2=94=80 000111 =E2=94=80 OPC_MXU__POOL02 =E2=94=80= =E2=94=AC=E2=94=80 000 =E2=94=80 OPC_MXU_S32CPS + * =E2=94=82 =E2=94=9C=E2=94=80 010 = =E2=94=80 OPC_MXU_D16CPS + * =E2=94=82 =E2=94=9C=E2=94=80 100 = =E2=94=80 OPC_MXU_Q8ABD + * =E2=94=82 =E2=94=94=E2=94=80 110 = =E2=94=80 OPC_MXU_Q16SAT + * =E2=94=9C=E2=94=80 001000 =E2=94=80 OPC_MXU_D16MUL + * =E2=94=82 25..24 + * =E2=94=9C=E2=94=80 001001 =E2=94=80 OPC_MXU__POOL03 =E2=94=80= =E2=94=AC=E2=94=80 00 =E2=94=80 OPC_MXU_D16MULF + * =E2=94=82 =E2=94=94=E2=94=80 01 =E2= =94=80 OPC_MXU_D16MULE + * =E2=94=9C=E2=94=80 001010 =E2=94=80 OPC_MXU_D16MAC + * =E2=94=9C=E2=94=80 001011 =E2=94=80 OPC_MXU_D16MACF + * =E2=94=9C=E2=94=80 001100 =E2=94=80 OPC_MXU_D16MADL + * =E2=94=9C=E2=94=80 001101 =E2=94=80 OPC_MXU_S16MAD + * =E2=94=9C=E2=94=80 001110 =E2=94=80 OPC_MXU_Q16ADD + * =E2=94=9C=E2=94=80 001111 =E2=94=80 OPC_MXU_D16MACE 23 + * =E2=94=82 =E2=94=8C=E2=94=80 0 =E2= =94=80 OPC_MXU_S32LDD + * =E2=94=9C=E2=94=80 010000 =E2=94=80 OPC_MXU__POOL04 =E2=94=80= =E2=94=B4=E2=94=80 1 =E2=94=80 OPC_MXU_S32LDDR + * =E2=94=82 + * =E2=94=82 23 + * =E2=94=9C=E2=94=80 010001 =E2=94=80 OPC_MXU__POOL05 =E2=94=80= =E2=94=AC=E2=94=80 0 =E2=94=80 OPC_MXU_S32STD + * =E2=94=82 =E2=94=94=E2=94=80 1 =E2= =94=80 OPC_MXU_S32STDR + * =E2=94=82 + * =E2=94=82 13..10 + * =E2=94=9C=E2=94=80 010010 =E2=94=80 OPC_MXU__POOL06 =E2=94=80= =E2=94=AC=E2=94=80 0000 =E2=94=80 OPC_MXU_S32LDDV + * =E2=94=82 =E2=94=94=E2=94=80 0001 = =E2=94=80 OPC_MXU_S32LDDVR + * =E2=94=82 + * =E2=94=82 13..10 + * =E2=94=9C=E2=94=80 010011 =E2=94=80 OPC_MXU__POOL07 =E2=94=80= =E2=94=AC=E2=94=80 0000 =E2=94=80 OPC_MXU_S32STDV + * =E2=94=82 =E2=94=94=E2=94=80 0001 = =E2=94=80 OPC_MXU_S32STDVR + * =E2=94=82 + * =E2=94=82 23 + * =E2=94=9C=E2=94=80 010100 =E2=94=80 OPC_MXU__POOL08 =E2=94=80= =E2=94=AC=E2=94=80 0 =E2=94=80 OPC_MXU_S32LDI + * =E2=94=82 =E2=94=94=E2=94=80 1 =E2= =94=80 OPC_MXU_S32LDIR + * =E2=94=82 + * =E2=94=82 23 + * =E2=94=9C=E2=94=80 010101 =E2=94=80 OPC_MXU__POOL09 =E2=94=80= =E2=94=AC=E2=94=80 0 =E2=94=80 OPC_MXU_S32SDI + * =E2=94=82 =E2=94=94=E2=94=80 1 =E2= =94=80 OPC_MXU_S32SDIR + * =E2=94=82 + * =E2=94=82 13..10 + * =E2=94=9C=E2=94=80 010110 =E2=94=80 OPC_MXU__POOL10 =E2=94=80= =E2=94=AC=E2=94=80 0000 =E2=94=80 OPC_MXU_S32LDIV + * =E2=94=82 =E2=94=94=E2=94=80 0001 = =E2=94=80 OPC_MXU_S32LDIVR + * =E2=94=82 + * =E2=94=82 13..10 + * =E2=94=9C=E2=94=80 010111 =E2=94=80 OPC_MXU__POOL11 =E2=94=80= =E2=94=AC=E2=94=80 0000 =E2=94=80 OPC_MXU_S32SDIV + * =E2=94=82 =E2=94=94=E2=94=80 0001 = =E2=94=80 OPC_MXU_S32SDIVR + * =E2=94=9C=E2=94=80 011000 =E2=94=80 OPC_MXU_D32ADD + * =E2=94=82 23..22 + * MXU =E2=94=9C=E2=94=80 011001 =E2=94=80 OPC_MXU__POOL12 =E2=94=80= =E2=94=AC=E2=94=80 00 =E2=94=80 OPC_MXU_D32ACC + * opcodes =E2=94=80=E2=94=A4 =E2=94=9C=E2=94= =80 01 =E2=94=80 OPC_MXU_D32ACCM + * =E2=94=82 =E2=94=94=E2=94=80 10 =E2= =94=80 OPC_MXU_D32ASUM + * =E2=94=9C=E2=94=80 011010 =E2=94=80 + * =E2=94=82 23..22 + * =E2=94=9C=E2=94=80 011011 =E2=94=80 OPC_MXU__POOL13 =E2=94=80= =E2=94=AC=E2=94=80 00 =E2=94=80 OPC_MXU_Q16ACC + * =E2=94=82 =E2=94=9C=E2=94=80 01 =E2= =94=80 OPC_MXU_Q16ACCM + * =E2=94=82 =E2=94=94=E2=94=80 10 =E2= =94=80 OPC_MXU_Q16ASUM + * =E2=94=82 + * =E2=94=82 23..22 + * =E2=94=9C=E2=94=80 011100 =E2=94=80 OPC_MXU__POOL14 =E2=94=80= =E2=94=AC=E2=94=80 00 =E2=94=80 OPC_MXU_Q8ADDE + * =E2=94=82 =E2=94=9C=E2=94=80 01 =E2= =94=80 OPC_MXU_D8SUM + * =E2=94=9C=E2=94=80 011101 =E2=94=80 OPC_MXU_Q8ACCE =E2=94=94= =E2=94=80 10 =E2=94=80 OPC_MXU_D8SUMC + * =E2=94=9C=E2=94=80 011110 =E2=94=80 + * =E2=94=9C=E2=94=80 011111 =E2=94=80 + * =E2=94=9C=E2=94=80 100000 =E2=94=80 (overlaps= with CLZ) + * =E2=94=9C=E2=94=80 100001 =E2=94=80 (overlaps= with CLO) + * =E2=94=9C=E2=94=80 100010 =E2=94=80 OPC_MXU_S8LDD + * =E2=94=9C=E2=94=80 100011 =E2=94=80 OPC_MXU_S8STD 15..14 + * =E2=94=9C=E2=94=80 100100 =E2=94=80 OPC_MXU_S8LDI =E2=94=8C= =E2=94=80 00 =E2=94=80 OPC_MXU_S32MUL + * =E2=94=9C=E2=94=80 100101 =E2=94=80 OPC_MXU_S8SDI =E2=94=9C= =E2=94=80 00 =E2=94=80 OPC_MXU_S32MULU + * =E2=94=82 =E2=94=9C=E2=94=80 00 =E2= =94=80 OPC_MXU_S32EXTR + * =E2=94=9C=E2=94=80 100110 =E2=94=80 OPC_MXU__POOL15 =E2=94=80= =E2=94=B4=E2=94=80 00 =E2=94=80 OPC_MXU_S32EXTRV + * =E2=94=82 + * =E2=94=82 20..18 + * =E2=94=9C=E2=94=80 100111 =E2=94=80 OPC_MXU__POOL16 =E2=94=80= =E2=94=AC=E2=94=80 000 =E2=94=80 OPC_MXU_D32SARW + * =E2=94=82 =E2=94=9C=E2=94=80 001 = =E2=94=80 OPC_MXU_S32ALN + * =E2=94=82 =E2=94=9C=E2=94=80 010 = =E2=94=80 OPC_MXU_S32ALNI + * =E2=94=82 =E2=94=9C=E2=94=80 011 = =E2=94=80 OPC_MXU_S32LUI + * =E2=94=82 =E2=94=9C=E2=94=80 100 = =E2=94=80 OPC_MXU_S32NOR + * =E2=94=82 =E2=94=9C=E2=94=80 101 = =E2=94=80 OPC_MXU_S32AND + * =E2=94=82 =E2=94=9C=E2=94=80 110 = =E2=94=80 OPC_MXU_S32OR + * =E2=94=82 =E2=94=94=E2=94=80 111 = =E2=94=80 OPC_MXU_S32XOR + * =E2=94=82 + * =E2=94=82 7..5 + * =E2=94=9C=E2=94=80 101000 =E2=94=80 OPC_MXU__POOL17 =E2=94=80= =E2=94=AC=E2=94=80 000 =E2=94=80 OPC_MXU_LXB + * =E2=94=82 =E2=94=9C=E2=94=80 001 = =E2=94=80 OPC_MXU_LXH + * =E2=94=9C=E2=94=80 101001 =E2=94=80 =E2=94=9C= =E2=94=80 011 =E2=94=80 OPC_MXU_LXW + * =E2=94=9C=E2=94=80 101010 =E2=94=80 OPC_MXU_S16LDD =E2=94=9C= =E2=94=80 100 =E2=94=80 OPC_MXU_LXBU + * =E2=94=9C=E2=94=80 101011 =E2=94=80 OPC_MXU_S16STD =E2=94=94= =E2=94=80 101 =E2=94=80 OPC_MXU_LXHU + * =E2=94=9C=E2=94=80 101100 =E2=94=80 OPC_MXU_S16LDI + * =E2=94=9C=E2=94=80 101101 =E2=94=80 OPC_MXU_S16SDI + * =E2=94=9C=E2=94=80 101110 =E2=94=80 OPC_MXU_S32M2I + * =E2=94=9C=E2=94=80 101111 =E2=94=80 OPC_MXU_S32I2M + * =E2=94=9C=E2=94=80 110000 =E2=94=80 OPC_MXU_D32SLL + * =E2=94=9C=E2=94=80 110001 =E2=94=80 OPC_MXU_D32SLR 20..18 + * =E2=94=9C=E2=94=80 110010 =E2=94=80 OPC_MXU_D32SARL =E2=94=8C= =E2=94=80 000 =E2=94=80 OPC_MXU_D32SLLV + * =E2=94=9C=E2=94=80 110011 =E2=94=80 OPC_MXU_D32SAR =E2=94=9C= =E2=94=80 001 =E2=94=80 OPC_MXU_D32SLRV + * =E2=94=9C=E2=94=80 110100 =E2=94=80 OPC_MXU_Q16SLL =E2=94=9C= =E2=94=80 010 =E2=94=80 OPC_MXU_D32SARV + * =E2=94=9C=E2=94=80 110101 =E2=94=80 OPC_MXU_Q16SLR =E2=94=9C= =E2=94=80 011 =E2=94=80 OPC_MXU_Q16SLLV + * =E2=94=82 =E2=94=9C=E2=94=80 100 = =E2=94=80 OPC_MXU_Q16SLRV + * =E2=94=9C=E2=94=80 110110 =E2=94=80 OPC_MXU__POOL18 =E2=94=80= =E2=94=B4=E2=94=80 101 =E2=94=80 OPC_MXU_Q16SARV + * =E2=94=82 + * =E2=94=9C=E2=94=80 110111 =E2=94=80 OPC_MXU_Q16SAR + * =E2=94=82 23..22 + * =E2=94=9C=E2=94=80 111000 =E2=94=80 OPC_MXU__POOL19 =E2=94=80= =E2=94=AC=E2=94=80 00 =E2=94=80 OPC_MXU_Q8MUL + * =E2=94=82 =E2=94=94=E2=94=80 01 =E2= =94=80 OPC_MXU_Q8MULSU + * =E2=94=82 + * =E2=94=82 20..18 + * =E2=94=9C=E2=94=80 111001 =E2=94=80 OPC_MXU__POOL20 =E2=94=80= =E2=94=AC=E2=94=80 000 =E2=94=80 OPC_MXU_Q8MOVZ + * =E2=94=82 =E2=94=9C=E2=94=80 001 = =E2=94=80 OPC_MXU_Q8MOVN + * =E2=94=82 =E2=94=9C=E2=94=80 010 = =E2=94=80 OPC_MXU_D16MOVZ + * =E2=94=82 =E2=94=9C=E2=94=80 011 = =E2=94=80 OPC_MXU_D16MOVN + * =E2=94=82 =E2=94=9C=E2=94=80 100 = =E2=94=80 OPC_MXU_S32MOVZ + * =E2=94=82 =E2=94=94=E2=94=80 101 = =E2=94=80 OPC_MXU_S32MOVN + * =E2=94=82 + * =E2=94=82 23..22 + * =E2=94=9C=E2=94=80 111010 =E2=94=80 OPC_MXU__POOL21 =E2=94=80= =E2=94=AC=E2=94=80 00 =E2=94=80 OPC_MXU_Q8MAC + * =E2=94=82 =E2=94=94=E2=94=80 10 =E2= =94=80 OPC_MXU_Q8MACSU + * =E2=94=9C=E2=94=80 111011 =E2=94=80 OPC_MXU_Q16SCOP + * =E2=94=9C=E2=94=80 111100 =E2=94=80 OPC_MXU_Q8MADL + * =E2=94=9C=E2=94=80 111101 =E2=94=80 OPC_MXU_S32SFL + * =E2=94=9C=E2=94=80 111110 =E2=94=80 OPC_MXU_Q8SAD + * =E2=94=94=E2=94=80 111111 =E2=94=80 (overlaps= with SDBBP) + * + * + * Compiled after: + * + * "XBurst=C2=AE Instruction Set Architecture MIPS eXtension/enhanced Un= it + * Programming Manual", Ingenic Semiconductor Co, Ltd., revision June 2,= 2017 + */ + +enum { + OPC_MXU__POOL00 =3D 0x03, + OPC_MXU_D16MUL =3D 0x08, + OPC_MXU_D16MAC =3D 0x0A, + OPC_MXU__POOL04 =3D 0x10, + OPC_MXU_S8LDD =3D 0x22, + OPC_MXU__POOL16 =3D 0x27, + OPC_MXU_S32M2I =3D 0x2E, + OPC_MXU_S32I2M =3D 0x2F, + OPC_MXU__POOL19 =3D 0x38, +}; + + +/* + * MXU pool 00 + */ +enum { + OPC_MXU_S32MAX =3D 0x00, + OPC_MXU_S32MIN =3D 0x01, + OPC_MXU_D16MAX =3D 0x02, + OPC_MXU_D16MIN =3D 0x03, + OPC_MXU_Q8MAX =3D 0x04, + OPC_MXU_Q8MIN =3D 0x05, +}; + +/* + * MXU pool 04 + */ +enum { + OPC_MXU_S32LDD =3D 0x00, + OPC_MXU_S32LDDR =3D 0x01, +}; + +/* + * MXU pool 16 + */ +enum { + OPC_MXU_S32ALNI =3D 0x02, + OPC_MXU_S32NOR =3D 0x04, + OPC_MXU_S32AND =3D 0x05, + OPC_MXU_S32OR =3D 0x06, + OPC_MXU_S32XOR =3D 0x07, +}; + +/* + * MXU pool 19 + */ +enum { + OPC_MXU_Q8MUL =3D 0x00, + OPC_MXU_Q8MULSU =3D 0x01, +}; + +/* MXU accumulate add/subtract 1-bit pattern 'aptn1' */ +#define MXU_APTN1_A 0 +#define MXU_APTN1_S 1 + +/* MXU accumulate add/subtract 2-bit pattern 'aptn2' */ +#define MXU_APTN2_AA 0 +#define MXU_APTN2_AS 1 +#define MXU_APTN2_SA 2 +#define MXU_APTN2_SS 3 + +/* MXU execute add/subtract 2-bit pattern 'eptn2' */ +#define MXU_EPTN2_AA 0 +#define MXU_EPTN2_AS 1 +#define MXU_EPTN2_SA 2 +#define MXU_EPTN2_SS 3 + +/* MXU operand getting pattern 'optn2' */ +#define MXU_OPTN2_PTN0 0 +#define MXU_OPTN2_PTN1 1 +#define MXU_OPTN2_PTN2 2 +#define MXU_OPTN2_PTN3 3 +/* alternative naming scheme for 'optn2' */ +#define MXU_OPTN2_WW 0 +#define MXU_OPTN2_LW 1 +#define MXU_OPTN2_HW 2 +#define MXU_OPTN2_XW 3 + +/* MXU operand getting pattern 'optn3' */ +#define MXU_OPTN3_PTN0 0 +#define MXU_OPTN3_PTN1 1 +#define MXU_OPTN3_PTN2 2 +#define MXU_OPTN3_PTN3 3 +#define MXU_OPTN3_PTN4 4 +#define MXU_OPTN3_PTN5 5 +#define MXU_OPTN3_PTN6 6 +#define MXU_OPTN3_PTN7 7 + +/* MXU registers */ +static TCGv mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1]; +static TCGv mxu_CR; + +static const char * const mxuregnames[] =3D { + "XR1", "XR2", "XR3", "XR4", "XR5", "XR6", "XR7", "XR8", + "XR9", "XR10", "XR11", "XR12", "XR13", "XR14", "XR15", "MXU_CR", +}; + +void mxu_translate_init(void) +{ + for (unsigned i =3D 0; i < NUMBER_OF_MXU_REGISTERS - 1; i++) { + mxu_gpr[i] =3D tcg_global_mem_new(cpu_env, + offsetof(CPUMIPSState, active_tc.m= xu_gpr[i]), + mxuregnames[i]); + } + + mxu_CR =3D tcg_global_mem_new(cpu_env, + offsetof(CPUMIPSState, active_tc.mxu_cr), + mxuregnames[NUMBER_OF_MXU_REGISTERS - 1]); +} + +/* MXU General purpose registers moves. */ +static inline void gen_load_mxu_gpr(TCGv t, unsigned int reg) +{ + if (reg =3D=3D 0) { + tcg_gen_movi_tl(t, 0); + } else if (reg <=3D 15) { + tcg_gen_mov_tl(t, mxu_gpr[reg - 1]); + } +} + +static inline void gen_store_mxu_gpr(TCGv t, unsigned int reg) +{ + if (reg > 0 && reg <=3D 15) { + tcg_gen_mov_tl(mxu_gpr[reg - 1], t); + } +} + +/* MXU control register moves. */ +static inline void gen_load_mxu_cr(TCGv t) +{ + tcg_gen_mov_tl(t, mxu_CR); +} + +static inline void gen_store_mxu_cr(TCGv t) +{ + /* TODO: Add handling of RW rules for MXU_CR. */ + tcg_gen_mov_tl(mxu_CR, t); +} + +/* + * S32I2M XRa, rb - Register move from GRF to XRF + */ +static void gen_mxu_s32i2m(DisasContext *ctx) +{ + TCGv t0; + uint32_t XRa, Rb; + + t0 =3D tcg_temp_new(); + + XRa =3D extract32(ctx->opcode, 6, 5); + Rb =3D extract32(ctx->opcode, 16, 5); + + gen_load_gpr(t0, Rb); + if (XRa <=3D 15) { + gen_store_mxu_gpr(t0, XRa); + } else if (XRa =3D=3D 16) { + gen_store_mxu_cr(t0); + } + + tcg_temp_free(t0); +} + +/* + * S32M2I XRa, rb - Register move from XRF to GRF + */ +static void gen_mxu_s32m2i(DisasContext *ctx) +{ + TCGv t0; + uint32_t XRa, Rb; + + t0 =3D tcg_temp_new(); + + XRa =3D extract32(ctx->opcode, 6, 5); + Rb =3D extract32(ctx->opcode, 16, 5); + + if (XRa <=3D 15) { + gen_load_mxu_gpr(t0, XRa); + } else if (XRa =3D=3D 16) { + gen_load_mxu_cr(t0); + } + + gen_store_gpr(t0, Rb); + + tcg_temp_free(t0); +} + +/* + * S8LDD XRa, Rb, s8, optn3 - Load a byte from memory to XRF + */ +static void gen_mxu_s8ldd(DisasContext *ctx) +{ + TCGv t0, t1; + uint32_t XRa, Rb, s8, optn3; + + t0 =3D tcg_temp_new(); + t1 =3D tcg_temp_new(); + + XRa =3D extract32(ctx->opcode, 6, 4); + s8 =3D extract32(ctx->opcode, 10, 8); + optn3 =3D extract32(ctx->opcode, 18, 3); + Rb =3D extract32(ctx->opcode, 21, 5); + + gen_load_gpr(t0, Rb); + tcg_gen_addi_tl(t0, t0, (int8_t)s8); + + switch (optn3) { + /* XRa[7:0] =3D tmp8 */ + case MXU_OPTN3_PTN0: + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); + gen_load_mxu_gpr(t0, XRa); + tcg_gen_deposit_tl(t0, t0, t1, 0, 8); + break; + /* XRa[15:8] =3D tmp8 */ + case MXU_OPTN3_PTN1: + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); + gen_load_mxu_gpr(t0, XRa); + tcg_gen_deposit_tl(t0, t0, t1, 8, 8); + break; + /* XRa[23:16] =3D tmp8 */ + case MXU_OPTN3_PTN2: + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); + gen_load_mxu_gpr(t0, XRa); + tcg_gen_deposit_tl(t0, t0, t1, 16, 8); + break; + /* XRa[31:24] =3D tmp8 */ + case MXU_OPTN3_PTN3: + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); + gen_load_mxu_gpr(t0, XRa); + tcg_gen_deposit_tl(t0, t0, t1, 24, 8); + break; + /* XRa =3D {8'b0, tmp8, 8'b0, tmp8} */ + case MXU_OPTN3_PTN4: + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); + tcg_gen_deposit_tl(t0, t1, t1, 16, 16); + break; + /* XRa =3D {tmp8, 8'b0, tmp8, 8'b0} */ + case MXU_OPTN3_PTN5: + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); + tcg_gen_shli_tl(t1, t1, 8); + tcg_gen_deposit_tl(t0, t1, t1, 16, 16); + break; + /* XRa =3D {{8{sign of tmp8}}, tmp8, {8{sign of tmp8}}, tmp8} */ + case MXU_OPTN3_PTN6: + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_SB); + tcg_gen_mov_tl(t0, t1); + tcg_gen_andi_tl(t0, t0, 0xFF00FFFF); + tcg_gen_shli_tl(t1, t1, 16); + tcg_gen_or_tl(t0, t0, t1); + break; + /* XRa =3D {tmp8, tmp8, tmp8, tmp8} */ + case MXU_OPTN3_PTN7: + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); + tcg_gen_deposit_tl(t1, t1, t1, 8, 8); + tcg_gen_deposit_tl(t0, t1, t1, 16, 16); + break; + } + + gen_store_mxu_gpr(t0, XRa); + + tcg_temp_free(t0); + tcg_temp_free(t1); +} + +/* + * D16MUL XRa, XRb, XRc, XRd, optn2 - Signed 16 bit pattern multiplication + */ +static void gen_mxu_d16mul(DisasContext *ctx) +{ + TCGv t0, t1, t2, t3; + uint32_t XRa, XRb, XRc, XRd, optn2; + + t0 =3D tcg_temp_new(); + t1 =3D tcg_temp_new(); + t2 =3D tcg_temp_new(); + t3 =3D tcg_temp_new(); + + XRa =3D extract32(ctx->opcode, 6, 4); + XRb =3D extract32(ctx->opcode, 10, 4); + XRc =3D extract32(ctx->opcode, 14, 4); + XRd =3D extract32(ctx->opcode, 18, 4); + optn2 =3D extract32(ctx->opcode, 22, 2); + + gen_load_mxu_gpr(t1, XRb); + tcg_gen_sextract_tl(t0, t1, 0, 16); + tcg_gen_sextract_tl(t1, t1, 16, 16); + gen_load_mxu_gpr(t3, XRc); + tcg_gen_sextract_tl(t2, t3, 0, 16); + tcg_gen_sextract_tl(t3, t3, 16, 16); + + switch (optn2) { + case MXU_OPTN2_WW: /* XRB.H*XRC.H =3D=3D lop, XRB.L*XRC.L =3D=3D rop */ + tcg_gen_mul_tl(t3, t1, t3); + tcg_gen_mul_tl(t2, t0, t2); + break; + case MXU_OPTN2_LW: /* XRB.L*XRC.H =3D=3D lop, XRB.L*XRC.L =3D=3D rop */ + tcg_gen_mul_tl(t3, t0, t3); + tcg_gen_mul_tl(t2, t0, t2); + break; + case MXU_OPTN2_HW: /* XRB.H*XRC.H =3D=3D lop, XRB.H*XRC.L =3D=3D rop */ + tcg_gen_mul_tl(t3, t1, t3); + tcg_gen_mul_tl(t2, t1, t2); + break; + case MXU_OPTN2_XW: /* XRB.L*XRC.H =3D=3D lop, XRB.H*XRC.L =3D=3D rop */ + tcg_gen_mul_tl(t3, t0, t3); + tcg_gen_mul_tl(t2, t1, t2); + break; + } + gen_store_mxu_gpr(t3, XRa); + gen_store_mxu_gpr(t2, XRd); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(t2); + tcg_temp_free(t3); +} + +/* + * D16MAC XRa, XRb, XRc, XRd, aptn2, optn2 - Signed 16 bit pattern multiply + * and accumulate + */ +static void gen_mxu_d16mac(DisasContext *ctx) +{ + TCGv t0, t1, t2, t3; + uint32_t XRa, XRb, XRc, XRd, optn2, aptn2; + + t0 =3D tcg_temp_new(); + t1 =3D tcg_temp_new(); + t2 =3D tcg_temp_new(); + t3 =3D tcg_temp_new(); + + XRa =3D extract32(ctx->opcode, 6, 4); + XRb =3D extract32(ctx->opcode, 10, 4); + XRc =3D extract32(ctx->opcode, 14, 4); + XRd =3D extract32(ctx->opcode, 18, 4); + optn2 =3D extract32(ctx->opcode, 22, 2); + aptn2 =3D extract32(ctx->opcode, 24, 2); + + gen_load_mxu_gpr(t1, XRb); + tcg_gen_sextract_tl(t0, t1, 0, 16); + tcg_gen_sextract_tl(t1, t1, 16, 16); + + gen_load_mxu_gpr(t3, XRc); + tcg_gen_sextract_tl(t2, t3, 0, 16); + tcg_gen_sextract_tl(t3, t3, 16, 16); + + switch (optn2) { + case MXU_OPTN2_WW: /* XRB.H*XRC.H =3D=3D lop, XRB.L*XRC.L =3D=3D rop */ + tcg_gen_mul_tl(t3, t1, t3); + tcg_gen_mul_tl(t2, t0, t2); + break; + case MXU_OPTN2_LW: /* XRB.L*XRC.H =3D=3D lop, XRB.L*XRC.L =3D=3D rop */ + tcg_gen_mul_tl(t3, t0, t3); + tcg_gen_mul_tl(t2, t0, t2); + break; + case MXU_OPTN2_HW: /* XRB.H*XRC.H =3D=3D lop, XRB.H*XRC.L =3D=3D rop */ + tcg_gen_mul_tl(t3, t1, t3); + tcg_gen_mul_tl(t2, t1, t2); + break; + case MXU_OPTN2_XW: /* XRB.L*XRC.H =3D=3D lop, XRB.H*XRC.L =3D=3D rop */ + tcg_gen_mul_tl(t3, t0, t3); + tcg_gen_mul_tl(t2, t1, t2); + break; + } + gen_load_mxu_gpr(t0, XRa); + gen_load_mxu_gpr(t1, XRd); + + switch (aptn2) { + case MXU_APTN2_AA: + tcg_gen_add_tl(t3, t0, t3); + tcg_gen_add_tl(t2, t1, t2); + break; + case MXU_APTN2_AS: + tcg_gen_add_tl(t3, t0, t3); + tcg_gen_sub_tl(t2, t1, t2); + break; + case MXU_APTN2_SA: + tcg_gen_sub_tl(t3, t0, t3); + tcg_gen_add_tl(t2, t1, t2); + break; + case MXU_APTN2_SS: + tcg_gen_sub_tl(t3, t0, t3); + tcg_gen_sub_tl(t2, t1, t2); + break; + } + gen_store_mxu_gpr(t3, XRa); + gen_store_mxu_gpr(t2, XRd); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(t2); + tcg_temp_free(t3); +} + +/* + * Q8MUL XRa, XRb, XRc, XRd - Parallel unsigned 8 bit pattern multiply + * Q8MULSU XRa, XRb, XRc, XRd - Parallel signed 8 bit pattern multiply + */ +static void gen_mxu_q8mul_q8mulsu(DisasContext *ctx) +{ + TCGv t0, t1, t2, t3, t4, t5, t6, t7; + uint32_t XRa, XRb, XRc, XRd, sel; + + t0 =3D tcg_temp_new(); + t1 =3D tcg_temp_new(); + t2 =3D tcg_temp_new(); + t3 =3D tcg_temp_new(); + t4 =3D tcg_temp_new(); + t5 =3D tcg_temp_new(); + t6 =3D tcg_temp_new(); + t7 =3D tcg_temp_new(); + + XRa =3D extract32(ctx->opcode, 6, 4); + XRb =3D extract32(ctx->opcode, 10, 4); + XRc =3D extract32(ctx->opcode, 14, 4); + XRd =3D extract32(ctx->opcode, 18, 4); + sel =3D extract32(ctx->opcode, 22, 2); + + gen_load_mxu_gpr(t3, XRb); + gen_load_mxu_gpr(t7, XRc); + + if (sel =3D=3D 0x2) { + /* Q8MULSU */ + tcg_gen_ext8s_tl(t0, t3); + tcg_gen_shri_tl(t3, t3, 8); + tcg_gen_ext8s_tl(t1, t3); + tcg_gen_shri_tl(t3, t3, 8); + tcg_gen_ext8s_tl(t2, t3); + tcg_gen_shri_tl(t3, t3, 8); + tcg_gen_ext8s_tl(t3, t3); + } else { + /* Q8MUL */ + tcg_gen_ext8u_tl(t0, t3); + tcg_gen_shri_tl(t3, t3, 8); + tcg_gen_ext8u_tl(t1, t3); + tcg_gen_shri_tl(t3, t3, 8); + tcg_gen_ext8u_tl(t2, t3); + tcg_gen_shri_tl(t3, t3, 8); + tcg_gen_ext8u_tl(t3, t3); + } + + tcg_gen_ext8u_tl(t4, t7); + tcg_gen_shri_tl(t7, t7, 8); + tcg_gen_ext8u_tl(t5, t7); + tcg_gen_shri_tl(t7, t7, 8); + tcg_gen_ext8u_tl(t6, t7); + tcg_gen_shri_tl(t7, t7, 8); + tcg_gen_ext8u_tl(t7, t7); + + tcg_gen_mul_tl(t0, t0, t4); + tcg_gen_mul_tl(t1, t1, t5); + tcg_gen_mul_tl(t2, t2, t6); + tcg_gen_mul_tl(t3, t3, t7); + + tcg_gen_andi_tl(t0, t0, 0xFFFF); + tcg_gen_andi_tl(t1, t1, 0xFFFF); + tcg_gen_andi_tl(t2, t2, 0xFFFF); + tcg_gen_andi_tl(t3, t3, 0xFFFF); + + tcg_gen_shli_tl(t1, t1, 16); + tcg_gen_shli_tl(t3, t3, 16); + + tcg_gen_or_tl(t0, t0, t1); + tcg_gen_or_tl(t1, t2, t3); + + gen_store_mxu_gpr(t0, XRd); + gen_store_mxu_gpr(t1, XRa); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(t2); + tcg_temp_free(t3); + tcg_temp_free(t4); + tcg_temp_free(t5); + tcg_temp_free(t6); + tcg_temp_free(t7); +} + +/* + * S32LDD XRa, Rb, S12 - Load a word from memory to XRF + * S32LDDR XRa, Rb, S12 - Load a word from memory to XRF, reversed byte se= q. + */ +static void gen_mxu_s32ldd_s32lddr(DisasContext *ctx) +{ + TCGv t0, t1; + uint32_t XRa, Rb, s12, sel; + + t0 =3D tcg_temp_new(); + t1 =3D tcg_temp_new(); + + XRa =3D extract32(ctx->opcode, 6, 4); + s12 =3D extract32(ctx->opcode, 10, 10); + sel =3D extract32(ctx->opcode, 20, 1); + Rb =3D extract32(ctx->opcode, 21, 5); + + gen_load_gpr(t0, Rb); + + tcg_gen_movi_tl(t1, s12); + tcg_gen_shli_tl(t1, t1, 2); + if (s12 & 0x200) { + tcg_gen_ori_tl(t1, t1, 0xFFFFF000); + } + tcg_gen_add_tl(t1, t0, t1); + tcg_gen_qemu_ld_tl(t1, t1, ctx->mem_idx, MO_SL); + + if (sel =3D=3D 1) { + /* S32LDDR */ + tcg_gen_bswap32_tl(t1, t1); + } + gen_store_mxu_gpr(t1, XRa); + + tcg_temp_free(t0); + tcg_temp_free(t1); +} + + +/* + * MXU instruction category: logic + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + * + * S32NOR S32AND S32OR S32XOR + */ + +/* + * S32NOR XRa, XRb, XRc + * Update XRa with the result of logical bitwise 'nor' operation + * applied to the content of XRb and XRc. + */ +static void gen_mxu_S32NOR(DisasContext *ctx) +{ + uint32_t pad, XRc, XRb, XRa; + + pad =3D extract32(ctx->opcode, 21, 5); + XRc =3D extract32(ctx->opcode, 14, 4); + XRb =3D extract32(ctx->opcode, 10, 4); + XRa =3D extract32(ctx->opcode, 6, 4); + + if (unlikely(pad !=3D 0)) { + /* opcode padding incorrect -> do nothing */ + } else if (unlikely(XRa =3D=3D 0)) { + /* destination is zero register -> do nothing */ + } else if (unlikely((XRb =3D=3D 0) && (XRc =3D=3D 0))) { + /* both operands zero registers -> just set destination to all 1s = */ + tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0xFFFFFFFF); + } else if (unlikely(XRb =3D=3D 0)) { + /* XRb zero register -> just set destination to the negation of XR= c */ + tcg_gen_not_i32(mxu_gpr[XRa - 1], mxu_gpr[XRc - 1]); + } else if (unlikely(XRc =3D=3D 0)) { + /* XRa zero register -> just set destination to the negation of XR= b */ + tcg_gen_not_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); + } else if (unlikely(XRb =3D=3D XRc)) { + /* both operands same -> just set destination to the negation of X= Rb */ + tcg_gen_not_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); + } else { + /* the most general case */ + tcg_gen_nor_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], mxu_gpr[XRc - = 1]); + } +} + +/* + * S32AND XRa, XRb, XRc + * Update XRa with the result of logical bitwise 'and' operation + * applied to the content of XRb and XRc. + */ +static void gen_mxu_S32AND(DisasContext *ctx) +{ + uint32_t pad, XRc, XRb, XRa; + + pad =3D extract32(ctx->opcode, 21, 5); + XRc =3D extract32(ctx->opcode, 14, 4); + XRb =3D extract32(ctx->opcode, 10, 4); + XRa =3D extract32(ctx->opcode, 6, 4); + + if (unlikely(pad !=3D 0)) { + /* opcode padding incorrect -> do nothing */ + } else if (unlikely(XRa =3D=3D 0)) { + /* destination is zero register -> do nothing */ + } else if (unlikely((XRb =3D=3D 0) || (XRc =3D=3D 0))) { + /* one of operands zero register -> just set destination to all 0s= */ + tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); + } else if (unlikely(XRb =3D=3D XRc)) { + /* both operands same -> just set destination to one of them */ + tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); + } else { + /* the most general case */ + tcg_gen_and_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], mxu_gpr[XRc - = 1]); + } +} + +/* + * S32OR XRa, XRb, XRc + * Update XRa with the result of logical bitwise 'or' operation + * applied to the content of XRb and XRc. + */ +static void gen_mxu_S32OR(DisasContext *ctx) +{ + uint32_t pad, XRc, XRb, XRa; + + pad =3D extract32(ctx->opcode, 21, 5); + XRc =3D extract32(ctx->opcode, 14, 4); + XRb =3D extract32(ctx->opcode, 10, 4); + XRa =3D extract32(ctx->opcode, 6, 4); + + if (unlikely(pad !=3D 0)) { + /* opcode padding incorrect -> do nothing */ + } else if (unlikely(XRa =3D=3D 0)) { + /* destination is zero register -> do nothing */ + } else if (unlikely((XRb =3D=3D 0) && (XRc =3D=3D 0))) { + /* both operands zero registers -> just set destination to all 0s = */ + tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); + } else if (unlikely(XRb =3D=3D 0)) { + /* XRb zero register -> just set destination to the content of XRc= */ + tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRc - 1]); + } else if (unlikely(XRc =3D=3D 0)) { + /* XRc zero register -> just set destination to the content of XRb= */ + tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); + } else if (unlikely(XRb =3D=3D XRc)) { + /* both operands same -> just set destination to one of them */ + tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); + } else { + /* the most general case */ + tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], mxu_gpr[XRc - 1= ]); + } +} + +/* + * S32XOR XRa, XRb, XRc + * Update XRa with the result of logical bitwise 'xor' operation + * applied to the content of XRb and XRc. + */ +static void gen_mxu_S32XOR(DisasContext *ctx) +{ + uint32_t pad, XRc, XRb, XRa; + + pad =3D extract32(ctx->opcode, 21, 5); + XRc =3D extract32(ctx->opcode, 14, 4); + XRb =3D extract32(ctx->opcode, 10, 4); + XRa =3D extract32(ctx->opcode, 6, 4); + + if (unlikely(pad !=3D 0)) { + /* opcode padding incorrect -> do nothing */ + } else if (unlikely(XRa =3D=3D 0)) { + /* destination is zero register -> do nothing */ + } else if (unlikely((XRb =3D=3D 0) && (XRc =3D=3D 0))) { + /* both operands zero registers -> just set destination to all 0s = */ + tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); + } else if (unlikely(XRb =3D=3D 0)) { + /* XRb zero register -> just set destination to the content of XRc= */ + tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRc - 1]); + } else if (unlikely(XRc =3D=3D 0)) { + /* XRc zero register -> just set destination to the content of XRb= */ + tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); + } else if (unlikely(XRb =3D=3D XRc)) { + /* both operands same -> just set destination to all 0s */ + tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); + } else { + /* the most general case */ + tcg_gen_xor_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], mxu_gpr[XRc - = 1]); + } +} + + +/* + * MXU instruction category max/min + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + * + * S32MAX D16MAX Q8MAX + * S32MIN D16MIN Q8MIN + */ + +/* + * S32MAX XRa, XRb, XRc + * Update XRa with the maximum of signed 32-bit integers contained + * in XRb and XRc. + * + * S32MIN XRa, XRb, XRc + * Update XRa with the minimum of signed 32-bit integers contained + * in XRb and XRc. + */ +static void gen_mxu_S32MAX_S32MIN(DisasContext *ctx) +{ + uint32_t pad, opc, XRc, XRb, XRa; + + pad =3D extract32(ctx->opcode, 21, 5); + opc =3D extract32(ctx->opcode, 18, 3); + XRc =3D extract32(ctx->opcode, 14, 4); + XRb =3D extract32(ctx->opcode, 10, 4); + XRa =3D extract32(ctx->opcode, 6, 4); + + if (unlikely(pad !=3D 0)) { + /* opcode padding incorrect -> do nothing */ + } else if (unlikely(XRa =3D=3D 0)) { + /* destination is zero register -> do nothing */ + } else if (unlikely((XRb =3D=3D 0) && (XRc =3D=3D 0))) { + /* both operands zero registers -> just set destination to zero */ + tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); + } else if (unlikely((XRb =3D=3D 0) || (XRc =3D=3D 0))) { + /* exactly one operand is zero register - find which one is not...= */ + uint32_t XRx =3D XRb ? XRb : XRc; + /* ...and do max/min operation with one operand 0 */ + if (opc =3D=3D OPC_MXU_S32MAX) { + tcg_gen_smax_i32(mxu_gpr[XRa - 1], mxu_gpr[XRx - 1], 0); + } else { + tcg_gen_smin_i32(mxu_gpr[XRa - 1], mxu_gpr[XRx - 1], 0); + } + } else if (unlikely(XRb =3D=3D XRc)) { + /* both operands same -> just set destination to one of them */ + tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); + } else { + /* the most general case */ + if (opc =3D=3D OPC_MXU_S32MAX) { + tcg_gen_smax_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], + mxu_gpr[XRc - 1]); + } else { + tcg_gen_smin_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], + mxu_gpr[XRc - 1]); + } + } +} + +/* + * D16MAX + * Update XRa with the 16-bit-wise maximums of signed integers + * contained in XRb and XRc. + * + * D16MIN + * Update XRa with the 16-bit-wise minimums of signed integers + * contained in XRb and XRc. + */ +static void gen_mxu_D16MAX_D16MIN(DisasContext *ctx) +{ + uint32_t pad, opc, XRc, XRb, XRa; + + pad =3D extract32(ctx->opcode, 21, 5); + opc =3D extract32(ctx->opcode, 18, 3); + XRc =3D extract32(ctx->opcode, 14, 4); + XRb =3D extract32(ctx->opcode, 10, 4); + XRa =3D extract32(ctx->opcode, 6, 4); + + if (unlikely(pad !=3D 0)) { + /* opcode padding incorrect -> do nothing */ + } else if (unlikely(XRc =3D=3D 0)) { + /* destination is zero register -> do nothing */ + } else if (unlikely((XRb =3D=3D 0) && (XRa =3D=3D 0))) { + /* both operands zero registers -> just set destination to zero */ + tcg_gen_movi_i32(mxu_gpr[XRc - 1], 0); + } else if (unlikely((XRb =3D=3D 0) || (XRa =3D=3D 0))) { + /* exactly one operand is zero register - find which one is not...= */ + uint32_t XRx =3D XRb ? XRb : XRc; + /* ...and do half-word-wise max/min with one operand 0 */ + TCGv_i32 t0 =3D tcg_temp_new(); + TCGv_i32 t1 =3D tcg_const_i32(0); + + /* the left half-word first */ + tcg_gen_andi_i32(t0, mxu_gpr[XRx - 1], 0xFFFF0000); + if (opc =3D=3D OPC_MXU_D16MAX) { + tcg_gen_smax_i32(mxu_gpr[XRa - 1], t0, t1); + } else { + tcg_gen_smin_i32(mxu_gpr[XRa - 1], t0, t1); + } + + /* the right half-word */ + tcg_gen_andi_i32(t0, mxu_gpr[XRx - 1], 0x0000FFFF); + /* move half-words to the leftmost position */ + tcg_gen_shli_i32(t0, t0, 16); + /* t0 will be max/min of t0 and t1 */ + if (opc =3D=3D OPC_MXU_D16MAX) { + tcg_gen_smax_i32(t0, t0, t1); + } else { + tcg_gen_smin_i32(t0, t0, t1); + } + /* return resulting half-words to its original position */ + tcg_gen_shri_i32(t0, t0, 16); + /* finally update the destination */ + tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0); + + tcg_temp_free(t1); + tcg_temp_free(t0); + } else if (unlikely(XRb =3D=3D XRc)) { + /* both operands same -> just set destination to one of them */ + tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); + } else { + /* the most general case */ + TCGv_i32 t0 =3D tcg_temp_new(); + TCGv_i32 t1 =3D tcg_temp_new(); + + /* the left half-word first */ + tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0xFFFF0000); + tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0xFFFF0000); + if (opc =3D=3D OPC_MXU_D16MAX) { + tcg_gen_smax_i32(mxu_gpr[XRa - 1], t0, t1); + } else { + tcg_gen_smin_i32(mxu_gpr[XRa - 1], t0, t1); + } + + /* the right half-word */ + tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0x0000FFFF); + tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0x0000FFFF); + /* move half-words to the leftmost position */ + tcg_gen_shli_i32(t0, t0, 16); + tcg_gen_shli_i32(t1, t1, 16); + /* t0 will be max/min of t0 and t1 */ + if (opc =3D=3D OPC_MXU_D16MAX) { + tcg_gen_smax_i32(t0, t0, t1); + } else { + tcg_gen_smin_i32(t0, t0, t1); + } + /* return resulting half-words to its original position */ + tcg_gen_shri_i32(t0, t0, 16); + /* finally update the destination */ + tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0); + + tcg_temp_free(t1); + tcg_temp_free(t0); + } +} + +/* + * Q8MAX + * Update XRa with the 8-bit-wise maximums of signed integers + * contained in XRb and XRc. + * + * Q8MIN + * Update XRa with the 8-bit-wise minimums of signed integers + * contained in XRb and XRc. + */ +static void gen_mxu_Q8MAX_Q8MIN(DisasContext *ctx) +{ + uint32_t pad, opc, XRc, XRb, XRa; + + pad =3D extract32(ctx->opcode, 21, 5); + opc =3D extract32(ctx->opcode, 18, 3); + XRc =3D extract32(ctx->opcode, 14, 4); + XRb =3D extract32(ctx->opcode, 10, 4); + XRa =3D extract32(ctx->opcode, 6, 4); + + if (unlikely(pad !=3D 0)) { + /* opcode padding incorrect -> do nothing */ + } else if (unlikely(XRa =3D=3D 0)) { + /* destination is zero register -> do nothing */ + } else if (unlikely((XRb =3D=3D 0) && (XRc =3D=3D 0))) { + /* both operands zero registers -> just set destination to zero */ + tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); + } else if (unlikely((XRb =3D=3D 0) || (XRc =3D=3D 0))) { + /* exactly one operand is zero register - make it be the first...*/ + uint32_t XRx =3D XRb ? XRb : XRc; + /* ...and do byte-wise max/min with one operand 0 */ + TCGv_i32 t0 =3D tcg_temp_new(); + TCGv_i32 t1 =3D tcg_const_i32(0); + int32_t i; + + /* the leftmost byte (byte 3) first */ + tcg_gen_andi_i32(t0, mxu_gpr[XRx - 1], 0xFF000000); + if (opc =3D=3D OPC_MXU_Q8MAX) { + tcg_gen_smax_i32(mxu_gpr[XRa - 1], t0, t1); + } else { + tcg_gen_smin_i32(mxu_gpr[XRa - 1], t0, t1); + } + + /* bytes 2, 1, 0 */ + for (i =3D 2; i >=3D 0; i--) { + /* extract the byte */ + tcg_gen_andi_i32(t0, mxu_gpr[XRx - 1], 0xFF << (8 * i)); + /* move the byte to the leftmost position */ + tcg_gen_shli_i32(t0, t0, 8 * (3 - i)); + /* t0 will be max/min of t0 and t1 */ + if (opc =3D=3D OPC_MXU_Q8MAX) { + tcg_gen_smax_i32(t0, t0, t1); + } else { + tcg_gen_smin_i32(t0, t0, t1); + } + /* return resulting byte to its original position */ + tcg_gen_shri_i32(t0, t0, 8 * (3 - i)); + /* finally update the destination */ + tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0); + } + + tcg_temp_free(t1); + tcg_temp_free(t0); + } else if (unlikely(XRb =3D=3D XRc)) { + /* both operands same -> just set destination to one of them */ + tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); + } else { + /* the most general case */ + TCGv_i32 t0 =3D tcg_temp_new(); + TCGv_i32 t1 =3D tcg_temp_new(); + int32_t i; + + /* the leftmost bytes (bytes 3) first */ + tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0xFF000000); + tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0xFF000000); + if (opc =3D=3D OPC_MXU_Q8MAX) { + tcg_gen_smax_i32(mxu_gpr[XRa - 1], t0, t1); + } else { + tcg_gen_smin_i32(mxu_gpr[XRa - 1], t0, t1); + } + + /* bytes 2, 1, 0 */ + for (i =3D 2; i >=3D 0; i--) { + /* extract corresponding bytes */ + tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0xFF << (8 * i)); + tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0xFF << (8 * i)); + /* move the bytes to the leftmost position */ + tcg_gen_shli_i32(t0, t0, 8 * (3 - i)); + tcg_gen_shli_i32(t1, t1, 8 * (3 - i)); + /* t0 will be max/min of t0 and t1 */ + if (opc =3D=3D OPC_MXU_Q8MAX) { + tcg_gen_smax_i32(t0, t0, t1); + } else { + tcg_gen_smin_i32(t0, t0, t1); + } + /* return resulting byte to its original position */ + tcg_gen_shri_i32(t0, t0, 8 * (3 - i)); + /* finally update the destination */ + tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0); + } + + tcg_temp_free(t1); + tcg_temp_free(t0); + } +} + + +/* + * MXU instruction category: align + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + * + * S32ALN S32ALNI + */ + +/* + * S32ALNI XRc, XRb, XRa, optn3 + * Arrange bytes from XRb and XRc according to one of five sets of + * rules determined by optn3, and place the result in XRa. + */ +static void gen_mxu_S32ALNI(DisasContext *ctx) +{ + uint32_t optn3, pad, XRc, XRb, XRa; + + optn3 =3D extract32(ctx->opcode, 23, 3); + pad =3D extract32(ctx->opcode, 21, 2); + XRc =3D extract32(ctx->opcode, 14, 4); + XRb =3D extract32(ctx->opcode, 10, 4); + XRa =3D extract32(ctx->opcode, 6, 4); + + if (unlikely(pad !=3D 0)) { + /* opcode padding incorrect -> do nothing */ + } else if (unlikely(XRa =3D=3D 0)) { + /* destination is zero register -> do nothing */ + } else if (unlikely((XRb =3D=3D 0) && (XRc =3D=3D 0))) { + /* both operands zero registers -> just set destination to all 0s = */ + tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); + } else if (unlikely(XRb =3D=3D 0)) { + /* XRb zero register -> just appropriatelly shift XRc into XRa */ + switch (optn3) { + case MXU_OPTN3_PTN0: + tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); + break; + case MXU_OPTN3_PTN1: + case MXU_OPTN3_PTN2: + case MXU_OPTN3_PTN3: + tcg_gen_shri_i32(mxu_gpr[XRa - 1], mxu_gpr[XRc - 1], + 8 * (4 - optn3)); + break; + case MXU_OPTN3_PTN4: + tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRc - 1]); + break; + } + } else if (unlikely(XRc =3D=3D 0)) { + /* XRc zero register -> just appropriatelly shift XRb into XRa */ + switch (optn3) { + case MXU_OPTN3_PTN0: + tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); + break; + case MXU_OPTN3_PTN1: + case MXU_OPTN3_PTN2: + case MXU_OPTN3_PTN3: + tcg_gen_shri_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], 8 * optn3= ); + break; + case MXU_OPTN3_PTN4: + tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); + break; + } + } else if (unlikely(XRb =3D=3D XRc)) { + /* both operands same -> just rotation or moving from any of them = */ + switch (optn3) { + case MXU_OPTN3_PTN0: + case MXU_OPTN3_PTN4: + tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); + break; + case MXU_OPTN3_PTN1: + case MXU_OPTN3_PTN2: + case MXU_OPTN3_PTN3: + tcg_gen_rotli_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], 8 * optn= 3); + break; + } + } else { + /* the most general case */ + switch (optn3) { + case MXU_OPTN3_PTN0: + { + /* */ + /* XRb XRc */ + /* +---------------+ */ + /* | A B C D | E F G H */ + /* +-------+-------+ */ + /* | */ + /* XRa */ + /* */ + + tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); + } + break; + case MXU_OPTN3_PTN1: + { + /* */ + /* XRb XRc */ + /* +-------------------+ */ + /* A | B C D E | F G H */ + /* +---------+---------+ */ + /* | */ + /* XRa */ + /* */ + + TCGv_i32 t0 =3D tcg_temp_new(); + TCGv_i32 t1 =3D tcg_temp_new(); + + tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0x00FFFFFF); + tcg_gen_shli_i32(t0, t0, 8); + + tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0xFF000000); + tcg_gen_shri_i32(t1, t1, 24); + + tcg_gen_or_i32(mxu_gpr[XRa - 1], t0, t1); + + tcg_temp_free(t1); + tcg_temp_free(t0); + } + break; + case MXU_OPTN3_PTN2: + { + /* */ + /* XRb XRc */ + /* +-------------------+ */ + /* A B | C D E F | G H */ + /* +---------+---------+ */ + /* | */ + /* XRa */ + /* */ + + TCGv_i32 t0 =3D tcg_temp_new(); + TCGv_i32 t1 =3D tcg_temp_new(); + + tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0x0000FFFF); + tcg_gen_shli_i32(t0, t0, 16); + + tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0xFFFF0000); + tcg_gen_shri_i32(t1, t1, 16); + + tcg_gen_or_i32(mxu_gpr[XRa - 1], t0, t1); + + tcg_temp_free(t1); + tcg_temp_free(t0); + } + break; + case MXU_OPTN3_PTN3: + { + /* */ + /* XRb XRc */ + /* +-------------------+ */ + /* A B C | D E F G | H */ + /* +---------+---------+ */ + /* | */ + /* XRa */ + /* */ + + TCGv_i32 t0 =3D tcg_temp_new(); + TCGv_i32 t1 =3D tcg_temp_new(); + + tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0x000000FF); + tcg_gen_shli_i32(t0, t0, 24); + + tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0xFFFFFF00); + tcg_gen_shri_i32(t1, t1, 8); + + tcg_gen_or_i32(mxu_gpr[XRa - 1], t0, t1); + + tcg_temp_free(t1); + tcg_temp_free(t0); + } + break; + case MXU_OPTN3_PTN4: + { + /* */ + /* XRb XRc */ + /* +---------------+ */ + /* A B C D | E F G H | */ + /* +-------+-------+ */ + /* | */ + /* XRa */ + /* */ + + tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRc - 1]); + } + break; + } + } +} + + +/* + * Decoding engine for MXU + * =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + */ + +static void decode_opc_mxu__pool00(DisasContext *ctx) +{ + uint32_t opcode =3D extract32(ctx->opcode, 18, 3); + + switch (opcode) { + case OPC_MXU_S32MAX: + case OPC_MXU_S32MIN: + gen_mxu_S32MAX_S32MIN(ctx); + break; + case OPC_MXU_D16MAX: + case OPC_MXU_D16MIN: + gen_mxu_D16MAX_D16MIN(ctx); + break; + case OPC_MXU_Q8MAX: + case OPC_MXU_Q8MIN: + gen_mxu_Q8MAX_Q8MIN(ctx); + break; + default: + MIPS_INVAL("decode_opc_mxu"); + gen_reserved_instruction(ctx); + break; + } +} + +static void decode_opc_mxu__pool04(DisasContext *ctx) +{ + uint32_t opcode =3D extract32(ctx->opcode, 20, 1); + + switch (opcode) { + case OPC_MXU_S32LDD: + case OPC_MXU_S32LDDR: + gen_mxu_s32ldd_s32lddr(ctx); + break; + default: + MIPS_INVAL("decode_opc_mxu"); + gen_reserved_instruction(ctx); + break; + } +} + +static void decode_opc_mxu__pool16(DisasContext *ctx) +{ + uint32_t opcode =3D extract32(ctx->opcode, 18, 3); + + switch (opcode) { + case OPC_MXU_S32ALNI: + gen_mxu_S32ALNI(ctx); + break; + case OPC_MXU_S32NOR: + gen_mxu_S32NOR(ctx); + break; + case OPC_MXU_S32AND: + gen_mxu_S32AND(ctx); + break; + case OPC_MXU_S32OR: + gen_mxu_S32OR(ctx); + break; + case OPC_MXU_S32XOR: + gen_mxu_S32XOR(ctx); + break; + default: + MIPS_INVAL("decode_opc_mxu"); + gen_reserved_instruction(ctx); + break; + } +} + +static void decode_opc_mxu__pool19(DisasContext *ctx) +{ + uint32_t opcode =3D extract32(ctx->opcode, 22, 2); + + switch (opcode) { + case OPC_MXU_Q8MUL: + case OPC_MXU_Q8MULSU: + gen_mxu_q8mul_q8mulsu(ctx); + break; + default: + MIPS_INVAL("decode_opc_mxu"); + gen_reserved_instruction(ctx); + break; + } +} + +bool decode_ase_mxu(DisasContext *ctx, uint32_t insn) +{ + uint32_t opcode =3D extract32(insn, 0, 6); + + if (opcode =3D=3D OPC_MXU_S32M2I) { + gen_mxu_s32m2i(ctx); + return true; + } + + if (opcode =3D=3D OPC_MXU_S32I2M) { + gen_mxu_s32i2m(ctx); + return true; + } + + { + TCGv t_mxu_cr =3D tcg_temp_new(); + TCGLabel *l_exit =3D gen_new_label(); + + gen_load_mxu_cr(t_mxu_cr); + tcg_gen_andi_tl(t_mxu_cr, t_mxu_cr, MXU_CR_MXU_EN); + tcg_gen_brcondi_tl(TCG_COND_NE, t_mxu_cr, MXU_CR_MXU_EN, l_exit); + + switch (opcode) { + case OPC_MXU__POOL00: + decode_opc_mxu__pool00(ctx); + break; + case OPC_MXU_D16MUL: + gen_mxu_d16mul(ctx); + break; + case OPC_MXU_D16MAC: + gen_mxu_d16mac(ctx); + break; + case OPC_MXU__POOL04: + decode_opc_mxu__pool04(ctx); + break; + case OPC_MXU_S8LDD: + gen_mxu_s8ldd(ctx); + break; + case OPC_MXU__POOL16: + decode_opc_mxu__pool16(ctx); + break; + case OPC_MXU__POOL19: + decode_opc_mxu__pool19(ctx); + break; + default: + MIPS_INVAL("decode_opc_mxu"); + gen_reserved_instruction(ctx); + } + + gen_set_label(l_exit); + tcg_temp_free(t_mxu_cr); + } + + return true; +} diff --git a/target/mips/translate.c b/target/mips/translate.c index a1a9a850085..92dcd2a54be 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1129,392 +1129,6 @@ enum { OPC_NMSUB_PS =3D 0x3E | OPC_CP3, }; =20 -/* - * - * AN OVERVIEW OF MXU EXTENSION INSTRUCTION SET - * =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D - * - * - * MXU (full name: MIPS eXtension/enhanced Unit) is a SIMD extension of MI= PS32 - * instructions set. It is designed to fit the needs of signal, graphical = and - * video processing applications. MXU instruction set is used in Xburst fa= mily - * of microprocessors by Ingenic. - * - * MXU unit contains 17 registers called X0-X16. X0 is always zero, and X1= 6 is - * the control register. - * - * - * The notation used in MXU assembler mnemonics - * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - * - * Register operands: - * - * XRa, XRb, XRc, XRd - MXU registers - * Rb, Rc, Rd, Rs, Rt - general purpose MIPS registers - * - * Non-register operands: - * - * aptn1 - 1-bit accumulate add/subtract pattern - * aptn2 - 2-bit accumulate add/subtract pattern - * eptn2 - 2-bit execute add/subtract pattern - * optn2 - 2-bit operand pattern - * optn3 - 3-bit operand pattern - * sft4 - 4-bit shift amount - * strd2 - 2-bit stride amount - * - * Prefixes: - * - * Level of parallelism: Operand size: - * S - single operation at a time 32 - word - * D - two operations in parallel 16 - half word - * Q - four operations in parallel 8 - byte - * - * Operations: - * - * ADD - Add or subtract - * ADDC - Add with carry-in - * ACC - Accumulate - * ASUM - Sum together then accumulate (add or subtract) - * ASUMC - Sum together then accumulate (add or subtract) with carry-in - * AVG - Average between 2 operands - * ABD - Absolute difference - * ALN - Align data - * AND - Logical bitwise 'and' operation - * CPS - Copy sign - * EXTR - Extract bits - * I2M - Move from GPR register to MXU register - * LDD - Load data from memory to XRF - * LDI - Load data from memory to XRF (and increase the address base) - * LUI - Load unsigned immediate - * MUL - Multiply - * MULU - Unsigned multiply - * MADD - 64-bit operand add 32x32 product - * MSUB - 64-bit operand subtract 32x32 product - * MAC - Multiply and accumulate (add or subtract) - * MAD - Multiply and add or subtract - * MAX - Maximum between 2 operands - * MIN - Minimum between 2 operands - * M2I - Move from MXU register to GPR register - * MOVZ - Move if zero - * MOVN - Move if non-zero - * NOR - Logical bitwise 'nor' operation - * OR - Logical bitwise 'or' operation - * STD - Store data from XRF to memory - * SDI - Store data from XRF to memory (and increase the address base) - * SLT - Set of less than comparison - * SAD - Sum of absolute differences - * SLL - Logical shift left - * SLR - Logical shift right - * SAR - Arithmetic shift right - * SAT - Saturation - * SFL - Shuffle - * SCOP - Calculate x=E2=80=99s scope (-1, means x<0; 0, means x=3D=3D0= ; 1, means x>0) - * XOR - Logical bitwise 'exclusive or' operation - * - * Suffixes: - * - * E - Expand results - * F - Fixed point multiplication - * L - Low part result - * R - Doing rounding - * V - Variable instead of immediate - * W - Combine above L and V - * - * - * The list of MXU instructions grouped by functionality - * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - * - * Load/Store instructions Multiplication instructions - * ----------------------- --------------------------- - * - * S32LDD XRa, Rb, s12 S32MADD XRa, XRd, Rs, Rt - * S32STD XRa, Rb, s12 S32MADDU XRa, XRd, Rs, Rt - * S32LDDV XRa, Rb, rc, strd2 S32MSUB XRa, XRd, Rs, Rt - * S32STDV XRa, Rb, rc, strd2 S32MSUBU XRa, XRd, Rs, Rt - * S32LDI XRa, Rb, s12 S32MUL XRa, XRd, Rs, Rt - * S32SDI XRa, Rb, s12 S32MULU XRa, XRd, Rs, Rt - * S32LDIV XRa, Rb, rc, strd2 D16MUL XRa, XRb, XRc, XRd, optn2 - * S32SDIV XRa, Rb, rc, strd2 D16MULE XRa, XRb, XRc, optn2 - * S32LDDR XRa, Rb, s12 D16MULF XRa, XRb, XRc, optn2 - * S32STDR XRa, Rb, s12 D16MAC XRa, XRb, XRc, XRd, aptn2, op= tn2 - * S32LDDVR XRa, Rb, rc, strd2 D16MACE XRa, XRb, XRc, XRd, aptn2, o= ptn2 - * S32STDVR XRa, Rb, rc, strd2 D16MACF XRa, XRb, XRc, XRd, aptn2, o= ptn2 - * S32LDIR XRa, Rb, s12 D16MADL XRa, XRb, XRc, XRd, aptn2, o= ptn2 - * S32SDIR XRa, Rb, s12 S16MAD XRa, XRb, XRc, XRd, aptn1, op= tn2 - * S32LDIVR XRa, Rb, rc, strd2 Q8MUL XRa, XRb, XRc, XRd - * S32SDIVR XRa, Rb, rc, strd2 Q8MULSU XRa, XRb, XRc, XRd - * S16LDD XRa, Rb, s10, eptn2 Q8MAC XRa, XRb, XRc, XRd, aptn2 - * S16STD XRa, Rb, s10, eptn2 Q8MACSU XRa, XRb, XRc, XRd, aptn2 - * S16LDI XRa, Rb, s10, eptn2 Q8MADL XRa, XRb, XRc, XRd, aptn2 - * S16SDI XRa, Rb, s10, eptn2 - * S8LDD XRa, Rb, s8, eptn3 - * S8STD XRa, Rb, s8, eptn3 Addition and subtraction instructions - * S8LDI XRa, Rb, s8, eptn3 ------------------------------------- - * S8SDI XRa, Rb, s8, eptn3 - * LXW Rd, Rs, Rt, strd2 D32ADD XRa, XRb, XRc, XRd, eptn2 - * LXH Rd, Rs, Rt, strd2 D32ADDC XRa, XRb, XRc, XRd - * LXHU Rd, Rs, Rt, strd2 D32ACC XRa, XRb, XRc, XRd, eptn2 - * LXB Rd, Rs, Rt, strd2 D32ACCM XRa, XRb, XRc, XRd, eptn2 - * LXBU Rd, Rs, Rt, strd2 D32ASUM XRa, XRb, XRc, XRd, eptn2 - * S32CPS XRa, XRb, XRc - * Q16ADD XRa, XRb, XRc, XRd, eptn2, op= tn2 - * Comparison instructions Q16ACC XRa, XRb, XRc, XRd, eptn2 - * ----------------------- Q16ACCM XRa, XRb, XRc, XRd, eptn2 - * D16ASUM XRa, XRb, XRc, XRd, eptn2 - * S32MAX XRa, XRb, XRc D16CPS XRa, XRb, - * S32MIN XRa, XRb, XRc D16AVG XRa, XRb, XRc - * S32SLT XRa, XRb, XRc D16AVGR XRa, XRb, XRc - * S32MOVZ XRa, XRb, XRc Q8ADD XRa, XRb, XRc, eptn2 - * S32MOVN XRa, XRb, XRc Q8ADDE XRa, XRb, XRc, XRd, eptn2 - * D16MAX XRa, XRb, XRc Q8ACCE XRa, XRb, XRc, XRd, eptn2 - * D16MIN XRa, XRb, XRc Q8ABD XRa, XRb, XRc - * D16SLT XRa, XRb, XRc Q8SAD XRa, XRb, XRc, XRd - * D16MOVZ XRa, XRb, XRc Q8AVG XRa, XRb, XRc - * D16MOVN XRa, XRb, XRc Q8AVGR XRa, XRb, XRc - * Q8MAX XRa, XRb, XRc D8SUM XRa, XRb, XRc, XRd - * Q8MIN XRa, XRb, XRc D8SUMC XRa, XRb, XRc, XRd - * Q8SLT XRa, XRb, XRc - * Q8SLTU XRa, XRb, XRc - * Q8MOVZ XRa, XRb, XRc Shift instructions - * Q8MOVN XRa, XRb, XRc ------------------ - * - * D32SLL XRa, XRb, XRc, XRd, sft4 - * Bitwise instructions D32SLR XRa, XRb, XRc, XRd, sft4 - * -------------------- D32SAR XRa, XRb, XRc, XRd, sft4 - * D32SARL XRa, XRb, XRc, sft4 - * S32NOR XRa, XRb, XRc D32SLLV XRa, XRb, Rb - * S32AND XRa, XRb, XRc D32SLRV XRa, XRb, Rb - * S32XOR XRa, XRb, XRc D32SARV XRa, XRb, Rb - * S32OR XRa, XRb, XRc D32SARW XRa, XRb, XRc, Rb - * Q16SLL XRa, XRb, XRc, XRd, sft4 - * Q16SLR XRa, XRb, XRc, XRd, sft4 - * Miscellaneous instructions Q16SAR XRa, XRb, XRc, XRd, sft4 - * ------------------------- Q16SLLV XRa, XRb, Rb - * Q16SLRV XRa, XRb, Rb - * S32SFL XRa, XRb, XRc, XRd, optn2 Q16SARV XRa, XRb, Rb - * S32ALN XRa, XRb, XRc, Rb - * S32ALNI XRa, XRb, XRc, s3 - * S32LUI XRa, s8, optn3 Move instructions - * S32EXTR XRa, XRb, Rb, bits5 ----------------- - * S32EXTRV XRa, XRb, Rs, Rt - * Q16SCOP XRa, XRb, XRc, XRd S32M2I XRa, Rb - * Q16SAT XRa, XRb, XRc S32I2M XRa, Rb - * - * - * The opcode organization of MXU instructions - * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - * - * The bits 31..26 of all MXU instructions are equal to 0x1C (also referred - * as opcode SPECIAL2 in the base MIPS ISA). The organization and meaning = of - * other bits up to the instruction level is as follows: - * - * bits - * 05..00 - * - * =E2=94=8C=E2=94=80 000000 =E2=94=80 OPC_MXU_S32MADD - * =E2=94=9C=E2=94=80 000001 =E2=94=80 OPC_MXU_S32MADDU - * =E2=94=9C=E2=94=80 000010 =E2=94=80 (non-MXU = OPC_MUL) - * =E2=94=82 - * =E2=94=82 20..18 - * =E2=94=9C=E2=94=80 000011 =E2=94=80 OPC_MXU__POOL00 =E2=94=80= =E2=94=AC=E2=94=80 000 =E2=94=80 OPC_MXU_S32MAX - * =E2=94=82 =E2=94=9C=E2=94=80 001 = =E2=94=80 OPC_MXU_S32MIN - * =E2=94=82 =E2=94=9C=E2=94=80 010 = =E2=94=80 OPC_MXU_D16MAX - * =E2=94=82 =E2=94=9C=E2=94=80 011 = =E2=94=80 OPC_MXU_D16MIN - * =E2=94=82 =E2=94=9C=E2=94=80 100 = =E2=94=80 OPC_MXU_Q8MAX - * =E2=94=82 =E2=94=9C=E2=94=80 101 = =E2=94=80 OPC_MXU_Q8MIN - * =E2=94=82 =E2=94=9C=E2=94=80 110 = =E2=94=80 OPC_MXU_Q8SLT - * =E2=94=82 =E2=94=94=E2=94=80 111 = =E2=94=80 OPC_MXU_Q8SLTU - * =E2=94=9C=E2=94=80 000100 =E2=94=80 OPC_MXU_S32MSUB - * =E2=94=9C=E2=94=80 000101 =E2=94=80 OPC_MXU_S32MSUBU 20..18 - * =E2=94=9C=E2=94=80 000110 =E2=94=80 OPC_MXU__POOL01 =E2=94=80= =E2=94=AC=E2=94=80 000 =E2=94=80 OPC_MXU_S32SLT - * =E2=94=82 =E2=94=9C=E2=94=80 001 = =E2=94=80 OPC_MXU_D16SLT - * =E2=94=82 =E2=94=9C=E2=94=80 010 = =E2=94=80 OPC_MXU_D16AVG - * =E2=94=82 =E2=94=9C=E2=94=80 011 = =E2=94=80 OPC_MXU_D16AVGR - * =E2=94=82 =E2=94=9C=E2=94=80 100 = =E2=94=80 OPC_MXU_Q8AVG - * =E2=94=82 =E2=94=9C=E2=94=80 101 = =E2=94=80 OPC_MXU_Q8AVGR - * =E2=94=82 =E2=94=94=E2=94=80 111 = =E2=94=80 OPC_MXU_Q8ADD - * =E2=94=82 - * =E2=94=82 20..18 - * =E2=94=9C=E2=94=80 000111 =E2=94=80 OPC_MXU__POOL02 =E2=94=80= =E2=94=AC=E2=94=80 000 =E2=94=80 OPC_MXU_S32CPS - * =E2=94=82 =E2=94=9C=E2=94=80 010 = =E2=94=80 OPC_MXU_D16CPS - * =E2=94=82 =E2=94=9C=E2=94=80 100 = =E2=94=80 OPC_MXU_Q8ABD - * =E2=94=82 =E2=94=94=E2=94=80 110 = =E2=94=80 OPC_MXU_Q16SAT - * =E2=94=9C=E2=94=80 001000 =E2=94=80 OPC_MXU_D16MUL - * =E2=94=82 25..24 - * =E2=94=9C=E2=94=80 001001 =E2=94=80 OPC_MXU__POOL03 =E2=94=80= =E2=94=AC=E2=94=80 00 =E2=94=80 OPC_MXU_D16MULF - * =E2=94=82 =E2=94=94=E2=94=80 01 =E2= =94=80 OPC_MXU_D16MULE - * =E2=94=9C=E2=94=80 001010 =E2=94=80 OPC_MXU_D16MAC - * =E2=94=9C=E2=94=80 001011 =E2=94=80 OPC_MXU_D16MACF - * =E2=94=9C=E2=94=80 001100 =E2=94=80 OPC_MXU_D16MADL - * =E2=94=9C=E2=94=80 001101 =E2=94=80 OPC_MXU_S16MAD - * =E2=94=9C=E2=94=80 001110 =E2=94=80 OPC_MXU_Q16ADD - * =E2=94=9C=E2=94=80 001111 =E2=94=80 OPC_MXU_D16MACE 23 - * =E2=94=82 =E2=94=8C=E2=94=80 0 =E2= =94=80 OPC_MXU_S32LDD - * =E2=94=9C=E2=94=80 010000 =E2=94=80 OPC_MXU__POOL04 =E2=94=80= =E2=94=B4=E2=94=80 1 =E2=94=80 OPC_MXU_S32LDDR - * =E2=94=82 - * =E2=94=82 23 - * =E2=94=9C=E2=94=80 010001 =E2=94=80 OPC_MXU__POOL05 =E2=94=80= =E2=94=AC=E2=94=80 0 =E2=94=80 OPC_MXU_S32STD - * =E2=94=82 =E2=94=94=E2=94=80 1 =E2= =94=80 OPC_MXU_S32STDR - * =E2=94=82 - * =E2=94=82 13..10 - * =E2=94=9C=E2=94=80 010010 =E2=94=80 OPC_MXU__POOL06 =E2=94=80= =E2=94=AC=E2=94=80 0000 =E2=94=80 OPC_MXU_S32LDDV - * =E2=94=82 =E2=94=94=E2=94=80 0001 = =E2=94=80 OPC_MXU_S32LDDVR - * =E2=94=82 - * =E2=94=82 13..10 - * =E2=94=9C=E2=94=80 010011 =E2=94=80 OPC_MXU__POOL07 =E2=94=80= =E2=94=AC=E2=94=80 0000 =E2=94=80 OPC_MXU_S32STDV - * =E2=94=82 =E2=94=94=E2=94=80 0001 = =E2=94=80 OPC_MXU_S32STDVR - * =E2=94=82 - * =E2=94=82 23 - * =E2=94=9C=E2=94=80 010100 =E2=94=80 OPC_MXU__POOL08 =E2=94=80= =E2=94=AC=E2=94=80 0 =E2=94=80 OPC_MXU_S32LDI - * =E2=94=82 =E2=94=94=E2=94=80 1 =E2= =94=80 OPC_MXU_S32LDIR - * =E2=94=82 - * =E2=94=82 23 - * =E2=94=9C=E2=94=80 010101 =E2=94=80 OPC_MXU__POOL09 =E2=94=80= =E2=94=AC=E2=94=80 0 =E2=94=80 OPC_MXU_S32SDI - * =E2=94=82 =E2=94=94=E2=94=80 1 =E2= =94=80 OPC_MXU_S32SDIR - * =E2=94=82 - * =E2=94=82 13..10 - * =E2=94=9C=E2=94=80 010110 =E2=94=80 OPC_MXU__POOL10 =E2=94=80= =E2=94=AC=E2=94=80 0000 =E2=94=80 OPC_MXU_S32LDIV - * =E2=94=82 =E2=94=94=E2=94=80 0001 = =E2=94=80 OPC_MXU_S32LDIVR - * =E2=94=82 - * =E2=94=82 13..10 - * =E2=94=9C=E2=94=80 010111 =E2=94=80 OPC_MXU__POOL11 =E2=94=80= =E2=94=AC=E2=94=80 0000 =E2=94=80 OPC_MXU_S32SDIV - * =E2=94=82 =E2=94=94=E2=94=80 0001 = =E2=94=80 OPC_MXU_S32SDIVR - * =E2=94=9C=E2=94=80 011000 =E2=94=80 OPC_MXU_D32ADD - * =E2=94=82 23..22 - * MXU =E2=94=9C=E2=94=80 011001 =E2=94=80 OPC_MXU__POOL12 =E2=94=80= =E2=94=AC=E2=94=80 00 =E2=94=80 OPC_MXU_D32ACC - * opcodes =E2=94=80=E2=94=A4 =E2=94=9C=E2=94= =80 01 =E2=94=80 OPC_MXU_D32ACCM - * =E2=94=82 =E2=94=94=E2=94=80 10 =E2= =94=80 OPC_MXU_D32ASUM - * =E2=94=9C=E2=94=80 011010 =E2=94=80 - * =E2=94=82 23..22 - * =E2=94=9C=E2=94=80 011011 =E2=94=80 OPC_MXU__POOL13 =E2=94=80= =E2=94=AC=E2=94=80 00 =E2=94=80 OPC_MXU_Q16ACC - * =E2=94=82 =E2=94=9C=E2=94=80 01 =E2= =94=80 OPC_MXU_Q16ACCM - * =E2=94=82 =E2=94=94=E2=94=80 10 =E2= =94=80 OPC_MXU_Q16ASUM - * =E2=94=82 - * =E2=94=82 23..22 - * =E2=94=9C=E2=94=80 011100 =E2=94=80 OPC_MXU__POOL14 =E2=94=80= =E2=94=AC=E2=94=80 00 =E2=94=80 OPC_MXU_Q8ADDE - * =E2=94=82 =E2=94=9C=E2=94=80 01 =E2= =94=80 OPC_MXU_D8SUM - * =E2=94=9C=E2=94=80 011101 =E2=94=80 OPC_MXU_Q8ACCE =E2=94=94= =E2=94=80 10 =E2=94=80 OPC_MXU_D8SUMC - * =E2=94=9C=E2=94=80 011110 =E2=94=80 - * =E2=94=9C=E2=94=80 011111 =E2=94=80 - * =E2=94=9C=E2=94=80 100000 =E2=94=80 (overlaps= with CLZ) - * =E2=94=9C=E2=94=80 100001 =E2=94=80 (overlaps= with CLO) - * =E2=94=9C=E2=94=80 100010 =E2=94=80 OPC_MXU_S8LDD - * =E2=94=9C=E2=94=80 100011 =E2=94=80 OPC_MXU_S8STD 15..14 - * =E2=94=9C=E2=94=80 100100 =E2=94=80 OPC_MXU_S8LDI =E2=94=8C= =E2=94=80 00 =E2=94=80 OPC_MXU_S32MUL - * =E2=94=9C=E2=94=80 100101 =E2=94=80 OPC_MXU_S8SDI =E2=94=9C= =E2=94=80 00 =E2=94=80 OPC_MXU_S32MULU - * =E2=94=82 =E2=94=9C=E2=94=80 00 =E2= =94=80 OPC_MXU_S32EXTR - * =E2=94=9C=E2=94=80 100110 =E2=94=80 OPC_MXU__POOL15 =E2=94=80= =E2=94=B4=E2=94=80 00 =E2=94=80 OPC_MXU_S32EXTRV - * =E2=94=82 - * =E2=94=82 20..18 - * =E2=94=9C=E2=94=80 100111 =E2=94=80 OPC_MXU__POOL16 =E2=94=80= =E2=94=AC=E2=94=80 000 =E2=94=80 OPC_MXU_D32SARW - * =E2=94=82 =E2=94=9C=E2=94=80 001 = =E2=94=80 OPC_MXU_S32ALN - * =E2=94=82 =E2=94=9C=E2=94=80 010 = =E2=94=80 OPC_MXU_S32ALNI - * =E2=94=82 =E2=94=9C=E2=94=80 011 = =E2=94=80 OPC_MXU_S32LUI - * =E2=94=82 =E2=94=9C=E2=94=80 100 = =E2=94=80 OPC_MXU_S32NOR - * =E2=94=82 =E2=94=9C=E2=94=80 101 = =E2=94=80 OPC_MXU_S32AND - * =E2=94=82 =E2=94=9C=E2=94=80 110 = =E2=94=80 OPC_MXU_S32OR - * =E2=94=82 =E2=94=94=E2=94=80 111 = =E2=94=80 OPC_MXU_S32XOR - * =E2=94=82 - * =E2=94=82 7..5 - * =E2=94=9C=E2=94=80 101000 =E2=94=80 OPC_MXU__POOL17 =E2=94=80= =E2=94=AC=E2=94=80 000 =E2=94=80 OPC_MXU_LXB - * =E2=94=82 =E2=94=9C=E2=94=80 001 = =E2=94=80 OPC_MXU_LXH - * =E2=94=9C=E2=94=80 101001 =E2=94=80 =E2=94=9C= =E2=94=80 011 =E2=94=80 OPC_MXU_LXW - * =E2=94=9C=E2=94=80 101010 =E2=94=80 OPC_MXU_S16LDD =E2=94=9C= =E2=94=80 100 =E2=94=80 OPC_MXU_LXBU - * =E2=94=9C=E2=94=80 101011 =E2=94=80 OPC_MXU_S16STD =E2=94=94= =E2=94=80 101 =E2=94=80 OPC_MXU_LXHU - * =E2=94=9C=E2=94=80 101100 =E2=94=80 OPC_MXU_S16LDI - * =E2=94=9C=E2=94=80 101101 =E2=94=80 OPC_MXU_S16SDI - * =E2=94=9C=E2=94=80 101110 =E2=94=80 OPC_MXU_S32M2I - * =E2=94=9C=E2=94=80 101111 =E2=94=80 OPC_MXU_S32I2M - * =E2=94=9C=E2=94=80 110000 =E2=94=80 OPC_MXU_D32SLL - * =E2=94=9C=E2=94=80 110001 =E2=94=80 OPC_MXU_D32SLR 20..18 - * =E2=94=9C=E2=94=80 110010 =E2=94=80 OPC_MXU_D32SARL =E2=94=8C= =E2=94=80 000 =E2=94=80 OPC_MXU_D32SLLV - * =E2=94=9C=E2=94=80 110011 =E2=94=80 OPC_MXU_D32SAR =E2=94=9C= =E2=94=80 001 =E2=94=80 OPC_MXU_D32SLRV - * =E2=94=9C=E2=94=80 110100 =E2=94=80 OPC_MXU_Q16SLL =E2=94=9C= =E2=94=80 010 =E2=94=80 OPC_MXU_D32SARV - * =E2=94=9C=E2=94=80 110101 =E2=94=80 OPC_MXU_Q16SLR =E2=94=9C= =E2=94=80 011 =E2=94=80 OPC_MXU_Q16SLLV - * =E2=94=82 =E2=94=9C=E2=94=80 100 = =E2=94=80 OPC_MXU_Q16SLRV - * =E2=94=9C=E2=94=80 110110 =E2=94=80 OPC_MXU__POOL18 =E2=94=80= =E2=94=B4=E2=94=80 101 =E2=94=80 OPC_MXU_Q16SARV - * =E2=94=82 - * =E2=94=9C=E2=94=80 110111 =E2=94=80 OPC_MXU_Q16SAR - * =E2=94=82 23..22 - * =E2=94=9C=E2=94=80 111000 =E2=94=80 OPC_MXU__POOL19 =E2=94=80= =E2=94=AC=E2=94=80 00 =E2=94=80 OPC_MXU_Q8MUL - * =E2=94=82 =E2=94=94=E2=94=80 01 =E2= =94=80 OPC_MXU_Q8MULSU - * =E2=94=82 - * =E2=94=82 20..18 - * =E2=94=9C=E2=94=80 111001 =E2=94=80 OPC_MXU__POOL20 =E2=94=80= =E2=94=AC=E2=94=80 000 =E2=94=80 OPC_MXU_Q8MOVZ - * =E2=94=82 =E2=94=9C=E2=94=80 001 = =E2=94=80 OPC_MXU_Q8MOVN - * =E2=94=82 =E2=94=9C=E2=94=80 010 = =E2=94=80 OPC_MXU_D16MOVZ - * =E2=94=82 =E2=94=9C=E2=94=80 011 = =E2=94=80 OPC_MXU_D16MOVN - * =E2=94=82 =E2=94=9C=E2=94=80 100 = =E2=94=80 OPC_MXU_S32MOVZ - * =E2=94=82 =E2=94=94=E2=94=80 101 = =E2=94=80 OPC_MXU_S32MOVN - * =E2=94=82 - * =E2=94=82 23..22 - * =E2=94=9C=E2=94=80 111010 =E2=94=80 OPC_MXU__POOL21 =E2=94=80= =E2=94=AC=E2=94=80 00 =E2=94=80 OPC_MXU_Q8MAC - * =E2=94=82 =E2=94=94=E2=94=80 10 =E2= =94=80 OPC_MXU_Q8MACSU - * =E2=94=9C=E2=94=80 111011 =E2=94=80 OPC_MXU_Q16SCOP - * =E2=94=9C=E2=94=80 111100 =E2=94=80 OPC_MXU_Q8MADL - * =E2=94=9C=E2=94=80 111101 =E2=94=80 OPC_MXU_S32SFL - * =E2=94=9C=E2=94=80 111110 =E2=94=80 OPC_MXU_Q8SAD - * =E2=94=94=E2=94=80 111111 =E2=94=80 (overlaps= with SDBBP) - * - * - * Compiled after: - * - * "XBurst=C2=AE Instruction Set Architecture MIPS eXtension/enhanced Un= it - * Programming Manual", Ingenic Semiconductor Co, Ltd., revision June 2,= 2017 - */ - -enum { - OPC_MXU__POOL00 =3D 0x03, - OPC_MXU_D16MUL =3D 0x08, - OPC_MXU_D16MAC =3D 0x0A, - OPC_MXU__POOL04 =3D 0x10, - OPC_MXU_S8LDD =3D 0x22, - OPC_MXU__POOL16 =3D 0x27, - OPC_MXU_S32M2I =3D 0x2E, - OPC_MXU_S32I2M =3D 0x2F, - OPC_MXU__POOL19 =3D 0x38, -}; - - -/* - * MXU pool 00 - */ -enum { - OPC_MXU_S32MAX =3D 0x00, - OPC_MXU_S32MIN =3D 0x01, - OPC_MXU_D16MAX =3D 0x02, - OPC_MXU_D16MIN =3D 0x03, - OPC_MXU_Q8MAX =3D 0x04, - OPC_MXU_Q8MIN =3D 0x05, -}; - -/* - * MXU pool 04 - */ -enum { - OPC_MXU_S32LDD =3D 0x00, - OPC_MXU_S32LDDR =3D 0x01, -}; - -/* - * MXU pool 16 - */ -enum { - OPC_MXU_S32ALNI =3D 0x02, - OPC_MXU_S32NOR =3D 0x04, - OPC_MXU_S32AND =3D 0x05, - OPC_MXU_S32OR =3D 0x06, - OPC_MXU_S32XOR =3D 0x07, -}; - -/* - * MXU pool 19 - */ -enum { - OPC_MXU_Q8MUL =3D 0x00, - OPC_MXU_Q8MULSU =3D 0x01, -}; - /* * Overview of the TX79-specific instruction set * =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D @@ -1965,12 +1579,6 @@ static TCGv_i32 hflags; TCGv_i32 fpu_fcr0, fpu_fcr31; TCGv_i64 fpu_f64[32]; =20 -#if !defined(TARGET_MIPS64) -/* MXU registers */ -static TCGv mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1]; -static TCGv mxu_CR; -#endif - #include "exec/gen-icount.h" =20 #define gen_helper_0e0i(name, arg) do { \ @@ -2040,26 +1648,6 @@ static const char * const fregnames[] =3D { "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", }; =20 -#if !defined(TARGET_MIPS64) -static const char * const mxuregnames[] =3D { - "XR1", "XR2", "XR3", "XR4", "XR5", "XR6", "XR7", "XR8", - "XR9", "XR10", "XR11", "XR12", "XR13", "XR14", "XR15", "MXU_CR", -}; - -void mxu_translate_init(void) -{ - for (unsigned i =3D 0; i < NUMBER_OF_MXU_REGISTERS - 1; i++) { - mxu_gpr[i] =3D tcg_global_mem_new(cpu_env, - offsetof(CPUMIPSState, active_tc.m= xu_gpr[i]), - mxuregnames[i]); - } - - mxu_CR =3D tcg_global_mem_new(cpu_env, - offsetof(CPUMIPSState, active_tc.mxu_cr), - mxuregnames[NUMBER_OF_MXU_REGISTERS - 1]); -} -#endif /* !TARGET_MIPS64 */ - /* General purpose registers moves. */ void gen_load_gpr(TCGv t, int reg) { @@ -2143,38 +1731,6 @@ static inline void gen_store_srsgpr(int from, int to) } } =20 -#if !defined(TARGET_MIPS64) -/* MXU General purpose registers moves. */ -static inline void gen_load_mxu_gpr(TCGv t, unsigned int reg) -{ - if (reg =3D=3D 0) { - tcg_gen_movi_tl(t, 0); - } else if (reg <=3D 15) { - tcg_gen_mov_tl(t, mxu_gpr[reg - 1]); - } -} - -static inline void gen_store_mxu_gpr(TCGv t, unsigned int reg) -{ - if (reg > 0 && reg <=3D 15) { - tcg_gen_mov_tl(mxu_gpr[reg - 1], t); - } -} - -/* MXU control register moves. */ -static inline void gen_load_mxu_cr(TCGv t) -{ - tcg_gen_mov_tl(t, mxu_CR); -} - -static inline void gen_store_mxu_cr(TCGv t) -{ - /* TODO: Add handling of RW rules for MXU_CR. */ - tcg_gen_mov_tl(mxu_CR, t); -} -#endif - - /* Tests */ static inline void gen_save_pc(target_ulong pc) { @@ -24690,1167 +24246,6 @@ static void gen_mmi_pcpyud(DisasContext *ctx) =20 #endif =20 - -#if !defined(TARGET_MIPS64) - -/* MXU accumulate add/subtract 1-bit pattern 'aptn1' */ -#define MXU_APTN1_A 0 -#define MXU_APTN1_S 1 - -/* MXU accumulate add/subtract 2-bit pattern 'aptn2' */ -#define MXU_APTN2_AA 0 -#define MXU_APTN2_AS 1 -#define MXU_APTN2_SA 2 -#define MXU_APTN2_SS 3 - -/* MXU execute add/subtract 2-bit pattern 'eptn2' */ -#define MXU_EPTN2_AA 0 -#define MXU_EPTN2_AS 1 -#define MXU_EPTN2_SA 2 -#define MXU_EPTN2_SS 3 - -/* MXU operand getting pattern 'optn2' */ -#define MXU_OPTN2_PTN0 0 -#define MXU_OPTN2_PTN1 1 -#define MXU_OPTN2_PTN2 2 -#define MXU_OPTN2_PTN3 3 -/* alternative naming scheme for 'optn2' */ -#define MXU_OPTN2_WW 0 -#define MXU_OPTN2_LW 1 -#define MXU_OPTN2_HW 2 -#define MXU_OPTN2_XW 3 - -/* MXU operand getting pattern 'optn3' */ -#define MXU_OPTN3_PTN0 0 -#define MXU_OPTN3_PTN1 1 -#define MXU_OPTN3_PTN2 2 -#define MXU_OPTN3_PTN3 3 -#define MXU_OPTN3_PTN4 4 -#define MXU_OPTN3_PTN5 5 -#define MXU_OPTN3_PTN6 6 -#define MXU_OPTN3_PTN7 7 - - -/* - * S32I2M XRa, rb - Register move from GRF to XRF - */ -static void gen_mxu_s32i2m(DisasContext *ctx) -{ - TCGv t0; - uint32_t XRa, Rb; - - t0 =3D tcg_temp_new(); - - XRa =3D extract32(ctx->opcode, 6, 5); - Rb =3D extract32(ctx->opcode, 16, 5); - - gen_load_gpr(t0, Rb); - if (XRa <=3D 15) { - gen_store_mxu_gpr(t0, XRa); - } else if (XRa =3D=3D 16) { - gen_store_mxu_cr(t0); - } - - tcg_temp_free(t0); -} - -/* - * S32M2I XRa, rb - Register move from XRF to GRF - */ -static void gen_mxu_s32m2i(DisasContext *ctx) -{ - TCGv t0; - uint32_t XRa, Rb; - - t0 =3D tcg_temp_new(); - - XRa =3D extract32(ctx->opcode, 6, 5); - Rb =3D extract32(ctx->opcode, 16, 5); - - if (XRa <=3D 15) { - gen_load_mxu_gpr(t0, XRa); - } else if (XRa =3D=3D 16) { - gen_load_mxu_cr(t0); - } - - gen_store_gpr(t0, Rb); - - tcg_temp_free(t0); -} - -/* - * S8LDD XRa, Rb, s8, optn3 - Load a byte from memory to XRF - */ -static void gen_mxu_s8ldd(DisasContext *ctx) -{ - TCGv t0, t1; - uint32_t XRa, Rb, s8, optn3; - - t0 =3D tcg_temp_new(); - t1 =3D tcg_temp_new(); - - XRa =3D extract32(ctx->opcode, 6, 4); - s8 =3D extract32(ctx->opcode, 10, 8); - optn3 =3D extract32(ctx->opcode, 18, 3); - Rb =3D extract32(ctx->opcode, 21, 5); - - gen_load_gpr(t0, Rb); - tcg_gen_addi_tl(t0, t0, (int8_t)s8); - - switch (optn3) { - /* XRa[7:0] =3D tmp8 */ - case MXU_OPTN3_PTN0: - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); - gen_load_mxu_gpr(t0, XRa); - tcg_gen_deposit_tl(t0, t0, t1, 0, 8); - break; - /* XRa[15:8] =3D tmp8 */ - case MXU_OPTN3_PTN1: - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); - gen_load_mxu_gpr(t0, XRa); - tcg_gen_deposit_tl(t0, t0, t1, 8, 8); - break; - /* XRa[23:16] =3D tmp8 */ - case MXU_OPTN3_PTN2: - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); - gen_load_mxu_gpr(t0, XRa); - tcg_gen_deposit_tl(t0, t0, t1, 16, 8); - break; - /* XRa[31:24] =3D tmp8 */ - case MXU_OPTN3_PTN3: - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); - gen_load_mxu_gpr(t0, XRa); - tcg_gen_deposit_tl(t0, t0, t1, 24, 8); - break; - /* XRa =3D {8'b0, tmp8, 8'b0, tmp8} */ - case MXU_OPTN3_PTN4: - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); - tcg_gen_deposit_tl(t0, t1, t1, 16, 16); - break; - /* XRa =3D {tmp8, 8'b0, tmp8, 8'b0} */ - case MXU_OPTN3_PTN5: - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); - tcg_gen_shli_tl(t1, t1, 8); - tcg_gen_deposit_tl(t0, t1, t1, 16, 16); - break; - /* XRa =3D {{8{sign of tmp8}}, tmp8, {8{sign of tmp8}}, tmp8} */ - case MXU_OPTN3_PTN6: - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_SB); - tcg_gen_mov_tl(t0, t1); - tcg_gen_andi_tl(t0, t0, 0xFF00FFFF); - tcg_gen_shli_tl(t1, t1, 16); - tcg_gen_or_tl(t0, t0, t1); - break; - /* XRa =3D {tmp8, tmp8, tmp8, tmp8} */ - case MXU_OPTN3_PTN7: - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); - tcg_gen_deposit_tl(t1, t1, t1, 8, 8); - tcg_gen_deposit_tl(t0, t1, t1, 16, 16); - break; - } - - gen_store_mxu_gpr(t0, XRa); - - tcg_temp_free(t0); - tcg_temp_free(t1); -} - -/* - * D16MUL XRa, XRb, XRc, XRd, optn2 - Signed 16 bit pattern multiplication - */ -static void gen_mxu_d16mul(DisasContext *ctx) -{ - TCGv t0, t1, t2, t3; - uint32_t XRa, XRb, XRc, XRd, optn2; - - t0 =3D tcg_temp_new(); - t1 =3D tcg_temp_new(); - t2 =3D tcg_temp_new(); - t3 =3D tcg_temp_new(); - - XRa =3D extract32(ctx->opcode, 6, 4); - XRb =3D extract32(ctx->opcode, 10, 4); - XRc =3D extract32(ctx->opcode, 14, 4); - XRd =3D extract32(ctx->opcode, 18, 4); - optn2 =3D extract32(ctx->opcode, 22, 2); - - gen_load_mxu_gpr(t1, XRb); - tcg_gen_sextract_tl(t0, t1, 0, 16); - tcg_gen_sextract_tl(t1, t1, 16, 16); - gen_load_mxu_gpr(t3, XRc); - tcg_gen_sextract_tl(t2, t3, 0, 16); - tcg_gen_sextract_tl(t3, t3, 16, 16); - - switch (optn2) { - case MXU_OPTN2_WW: /* XRB.H*XRC.H =3D=3D lop, XRB.L*XRC.L =3D=3D rop */ - tcg_gen_mul_tl(t3, t1, t3); - tcg_gen_mul_tl(t2, t0, t2); - break; - case MXU_OPTN2_LW: /* XRB.L*XRC.H =3D=3D lop, XRB.L*XRC.L =3D=3D rop */ - tcg_gen_mul_tl(t3, t0, t3); - tcg_gen_mul_tl(t2, t0, t2); - break; - case MXU_OPTN2_HW: /* XRB.H*XRC.H =3D=3D lop, XRB.H*XRC.L =3D=3D rop */ - tcg_gen_mul_tl(t3, t1, t3); - tcg_gen_mul_tl(t2, t1, t2); - break; - case MXU_OPTN2_XW: /* XRB.L*XRC.H =3D=3D lop, XRB.H*XRC.L =3D=3D rop */ - tcg_gen_mul_tl(t3, t0, t3); - tcg_gen_mul_tl(t2, t1, t2); - break; - } - gen_store_mxu_gpr(t3, XRa); - gen_store_mxu_gpr(t2, XRd); - - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_temp_free(t2); - tcg_temp_free(t3); -} - -/* - * D16MAC XRa, XRb, XRc, XRd, aptn2, optn2 - Signed 16 bit pattern multiply - * and accumulate - */ -static void gen_mxu_d16mac(DisasContext *ctx) -{ - TCGv t0, t1, t2, t3; - uint32_t XRa, XRb, XRc, XRd, optn2, aptn2; - - t0 =3D tcg_temp_new(); - t1 =3D tcg_temp_new(); - t2 =3D tcg_temp_new(); - t3 =3D tcg_temp_new(); - - XRa =3D extract32(ctx->opcode, 6, 4); - XRb =3D extract32(ctx->opcode, 10, 4); - XRc =3D extract32(ctx->opcode, 14, 4); - XRd =3D extract32(ctx->opcode, 18, 4); - optn2 =3D extract32(ctx->opcode, 22, 2); - aptn2 =3D extract32(ctx->opcode, 24, 2); - - gen_load_mxu_gpr(t1, XRb); - tcg_gen_sextract_tl(t0, t1, 0, 16); - tcg_gen_sextract_tl(t1, t1, 16, 16); - - gen_load_mxu_gpr(t3, XRc); - tcg_gen_sextract_tl(t2, t3, 0, 16); - tcg_gen_sextract_tl(t3, t3, 16, 16); - - switch (optn2) { - case MXU_OPTN2_WW: /* XRB.H*XRC.H =3D=3D lop, XRB.L*XRC.L =3D=3D rop */ - tcg_gen_mul_tl(t3, t1, t3); - tcg_gen_mul_tl(t2, t0, t2); - break; - case MXU_OPTN2_LW: /* XRB.L*XRC.H =3D=3D lop, XRB.L*XRC.L =3D=3D rop */ - tcg_gen_mul_tl(t3, t0, t3); - tcg_gen_mul_tl(t2, t0, t2); - break; - case MXU_OPTN2_HW: /* XRB.H*XRC.H =3D=3D lop, XRB.H*XRC.L =3D=3D rop */ - tcg_gen_mul_tl(t3, t1, t3); - tcg_gen_mul_tl(t2, t1, t2); - break; - case MXU_OPTN2_XW: /* XRB.L*XRC.H =3D=3D lop, XRB.H*XRC.L =3D=3D rop */ - tcg_gen_mul_tl(t3, t0, t3); - tcg_gen_mul_tl(t2, t1, t2); - break; - } - gen_load_mxu_gpr(t0, XRa); - gen_load_mxu_gpr(t1, XRd); - - switch (aptn2) { - case MXU_APTN2_AA: - tcg_gen_add_tl(t3, t0, t3); - tcg_gen_add_tl(t2, t1, t2); - break; - case MXU_APTN2_AS: - tcg_gen_add_tl(t3, t0, t3); - tcg_gen_sub_tl(t2, t1, t2); - break; - case MXU_APTN2_SA: - tcg_gen_sub_tl(t3, t0, t3); - tcg_gen_add_tl(t2, t1, t2); - break; - case MXU_APTN2_SS: - tcg_gen_sub_tl(t3, t0, t3); - tcg_gen_sub_tl(t2, t1, t2); - break; - } - gen_store_mxu_gpr(t3, XRa); - gen_store_mxu_gpr(t2, XRd); - - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_temp_free(t2); - tcg_temp_free(t3); -} - -/* - * Q8MUL XRa, XRb, XRc, XRd - Parallel unsigned 8 bit pattern multiply - * Q8MULSU XRa, XRb, XRc, XRd - Parallel signed 8 bit pattern multiply - */ -static void gen_mxu_q8mul_q8mulsu(DisasContext *ctx) -{ - TCGv t0, t1, t2, t3, t4, t5, t6, t7; - uint32_t XRa, XRb, XRc, XRd, sel; - - t0 =3D tcg_temp_new(); - t1 =3D tcg_temp_new(); - t2 =3D tcg_temp_new(); - t3 =3D tcg_temp_new(); - t4 =3D tcg_temp_new(); - t5 =3D tcg_temp_new(); - t6 =3D tcg_temp_new(); - t7 =3D tcg_temp_new(); - - XRa =3D extract32(ctx->opcode, 6, 4); - XRb =3D extract32(ctx->opcode, 10, 4); - XRc =3D extract32(ctx->opcode, 14, 4); - XRd =3D extract32(ctx->opcode, 18, 4); - sel =3D extract32(ctx->opcode, 22, 2); - - gen_load_mxu_gpr(t3, XRb); - gen_load_mxu_gpr(t7, XRc); - - if (sel =3D=3D 0x2) { - /* Q8MULSU */ - tcg_gen_ext8s_tl(t0, t3); - tcg_gen_shri_tl(t3, t3, 8); - tcg_gen_ext8s_tl(t1, t3); - tcg_gen_shri_tl(t3, t3, 8); - tcg_gen_ext8s_tl(t2, t3); - tcg_gen_shri_tl(t3, t3, 8); - tcg_gen_ext8s_tl(t3, t3); - } else { - /* Q8MUL */ - tcg_gen_ext8u_tl(t0, t3); - tcg_gen_shri_tl(t3, t3, 8); - tcg_gen_ext8u_tl(t1, t3); - tcg_gen_shri_tl(t3, t3, 8); - tcg_gen_ext8u_tl(t2, t3); - tcg_gen_shri_tl(t3, t3, 8); - tcg_gen_ext8u_tl(t3, t3); - } - - tcg_gen_ext8u_tl(t4, t7); - tcg_gen_shri_tl(t7, t7, 8); - tcg_gen_ext8u_tl(t5, t7); - tcg_gen_shri_tl(t7, t7, 8); - tcg_gen_ext8u_tl(t6, t7); - tcg_gen_shri_tl(t7, t7, 8); - tcg_gen_ext8u_tl(t7, t7); - - tcg_gen_mul_tl(t0, t0, t4); - tcg_gen_mul_tl(t1, t1, t5); - tcg_gen_mul_tl(t2, t2, t6); - tcg_gen_mul_tl(t3, t3, t7); - - tcg_gen_andi_tl(t0, t0, 0xFFFF); - tcg_gen_andi_tl(t1, t1, 0xFFFF); - tcg_gen_andi_tl(t2, t2, 0xFFFF); - tcg_gen_andi_tl(t3, t3, 0xFFFF); - - tcg_gen_shli_tl(t1, t1, 16); - tcg_gen_shli_tl(t3, t3, 16); - - tcg_gen_or_tl(t0, t0, t1); - tcg_gen_or_tl(t1, t2, t3); - - gen_store_mxu_gpr(t0, XRd); - gen_store_mxu_gpr(t1, XRa); - - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_temp_free(t2); - tcg_temp_free(t3); - tcg_temp_free(t4); - tcg_temp_free(t5); - tcg_temp_free(t6); - tcg_temp_free(t7); -} - -/* - * S32LDD XRa, Rb, S12 - Load a word from memory to XRF - * S32LDDR XRa, Rb, S12 - Load a word from memory to XRF, reversed byte se= q. - */ -static void gen_mxu_s32ldd_s32lddr(DisasContext *ctx) -{ - TCGv t0, t1; - uint32_t XRa, Rb, s12, sel; - - t0 =3D tcg_temp_new(); - t1 =3D tcg_temp_new(); - - XRa =3D extract32(ctx->opcode, 6, 4); - s12 =3D extract32(ctx->opcode, 10, 10); - sel =3D extract32(ctx->opcode, 20, 1); - Rb =3D extract32(ctx->opcode, 21, 5); - - gen_load_gpr(t0, Rb); - - tcg_gen_movi_tl(t1, s12); - tcg_gen_shli_tl(t1, t1, 2); - if (s12 & 0x200) { - tcg_gen_ori_tl(t1, t1, 0xFFFFF000); - } - tcg_gen_add_tl(t1, t0, t1); - tcg_gen_qemu_ld_tl(t1, t1, ctx->mem_idx, MO_SL); - - if (sel =3D=3D 1) { - /* S32LDDR */ - tcg_gen_bswap32_tl(t1, t1); - } - gen_store_mxu_gpr(t1, XRa); - - tcg_temp_free(t0); - tcg_temp_free(t1); -} - - -/* - * MXU instruction category: logic - * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - * - * S32NOR S32AND S32OR S32XOR - */ - -/* - * S32NOR XRa, XRb, XRc - * Update XRa with the result of logical bitwise 'nor' operation - * applied to the content of XRb and XRc. - */ -static void gen_mxu_S32NOR(DisasContext *ctx) -{ - uint32_t pad, XRc, XRb, XRa; - - pad =3D extract32(ctx->opcode, 21, 5); - XRc =3D extract32(ctx->opcode, 14, 4); - XRb =3D extract32(ctx->opcode, 10, 4); - XRa =3D extract32(ctx->opcode, 6, 4); - - if (unlikely(pad !=3D 0)) { - /* opcode padding incorrect -> do nothing */ - } else if (unlikely(XRa =3D=3D 0)) { - /* destination is zero register -> do nothing */ - } else if (unlikely((XRb =3D=3D 0) && (XRc =3D=3D 0))) { - /* both operands zero registers -> just set destination to all 1s = */ - tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0xFFFFFFFF); - } else if (unlikely(XRb =3D=3D 0)) { - /* XRb zero register -> just set destination to the negation of XR= c */ - tcg_gen_not_i32(mxu_gpr[XRa - 1], mxu_gpr[XRc - 1]); - } else if (unlikely(XRc =3D=3D 0)) { - /* XRa zero register -> just set destination to the negation of XR= b */ - tcg_gen_not_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); - } else if (unlikely(XRb =3D=3D XRc)) { - /* both operands same -> just set destination to the negation of X= Rb */ - tcg_gen_not_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); - } else { - /* the most general case */ - tcg_gen_nor_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], mxu_gpr[XRc - = 1]); - } -} - -/* - * S32AND XRa, XRb, XRc - * Update XRa with the result of logical bitwise 'and' operation - * applied to the content of XRb and XRc. - */ -static void gen_mxu_S32AND(DisasContext *ctx) -{ - uint32_t pad, XRc, XRb, XRa; - - pad =3D extract32(ctx->opcode, 21, 5); - XRc =3D extract32(ctx->opcode, 14, 4); - XRb =3D extract32(ctx->opcode, 10, 4); - XRa =3D extract32(ctx->opcode, 6, 4); - - if (unlikely(pad !=3D 0)) { - /* opcode padding incorrect -> do nothing */ - } else if (unlikely(XRa =3D=3D 0)) { - /* destination is zero register -> do nothing */ - } else if (unlikely((XRb =3D=3D 0) || (XRc =3D=3D 0))) { - /* one of operands zero register -> just set destination to all 0s= */ - tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); - } else if (unlikely(XRb =3D=3D XRc)) { - /* both operands same -> just set destination to one of them */ - tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); - } else { - /* the most general case */ - tcg_gen_and_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], mxu_gpr[XRc - = 1]); - } -} - -/* - * S32OR XRa, XRb, XRc - * Update XRa with the result of logical bitwise 'or' operation - * applied to the content of XRb and XRc. - */ -static void gen_mxu_S32OR(DisasContext *ctx) -{ - uint32_t pad, XRc, XRb, XRa; - - pad =3D extract32(ctx->opcode, 21, 5); - XRc =3D extract32(ctx->opcode, 14, 4); - XRb =3D extract32(ctx->opcode, 10, 4); - XRa =3D extract32(ctx->opcode, 6, 4); - - if (unlikely(pad !=3D 0)) { - /* opcode padding incorrect -> do nothing */ - } else if (unlikely(XRa =3D=3D 0)) { - /* destination is zero register -> do nothing */ - } else if (unlikely((XRb =3D=3D 0) && (XRc =3D=3D 0))) { - /* both operands zero registers -> just set destination to all 0s = */ - tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); - } else if (unlikely(XRb =3D=3D 0)) { - /* XRb zero register -> just set destination to the content of XRc= */ - tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRc - 1]); - } else if (unlikely(XRc =3D=3D 0)) { - /* XRc zero register -> just set destination to the content of XRb= */ - tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); - } else if (unlikely(XRb =3D=3D XRc)) { - /* both operands same -> just set destination to one of them */ - tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); - } else { - /* the most general case */ - tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], mxu_gpr[XRc - 1= ]); - } -} - -/* - * S32XOR XRa, XRb, XRc - * Update XRa with the result of logical bitwise 'xor' operation - * applied to the content of XRb and XRc. - */ -static void gen_mxu_S32XOR(DisasContext *ctx) -{ - uint32_t pad, XRc, XRb, XRa; - - pad =3D extract32(ctx->opcode, 21, 5); - XRc =3D extract32(ctx->opcode, 14, 4); - XRb =3D extract32(ctx->opcode, 10, 4); - XRa =3D extract32(ctx->opcode, 6, 4); - - if (unlikely(pad !=3D 0)) { - /* opcode padding incorrect -> do nothing */ - } else if (unlikely(XRa =3D=3D 0)) { - /* destination is zero register -> do nothing */ - } else if (unlikely((XRb =3D=3D 0) && (XRc =3D=3D 0))) { - /* both operands zero registers -> just set destination to all 0s = */ - tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); - } else if (unlikely(XRb =3D=3D 0)) { - /* XRb zero register -> just set destination to the content of XRc= */ - tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRc - 1]); - } else if (unlikely(XRc =3D=3D 0)) { - /* XRc zero register -> just set destination to the content of XRb= */ - tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); - } else if (unlikely(XRb =3D=3D XRc)) { - /* both operands same -> just set destination to all 0s */ - tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); - } else { - /* the most general case */ - tcg_gen_xor_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], mxu_gpr[XRc - = 1]); - } -} - - -/* - * MXU instruction category max/min - * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - * - * S32MAX D16MAX Q8MAX - * S32MIN D16MIN Q8MIN - */ - -/* - * S32MAX XRa, XRb, XRc - * Update XRa with the maximum of signed 32-bit integers contained - * in XRb and XRc. - * - * S32MIN XRa, XRb, XRc - * Update XRa with the minimum of signed 32-bit integers contained - * in XRb and XRc. - */ -static void gen_mxu_S32MAX_S32MIN(DisasContext *ctx) -{ - uint32_t pad, opc, XRc, XRb, XRa; - - pad =3D extract32(ctx->opcode, 21, 5); - opc =3D extract32(ctx->opcode, 18, 3); - XRc =3D extract32(ctx->opcode, 14, 4); - XRb =3D extract32(ctx->opcode, 10, 4); - XRa =3D extract32(ctx->opcode, 6, 4); - - if (unlikely(pad !=3D 0)) { - /* opcode padding incorrect -> do nothing */ - } else if (unlikely(XRa =3D=3D 0)) { - /* destination is zero register -> do nothing */ - } else if (unlikely((XRb =3D=3D 0) && (XRc =3D=3D 0))) { - /* both operands zero registers -> just set destination to zero */ - tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); - } else if (unlikely((XRb =3D=3D 0) || (XRc =3D=3D 0))) { - /* exactly one operand is zero register - find which one is not...= */ - uint32_t XRx =3D XRb ? XRb : XRc; - /* ...and do max/min operation with one operand 0 */ - if (opc =3D=3D OPC_MXU_S32MAX) { - tcg_gen_smax_i32(mxu_gpr[XRa - 1], mxu_gpr[XRx - 1], 0); - } else { - tcg_gen_smin_i32(mxu_gpr[XRa - 1], mxu_gpr[XRx - 1], 0); - } - } else if (unlikely(XRb =3D=3D XRc)) { - /* both operands same -> just set destination to one of them */ - tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); - } else { - /* the most general case */ - if (opc =3D=3D OPC_MXU_S32MAX) { - tcg_gen_smax_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], - mxu_gpr[XRc - 1]); - } else { - tcg_gen_smin_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], - mxu_gpr[XRc - 1]); - } - } -} - -/* - * D16MAX - * Update XRa with the 16-bit-wise maximums of signed integers - * contained in XRb and XRc. - * - * D16MIN - * Update XRa with the 16-bit-wise minimums of signed integers - * contained in XRb and XRc. - */ -static void gen_mxu_D16MAX_D16MIN(DisasContext *ctx) -{ - uint32_t pad, opc, XRc, XRb, XRa; - - pad =3D extract32(ctx->opcode, 21, 5); - opc =3D extract32(ctx->opcode, 18, 3); - XRc =3D extract32(ctx->opcode, 14, 4); - XRb =3D extract32(ctx->opcode, 10, 4); - XRa =3D extract32(ctx->opcode, 6, 4); - - if (unlikely(pad !=3D 0)) { - /* opcode padding incorrect -> do nothing */ - } else if (unlikely(XRc =3D=3D 0)) { - /* destination is zero register -> do nothing */ - } else if (unlikely((XRb =3D=3D 0) && (XRa =3D=3D 0))) { - /* both operands zero registers -> just set destination to zero */ - tcg_gen_movi_i32(mxu_gpr[XRc - 1], 0); - } else if (unlikely((XRb =3D=3D 0) || (XRa =3D=3D 0))) { - /* exactly one operand is zero register - find which one is not...= */ - uint32_t XRx =3D XRb ? XRb : XRc; - /* ...and do half-word-wise max/min with one operand 0 */ - TCGv_i32 t0 =3D tcg_temp_new(); - TCGv_i32 t1 =3D tcg_const_i32(0); - - /* the left half-word first */ - tcg_gen_andi_i32(t0, mxu_gpr[XRx - 1], 0xFFFF0000); - if (opc =3D=3D OPC_MXU_D16MAX) { - tcg_gen_smax_i32(mxu_gpr[XRa - 1], t0, t1); - } else { - tcg_gen_smin_i32(mxu_gpr[XRa - 1], t0, t1); - } - - /* the right half-word */ - tcg_gen_andi_i32(t0, mxu_gpr[XRx - 1], 0x0000FFFF); - /* move half-words to the leftmost position */ - tcg_gen_shli_i32(t0, t0, 16); - /* t0 will be max/min of t0 and t1 */ - if (opc =3D=3D OPC_MXU_D16MAX) { - tcg_gen_smax_i32(t0, t0, t1); - } else { - tcg_gen_smin_i32(t0, t0, t1); - } - /* return resulting half-words to its original position */ - tcg_gen_shri_i32(t0, t0, 16); - /* finally update the destination */ - tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0); - - tcg_temp_free(t1); - tcg_temp_free(t0); - } else if (unlikely(XRb =3D=3D XRc)) { - /* both operands same -> just set destination to one of them */ - tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); - } else { - /* the most general case */ - TCGv_i32 t0 =3D tcg_temp_new(); - TCGv_i32 t1 =3D tcg_temp_new(); - - /* the left half-word first */ - tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0xFFFF0000); - tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0xFFFF0000); - if (opc =3D=3D OPC_MXU_D16MAX) { - tcg_gen_smax_i32(mxu_gpr[XRa - 1], t0, t1); - } else { - tcg_gen_smin_i32(mxu_gpr[XRa - 1], t0, t1); - } - - /* the right half-word */ - tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0x0000FFFF); - tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0x0000FFFF); - /* move half-words to the leftmost position */ - tcg_gen_shli_i32(t0, t0, 16); - tcg_gen_shli_i32(t1, t1, 16); - /* t0 will be max/min of t0 and t1 */ - if (opc =3D=3D OPC_MXU_D16MAX) { - tcg_gen_smax_i32(t0, t0, t1); - } else { - tcg_gen_smin_i32(t0, t0, t1); - } - /* return resulting half-words to its original position */ - tcg_gen_shri_i32(t0, t0, 16); - /* finally update the destination */ - tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0); - - tcg_temp_free(t1); - tcg_temp_free(t0); - } -} - -/* - * Q8MAX - * Update XRa with the 8-bit-wise maximums of signed integers - * contained in XRb and XRc. - * - * Q8MIN - * Update XRa with the 8-bit-wise minimums of signed integers - * contained in XRb and XRc. - */ -static void gen_mxu_Q8MAX_Q8MIN(DisasContext *ctx) -{ - uint32_t pad, opc, XRc, XRb, XRa; - - pad =3D extract32(ctx->opcode, 21, 5); - opc =3D extract32(ctx->opcode, 18, 3); - XRc =3D extract32(ctx->opcode, 14, 4); - XRb =3D extract32(ctx->opcode, 10, 4); - XRa =3D extract32(ctx->opcode, 6, 4); - - if (unlikely(pad !=3D 0)) { - /* opcode padding incorrect -> do nothing */ - } else if (unlikely(XRa =3D=3D 0)) { - /* destination is zero register -> do nothing */ - } else if (unlikely((XRb =3D=3D 0) && (XRc =3D=3D 0))) { - /* both operands zero registers -> just set destination to zero */ - tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); - } else if (unlikely((XRb =3D=3D 0) || (XRc =3D=3D 0))) { - /* exactly one operand is zero register - make it be the first...*/ - uint32_t XRx =3D XRb ? XRb : XRc; - /* ...and do byte-wise max/min with one operand 0 */ - TCGv_i32 t0 =3D tcg_temp_new(); - TCGv_i32 t1 =3D tcg_const_i32(0); - int32_t i; - - /* the leftmost byte (byte 3) first */ - tcg_gen_andi_i32(t0, mxu_gpr[XRx - 1], 0xFF000000); - if (opc =3D=3D OPC_MXU_Q8MAX) { - tcg_gen_smax_i32(mxu_gpr[XRa - 1], t0, t1); - } else { - tcg_gen_smin_i32(mxu_gpr[XRa - 1], t0, t1); - } - - /* bytes 2, 1, 0 */ - for (i =3D 2; i >=3D 0; i--) { - /* extract the byte */ - tcg_gen_andi_i32(t0, mxu_gpr[XRx - 1], 0xFF << (8 * i)); - /* move the byte to the leftmost position */ - tcg_gen_shli_i32(t0, t0, 8 * (3 - i)); - /* t0 will be max/min of t0 and t1 */ - if (opc =3D=3D OPC_MXU_Q8MAX) { - tcg_gen_smax_i32(t0, t0, t1); - } else { - tcg_gen_smin_i32(t0, t0, t1); - } - /* return resulting byte to its original position */ - tcg_gen_shri_i32(t0, t0, 8 * (3 - i)); - /* finally update the destination */ - tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0); - } - - tcg_temp_free(t1); - tcg_temp_free(t0); - } else if (unlikely(XRb =3D=3D XRc)) { - /* both operands same -> just set destination to one of them */ - tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); - } else { - /* the most general case */ - TCGv_i32 t0 =3D tcg_temp_new(); - TCGv_i32 t1 =3D tcg_temp_new(); - int32_t i; - - /* the leftmost bytes (bytes 3) first */ - tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0xFF000000); - tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0xFF000000); - if (opc =3D=3D OPC_MXU_Q8MAX) { - tcg_gen_smax_i32(mxu_gpr[XRa - 1], t0, t1); - } else { - tcg_gen_smin_i32(mxu_gpr[XRa - 1], t0, t1); - } - - /* bytes 2, 1, 0 */ - for (i =3D 2; i >=3D 0; i--) { - /* extract corresponding bytes */ - tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0xFF << (8 * i)); - tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0xFF << (8 * i)); - /* move the bytes to the leftmost position */ - tcg_gen_shli_i32(t0, t0, 8 * (3 - i)); - tcg_gen_shli_i32(t1, t1, 8 * (3 - i)); - /* t0 will be max/min of t0 and t1 */ - if (opc =3D=3D OPC_MXU_Q8MAX) { - tcg_gen_smax_i32(t0, t0, t1); - } else { - tcg_gen_smin_i32(t0, t0, t1); - } - /* return resulting byte to its original position */ - tcg_gen_shri_i32(t0, t0, 8 * (3 - i)); - /* finally update the destination */ - tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0); - } - - tcg_temp_free(t1); - tcg_temp_free(t0); - } -} - - -/* - * MXU instruction category: align - * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - * - * S32ALN S32ALNI - */ - -/* - * S32ALNI XRc, XRb, XRa, optn3 - * Arrange bytes from XRb and XRc according to one of five sets of - * rules determined by optn3, and place the result in XRa. - */ -static void gen_mxu_S32ALNI(DisasContext *ctx) -{ - uint32_t optn3, pad, XRc, XRb, XRa; - - optn3 =3D extract32(ctx->opcode, 23, 3); - pad =3D extract32(ctx->opcode, 21, 2); - XRc =3D extract32(ctx->opcode, 14, 4); - XRb =3D extract32(ctx->opcode, 10, 4); - XRa =3D extract32(ctx->opcode, 6, 4); - - if (unlikely(pad !=3D 0)) { - /* opcode padding incorrect -> do nothing */ - } else if (unlikely(XRa =3D=3D 0)) { - /* destination is zero register -> do nothing */ - } else if (unlikely((XRb =3D=3D 0) && (XRc =3D=3D 0))) { - /* both operands zero registers -> just set destination to all 0s = */ - tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); - } else if (unlikely(XRb =3D=3D 0)) { - /* XRb zero register -> just appropriatelly shift XRc into XRa */ - switch (optn3) { - case MXU_OPTN3_PTN0: - tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); - break; - case MXU_OPTN3_PTN1: - case MXU_OPTN3_PTN2: - case MXU_OPTN3_PTN3: - tcg_gen_shri_i32(mxu_gpr[XRa - 1], mxu_gpr[XRc - 1], - 8 * (4 - optn3)); - break; - case MXU_OPTN3_PTN4: - tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRc - 1]); - break; - } - } else if (unlikely(XRc =3D=3D 0)) { - /* XRc zero register -> just appropriatelly shift XRb into XRa */ - switch (optn3) { - case MXU_OPTN3_PTN0: - tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); - break; - case MXU_OPTN3_PTN1: - case MXU_OPTN3_PTN2: - case MXU_OPTN3_PTN3: - tcg_gen_shri_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], 8 * optn3= ); - break; - case MXU_OPTN3_PTN4: - tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); - break; - } - } else if (unlikely(XRb =3D=3D XRc)) { - /* both operands same -> just rotation or moving from any of them = */ - switch (optn3) { - case MXU_OPTN3_PTN0: - case MXU_OPTN3_PTN4: - tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); - break; - case MXU_OPTN3_PTN1: - case MXU_OPTN3_PTN2: - case MXU_OPTN3_PTN3: - tcg_gen_rotli_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], 8 * optn= 3); - break; - } - } else { - /* the most general case */ - switch (optn3) { - case MXU_OPTN3_PTN0: - { - /* */ - /* XRb XRc */ - /* +---------------+ */ - /* | A B C D | E F G H */ - /* +-------+-------+ */ - /* | */ - /* XRa */ - /* */ - - tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); - } - break; - case MXU_OPTN3_PTN1: - { - /* */ - /* XRb XRc */ - /* +-------------------+ */ - /* A | B C D E | F G H */ - /* +---------+---------+ */ - /* | */ - /* XRa */ - /* */ - - TCGv_i32 t0 =3D tcg_temp_new(); - TCGv_i32 t1 =3D tcg_temp_new(); - - tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0x00FFFFFF); - tcg_gen_shli_i32(t0, t0, 8); - - tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0xFF000000); - tcg_gen_shri_i32(t1, t1, 24); - - tcg_gen_or_i32(mxu_gpr[XRa - 1], t0, t1); - - tcg_temp_free(t1); - tcg_temp_free(t0); - } - break; - case MXU_OPTN3_PTN2: - { - /* */ - /* XRb XRc */ - /* +-------------------+ */ - /* A B | C D E F | G H */ - /* +---------+---------+ */ - /* | */ - /* XRa */ - /* */ - - TCGv_i32 t0 =3D tcg_temp_new(); - TCGv_i32 t1 =3D tcg_temp_new(); - - tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0x0000FFFF); - tcg_gen_shli_i32(t0, t0, 16); - - tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0xFFFF0000); - tcg_gen_shri_i32(t1, t1, 16); - - tcg_gen_or_i32(mxu_gpr[XRa - 1], t0, t1); - - tcg_temp_free(t1); - tcg_temp_free(t0); - } - break; - case MXU_OPTN3_PTN3: - { - /* */ - /* XRb XRc */ - /* +-------------------+ */ - /* A B C | D E F G | H */ - /* +---------+---------+ */ - /* | */ - /* XRa */ - /* */ - - TCGv_i32 t0 =3D tcg_temp_new(); - TCGv_i32 t1 =3D tcg_temp_new(); - - tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0x000000FF); - tcg_gen_shli_i32(t0, t0, 24); - - tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0xFFFFFF00); - tcg_gen_shri_i32(t1, t1, 8); - - tcg_gen_or_i32(mxu_gpr[XRa - 1], t0, t1); - - tcg_temp_free(t1); - tcg_temp_free(t0); - } - break; - case MXU_OPTN3_PTN4: - { - /* */ - /* XRb XRc */ - /* +---------------+ */ - /* A B C D | E F G H | */ - /* +-------+-------+ */ - /* | */ - /* XRa */ - /* */ - - tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRc - 1]); - } - break; - } - } -} - - -/* - * Decoding engine for MXU - * =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D - */ - -static void decode_opc_mxu__pool00(DisasContext *ctx) -{ - uint32_t opcode =3D extract32(ctx->opcode, 18, 3); - - switch (opcode) { - case OPC_MXU_S32MAX: - case OPC_MXU_S32MIN: - gen_mxu_S32MAX_S32MIN(ctx); - break; - case OPC_MXU_D16MAX: - case OPC_MXU_D16MIN: - gen_mxu_D16MAX_D16MIN(ctx); - break; - case OPC_MXU_Q8MAX: - case OPC_MXU_Q8MIN: - gen_mxu_Q8MAX_Q8MIN(ctx); - break; - default: - MIPS_INVAL("decode_opc_mxu"); - gen_reserved_instruction(ctx); - break; - } -} - -static void decode_opc_mxu__pool04(DisasContext *ctx) -{ - uint32_t opcode =3D extract32(ctx->opcode, 20, 1); - - switch (opcode) { - case OPC_MXU_S32LDD: - case OPC_MXU_S32LDDR: - gen_mxu_s32ldd_s32lddr(ctx); - break; - default: - MIPS_INVAL("decode_opc_mxu"); - gen_reserved_instruction(ctx); - break; - } -} - -static void decode_opc_mxu__pool16(DisasContext *ctx) -{ - uint32_t opcode =3D extract32(ctx->opcode, 18, 3); - - switch (opcode) { - case OPC_MXU_S32ALNI: - gen_mxu_S32ALNI(ctx); - break; - case OPC_MXU_S32NOR: - gen_mxu_S32NOR(ctx); - break; - case OPC_MXU_S32AND: - gen_mxu_S32AND(ctx); - break; - case OPC_MXU_S32OR: - gen_mxu_S32OR(ctx); - break; - case OPC_MXU_S32XOR: - gen_mxu_S32XOR(ctx); - break; - default: - MIPS_INVAL("decode_opc_mxu"); - gen_reserved_instruction(ctx); - break; - } -} - -static void decode_opc_mxu__pool19(DisasContext *ctx) -{ - uint32_t opcode =3D extract32(ctx->opcode, 22, 2); - - switch (opcode) { - case OPC_MXU_Q8MUL: - case OPC_MXU_Q8MULSU: - gen_mxu_q8mul_q8mulsu(ctx); - break; - default: - MIPS_INVAL("decode_opc_mxu"); - gen_reserved_instruction(ctx); - break; - } -} - -/* - * Main MXU decoding function - */ -bool decode_ase_mxu(DisasContext *ctx, uint32_t insn) -{ - uint32_t opcode =3D extract32(insn, 0, 6); - - if (opcode =3D=3D OPC_MXU_S32M2I) { - gen_mxu_s32m2i(ctx); - return true; - } - - if (opcode =3D=3D OPC_MXU_S32I2M) { - gen_mxu_s32i2m(ctx); - return true; - } - - { - TCGv t_mxu_cr =3D tcg_temp_new(); - TCGLabel *l_exit =3D gen_new_label(); - - gen_load_mxu_cr(t_mxu_cr); - tcg_gen_andi_tl(t_mxu_cr, t_mxu_cr, MXU_CR_MXU_EN); - tcg_gen_brcondi_tl(TCG_COND_NE, t_mxu_cr, MXU_CR_MXU_EN, l_exit); - - switch (opcode) { - case OPC_MXU__POOL00: - decode_opc_mxu__pool00(ctx); - break; - case OPC_MXU_D16MUL: - gen_mxu_d16mul(ctx); - break; - case OPC_MXU_D16MAC: - gen_mxu_d16mac(ctx); - break; - case OPC_MXU__POOL04: - decode_opc_mxu__pool04(ctx); - break; - case OPC_MXU_S8LDD: - gen_mxu_s8ldd(ctx); - break; - case OPC_MXU__POOL16: - decode_opc_mxu__pool16(ctx); - break; - case OPC_MXU__POOL19: - decode_opc_mxu__pool19(ctx); - break; - default: - MIPS_INVAL("decode_opc_mxu"); - gen_reserved_instruction(ctx); - } - - gen_set_label(l_exit); - tcg_temp_free(t_mxu_cr); - } - - return true; -} - -#endif /* !defined(TARGET_MIPS64) */ - - static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ct= x) { int rs, rt, rd; diff --git a/target/mips/meson.build b/target/mips/meson.build index 53580633ce0..4a951e522d4 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -24,6 +24,10 @@ 'translate.c', 'translate_addr_const.c', )) +mips_tcg_ss.add(when: 'TARGET_MIPS64', if_false: files( + 'mxu_translate.c', +)) + mips_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) =20 mips_softmmu_ss =3D ss.source_set() --=20 2.26.2 From nobody Sat May 18 21:45:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.44 as permitted sender) client-ip=209.85.221.44; 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[88.21.201.17]) by smtp.gmail.com with ESMTPSA id f22sm7274974wmc.33.2021.03.13.11.50.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Mar 2021 11:50:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dJN4s/QBRDf82xfd1MF/HucGEm4ujocGtjrEvCQHbMw=; b=gAhE3tx1POQ3OoeOFNygvXYvWClFEd/fefUJKUquXE+lAJtBabNBf1OPhcgLdlfw2Q UPftBL5i9XmJ0ZOkXGnLvTb0SGjA6KTalb57M3L3RzC/IWa45x7BN5WAghH8WLwQcAkf c6IefHoOCuxxUixcmlqNf6zEqNpJDoY5SwPVZP/Gj0CfIUS9zKRo7plhhTb0Ks4PCMMm aE5QmdT+Lj9WlSyGzX6yFabj1xrLFA17PVnAU8iRxyoypEXA/JJem6SOMRUPtSXP3ZgM b8VlnoguamzqJNsimVXmh0zIuTBLbm5UrDa2raG7E+QwQzApz8wIpfo7Z9o+zoEAaOms ZSMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=dJN4s/QBRDf82xfd1MF/HucGEm4ujocGtjrEvCQHbMw=; b=UMJr7ALI1j8NkYS4jlc4OZJTHNiqzfAgo23lkV0VC2dvUsJzuPGK6VI4togz4P22qa 8d0hoTvDZkg+sUVIYNr0Olg2M5vmz1OPeDUGLGxDb0nF2h3Im+HyCgxMl5EGE068Y0IJ wVvmYivfIN4fEsOffmwiX0EGisUoo8kWXr7bgqZ7RprZbrtSw3M2mQSflLI6JVJwKGHY DxszhSzuailYczvxNwo1umv9eWswcv9gkZdaKIh0LU9b/qnsMNQ38+xdnpcz2FL6iChr niQ11Ac33DhcFg1jxREQxEHtIwfMTBWJIm3EqUVNCeNZMbP0DN0+BgjVZ809ol5Sd771 KmWQ== X-Gm-Message-State: AOAM532NfstFlU7j66OzYCgPJiVrOlA2JyeeJzFh+rrXKqizJxvw9swM A4DA68rGH4pJuShi4GnZ188= X-Google-Smtp-Source: ABdhPJwtHrLJ6hyr7BojDEHEzUchrWi4k1M3DmrDsB6bPlLq+4GQs/PZhRzybflJ8BoaRvy28AQb7Q== X-Received: by 2002:adf:de92:: with SMTP id w18mr19877087wrl.217.1615665007195; Sat, 13 Mar 2021 11:50:07 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 19/27] target/mips: Use gen_load_gpr[_hi]() when possible Date: Sat, 13 Mar 2021 20:48:21 +0100 Message-Id: <20210313194829.2193621-20-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210313194829.2193621-1-f4bug@amsat.org> References: <20210313194829.2193621-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Use gen_load_gpr[_hi]() instead of open coding it. Patch generated using the following spatch script: @gen_load_gpr@ identifier reg_idx; expression tcg_reg; @@ -if (reg_idx =3D=3D 0) { - tcg_gen_movi_tl(tcg_reg, 0); -} else { - tcg_gen_mov_tl(tcg_reg, cpu_gpr[reg_idx]); -} +gen_load_gpr(tcg_reg, reg_idx); @gen_load_gpr_hi@ identifier reg_idx; expression tcg_reg; @@ -if (reg_idx =3D=3D 0) { - tcg_gen_movi_i64(tcg_reg, 0); -} else { - tcg_gen_mov_i64(tcg_reg, cpu_gpr_hi[reg_idx]); -} +gen_load_gpr_hi(tcg_reg, reg_idx); Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20210308131604.460693-1-f4bug@amsat.org> --- target/mips/translate.c | 29 ++++++----------------------- 1 file changed, 6 insertions(+), 23 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 92dcd2a54be..d1335b9f9f8 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -10460,11 +10460,7 @@ static void gen_movci(DisasContext *ctx, int rd, i= nt rs, int cc, int tf) tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc)); tcg_gen_brcondi_i32(cond, t0, 0, l1); tcg_temp_free_i32(t0); - if (rs =3D=3D 0) { - tcg_gen_movi_tl(cpu_gpr[rd], 0); - } else { - tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]); - } + gen_load_gpr(cpu_gpr[rd], rs); gen_set_label(l1); } =20 @@ -14794,24 +14790,15 @@ static void gen_pool16c_insn(DisasContext *ctx) static inline void gen_movep(DisasContext *ctx, int enc_dest, int enc_rt, int enc_rs) { - int rd, rs, re, rt; + int rd, re; static const int rd_enc[] =3D { 5, 5, 6, 4, 4, 4, 4, 4 }; static const int re_enc[] =3D { 6, 7, 7, 21, 22, 5, 6, 7 }; static const int rs_rt_enc[] =3D { 0, 17, 2, 3, 16, 18, 19, 20 }; + rd =3D rd_enc[enc_dest]; re =3D re_enc[enc_dest]; - rs =3D rs_rt_enc[enc_rs]; - rt =3D rs_rt_enc[enc_rt]; - if (rs) { - tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]); - } else { - tcg_gen_movi_tl(cpu_gpr[rd], 0); - } - if (rt) { - tcg_gen_mov_tl(cpu_gpr[re], cpu_gpr[rt]); - } else { - tcg_gen_movi_tl(cpu_gpr[re], 0); - } + gen_load_gpr(cpu_gpr[rd], rs_rt_enc[enc_rs]); + gen_load_gpr(cpu_gpr[re], rs_rt_enc[enc_rt]); } =20 static void gen_pool16c_r6_insn(DisasContext *ctx) @@ -24229,11 +24216,7 @@ static void gen_mmi_pcpyud(DisasContext *ctx) if (rd =3D=3D 0) { /* nop */ } else { - if (rs =3D=3D 0) { - tcg_gen_movi_i64(cpu_gpr[rd], 0); - } else { - tcg_gen_mov_i64(cpu_gpr[rd], cpu_gpr_hi[rs]); - } + gen_load_gpr_hi(cpu_gpr[rd], rs); if (rt =3D=3D 0) { tcg_gen_movi_i64(cpu_gpr_hi[rd], 0); } else { --=20 2.26.2 From nobody Sat May 18 21:45:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.45 as permitted sender) client-ip=209.85.128.45; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f45.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.45 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1615665014; cv=none; d=zohomail.com; s=zohoarc; b=ShcszXux5QaF5XCAMpJUEiA8tJq8fyvLaIKCg5FZ+e/AdaQJCyCaEI97HwV+kIkRq4aUhoEoAGKQcZa+2snPp5R2LPeeBXNc6suxcKgtP4X4M7YM9pdJhY9O06vbDzbTkqm26RAwiYRu60P8xeEBm8tVJVhv5OUfqs3kZokvKZU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615665014; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=M6qu/V/LZSxJJIwYYckhLhw6x7JacwSDJzKHt1IT84Q=; b=Ke2D3awbj/7oOm3YQXR7bNKjg45fPFTO61zNUheq+ol8CKRTnAZmpbYX1+TBJa6HFDseNNN+wNmAiUvL5r6X696TLrY+7otZ9bc/3Rv+qeKeXOC6tLZeAs3EI/o9YYqPFpAxP5Tixe7f19UXIzkkz3CnLGmt7E/QFi5vJ2SxNG4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.45 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) by mx.zohomail.com with SMTPS id 1615665014046985.9027187215801; Sat, 13 Mar 2021 11:50:14 -0800 (PST) Received: by mail-wm1-f45.google.com with SMTP id r10-20020a05600c35cab029010c946c95easo17113077wmq.4 for ; Sat, 13 Mar 2021 11:50:13 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (17.red-88-21-201.staticip.rima-tde.net. [88.21.201.17]) by smtp.gmail.com with ESMTPSA id i8sm13785852wrx.43.2021.03.13.11.50.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Mar 2021 11:50:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=M6qu/V/LZSxJJIwYYckhLhw6x7JacwSDJzKHt1IT84Q=; b=kn+saM9TtvzQW4pK2eUCT2sy3sMf8tj1OTmU0vzlBVs41fcDCiMKZ5RpBeKEvb7cCq e0beRdgn8VF39YaK8YPwcRdq1mlJ+atTYBe0IB1e2Uv4eAYdlTVPKItQbu6i9+ZAM0oq eqJw5pN0VDbDxRFgKZklHYegmUzBoUzE7X1nkWItAyzXuSjvALWSK2pXMYeDhGFPuLT/ W8v+5Qd1BsdkuL6GZiXCPMbGem3U4pd8f/bdAMrdaz1rqyDT/D+lPfGSsJsYzqswR6ge gqOuN+F5FTA5DjYnTUWJxLcp8vlE1S8+uWAds3DH1fJDRdwyMbznfAc6CwGg9GgCpsgq u31Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=M6qu/V/LZSxJJIwYYckhLhw6x7JacwSDJzKHt1IT84Q=; b=XiwKRdlS6R4lqKL5fcEZ5nuu61c3gmd6lvtlVNs23sKd9uEptKLdlJVaHLXEtMn1Mv UMN4s92fvSrQFgb4+xoiWd1nXMNy+k3LTGmxLb6NHb2zSvjfOkE7hFq1xEkLuWFdXw5g 9HnjdvrKN/MwHKuXSsqF/cZMjiX2sKqrRrASZoBUGQpg6syKQk+Q38U4vcJXsi+DhV6c 67fK7WBbmiNj5Nt6jB1EcdY3XaMFIUU2sdM1ejuS0jixsMZAiXzPPFCB3An5aoJyrEdD xD3AutyZpjwn9fo9ZFvSePaPJWrEWgsC8QfCVaoIUXZvMXfhJH+FvgPCBSE1bx9fSjHP 8MpA== X-Gm-Message-State: AOAM532mTsEPW1TqnjqkkCi7SpcvjjIrt42AxNouWN06HUx/bAOyrHWx DA7zpstqV/B8uF73Yo841kM= X-Google-Smtp-Source: ABdhPJzuwHV3kJN84n6ObptA/ghd0PL47MQwMYMqSXcp+zQyKeIdmwFof+7vdyP2LqloFhT75leenA== X-Received: by 2002:a05:600c:190a:: with SMTP id j10mr18841269wmq.140.1615665012206; Sat, 13 Mar 2021 11:50:12 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 20/27] target/mips/tx79: Move MFHI1 / MFLO1 opcodes to decodetree Date: Sat, 13 Mar 2021 20:48:22 +0100 Message-Id: <20210313194829.2193621-21-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210313194829.2193621-1-f4bug@amsat.org> References: <20210313194829.2193621-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Introduce decodetree structure to decode the tx79 opcodes. Start it by moving the existing MFHI1 and MFLO1 opcodes. Remove unnecessary comments. As the TX79 share opcodes with the TX19/TX39/TX49 CPUs, we introduce the decode_ext_txx9() dispatcher where we will add the other decoders later. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20210214175912.732946-9-f4bug@amsat.org> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/translate.h | 4 ++++ target/mips/tx79.decode | 25 ++++++++++++++++++++++++ target/mips/translate.c | 15 +++------------ target/mips/tx79_translate.c | 37 ++++++++++++++++++++++++++++++++++++ target/mips/txx9_translate.c | 20 +++++++++++++++++++ target/mips/meson.build | 5 +++++ 6 files changed, 94 insertions(+), 12 deletions(-) create mode 100644 target/mips/tx79.decode create mode 100644 target/mips/tx79_translate.c create mode 100644 target/mips/txx9_translate.c diff --git a/target/mips/translate.h b/target/mips/translate.h index a807b3d2566..e4f2f26de89 100644 --- a/target/mips/translate.h +++ b/target/mips/translate.h @@ -185,5 +185,9 @@ bool decode_ase_mxu(DisasContext *ctx, uint32_t insn); /* decodetree generated */ bool decode_isa_rel6(DisasContext *ctx, uint32_t insn); bool decode_ase_msa(DisasContext *ctx, uint32_t insn); +bool decode_ext_txx9(DisasContext *ctx, uint32_t insn); +#if defined(TARGET_MIPS64) +bool decode_ext_tx79(DisasContext *ctx, uint32_t insn); +#endif =20 #endif diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode new file mode 100644 index 00000000000..2e287ebbf36 --- /dev/null +++ b/target/mips/tx79.decode @@ -0,0 +1,25 @@ +# Toshiba C790's instruction set +# +# Copyright (C) 2021 Philippe Mathieu-Daud=C3=A9 +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# +# Toshiba Appendix B C790-Specific Instruction Set Details + +########################################################################### +# Named attribute sets. These are used to make nice(er) names +# when creating helpers common to those for the individual +# instruction patterns. + +&rtype rs rt rd sa + +########################################################################### +# Named instruction formats. These are generally used to +# reduce the amount of duplication between instruction patterns. + +@rd ...... .......... rd:5 ..... ...... &rtype rs=3D0 rt= =3D0 sa=3D0 + +########################################################################### + +MFHI1 011100 0000000000 ..... 00000 010000 @rd +MFLO1 011100 0000000000 ..... 00000 010010 @rd diff --git a/target/mips/translate.c b/target/mips/translate.c index d1335b9f9f8..889c89696b1 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1360,9 +1360,7 @@ enum { MMI_OPC_PLZCW =3D 0x04 | MMI_OPC_CLASS_MMI, MMI_OPC_CLASS_MMI0 =3D 0x08 | MMI_OPC_CLASS_MMI, MMI_OPC_CLASS_MMI2 =3D 0x09 | MMI_OPC_CLASS_MMI, - MMI_OPC_MFHI1 =3D 0x10 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_= MFHI */ MMI_OPC_MTHI1 =3D 0x11 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_= MTHI */ - MMI_OPC_MFLO1 =3D 0x12 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_= MFLO */ MMI_OPC_MTLO1 =3D 0x13 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_= MTLO */ MMI_OPC_MULT1 =3D 0x18 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_= MULT */ MMI_OPC_MULTU1 =3D 0x19 | MMI_OPC_CLASS_MMI, /* Same min. as OPC_M= ULTU */ @@ -3469,12 +3467,6 @@ static void gen_shift(DisasContext *ctx, uint32_t op= c, static void gen_HILO1_tx79(DisasContext *ctx, uint32_t opc, int reg) { switch (opc) { - case MMI_OPC_MFHI1: - gen_store_gpr(cpu_HI[1], reg); - break; - case MMI_OPC_MFLO1: - gen_store_gpr(cpu_LO[1], reg); - break; case MMI_OPC_MTHI1: gen_load_gpr(cpu_HI[1], reg); break; @@ -25120,10 +25112,6 @@ static void decode_mmi(CPUMIPSState *env, DisasCon= text *ctx) case MMI_OPC_MTHI1: gen_HILO1_tx79(ctx, opc, rs); break; - case MMI_OPC_MFLO1: - case MMI_OPC_MFHI1: - gen_HILO1_tx79(ctx, opc, rd); - break; case MMI_OPC_PLZCW: /* TODO: MMI_OPC_PLZCW */ case MMI_OPC_PMFHL: /* TODO: MMI_OPC_PMFHL */ case MMI_OPC_PMTHL: /* TODO: MMI_OPC_PMTHL */ @@ -26095,6 +26083,9 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) if (cpu_supports_isa(env, ISA_MIPS_R6) && decode_isa_rel6(ctx, ctx->op= code)) { return; } + if (cpu_supports_isa(env, INSN_R5900) && decode_ext_txx9(ctx, ctx->opc= ode)) { + return; + } =20 if (decode_opc_legacy(env, ctx)) { return; diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c new file mode 100644 index 00000000000..22bd6033e55 --- /dev/null +++ b/target/mips/tx79_translate.c @@ -0,0 +1,37 @@ +/* + * Toshiba TX79-specific instructions translation routines + * + * Copyright (c) 2018 Fredrik Noring + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "tcg/tcg-op.h" +#include "exec/helper-gen.h" +#include "translate.h" + +/* Include the auto-generated decoder. */ +#include "decode-tx79.c.inc" + +bool decode_ext_tx79(DisasContext *ctx, uint32_t insn) +{ + if (TARGET_LONG_BITS =3D=3D 64 && decode_tx79(ctx, insn)) { + return true; + } + return false; +} + +static bool trans_MFHI1(DisasContext *ctx, arg_rtype *a) +{ + gen_store_gpr(cpu_HI[1], a->rd); + + return true; +} + +static bool trans_MFLO1(DisasContext *ctx, arg_rtype *a) +{ + gen_store_gpr(cpu_LO[1], a->rd); + + return true; +} diff --git a/target/mips/txx9_translate.c b/target/mips/txx9_translate.c new file mode 100644 index 00000000000..8a2c0b766bd --- /dev/null +++ b/target/mips/txx9_translate.c @@ -0,0 +1,20 @@ +/* + * Toshiba TXx9 instructions translation routines + * + * Copyright (c) 2021 Philippe Mathieu-Daud=C3=A9 + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "translate.h" + +bool decode_ext_txx9(DisasContext *ctx, uint32_t insn) +{ +#if defined(TARGET_MIPS64) + if (decode_ext_tx79(ctx, insn)) { + return true; + } +#endif + return false; +} diff --git a/target/mips/meson.build b/target/mips/meson.build index 4a951e522d4..3b131c4a7f6 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -3,6 +3,7 @@ decodetree.process('mips64r6.decode', extra_args: '--static-decode=3Ddec= ode_mips64r6'), decodetree.process('msa32.decode', extra_args: '--static-decode=3Ddecode= _msa32'), decodetree.process('msa64.decode', extra_args: '--static-decode=3Ddecode= _msa64'), + decodetree.process('tx79.decode', extra_args: '--static-decode=3Ddecode_= tx79'), ] =20 mips_ss =3D ss.source_set() @@ -23,6 +24,10 @@ 'tlb_helper.c', 'translate.c', 'translate_addr_const.c', + 'txx9_translate.c', +)) +mips_ss.add(when: ['CONFIG_TCG', 'TARGET_MIPS64'], if_true: files( + 'tx79_translate.c', )) mips_tcg_ss.add(when: 'TARGET_MIPS64', if_false: files( 'mxu_translate.c', --=20 2.26.2 From nobody Sat May 18 21:45:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.49 as permitted sender) client-ip=209.85.221.49; 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[88.21.201.17]) by smtp.gmail.com with ESMTPSA id v189sm7767583wme.39.2021.03.13.11.50.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Mar 2021 11:50:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=O314qlIj7arWsupg5EFdCLic7PcyuMDeKjWuDIw/LHI=; b=l++6N9cLMB0bCWNgWM/psccDets1YDL3iPf2g0xqAZtIAu1tHfPbXEAYgDgkbTThia B7Fs3OXv0It3K4KpyvT2wdbIJ+OqF+6E6HGCjCc9x/ZNBZHlL0vdaD/orhfCm8yQDzbl giu/NyN9ypMTQeygfG0lUIh5uu/7yp4HqXdkOUPDLdVdq38/pLfC30aqL6kbkArSqy8R xctRabEfA5UZ2t8PlOUfoNyJ8u8diqtbx2A4M6UMA/mxjS11i3t7kIo8NKpgwhJODAMQ oPI+OIVmJKrbp416UBISOIMUn0Aae7xq3gLqIDmNXWLhBbWdlyNn7SzgSTbwQBd0Nl7e bofw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=O314qlIj7arWsupg5EFdCLic7PcyuMDeKjWuDIw/LHI=; b=Oz5uA6hVdjmwMJXCBJqM0rMcP7f6QKd6bbBGemOLjxijEhH8bD2jI+94xPaBYmYOdc o/DwEUSMWRYb6corpDl8NbOV9Mx5kdwCQicculBWbIdhiGceNJmiuf4RqcpxtuozMDcc hC6evCBOdsJNQtyZTHn7lbnl4/7VrF6L99lVCmK6x0lku4W9sBMDBcY3Hn9yOK5FdZgL ExEXt1MXQ1YK3fBbD6c9zRbra5oPQUAeld08qajx9QnNXAZiKjIxbMzKd8EJrcU96C36 Mbbz6DYSv/VfpoiGrQUgzkmwLa8WAl4EzJxdMegtmlrijOMhVIn3SBIDj3VCHYovbOXu aQsA== X-Gm-Message-State: AOAM533yUMcGI+G97Nx9ojgSmh1Bdj3RTJxXYJNPUNdaPtDddK0KNyPu bFJXZy7QpftMvLpQpq8yeTc= X-Google-Smtp-Source: ABdhPJyQuCXSQLTtDPeYaBUpM1FF1OcIL9HyaX2aipMyVSrO7t5nPG+VsNLUnpVE1bv/WRbt2WsxOw== X-Received: by 2002:adf:a18a:: with SMTP id u10mr20259328wru.197.1615665017233; Sat, 13 Mar 2021 11:50:17 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 21/27] target/mips/tx79: Move MTHI1 / MTLO1 opcodes to decodetree Date: Sat, 13 Mar 2021 20:48:23 +0100 Message-Id: <20210313194829.2193621-22-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210313194829.2193621-1-f4bug@amsat.org> References: <20210313194829.2193621-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20210214175912.732946-10-f4bug@amsat.org> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/tx79.decode | 3 +++ target/mips/translate.c | 25 ------------------------- target/mips/tx79_translate.c | 14 ++++++++++++++ 3 files changed, 17 insertions(+), 25 deletions(-) diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode index 2e287ebbf36..30737da54e4 100644 --- a/target/mips/tx79.decode +++ b/target/mips/tx79.decode @@ -17,9 +17,12 @@ # Named instruction formats. These are generally used to # reduce the amount of duplication between instruction patterns. =20 +@rs ...... rs:5 ..... .......... ...... &rtype rt=3D0 rd= =3D0 sa=3D0 @rd ...... .......... rd:5 ..... ...... &rtype rs=3D0 rt= =3D0 sa=3D0 =20 ########################################################################### =20 MFHI1 011100 0000000000 ..... 00000 010000 @rd +MTHI1 011100 ..... 0000000000 00000 010001 @rs MFLO1 011100 0000000000 ..... 00000 010010 @rd +MTLO1 011100 ..... 0000000000 00000 010011 @rs diff --git a/target/mips/translate.c b/target/mips/translate.c index 889c89696b1..256e2956c4b 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1360,8 +1360,6 @@ enum { MMI_OPC_PLZCW =3D 0x04 | MMI_OPC_CLASS_MMI, MMI_OPC_CLASS_MMI0 =3D 0x08 | MMI_OPC_CLASS_MMI, MMI_OPC_CLASS_MMI2 =3D 0x09 | MMI_OPC_CLASS_MMI, - MMI_OPC_MTHI1 =3D 0x11 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_= MTHI */ - MMI_OPC_MTLO1 =3D 0x13 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_= MTLO */ MMI_OPC_MULT1 =3D 0x18 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_= MULT */ MMI_OPC_MULTU1 =3D 0x19 | MMI_OPC_CLASS_MMI, /* Same min. as OPC_M= ULTU */ MMI_OPC_DIV1 =3D 0x1A | MMI_OPC_CLASS_MMI, /* Same minor as OPC_= DIV */ @@ -3462,25 +3460,6 @@ static void gen_shift(DisasContext *ctx, uint32_t op= c, tcg_temp_free(t1); } =20 -#if defined(TARGET_MIPS64) -/* Copy GPR to and from TX79 HI1/LO1 register. */ -static void gen_HILO1_tx79(DisasContext *ctx, uint32_t opc, int reg) -{ - switch (opc) { - case MMI_OPC_MTHI1: - gen_load_gpr(cpu_HI[1], reg); - break; - case MMI_OPC_MTLO1: - gen_load_gpr(cpu_LO[1], reg); - break; - default: - MIPS_INVAL("mfthilo1 TX79"); - gen_reserved_instruction(ctx); - break; - } -} -#endif - /* Arithmetic on HI/LO registers */ static void gen_HILO(DisasContext *ctx, uint32_t opc, int acc, int reg) { @@ -25108,10 +25087,6 @@ static void decode_mmi(CPUMIPSState *env, DisasCon= text *ctx) case MMI_OPC_DIVU1: gen_div1_tx79(ctx, opc, rs, rt); break; - case MMI_OPC_MTLO1: - case MMI_OPC_MTHI1: - gen_HILO1_tx79(ctx, opc, rs); - break; case MMI_OPC_PLZCW: /* TODO: MMI_OPC_PLZCW */ case MMI_OPC_PMFHL: /* TODO: MMI_OPC_PMFHL */ case MMI_OPC_PMTHL: /* TODO: MMI_OPC_PMTHL */ diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c index 22bd6033e55..905245cece7 100644 --- a/target/mips/tx79_translate.c +++ b/target/mips/tx79_translate.c @@ -35,3 +35,17 @@ static bool trans_MFLO1(DisasContext *ctx, arg_rtype *a) =20 return true; } + +static bool trans_MTHI1(DisasContext *ctx, arg_rtype *a) +{ + gen_load_gpr(cpu_HI[1], a->rs); + + return true; +} + +static bool trans_MTLO1(DisasContext *ctx, arg_rtype *a) +{ + gen_load_gpr(cpu_LO[1], a->rs); + + return true; +} --=20 2.26.2 From nobody Sat May 18 21:45:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.48 as permitted sender) client-ip=209.85.128.48; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f48.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.48 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1615665024; cv=none; d=zohomail.com; s=zohoarc; b=G3CKCU5tqweLwbcqo7yq+nz7L9kJfckUOx22IsvM5ghqK7aDCiBUHrYhAfOl8Tht88h5H3vx1QheVF6v+Z+ZuvgjcwR5qyuObTKcVhx0GkZy94Et2oAEgCgCR3Chavei+pq+wT7RgR0zx2z6uMVn7FECPhX8sxQZHUillxe4vI0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615665024; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=jGTyoIUamQpmoS/rb5oXqjzJpXDppEWRvvKl92rVqa8=; b=ceYsVoBGJ5pNbkyhrulFTKrAyj13R9Ttj+eQbwELP59UEFKLZbZHrxHdJtHelZX4xv2Au5NDo/7GwQU57f+3mQHqhukmVzHzynmEdGwfezdsd0C/HmHkXXDVq+xZRwpnYS4WrKKyTtvUswtXKUMWvEVZfNYBQxK2+rd+9pwyZlc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.48 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) by mx.zohomail.com with SMTPS id 1615665024149135.5721942106743; Sat, 13 Mar 2021 11:50:24 -0800 (PST) Received: by mail-wm1-f48.google.com with SMTP id g8so5765132wmd.4 for ; Sat, 13 Mar 2021 11:50:23 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (17.red-88-21-201.staticip.rima-tde.net. [88.21.201.17]) by smtp.gmail.com with ESMTPSA id v2sm30603135wmj.1.2021.03.13.11.50.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Mar 2021 11:50:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jGTyoIUamQpmoS/rb5oXqjzJpXDppEWRvvKl92rVqa8=; b=bmuPiSL6ERHe13e7YKodCC47ViEfsNVy4Niq/Xf9feadn+75jZ+guC5Au91U5Jv/ln iz45Es3Ba18ep6cMCbzqWyazQEuEmHgxxCfdJf8nUKO4Dj3JvAyeNOJZCefOa/6Skzgf UMww2MrGAd8qBeeM5tf5P/ntOpAPP+dXI4YcpdYilBkts64UQsGUIqOlCRhCUKEQUhb5 UoVuKpM/Jzj1o+sx4AdaHoKeFCELOEAncQ4IxoEa4wob1nnpn6WudaK4WBfNHSP5oHWJ nlPdkLbXJsvVRGRIuOamQn69n1Wvr6AjulPM8lOksITZoPAW5AuVtIzOzu7ixmDlEG/r z+cg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=jGTyoIUamQpmoS/rb5oXqjzJpXDppEWRvvKl92rVqa8=; b=IgboXTIufaWwa2NvrytbakfptmwGKcKEveix63BP19TTvjo6ONGyCqtnbLjeW7yqT1 N1krwF9Ymy2YzmLH3UqCfXN6SKOAuUgOZUJy04K1E0PRbpp5xu37kZcg9DuQ4iTUlHSz p43f0J/KDfs+9yKVzODXnB+5u+Qh44GxeB3SS2N/uZ3VWRnScsINCwjGhSB1gXkyN4qX YIj6IH5Nxn8Crybc4Jzj2mAwx9x1sR7QYu3/zY4XoyTU3+mo8DHzuk9h0Dh/Ud0jq3xe 2MEDqRtSPa5AUB3vt/JBOrlNN+eeq1xkcZmjC5LGLVMvFuSo4MM6z0zdWqsSqM/qyN4+ METw== X-Gm-Message-State: AOAM533QvtVXa1wkozxp26X3Z56aFAQmfnteQblUXfoY7nXolgGGVLjk cH27Fy/eTiiVeYF5m4O3m/I= X-Google-Smtp-Source: ABdhPJwGP06v8LtQAIv5AeCBC+Fur6puTa7VZrjoej6h+64RTlSSX3K8sXTFewNrZeZwtSRA7gSoRA== X-Received: by 2002:a05:600c:4a06:: with SMTP id c6mr18922022wmp.35.1615665022380; Sat, 13 Mar 2021 11:50:22 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 22/27] target/mips/translate: Make gen_rdhwr() public Date: Sat, 13 Mar 2021 20:48:24 +0100 Message-Id: <20210313194829.2193621-23-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210313194829.2193621-1-f4bug@amsat.org> References: <20210313194829.2193621-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) We will use gen_rdhwr() outside of translate.c, make it public. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20210214175912.732946-28-f4bug@amsat.org> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/translate.h | 2 ++ target/mips/translate.c | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/mips/translate.h b/target/mips/translate.h index e4f2f26de89..2b3c7a69ec6 100644 --- a/target/mips/translate.h +++ b/target/mips/translate.h @@ -148,6 +148,8 @@ void gen_op_addr_add(DisasContext *ctx, TCGv ret, TCGv = arg0, TCGv arg1); bool gen_lsa(DisasContext *ctx, int rd, int rt, int rs, int sa); bool gen_dlsa(DisasContext *ctx, int rd, int rt, int rs, int sa); =20 +void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel); + extern TCGv cpu_gpr[32], cpu_PC; #if defined(TARGET_MIPS64) extern TCGv_i64 cpu_gpr_hi[32]; diff --git a/target/mips/translate.c b/target/mips/translate.c index 256e2956c4b..d4316c15d11 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -12349,7 +12349,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint3= 2_t opc, } } =20 -static void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel) +void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel) { TCGv t0; =20 --=20 2.26.2 From nobody Sat May 18 21:45:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.42 as permitted sender) client-ip=209.85.128.42; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f42.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.42 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1615665028; cv=none; d=zohomail.com; s=zohoarc; b=hba/hYLf9becOdL8aUFpKHo6YrrpkM+GkmsOrYMV3H3b44PCYS/x4yjMPM11UwMjvpvQjoGJw4grPmMjIAT1/bWPDjOJ5UBOC5LXb9RSWfXSFDwri2G8P/yIT5gm9+2iDbnJbjv+uN5yIlAMm2N3uaE9azB04s1jd5bPydZad4E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615665028; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=L1Cwa2OcYD4r+5VTw6PO/ARs0+y1qGMrO1MaA3wWpg0=; b=IPCTfJt3rCMa4TLAhazfKoBTRhMHBLZeu5Fq3sN2LzZch+H/7z2MHvB0yOANsGMjs/CdqXA+nSH7grcUce+6k51FZoF2Gt4lJnAo1vmLzwnoYY+RCeWAKODRf+uk5RORRlOdbuX/Ql8kVJTFw0zQYd08ImDqmehMwI80yhKZfMo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.42 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) by mx.zohomail.com with SMTPS id 1615665028953342.09461439358483; Sat, 13 Mar 2021 11:50:28 -0800 (PST) Received: by mail-wm1-f42.google.com with SMTP id g25so5746752wmh.0 for ; Sat, 13 Mar 2021 11:50:28 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (17.red-88-21-201.staticip.rima-tde.net. [88.21.201.17]) by smtp.gmail.com with ESMTPSA id m9sm13349948wro.52.2021.03.13.11.50.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Mar 2021 11:50:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=L1Cwa2OcYD4r+5VTw6PO/ARs0+y1qGMrO1MaA3wWpg0=; b=j3/9zx7faUrpCe7wglzGdBw/oh15ATPOse6nNncBeN3WdnJhZ4PJCkaxIxLkXNBrjB VHkWKVSixQLMik+xAIVMUxFFzkxc6b7TQL+1xPSkAKYU+SwInhRQpmzBaR1LDAaikS1q 6LxrRgSkQAgxUWW6TYQVd1/r61/bE6M2vylg6S9b5cda+G3seMghqwCraYXAHJPbUofh Xn0dHOMOzFc2l+B/R6F0Vf1yRZinmStU6LCgRR7OAloVjcsjz+8MTjmWR/IXi3HHQ33l sVWXdRvxLiBE3TH4LbVWXJg9o1WcCeE0PTNXulKieM1Vz9fqJQBX9hnCgjYiWCDrQsRN CBsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=L1Cwa2OcYD4r+5VTw6PO/ARs0+y1qGMrO1MaA3wWpg0=; b=BdNmOVyPHmgkgXkjeqnz2+cyHtHuCbU4OuWtWACEMaOEs581RsEaZOegBj4rsPWhL5 20jDnO0jgeCPYnMfY6reRe1Sxxc76ENPAZMbMOXPWQw7VKLt+MjYPN17joFMCU5dwADz XYRtpwP2VA8i9Kfl7JBCawYnj6AZ+Oed2zrEDzcmAkuLiJjvPvqqDGzYnWC4oissPQiE zfaIEkYTmGLyInmB2aMBDr8VvbmVD764bZuTV+W4Lzx+1HD5J1NoN5pUcN/rORg+Aw/T 1Kf3CMs0vFzWZd3YlnT2qW1AgELnifEnLBT2uBEmijrVF9PvAxTlsS99x82uiZpQEPGV /EFA== X-Gm-Message-State: AOAM533wiJYvEzoAb4XCoPYQf3i0dDCJrXaguT2hgPrhTWikIlc3LsEB Mubv7IJ+7IE3lrkyYF7THm0= X-Google-Smtp-Source: ABdhPJxIuUQkZzNhkbZVkiz0hxcd2x2VnFVHA9Y86CUW+BxDbRjbN1Cyo6UMrQuqKQT7THOfA2Fc7A== X-Received: by 2002:a7b:cf16:: with SMTP id l22mr18539234wmg.26.1615665027271; Sat, 13 Mar 2021 11:50:27 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 23/27] target/mips/translate: Simplify PCPYH using deposit_i64() Date: Sat, 13 Mar 2021 20:48:25 +0100 Message-Id: <20210313194829.2193621-24-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210313194829.2193621-1-f4bug@amsat.org> References: <20210313194829.2193621-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Simplify the PCPYH (Parallel Copy Halfword) instruction by using multiple calls to deposit_i64() which can be optimized by some TCG backends. Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20210214175912.732946-11-f4bug@amsat.org> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/translate.c | 34 ++++------------------------------ 1 file changed, 4 insertions(+), 30 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index d4316c15d11..1967c12d807 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -24091,36 +24091,10 @@ static void gen_mmi_pcpyh(DisasContext *ctx) tcg_gen_movi_i64(cpu_gpr[rd], 0); tcg_gen_movi_i64(cpu_gpr_hi[rd], 0); } else { - TCGv_i64 t0 =3D tcg_temp_new(); - TCGv_i64 t1 =3D tcg_temp_new(); - uint64_t mask =3D (1ULL << 16) - 1; - - tcg_gen_andi_i64(t0, cpu_gpr[rt], mask); - tcg_gen_movi_i64(t1, 0); - tcg_gen_or_i64(t1, t0, t1); - tcg_gen_shli_i64(t0, t0, 16); - tcg_gen_or_i64(t1, t0, t1); - tcg_gen_shli_i64(t0, t0, 16); - tcg_gen_or_i64(t1, t0, t1); - tcg_gen_shli_i64(t0, t0, 16); - tcg_gen_or_i64(t1, t0, t1); - - tcg_gen_mov_i64(cpu_gpr[rd], t1); - - tcg_gen_andi_i64(t0, cpu_gpr_hi[rt], mask); - tcg_gen_movi_i64(t1, 0); - tcg_gen_or_i64(t1, t0, t1); - tcg_gen_shli_i64(t0, t0, 16); - tcg_gen_or_i64(t1, t0, t1); - tcg_gen_shli_i64(t0, t0, 16); - tcg_gen_or_i64(t1, t0, t1); - tcg_gen_shli_i64(t0, t0, 16); - tcg_gen_or_i64(t1, t0, t1); - - tcg_gen_mov_i64(cpu_gpr_hi[rd], t1); - - tcg_temp_free(t0); - tcg_temp_free(t1); + tcg_gen_deposit_i64(cpu_gpr[rd], cpu_gpr[rt], cpu_gpr[rt], 16, 16); + tcg_gen_deposit_i64(cpu_gpr[rd], cpu_gpr[rd], cpu_gpr[rd], 32, 32); + tcg_gen_deposit_i64(cpu_gpr_hi[rd], cpu_gpr_hi[rt], cpu_gpr_hi[rt]= , 16, 16); + tcg_gen_deposit_i64(cpu_gpr_hi[rd], cpu_gpr_hi[rd], cpu_gpr_hi[rd]= , 32, 32); } } =20 --=20 2.26.2 From nobody Sat May 18 21:45:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.54 as permitted sender) client-ip=209.85.221.54; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f54.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.54 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1615665033; cv=none; d=zohomail.com; s=zohoarc; b=FxTPNqZY+MEwMFnXiCqNDpf8Vpd/ICVFbwThSZR2T9qTZG/RfpMHsBXhL7D10iJs+0dyMS5n4ToQP21VlvhWfnAjwwSVOqoBcHo52ogJCnDnaOrs4pLggLxK2zrGLnog6H1a2vP5eN6vtS9y3N5X5aeZnsAvOpV8J1UFKihXr/E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615665033; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/YG4Md8ZPkAURrr+St5wr7wofQ8IOyRe0AIoTOauk6w=; b=Tqw5k8r2+++xFSyAfIuDuJy9ot/8LBleGdcuJj+8LGyolqg5T15daDqrx/QGBXEUEh45xz6iGalkm8s/fsPJ3zy/tgBzs/7iL1Bsm+BVbxVuXa2fKYy0xdFHS5HA2EZYQ7TGKhB7IsaoI9bnThsORQK5cvfXs521lXVyBvL4FfA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.54 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-wr1-f54.google.com (mail-wr1-f54.google.com [209.85.221.54]) by mx.zohomail.com with SMTPS id 1615665033995530.627767057162; Sat, 13 Mar 2021 11:50:33 -0800 (PST) Received: by mail-wr1-f54.google.com with SMTP id v11so3613357wro.7 for ; Sat, 13 Mar 2021 11:50:33 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (17.red-88-21-201.staticip.rima-tde.net. [88.21.201.17]) by smtp.gmail.com with ESMTPSA id j16sm30759735wmi.2.2021.03.13.11.50.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Mar 2021 11:50:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/YG4Md8ZPkAURrr+St5wr7wofQ8IOyRe0AIoTOauk6w=; b=vYgB0HNgNBKvP6UeNTAtXoIymYFv1OqHz5syfDb6p6ZANQnangrXzZYGjReYwueeoD Au/2+s8Jm0soXoDh/vAl6lndXUiOPhUzPIG81Ot4BE1HFUoI6PmJDNDFUlQRbPpYpZTE aDlVpTmu08Ct3C8MkvYj3rFIH3MCg2R8QnI+/3io2KjWpk8dN0yqDK50vn4a+Y7d6Jxt mIlWeg2vMOu3tORDysL0AlB4FEJBlHWtzAZqT3bDmgk/cdGFp3F9l2h2ZXkqhMFol0rB yeWE8m46FILS71IUUMJhhnKYT9nWw5E7PqhM6H/f0IrsbF9euC4N1fA9m93x91T2NEEm yqqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=/YG4Md8ZPkAURrr+St5wr7wofQ8IOyRe0AIoTOauk6w=; b=R85ipV4v26T0ZkWSehe/hqXqszs/TTxxkrfyojWs2FHkeaSn8ZWbtWuleqt9S5laOp I60EsN/1acj5mI3ODj4BgQWV49aWEnH9/e5NnzSgwSEionIiMawK/deLVMdlGIgszMcS THx1pmMF7O71eHhIUDe+Bd+qSdLhmnb0QxwKNjh40W9aHb/Ou67tdi41Ukx4pUh6x4QP GCBOJiydpZfJ/IrlQeyasg8MtOMuYKDqrBZ/hmUdusn4K7X8UiczRHF3GCJLi5P5JZZP 3iDEUyeu0w0wvMCTUR3S1Cjs7TBmRETp5piQBQEI+Yf1fjQSb7y0AexDgSkcRPdgYLjj M6Tg== X-Gm-Message-State: AOAM531wvs3FjQpo3lvcSTarlfZV0NuhGxgTDUE0gJ+8WP9EV2NxllcY Mh5eL4u6xM/SgKttD5cDY8w= X-Google-Smtp-Source: ABdhPJyQxQ4OLLFzl5lnPIlPu3azDf+MAHIJOXFBIbTRpH0IKEl0TQOyjKpn+dPKRKekGrlB6SKP6Q== X-Received: by 2002:adf:dc4e:: with SMTP id m14mr20999837wrj.248.1615665032200; Sat, 13 Mar 2021 11:50:32 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 24/27] target/mips/tx79: Move PCPYH opcode to decodetree Date: Sat, 13 Mar 2021 20:48:26 +0100 Message-Id: <20210313194829.2193621-25-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210313194829.2193621-1-f4bug@amsat.org> References: <20210313194829.2193621-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Move the existing PCPYH opcode (Parallel Copy Halfword) to decodetree. Remove unnecessary code / comments. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20210214175912.732946-12-f4bug@amsat.org> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/tx79.decode | 5 +++++ target/mips/translate.c | 39 ------------------------------------ target/mips/tx79_translate.c | 22 ++++++++++++++++++++ 3 files changed, 27 insertions(+), 39 deletions(-) diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode index 30737da54e4..7af35458b0a 100644 --- a/target/mips/tx79.decode +++ b/target/mips/tx79.decode @@ -17,6 +17,7 @@ # Named instruction formats. These are generally used to # reduce the amount of duplication between instruction patterns. =20 +@rt_rd ...... ..... rt:5 rd:5 ..... ...... &rtype rs=3D0 sa= =3D0 @rs ...... rs:5 ..... .......... ...... &rtype rt=3D0 rd= =3D0 sa=3D0 @rd ...... .......... rd:5 ..... ...... &rtype rs=3D0 rt= =3D0 sa=3D0 =20 @@ -26,3 +27,7 @@ MFHI1 011100 0000000000 ..... 00000 010000 @= rd MTHI1 011100 ..... 0000000000 00000 010001 @rs MFLO1 011100 0000000000 ..... 00000 010010 @rd MTLO1 011100 ..... 0000000000 00000 010011 @rs + +# MMI3 + +PCPYH 011100 00000 ..... ..... 11011 101001 @rt_rd diff --git a/target/mips/translate.c b/target/mips/translate.c index 1967c12d807..80fcab5a564 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -24062,42 +24062,6 @@ static void decode_opc_special(CPUMIPSState *env, = DisasContext *ctx) * PEXTUW */ =20 -/* - * PCPYH rd, rt - * - * Parallel Copy Halfword - * - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+---------+---------+---------+-----------+ - * | MMI |0 0 0 0 0| rt | rd | PCPYH | MMI3 | - * +-----------+---------+---------+---------+---------+-----------+ - */ -static void gen_mmi_pcpyh(DisasContext *ctx) -{ - uint32_t pd, rt, rd; - uint32_t opcode; - - opcode =3D ctx->opcode; - - pd =3D extract32(opcode, 21, 5); - rt =3D extract32(opcode, 16, 5); - rd =3D extract32(opcode, 11, 5); - - if (unlikely(pd !=3D 0)) { - gen_reserved_instruction(ctx); - } else if (rd =3D=3D 0) { - /* nop */ - } else if (rt =3D=3D 0) { - tcg_gen_movi_i64(cpu_gpr[rd], 0); - tcg_gen_movi_i64(cpu_gpr_hi[rd], 0); - } else { - tcg_gen_deposit_i64(cpu_gpr[rd], cpu_gpr[rt], cpu_gpr[rt], 16, 16); - tcg_gen_deposit_i64(cpu_gpr[rd], cpu_gpr[rd], cpu_gpr[rd], 32, 32); - tcg_gen_deposit_i64(cpu_gpr_hi[rd], cpu_gpr_hi[rt], cpu_gpr_hi[rt]= , 16, 16); - tcg_gen_deposit_i64(cpu_gpr_hi[rd], cpu_gpr_hi[rd], cpu_gpr_hi[rd]= , 32, 32); - } -} - /* * PCPYLD rd, rs, rt * @@ -25016,9 +24980,6 @@ static void decode_mmi3(CPUMIPSState *env, DisasCon= text *ctx) case MMI_OPC_3_PEXCW: /* TODO: MMI_OPC_3_PEXCW */ gen_reserved_instruction(ctx); /* TODO: MMI_OPC_CLASS_MMI3 */ break; - case MMI_OPC_3_PCPYH: - gen_mmi_pcpyh(ctx); - break; case MMI_OPC_3_PCPYUD: gen_mmi_pcpyud(ctx); break; diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c index 905245cece7..d58b4fcd7b3 100644 --- a/target/mips/tx79_translate.c +++ b/target/mips/tx79_translate.c @@ -49,3 +49,25 @@ static bool trans_MTLO1(DisasContext *ctx, arg_rtype *a) =20 return true; } + +/* Parallel Copy Halfword */ +static bool trans_PCPYH(DisasContext *s, arg_rtype *a) +{ + if (a->rd =3D=3D 0) { + /* nop */ + return true; + } + + if (a->rt =3D=3D 0) { + tcg_gen_movi_i64(cpu_gpr[a->rd], 0); + tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0); + return true; + } + + tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rt], cpu_gpr[a->rt], 16= , 16); + tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], cpu_gpr[a->rd], 32= , 32); + tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rt], cpu_gpr_hi[a= ->rt], 16, 16); + tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rd], cpu_gpr_hi[a= ->rd], 32, 32); + + return true; +} --=20 2.26.2 From nobody Sat May 18 21:45:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.49 as permitted sender) client-ip=209.85.128.49; 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[88.21.201.17]) by smtp.gmail.com with ESMTPSA id q15sm13226557wrr.58.2021.03.13.11.50.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Mar 2021 11:50:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bYD0kz0+5thSbgQop2x/XNUgvdHEo6LE0U/VV3XWrfg=; b=SAXgLp6nqgKxb11+3BJAR0JPhNumR+RaCY8cSpr17u3vJYWCb9kc0DBZRfEghIyhNY 2hOH1eT4DILqS0FAd3GCSr2BYy7bj4tKdhfNaPvYtmdCEOtNeH9CeSgv/SOFNbEBnkPt 7eB6ZdwkuEiS7SDpEhoH1F/VKW/bFXJX+59B3/WZPtkQGXXKfsomr/FLrNiNHKoDN54L zqE1KLFvusiM957vRLILeTtz7JjbtifVGhSXP1SwHvlS9h/ZS+eKL2YCOsV7DPg0+LQW 1zG5cwpY84coeYKEuIMmDoCIorSIEm3ibrA6rnv2xu1ri10pjiwT0NwVNcC8qPEJDnQz FWOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=bYD0kz0+5thSbgQop2x/XNUgvdHEo6LE0U/VV3XWrfg=; b=n5OoWHWjDUFpdEdfkJhFqxXlA+L1j2/y77nvlB17xZ9VtemEsjX0LDgaJmTm9GMPbs wbJXksMFLw5WLiLr6xxy3/kdfX+vJMtfBWfpceN9dkT//qC56xsXCUCvtRwLFGNt5PwS GFnnOXp5H9b+xKaGw5uurTe4sxeehr0finDxHwaoJ3PPD4m0K6p6hGhg73DwUMvDN5Sy TmzldP5BggcCjFIB29nL4OejBd37FxMqWqKeoAZDHQfNNS93J+CBIMFJZPFM6M+bhs9a WoVFW/lzm+9yA7RqpliWbLERCaNPYY//jX13ejFynwaCU0OVRKc8FbiKnWfyA8NLhJQR QsYA== X-Gm-Message-State: AOAM532pinbZvC6m5H2C6K7vUzbrXbBhPdSrXOnIuiqQiTpWvYtYH5fE 0AEt548QyMd3CRjdsZlfUoo= X-Google-Smtp-Source: ABdhPJwpaoXd0WrHOaj6geaNbib+s2cUiGNa5RDhHbLYDJr3BCc+wWcO/+wT08TbDmCNu1S+lC8RTg== X-Received: by 2002:a1c:9849:: with SMTP id a70mr19829635wme.48.1615665037229; Sat, 13 Mar 2021 11:50:37 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 25/27] target/mips/tx79: Move PCPYLD / PCPYUD opcodes to decodetree Date: Sat, 13 Mar 2021 20:48:27 +0100 Message-Id: <20210313194829.2193621-26-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210313194829.2193621-1-f4bug@amsat.org> References: <20210313194829.2193621-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Move PCPYLD (Parallel Copy Lower Doubleword) and PCPYUD (Parallel Copy Upper Doubleword) to decodetree. Remove unnecessary code / comments. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20210214175912.732946-13-f4bug@amsat.org> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- v2: Use gen_load_gpr_hi (rth) --- target/mips/tx79.decode | 6 +++ target/mips/translate.c | 80 ------------------------------------ target/mips/tx79_translate.c | 42 +++++++++++++++++++ 3 files changed, 48 insertions(+), 80 deletions(-) diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode index 7af35458b0a..0f748b53a64 100644 --- a/target/mips/tx79.decode +++ b/target/mips/tx79.decode @@ -17,6 +17,7 @@ # Named instruction formats. These are generally used to # reduce the amount of duplication between instruction patterns. =20 +@rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &rtype sa=3D0 @rt_rd ...... ..... rt:5 rd:5 ..... ...... &rtype rs=3D0 sa= =3D0 @rs ...... rs:5 ..... .......... ...... &rtype rt=3D0 rd= =3D0 sa=3D0 @rd ...... .......... rd:5 ..... ...... &rtype rs=3D0 rt= =3D0 sa=3D0 @@ -28,6 +29,11 @@ MTHI1 011100 ..... 0000000000 00000 010001 = @rs MFLO1 011100 0000000000 ..... 00000 010010 @rd MTLO1 011100 ..... 0000000000 00000 010011 @rs =20 +# MMI2 + +PCPYLD 011100 ..... ..... ..... 01110 001001 @rs_rt_rd + # MMI3 =20 +PCPYUD 011100 ..... ..... ..... 01110 101001 @rs_rt_rd PCPYH 011100 00000 ..... ..... 11011 101001 @rt_rd diff --git a/target/mips/translate.c b/target/mips/translate.c index 80fcab5a564..08e4995c730 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -24062,80 +24062,6 @@ static void decode_opc_special(CPUMIPSState *env, = DisasContext *ctx) * PEXTUW */ =20 -/* - * PCPYLD rd, rs, rt - * - * Parallel Copy Lower Doubleword - * - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+---------+---------+---------+-----------+ - * | MMI | rs | rt | rd | PCPYLD | MMI2 | - * +-----------+---------+---------+---------+---------+-----------+ - */ -static void gen_mmi_pcpyld(DisasContext *ctx) -{ - uint32_t rs, rt, rd; - uint32_t opcode; - - opcode =3D ctx->opcode; - - rs =3D extract32(opcode, 21, 5); - rt =3D extract32(opcode, 16, 5); - rd =3D extract32(opcode, 11, 5); - - if (rd =3D=3D 0) { - /* nop */ - } else { - if (rs =3D=3D 0) { - tcg_gen_movi_i64(cpu_gpr_hi[rd], 0); - } else { - tcg_gen_mov_i64(cpu_gpr_hi[rd], cpu_gpr[rs]); - } - if (rt =3D=3D 0) { - tcg_gen_movi_i64(cpu_gpr[rd], 0); - } else { - if (rd !=3D rt) { - tcg_gen_mov_i64(cpu_gpr[rd], cpu_gpr[rt]); - } - } - } -} - -/* - * PCPYUD rd, rs, rt - * - * Parallel Copy Upper Doubleword - * - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+---------+---------+---------+-----------+ - * | MMI | rs | rt | rd | PCPYUD | MMI3 | - * +-----------+---------+---------+---------+---------+-----------+ - */ -static void gen_mmi_pcpyud(DisasContext *ctx) -{ - uint32_t rs, rt, rd; - uint32_t opcode; - - opcode =3D ctx->opcode; - - rs =3D extract32(opcode, 21, 5); - rt =3D extract32(opcode, 16, 5); - rd =3D extract32(opcode, 11, 5); - - if (rd =3D=3D 0) { - /* nop */ - } else { - gen_load_gpr_hi(cpu_gpr[rd], rs); - if (rt =3D=3D 0) { - tcg_gen_movi_i64(cpu_gpr_hi[rd], 0); - } else { - if (rd !=3D rt) { - tcg_gen_mov_i64(cpu_gpr_hi[rd], cpu_gpr_hi[rt]); - } - } - } -} - #endif =20 static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ct= x) @@ -24952,9 +24878,6 @@ static void decode_mmi2(CPUMIPSState *env, DisasCon= text *ctx) case MMI_OPC_2_PROT3W: /* TODO: MMI_OPC_2_PROT3W */ gen_reserved_instruction(ctx); /* TODO: MMI_OPC_CLASS_MMI2 */ break; - case MMI_OPC_2_PCPYLD: - gen_mmi_pcpyld(ctx); - break; default: MIPS_INVAL("TX79 MMI class MMI2"); gen_reserved_instruction(ctx); @@ -24980,9 +24903,6 @@ static void decode_mmi3(CPUMIPSState *env, DisasCon= text *ctx) case MMI_OPC_3_PEXCW: /* TODO: MMI_OPC_3_PEXCW */ gen_reserved_instruction(ctx); /* TODO: MMI_OPC_CLASS_MMI3 */ break; - case MMI_OPC_3_PCPYUD: - gen_mmi_pcpyud(ctx); - break; default: MIPS_INVAL("TX79 MMI class MMI3"); gen_reserved_instruction(ctx); diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c index d58b4fcd7b3..6e90eb64608 100644 --- a/target/mips/tx79_translate.c +++ b/target/mips/tx79_translate.c @@ -71,3 +71,45 @@ static bool trans_PCPYH(DisasContext *s, arg_rtype *a) =20 return true; } + +/* Parallel Copy Lower Doubleword */ +static bool trans_PCPYLD(DisasContext *s, arg_rtype *a) +{ + if (a->rd =3D=3D 0) { + /* nop */ + return true; + } + + if (a->rs =3D=3D 0) { + tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0); + } else { + tcg_gen_mov_i64(cpu_gpr_hi[a->rd], cpu_gpr[a->rs]); + } + + if (a->rt =3D=3D 0) { + tcg_gen_movi_i64(cpu_gpr[a->rd], 0); + } else if (a->rd !=3D a->rt) { + tcg_gen_mov_i64(cpu_gpr[a->rd], cpu_gpr[a->rt]); + } + + return true; +} + +/* Parallel Copy Upper Doubleword */ +static bool trans_PCPYUD(DisasContext *s, arg_rtype *a) +{ + if (a->rd =3D=3D 0) { + /* nop */ + return true; + } + + gen_load_gpr_hi(cpu_gpr[a->rd], a->rs); + + if (a->rt =3D=3D 0) { + tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0); + } else if (a->rd !=3D a->rt) { + tcg_gen_mov_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rt]); + } + + return true; +} --=20 2.26.2 From nobody Sat May 18 21:45:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.52 as permitted sender) client-ip=209.85.128.52; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f52.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.52 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1615665044; cv=none; d=zohomail.com; s=zohoarc; b=jxJ4mwwsO0jjD92v/0ukhLyf1oJ8djx5wxyx/1G+/Oy8dXBz5kZOp68ppYVjXgFkio9IJrz7TFuAnJ2yPBQqPKEcqr+4e0MdizX6vBH50QpMGV/nOoJnJM+sbUScGFj7iI6cYov9LcgTb7ZQsNcCkbzEHEFmcuDhFKmQu7zHv+o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615665044; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; 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[88.21.201.17]) by smtp.gmail.com with ESMTPSA id z25sm8411805wmi.23.2021.03.13.11.50.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Mar 2021 11:50:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1fg5pYXK5nizCP9KfPbyw6U0cSg5U2lFNK4tJdCC9w4=; b=bBll5ZfF9aI+EulQkQT/APbmvzIEC6tGa9azn/geYM3yeVhXIH7owFjHH4j87ahGOv zopkL0AQ++E9DEiOEcvJ+utaSQ2fPAZ3bRyNdCUDH/YjGaNF7isEpuqcfQKObtn8hzM9 A7cawf8x2pIbwboiu3hBQoIgST/nliHtPnGkBgdHnhiO10v7Opf2pvdXHVMW2XHxPHt9 ZAvWAJ4ZI1v6/YmNa3pW74zIsqxg7TKD67qUyDFcgieclgy8XNBfhajIfcu6vkLv9FlP WpvO+4giQGhoEAmC+Put0SdJ1qYB24gpWVzY7HwAwqgGOFqQutWkP52FSUv7Qx7ZscN4 VuGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=1fg5pYXK5nizCP9KfPbyw6U0cSg5U2lFNK4tJdCC9w4=; b=GQ3eudM08ySCkI07QtXNpdOJEYkRKthIujgkAfZmcxlNrn8y8VE082Kwx0Lq2HEq7G wMXzzN+HDu/6R8vsLpKd0R5KUQ7qMNUdThsGLy/gFvSBo+fAyAofiHpiDj9k4NSLzrjH NGUwEGna1b9QzyT93sD1DLMC3M8v6oB9XODD+XfEeOvSUvA4ExcmaRjEtl/v6kGWgb/c qvmzqT3gnoK4LHEevjVl1gB6AvtdmirWDa5BjeVpqlqlinT5AaxIhI8/qwhRFDDnSkhB A5qCsFsPhC4YZiByCGJ7XgV2htAT62k5JAzinIVHzgDfCMaUmNz+jUXsIfFYhcNWdadA W4ow== X-Gm-Message-State: AOAM532Vl1D757oQAQ/gtC/xeEV4p4goB+zrh1xsD/28TmODcsZlnH/d VQAm3ScChUfzlM7ckbeeg5c= X-Google-Smtp-Source: ABdhPJwJ8CL+harj4rmYNu18EcVa1v7X0ucXYYLepXhRBljXR4B6gCh9gMAGQIxtKANejs4BBFwPTQ== X-Received: by 2002:a05:600c:2215:: with SMTP id z21mr19345971wml.86.1615665042153; Sat, 13 Mar 2021 11:50:42 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 26/27] target/mips: Remove 'C790 Multimedia Instructions' dead code Date: Sat, 13 Mar 2021 20:48:28 +0100 Message-Id: <20210313194829.2193621-27-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210313194829.2193621-1-f4bug@amsat.org> References: <20210313194829.2193621-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) We have almost 400 lines of code full of /* TODO */ comments which end calling gen_reserved_instruction(). As we are not going to implement them, and all the caller's switch() default cases already call gen_reserved_instruction(), we can remove this altogether. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20210214175912.732946-14-f4bug@amsat.org> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/translate.c | 371 ---------------------------------------- 1 file changed, 371 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 08e4995c730..9334cd6df2e 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1357,207 +1357,12 @@ enum { enum { MMI_OPC_MADD =3D 0x00 | MMI_OPC_CLASS_MMI, /* Same as OPC_MADD */ MMI_OPC_MADDU =3D 0x01 | MMI_OPC_CLASS_MMI, /* Same as OPC_MADDU = */ - MMI_OPC_PLZCW =3D 0x04 | MMI_OPC_CLASS_MMI, - MMI_OPC_CLASS_MMI0 =3D 0x08 | MMI_OPC_CLASS_MMI, - MMI_OPC_CLASS_MMI2 =3D 0x09 | MMI_OPC_CLASS_MMI, MMI_OPC_MULT1 =3D 0x18 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_= MULT */ MMI_OPC_MULTU1 =3D 0x19 | MMI_OPC_CLASS_MMI, /* Same min. as OPC_M= ULTU */ MMI_OPC_DIV1 =3D 0x1A | MMI_OPC_CLASS_MMI, /* Same minor as OPC_= DIV */ MMI_OPC_DIVU1 =3D 0x1B | MMI_OPC_CLASS_MMI, /* Same minor as OPC_= DIVU */ MMI_OPC_MADD1 =3D 0x20 | MMI_OPC_CLASS_MMI, MMI_OPC_MADDU1 =3D 0x21 | MMI_OPC_CLASS_MMI, - MMI_OPC_CLASS_MMI1 =3D 0x28 | MMI_OPC_CLASS_MMI, - MMI_OPC_CLASS_MMI3 =3D 0x29 | MMI_OPC_CLASS_MMI, - MMI_OPC_PMFHL =3D 0x30 | MMI_OPC_CLASS_MMI, - MMI_OPC_PMTHL =3D 0x31 | MMI_OPC_CLASS_MMI, - MMI_OPC_PSLLH =3D 0x34 | MMI_OPC_CLASS_MMI, - MMI_OPC_PSRLH =3D 0x36 | MMI_OPC_CLASS_MMI, - MMI_OPC_PSRAH =3D 0x37 | MMI_OPC_CLASS_MMI, - MMI_OPC_PSLLW =3D 0x3C | MMI_OPC_CLASS_MMI, - MMI_OPC_PSRLW =3D 0x3E | MMI_OPC_CLASS_MMI, - MMI_OPC_PSRAW =3D 0x3F | MMI_OPC_CLASS_MMI, -}; - -/* - * MMI instructions with opcode field =3D MMI and bits 5..0 =3D MMI0: - * - * 31 26 10 6 5 0 - * +--------+----------------------+--------+--------+ - * | MMI | |function| MMI0 | - * +--------+----------------------+--------+--------+ - * - * function bits 7..6 - * bits | 0 | 1 | 2 | 3 - * 10..8 | 00 | 01 | 10 | 11 - * -------+-------+-------+-------+------- - * 0 000 | PADDW | PSUBW | PCGTW | PMAXW - * 1 001 | PADDH | PSUBH | PCGTH | PMAXH - * 2 010 | PADDB | PSUBB | PCGTB | * - * 3 011 | * | * | * | * - * 4 100 | PADDSW| PSUBSW| PEXTLW| PPACW - * 5 101 | PADDSH| PSUBSH| PEXTLH| PPACH - * 6 110 | PADDSB| PSUBSB| PEXTLB| PPACB - * 7 111 | * | * | PEXT5 | PPAC5 - */ - -#define MASK_MMI0(op) (MASK_OP_MAJOR(op) | ((op) & 0x7FF)) -enum { - MMI_OPC_0_PADDW =3D (0x00 << 6) | MMI_OPC_CLASS_MMI0, - MMI_OPC_0_PSUBW =3D (0x01 << 6) | MMI_OPC_CLASS_MMI0, - MMI_OPC_0_PCGTW =3D (0x02 << 6) | MMI_OPC_CLASS_MMI0, - MMI_OPC_0_PMAXW =3D (0x03 << 6) | MMI_OPC_CLASS_MMI0, - MMI_OPC_0_PADDH =3D (0x04 << 6) | MMI_OPC_CLASS_MMI0, - MMI_OPC_0_PSUBH =3D (0x05 << 6) | MMI_OPC_CLASS_MMI0, - MMI_OPC_0_PCGTH =3D (0x06 << 6) | MMI_OPC_CLASS_MMI0, - MMI_OPC_0_PMAXH =3D (0x07 << 6) | MMI_OPC_CLASS_MMI0, - MMI_OPC_0_PADDB =3D (0x08 << 6) | MMI_OPC_CLASS_MMI0, - MMI_OPC_0_PSUBB =3D (0x09 << 6) | MMI_OPC_CLASS_MMI0, - MMI_OPC_0_PCGTB =3D (0x0A << 6) | MMI_OPC_CLASS_MMI0, - MMI_OPC_0_PADDSW =3D (0x10 << 6) | MMI_OPC_CLASS_MMI0, - MMI_OPC_0_PSUBSW =3D (0x11 << 6) | MMI_OPC_CLASS_MMI0, - MMI_OPC_0_PEXTLW =3D (0x12 << 6) | MMI_OPC_CLASS_MMI0, - MMI_OPC_0_PPACW =3D (0x13 << 6) | MMI_OPC_CLASS_MMI0, - MMI_OPC_0_PADDSH =3D (0x14 << 6) | MMI_OPC_CLASS_MMI0, - MMI_OPC_0_PSUBSH =3D (0x15 << 6) | MMI_OPC_CLASS_MMI0, - MMI_OPC_0_PEXTLH =3D (0x16 << 6) | MMI_OPC_CLASS_MMI0, - MMI_OPC_0_PPACH =3D (0x17 << 6) | MMI_OPC_CLASS_MMI0, - MMI_OPC_0_PADDSB =3D (0x18 << 6) | MMI_OPC_CLASS_MMI0, - MMI_OPC_0_PSUBSB =3D (0x19 << 6) | MMI_OPC_CLASS_MMI0, - MMI_OPC_0_PEXTLB =3D (0x1A << 6) | MMI_OPC_CLASS_MMI0, - MMI_OPC_0_PPACB =3D (0x1B << 6) | MMI_OPC_CLASS_MMI0, - MMI_OPC_0_PEXT5 =3D (0x1E << 6) | MMI_OPC_CLASS_MMI0, - MMI_OPC_0_PPAC5 =3D (0x1F << 6) | MMI_OPC_CLASS_MMI0, -}; - -/* - * MMI instructions with opcode field =3D MMI and bits 5..0 =3D MMI1: - * - * 31 26 10 6 5 0 - * +--------+----------------------+--------+--------+ - * | MMI | |function| MMI1 | - * +--------+----------------------+--------+--------+ - * - * function bits 7..6 - * bits | 0 | 1 | 2 | 3 - * 10..8 | 00 | 01 | 10 | 11 - * -------+-------+-------+-------+------- - * 0 000 | * | PABSW | PCEQW | PMINW - * 1 001 | PADSBH| PABSH | PCEQH | PMINH - * 2 010 | * | * | PCEQB | * - * 3 011 | * | * | * | * - * 4 100 | PADDUW| PSUBUW| PEXTUW| * - * 5 101 | PADDUH| PSUBUH| PEXTUH| * - * 6 110 | PADDUB| PSUBUB| PEXTUB| QFSRV - * 7 111 | * | * | * | * - */ - -#define MASK_MMI1(op) (MASK_OP_MAJOR(op) | ((op) & 0x7FF)) -enum { - MMI_OPC_1_PABSW =3D (0x01 << 6) | MMI_OPC_CLASS_MMI1, - MMI_OPC_1_PCEQW =3D (0x02 << 6) | MMI_OPC_CLASS_MMI1, - MMI_OPC_1_PMINW =3D (0x03 << 6) | MMI_OPC_CLASS_MMI1, - MMI_OPC_1_PADSBH =3D (0x04 << 6) | MMI_OPC_CLASS_MMI1, - MMI_OPC_1_PABSH =3D (0x05 << 6) | MMI_OPC_CLASS_MMI1, - MMI_OPC_1_PCEQH =3D (0x06 << 6) | MMI_OPC_CLASS_MMI1, - MMI_OPC_1_PMINH =3D (0x07 << 6) | MMI_OPC_CLASS_MMI1, - MMI_OPC_1_PCEQB =3D (0x0A << 6) | MMI_OPC_CLASS_MMI1, - MMI_OPC_1_PADDUW =3D (0x10 << 6) | MMI_OPC_CLASS_MMI1, - MMI_OPC_1_PSUBUW =3D (0x11 << 6) | MMI_OPC_CLASS_MMI1, - MMI_OPC_1_PEXTUW =3D (0x12 << 6) | MMI_OPC_CLASS_MMI1, - MMI_OPC_1_PADDUH =3D (0x14 << 6) | MMI_OPC_CLASS_MMI1, - MMI_OPC_1_PSUBUH =3D (0x15 << 6) | MMI_OPC_CLASS_MMI1, - MMI_OPC_1_PEXTUH =3D (0x16 << 6) | MMI_OPC_CLASS_MMI1, - MMI_OPC_1_PADDUB =3D (0x18 << 6) | MMI_OPC_CLASS_MMI1, - MMI_OPC_1_PSUBUB =3D (0x19 << 6) | MMI_OPC_CLASS_MMI1, - MMI_OPC_1_PEXTUB =3D (0x1A << 6) | MMI_OPC_CLASS_MMI1, - MMI_OPC_1_QFSRV =3D (0x1B << 6) | MMI_OPC_CLASS_MMI1, -}; - -/* - * MMI instructions with opcode field =3D MMI and bits 5..0 =3D MMI2: - * - * 31 26 10 6 5 0 - * +--------+----------------------+--------+--------+ - * | MMI | |function| MMI2 | - * +--------+----------------------+--------+--------+ - * - * function bits 7..6 - * bits | 0 | 1 | 2 | 3 - * 10..8 | 00 | 01 | 10 | 11 - * -------+-------+-------+-------+------- - * 0 000 | PMADDW| * | PSLLVW| PSRLVW - * 1 001 | PMSUBW| * | * | * - * 2 010 | PMFHI | PMFLO | PINTH | * - * 3 011 | PMULTW| PDIVW | PCPYLD| * - * 4 100 | PMADDH| PHMADH| PAND | PXOR - * 5 101 | PMSUBH| PHMSBH| * | * - * 6 110 | * | * | PEXEH | PREVH - * 7 111 | PMULTH| PDIVBW| PEXEW | PROT3W - */ - -#define MASK_MMI2(op) (MASK_OP_MAJOR(op) | ((op) & 0x7FF)) -enum { - MMI_OPC_2_PMADDW =3D (0x00 << 6) | MMI_OPC_CLASS_MMI2, - MMI_OPC_2_PSLLVW =3D (0x02 << 6) | MMI_OPC_CLASS_MMI2, - MMI_OPC_2_PSRLVW =3D (0x03 << 6) | MMI_OPC_CLASS_MMI2, - MMI_OPC_2_PMSUBW =3D (0x04 << 6) | MMI_OPC_CLASS_MMI2, - MMI_OPC_2_PMFHI =3D (0x08 << 6) | MMI_OPC_CLASS_MMI2, - MMI_OPC_2_PMFLO =3D (0x09 << 6) | MMI_OPC_CLASS_MMI2, - MMI_OPC_2_PINTH =3D (0x0A << 6) | MMI_OPC_CLASS_MMI2, - MMI_OPC_2_PMULTW =3D (0x0C << 6) | MMI_OPC_CLASS_MMI2, - MMI_OPC_2_PDIVW =3D (0x0D << 6) | MMI_OPC_CLASS_MMI2, - MMI_OPC_2_PCPYLD =3D (0x0E << 6) | MMI_OPC_CLASS_MMI2, - MMI_OPC_2_PMADDH =3D (0x10 << 6) | MMI_OPC_CLASS_MMI2, - MMI_OPC_2_PHMADH =3D (0x11 << 6) | MMI_OPC_CLASS_MMI2, - MMI_OPC_2_PAND =3D (0x12 << 6) | MMI_OPC_CLASS_MMI2, - MMI_OPC_2_PXOR =3D (0x13 << 6) | MMI_OPC_CLASS_MMI2, - MMI_OPC_2_PMSUBH =3D (0x14 << 6) | MMI_OPC_CLASS_MMI2, - MMI_OPC_2_PHMSBH =3D (0x15 << 6) | MMI_OPC_CLASS_MMI2, - MMI_OPC_2_PEXEH =3D (0x1A << 6) | MMI_OPC_CLASS_MMI2, - MMI_OPC_2_PREVH =3D (0x1B << 6) | MMI_OPC_CLASS_MMI2, - MMI_OPC_2_PMULTH =3D (0x1C << 6) | MMI_OPC_CLASS_MMI2, - MMI_OPC_2_PDIVBW =3D (0x1D << 6) | MMI_OPC_CLASS_MMI2, - MMI_OPC_2_PEXEW =3D (0x1E << 6) | MMI_OPC_CLASS_MMI2, - MMI_OPC_2_PROT3W =3D (0x1F << 6) | MMI_OPC_CLASS_MMI2, -}; - -/* - * MMI instructions with opcode field =3D MMI and bits 5..0 =3D MMI3: - * - * 31 26 10 6 5 0 - * +--------+----------------------+--------+--------+ - * | MMI | |function| MMI3 | - * +--------+----------------------+--------+--------+ - * - * function bits 7..6 - * bits | 0 | 1 | 2 | 3 - * 10..8 | 00 | 01 | 10 | 11 - * -------+-------+-------+-------+------- - * 0 000 |PMADDUW| * | * | PSRAVW - * 1 001 | * | * | * | * - * 2 010 | PMTHI | PMTLO | PINTEH| * - * 3 011 |PMULTUW| PDIVUW| PCPYUD| * - * 4 100 | * | * | POR | PNOR - * 5 101 | * | * | * | * - * 6 110 | * | * | PEXCH | PCPYH - * 7 111 | * | * | PEXCW | * - */ - -#define MASK_MMI3(op) (MASK_OP_MAJOR(op) | ((op) & 0x7FF)) -enum { - MMI_OPC_3_PMADDUW =3D (0x00 << 6) | MMI_OPC_CLASS_MMI3, - MMI_OPC_3_PSRAVW =3D (0x03 << 6) | MMI_OPC_CLASS_MMI3, - MMI_OPC_3_PMTHI =3D (0x08 << 6) | MMI_OPC_CLASS_MMI3, - MMI_OPC_3_PMTLO =3D (0x09 << 6) | MMI_OPC_CLASS_MMI3, - MMI_OPC_3_PINTEH =3D (0x0A << 6) | MMI_OPC_CLASS_MMI3, - MMI_OPC_3_PMULTUW =3D (0x0C << 6) | MMI_OPC_CLASS_MMI3, - MMI_OPC_3_PDIVUW =3D (0x0D << 6) | MMI_OPC_CLASS_MMI3, - MMI_OPC_3_PCPYUD =3D (0x0E << 6) | MMI_OPC_CLASS_MMI3, - MMI_OPC_3_POR =3D (0x12 << 6) | MMI_OPC_CLASS_MMI3, - MMI_OPC_3_PNOR =3D (0x13 << 6) | MMI_OPC_CLASS_MMI3, - MMI_OPC_3_PEXCH =3D (0x1A << 6) | MMI_OPC_CLASS_MMI3, - MMI_OPC_3_PCPYH =3D (0x1B << 6) | MMI_OPC_CLASS_MMI3, - MMI_OPC_3_PEXCW =3D (0x1E << 6) | MMI_OPC_CLASS_MMI3, }; =20 /* global register indices */ @@ -24042,28 +23847,6 @@ static void decode_opc_special(CPUMIPSState *env, = DisasContext *ctx) } =20 =20 -#if defined(TARGET_MIPS64) - -/* - * - * MMI (MultiMedia Interface) ASE instructions - * =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D - */ - -/* - * MMI instructions category: data communication - * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - * - * PCPYH PEXCH PEXTLB PINTH PPACB PEXT5 PREVH - * PCPYLD PEXCW PEXTLH PINTEH PPACH PPAC5 PROT3W - * PCPYUD PEXEH PEXTLW PPACW - * PEXEW PEXTUB - * PEXTUH - * PEXTUW - */ - -#endif - static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ct= x) { int rs, rt, rd; @@ -24779,137 +24562,6 @@ static void decode_opc_special3_legacy(CPUMIPSSta= te *env, DisasContext *ctx) =20 #if defined(TARGET_MIPS64) =20 -static void decode_mmi0(CPUMIPSState *env, DisasContext *ctx) -{ - uint32_t opc =3D MASK_MMI0(ctx->opcode); - - switch (opc) { - case MMI_OPC_0_PADDW: /* TODO: MMI_OPC_0_PADDW */ - case MMI_OPC_0_PSUBW: /* TODO: MMI_OPC_0_PSUBW */ - case MMI_OPC_0_PCGTW: /* TODO: MMI_OPC_0_PCGTW */ - case MMI_OPC_0_PMAXW: /* TODO: MMI_OPC_0_PMAXW */ - case MMI_OPC_0_PADDH: /* TODO: MMI_OPC_0_PADDH */ - case MMI_OPC_0_PSUBH: /* TODO: MMI_OPC_0_PSUBH */ - case MMI_OPC_0_PCGTH: /* TODO: MMI_OPC_0_PCGTH */ - case MMI_OPC_0_PMAXH: /* TODO: MMI_OPC_0_PMAXH */ - case MMI_OPC_0_PADDB: /* TODO: MMI_OPC_0_PADDB */ - case MMI_OPC_0_PSUBB: /* TODO: MMI_OPC_0_PSUBB */ - case MMI_OPC_0_PCGTB: /* TODO: MMI_OPC_0_PCGTB */ - case MMI_OPC_0_PADDSW: /* TODO: MMI_OPC_0_PADDSW */ - case MMI_OPC_0_PSUBSW: /* TODO: MMI_OPC_0_PSUBSW */ - case MMI_OPC_0_PEXTLW: /* TODO: MMI_OPC_0_PEXTLW */ - case MMI_OPC_0_PPACW: /* TODO: MMI_OPC_0_PPACW */ - case MMI_OPC_0_PADDSH: /* TODO: MMI_OPC_0_PADDSH */ - case MMI_OPC_0_PSUBSH: /* TODO: MMI_OPC_0_PSUBSH */ - case MMI_OPC_0_PEXTLH: /* TODO: MMI_OPC_0_PEXTLH */ - case MMI_OPC_0_PPACH: /* TODO: MMI_OPC_0_PPACH */ - case MMI_OPC_0_PADDSB: /* TODO: MMI_OPC_0_PADDSB */ - case MMI_OPC_0_PSUBSB: /* TODO: MMI_OPC_0_PSUBSB */ - case MMI_OPC_0_PEXTLB: /* TODO: MMI_OPC_0_PEXTLB */ - case MMI_OPC_0_PPACB: /* TODO: MMI_OPC_0_PPACB */ - case MMI_OPC_0_PEXT5: /* TODO: MMI_OPC_0_PEXT5 */ - case MMI_OPC_0_PPAC5: /* TODO: MMI_OPC_0_PPAC5 */ - gen_reserved_instruction(ctx); /* TODO: MMI_OPC_CLASS_MMI0 */ - break; - default: - MIPS_INVAL("TX79 MMI class MMI0"); - gen_reserved_instruction(ctx); - break; - } -} - -static void decode_mmi1(CPUMIPSState *env, DisasContext *ctx) -{ - uint32_t opc =3D MASK_MMI1(ctx->opcode); - - switch (opc) { - case MMI_OPC_1_PABSW: /* TODO: MMI_OPC_1_PABSW */ - case MMI_OPC_1_PCEQW: /* TODO: MMI_OPC_1_PCEQW */ - case MMI_OPC_1_PMINW: /* TODO: MMI_OPC_1_PMINW */ - case MMI_OPC_1_PADSBH: /* TODO: MMI_OPC_1_PADSBH */ - case MMI_OPC_1_PABSH: /* TODO: MMI_OPC_1_PABSH */ - case MMI_OPC_1_PCEQH: /* TODO: MMI_OPC_1_PCEQH */ - case MMI_OPC_1_PMINH: /* TODO: MMI_OPC_1_PMINH */ - case MMI_OPC_1_PCEQB: /* TODO: MMI_OPC_1_PCEQB */ - case MMI_OPC_1_PADDUW: /* TODO: MMI_OPC_1_PADDUW */ - case MMI_OPC_1_PSUBUW: /* TODO: MMI_OPC_1_PSUBUW */ - case MMI_OPC_1_PEXTUW: /* TODO: MMI_OPC_1_PEXTUW */ - case MMI_OPC_1_PADDUH: /* TODO: MMI_OPC_1_PADDUH */ - case MMI_OPC_1_PSUBUH: /* TODO: MMI_OPC_1_PSUBUH */ - case MMI_OPC_1_PEXTUH: /* TODO: MMI_OPC_1_PEXTUH */ - case MMI_OPC_1_PADDUB: /* TODO: MMI_OPC_1_PADDUB */ - case MMI_OPC_1_PSUBUB: /* TODO: MMI_OPC_1_PSUBUB */ - case MMI_OPC_1_PEXTUB: /* TODO: MMI_OPC_1_PEXTUB */ - case MMI_OPC_1_QFSRV: /* TODO: MMI_OPC_1_QFSRV */ - gen_reserved_instruction(ctx); /* TODO: MMI_OPC_CLASS_MMI1 */ - break; - default: - MIPS_INVAL("TX79 MMI class MMI1"); - gen_reserved_instruction(ctx); - break; - } -} - -static void decode_mmi2(CPUMIPSState *env, DisasContext *ctx) -{ - uint32_t opc =3D MASK_MMI2(ctx->opcode); - - switch (opc) { - case MMI_OPC_2_PMADDW: /* TODO: MMI_OPC_2_PMADDW */ - case MMI_OPC_2_PSLLVW: /* TODO: MMI_OPC_2_PSLLVW */ - case MMI_OPC_2_PSRLVW: /* TODO: MMI_OPC_2_PSRLVW */ - case MMI_OPC_2_PMSUBW: /* TODO: MMI_OPC_2_PMSUBW */ - case MMI_OPC_2_PMFHI: /* TODO: MMI_OPC_2_PMFHI */ - case MMI_OPC_2_PMFLO: /* TODO: MMI_OPC_2_PMFLO */ - case MMI_OPC_2_PINTH: /* TODO: MMI_OPC_2_PINTH */ - case MMI_OPC_2_PMULTW: /* TODO: MMI_OPC_2_PMULTW */ - case MMI_OPC_2_PDIVW: /* TODO: MMI_OPC_2_PDIVW */ - case MMI_OPC_2_PMADDH: /* TODO: MMI_OPC_2_PMADDH */ - case MMI_OPC_2_PHMADH: /* TODO: MMI_OPC_2_PHMADH */ - case MMI_OPC_2_PAND: /* TODO: MMI_OPC_2_PAND */ - case MMI_OPC_2_PXOR: /* TODO: MMI_OPC_2_PXOR */ - case MMI_OPC_2_PMSUBH: /* TODO: MMI_OPC_2_PMSUBH */ - case MMI_OPC_2_PHMSBH: /* TODO: MMI_OPC_2_PHMSBH */ - case MMI_OPC_2_PEXEH: /* TODO: MMI_OPC_2_PEXEH */ - case MMI_OPC_2_PREVH: /* TODO: MMI_OPC_2_PREVH */ - case MMI_OPC_2_PMULTH: /* TODO: MMI_OPC_2_PMULTH */ - case MMI_OPC_2_PDIVBW: /* TODO: MMI_OPC_2_PDIVBW */ - case MMI_OPC_2_PEXEW: /* TODO: MMI_OPC_2_PEXEW */ - case MMI_OPC_2_PROT3W: /* TODO: MMI_OPC_2_PROT3W */ - gen_reserved_instruction(ctx); /* TODO: MMI_OPC_CLASS_MMI2 */ - break; - default: - MIPS_INVAL("TX79 MMI class MMI2"); - gen_reserved_instruction(ctx); - break; - } -} - -static void decode_mmi3(CPUMIPSState *env, DisasContext *ctx) -{ - uint32_t opc =3D MASK_MMI3(ctx->opcode); - - switch (opc) { - case MMI_OPC_3_PMADDUW: /* TODO: MMI_OPC_3_PMADDUW */ - case MMI_OPC_3_PSRAVW: /* TODO: MMI_OPC_3_PSRAVW */ - case MMI_OPC_3_PMTHI: /* TODO: MMI_OPC_3_PMTHI */ - case MMI_OPC_3_PMTLO: /* TODO: MMI_OPC_3_PMTLO */ - case MMI_OPC_3_PINTEH: /* TODO: MMI_OPC_3_PINTEH */ - case MMI_OPC_3_PMULTUW: /* TODO: MMI_OPC_3_PMULTUW */ - case MMI_OPC_3_PDIVUW: /* TODO: MMI_OPC_3_PDIVUW */ - case MMI_OPC_3_POR: /* TODO: MMI_OPC_3_POR */ - case MMI_OPC_3_PNOR: /* TODO: MMI_OPC_3_PNOR */ - case MMI_OPC_3_PEXCH: /* TODO: MMI_OPC_3_PEXCH */ - case MMI_OPC_3_PEXCW: /* TODO: MMI_OPC_3_PEXCW */ - gen_reserved_instruction(ctx); /* TODO: MMI_OPC_CLASS_MMI3 */ - break; - default: - MIPS_INVAL("TX79 MMI class MMI3"); - gen_reserved_instruction(ctx); - break; - } -} - static void decode_mmi(CPUMIPSState *env, DisasContext *ctx) { uint32_t opc =3D MASK_MMI(ctx->opcode); @@ -24918,18 +24570,6 @@ static void decode_mmi(CPUMIPSState *env, DisasCon= text *ctx) int rd =3D extract32(ctx->opcode, 11, 5); =20 switch (opc) { - case MMI_OPC_CLASS_MMI0: - decode_mmi0(env, ctx); - break; - case MMI_OPC_CLASS_MMI1: - decode_mmi1(env, ctx); - break; - case MMI_OPC_CLASS_MMI2: - decode_mmi2(env, ctx); - break; - case MMI_OPC_CLASS_MMI3: - decode_mmi3(env, ctx); - break; case MMI_OPC_MULT1: case MMI_OPC_MULTU1: case MMI_OPC_MADD: @@ -24942,17 +24582,6 @@ static void decode_mmi(CPUMIPSState *env, DisasCon= text *ctx) case MMI_OPC_DIVU1: gen_div1_tx79(ctx, opc, rs, rt); break; - case MMI_OPC_PLZCW: /* TODO: MMI_OPC_PLZCW */ - case MMI_OPC_PMFHL: /* TODO: MMI_OPC_PMFHL */ - case MMI_OPC_PMTHL: /* TODO: MMI_OPC_PMTHL */ - case MMI_OPC_PSLLH: /* TODO: MMI_OPC_PSLLH */ - case MMI_OPC_PSRLH: /* TODO: MMI_OPC_PSRLH */ - case MMI_OPC_PSRAH: /* TODO: MMI_OPC_PSRAH */ - case MMI_OPC_PSLLW: /* TODO: MMI_OPC_PSLLW */ - case MMI_OPC_PSRLW: /* TODO: MMI_OPC_PSRLW */ - case MMI_OPC_PSRAW: /* TODO: MMI_OPC_PSRAW */ - gen_reserved_instruction(ctx); /* TODO: MMI_OPC_CLASS_MMI */ - break; default: MIPS_INVAL("TX79 MMI class"); gen_reserved_instruction(ctx); --=20 2.26.2 From nobody Sat May 18 21:45:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.45 as permitted sender) client-ip=209.85.221.45; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f45.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.45 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1615665049; cv=none; d=zohomail.com; s=zohoarc; b=YhzmQns77sURLJQnd8NOZ5+Wx9MxxxeNItI1OHYAxXhY/U8qKDlvko2u8VLUtQUZb0+ZHGifcFBK01ERwHF3po/rBrsG0hVlTDf15IFSTxcosDDUqCB2IFnIUFH32+ZaDe1hJEpwMm37WEBR36qE6HPc7M0t16eyjbUOcIqZu2A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615665049; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; 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[88.21.201.17]) by smtp.gmail.com with ESMTPSA id w131sm7272644wmb.8.2021.03.13.11.50.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Mar 2021 11:50:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kGm2EJoc1XC488goSqqMRTpp1YQ8IuoqGvu+9pBStWE=; b=IJhORYTQxjz7HlVh5D/FjYbu69ZBakG74QBlp2N9C2tizdoPHJQDAPgIlx4DjyDfNK SeLMA4aM7+vOY+SX6CmSYsw4UWgjHjU5W2Uur6YLfbh9Mu/4F+IhqjUuUJQGURZ+AaYI MkCx4rQZpx2hiMZ3ukGZ9TPvBF53leVxdQiW2todHY02dUH6cziwuGmKECcfSe+nnnLP c77K27ocFTUjVEjOnwHvNgcX1Fu/6nM4Awsnuaz9tXxQyd+kYEKBLsil66WcBijA6Are lroxTzKR8yVLuL+bb9YZusihOP8Ygi/5hhr+Poc7qeriWGYXH4F06rhmcwC3qjh/IFGP J0Qw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=kGm2EJoc1XC488goSqqMRTpp1YQ8IuoqGvu+9pBStWE=; b=OP4qVR/Cjl5A+TB0QkQ1gd6CRoDkTO4bqKwbXZD2tswiWDkQVW8pCLI5KA3vaoG1Xh zm0I3KgTILGAKLBCz4cKbee52Hr0BVgwzWc/zlR6Ql+iEHx9ypFO+XkqKNisw94nwvpA Sa9IldVGHelcerPEp3ojMN3mU3nKFw1ub2vdQC8CY9EL1hYB2Twa6fZbM6HdaIiW0QZl A9SlmKPs2PGnyVD6jOspBTTQQFCofCrvzZcgM5ba4eRVC3BpxzxL943/prmQkEO/KKYJ Iw/2MaeqNf4U0PsTFSqyUrf0iOOViRu+9gWqmTXNji3bC9qbGb0wDFomxdPiC7/kbjnv gZOA== X-Gm-Message-State: AOAM532tnGg07cRBB+bnVpNkcy+RueauSgIlnlbyF8Qa1nyUbdYjyAu/ Hvr0LhU6tgF/lBBm7A0b1b3lZ7pAaclP6A== X-Google-Smtp-Source: ABdhPJxXjCSgavxjX1y/QGrYRrF+NatIoydh14mv00ZMoOFaYA0q/8TJEFY+nTuk/5PW8j+CJTMwjw== X-Received: by 2002:a05:6000:221:: with SMTP id l1mr19934338wrz.370.1615665047330; Sat, 13 Mar 2021 11:50:47 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 27/27] target/mips/tx79: Salvage instructions description comment Date: Sat, 13 Mar 2021 20:48:29 +0100 Message-Id: <20210313194829.2193621-28-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210313194829.2193621-1-f4bug@amsat.org> References: <20210313194829.2193621-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) This comment describing the tx79 opcodes is helpful. As we will implement these instructions in tx79_translate.c, move the comment there. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20210214175912.732946-15-f4bug@amsat.org> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/translate.c | 160 ----------------------------- target/mips/tx79_translate.c | 188 +++++++++++++++++++++++++++++++++++ 2 files changed, 188 insertions(+), 160 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 9334cd6df2e..c518bf3963b 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1130,166 +1130,6 @@ enum { }; =20 /* - * Overview of the TX79-specific instruction set - * =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D - * - * The R5900 and the C790 have 128-bit wide GPRs, where the upper 64 bits - * are only used by the specific quadword (128-bit) LQ/SQ load/store - * instructions and certain multimedia instructions (MMIs). These MMIs - * configure the 128-bit data path as two 64-bit, four 32-bit, eight 16-bit - * or sixteen 8-bit paths. - * - * Reference: - * - * The Toshiba TX System RISC TX79 Core Architecture manual, - * https://wiki.qemu.org/File:C790.pdf - * - * Three-Operand Multiply and Multiply-Add (4 instructions) - * -------------------------------------------------------- - * MADD [rd,] rs, rt Multiply/Add - * MADDU [rd,] rs, rt Multiply/Add Unsigned - * MULT [rd,] rs, rt Multiply (3-operand) - * MULTU [rd,] rs, rt Multiply Unsigned (3-operand) - * - * Multiply Instructions for Pipeline 1 (10 instructions) - * ------------------------------------------------------ - * MULT1 [rd,] rs, rt Multiply Pipeline 1 - * MULTU1 [rd,] rs, rt Multiply Unsigned Pipeline 1 - * DIV1 rs, rt Divide Pipeline 1 - * DIVU1 rs, rt Divide Unsigned Pipeline 1 - * MADD1 [rd,] rs, rt Multiply-Add Pipeline 1 - * MADDU1 [rd,] rs, rt Multiply-Add Unsigned Pipeline 1 - * MFHI1 rd Move From HI1 Register - * MFLO1 rd Move From LO1 Register - * MTHI1 rs Move To HI1 Register - * MTLO1 rs Move To LO1 Register - * - * Arithmetic (19 instructions) - * ---------------------------- - * PADDB rd, rs, rt Parallel Add Byte - * PSUBB rd, rs, rt Parallel Subtract Byte - * PADDH rd, rs, rt Parallel Add Halfword - * PSUBH rd, rs, rt Parallel Subtract Halfword - * PADDW rd, rs, rt Parallel Add Word - * PSUBW rd, rs, rt Parallel Subtract Word - * PADSBH rd, rs, rt Parallel Add/Subtract Halfword - * PADDSB rd, rs, rt Parallel Add with Signed Saturation Byte - * PSUBSB rd, rs, rt Parallel Subtract with Signed Saturation Byte - * PADDSH rd, rs, rt Parallel Add with Signed Saturation Halfword - * PSUBSH rd, rs, rt Parallel Subtract with Signed Saturation Half= word - * PADDSW rd, rs, rt Parallel Add with Signed Saturation Word - * PSUBSW rd, rs, rt Parallel Subtract with Signed Saturation Word - * PADDUB rd, rs, rt Parallel Add with Unsigned saturation Byte - * PSUBUB rd, rs, rt Parallel Subtract with Unsigned saturation By= te - * PADDUH rd, rs, rt Parallel Add with Unsigned saturation Halfword - * PSUBUH rd, rs, rt Parallel Subtract with Unsigned saturation Ha= lfword - * PADDUW rd, rs, rt Parallel Add with Unsigned saturation Word - * PSUBUW rd, rs, rt Parallel Subtract with Unsigned saturation Wo= rd - * - * Min/Max (4 instructions) - * ------------------------ - * PMAXH rd, rs, rt Parallel Maximum Halfword - * PMINH rd, rs, rt Parallel Minimum Halfword - * PMAXW rd, rs, rt Parallel Maximum Word - * PMINW rd, rs, rt Parallel Minimum Word - * - * Absolute (2 instructions) - * ------------------------- - * PABSH rd, rt Parallel Absolute Halfword - * PABSW rd, rt Parallel Absolute Word - * - * Logical (4 instructions) - * ------------------------ - * PAND rd, rs, rt Parallel AND - * POR rd, rs, rt Parallel OR - * PXOR rd, rs, rt Parallel XOR - * PNOR rd, rs, rt Parallel NOR - * - * Shift (9 instructions) - * ---------------------- - * PSLLH rd, rt, sa Parallel Shift Left Logical Halfword - * PSRLH rd, rt, sa Parallel Shift Right Logical Halfword - * PSRAH rd, rt, sa Parallel Shift Right Arithmetic Halfword - * PSLLW rd, rt, sa Parallel Shift Left Logical Word - * PSRLW rd, rt, sa Parallel Shift Right Logical Word - * PSRAW rd, rt, sa Parallel Shift Right Arithmetic Word - * PSLLVW rd, rt, rs Parallel Shift Left Logical Variable Word - * PSRLVW rd, rt, rs Parallel Shift Right Logical Variable Word - * PSRAVW rd, rt, rs Parallel Shift Right Arithmetic Variable Word - * - * Compare (6 instructions) - * ------------------------ - * PCGTB rd, rs, rt Parallel Compare for Greater Than Byte - * PCEQB rd, rs, rt Parallel Compare for Equal Byte - * PCGTH rd, rs, rt Parallel Compare for Greater Than Halfword - * PCEQH rd, rs, rt Parallel Compare for Equal Halfword - * PCGTW rd, rs, rt Parallel Compare for Greater Than Word - * PCEQW rd, rs, rt Parallel Compare for Equal Word - * - * LZC (1 instruction) - * ------------------- - * PLZCW rd, rs Parallel Leading Zero or One Count Word - * - * Quadword Load and Store (2 instructions) - * ---------------------------------------- - * LQ rt, offset(base) Load Quadword - * SQ rt, offset(base) Store Quadword - * - * Multiply and Divide (19 instructions) - * ------------------------------------- - * PMULTW rd, rs, rt Parallel Multiply Word - * PMULTUW rd, rs, rt Parallel Multiply Unsigned Word - * PDIVW rs, rt Parallel Divide Word - * PDIVUW rs, rt Parallel Divide Unsigned Word - * PMADDW rd, rs, rt Parallel Multiply-Add Word - * PMADDUW rd, rs, rt Parallel Multiply-Add Unsigned Word - * PMSUBW rd, rs, rt Parallel Multiply-Subtract Word - * PMULTH rd, rs, rt Parallel Multiply Halfword - * PMADDH rd, rs, rt Parallel Multiply-Add Halfword - * PMSUBH rd, rs, rt Parallel Multiply-Subtract Halfword - * PHMADH rd, rs, rt Parallel Horizontal Multiply-Add Halfword - * PHMSBH rd, rs, rt Parallel Horizontal Multiply-Subtract Halfword - * PDIVBW rs, rt Parallel Divide Broadcast Word - * PMFHI rd Parallel Move From HI Register - * PMFLO rd Parallel Move From LO Register - * PMTHI rs Parallel Move To HI Register - * PMTLO rs Parallel Move To LO Register - * PMFHL rd Parallel Move From HI/LO Register - * PMTHL rs Parallel Move To HI/LO Register - * - * Pack/Extend (11 instructions) - * ----------------------------- - * PPAC5 rd, rt Parallel Pack to 5 bits - * PPACB rd, rs, rt Parallel Pack to Byte - * PPACH rd, rs, rt Parallel Pack to Halfword - * PPACW rd, rs, rt Parallel Pack to Word - * PEXT5 rd, rt Parallel Extend Upper from 5 bits - * PEXTUB rd, rs, rt Parallel Extend Upper from Byte - * PEXTLB rd, rs, rt Parallel Extend Lower from Byte - * PEXTUH rd, rs, rt Parallel Extend Upper from Halfword - * PEXTLH rd, rs, rt Parallel Extend Lower from Halfword - * PEXTUW rd, rs, rt Parallel Extend Upper from Word - * PEXTLW rd, rs, rt Parallel Extend Lower from Word - * - * Others (16 instructions) - * ------------------------ - * PCPYH rd, rt Parallel Copy Halfword - * PCPYLD rd, rs, rt Parallel Copy Lower Doubleword - * PCPYUD rd, rs, rt Parallel Copy Upper Doubleword - * PREVH rd, rt Parallel Reverse Halfword - * PINTH rd, rs, rt Parallel Interleave Halfword - * PINTEH rd, rs, rt Parallel Interleave Even Halfword - * PEXEH rd, rt Parallel Exchange Even Halfword - * PEXCH rd, rt Parallel Exchange Center Halfword - * PEXEW rd, rt Parallel Exchange Even Word - * PEXCW rd, rt Parallel Exchange Center Word - * QFSRV rd, rs, rt Quadword Funnel Shift Right Variable - * MFSA rd Move from Shift Amount Register - * MTSA rs Move to Shift Amount Register - * MTSAB rs, immediate Move Byte Count to Shift Amount Register - * MTSAH rs, immediate Move Halfword Count to Shift Amount Register - * PROT3W rd, rt Parallel Rotate 3 Words - * * MMI (MultiMedia Instruction) encodings * =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D * diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c index 6e90eb64608..ad83774b977 100644 --- a/target/mips/tx79_translate.c +++ b/target/mips/tx79_translate.c @@ -14,6 +14,22 @@ /* Include the auto-generated decoder. */ #include "decode-tx79.c.inc" =20 +/* + * Overview of the TX79-specific instruction set + * =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + * + * The R5900 and the C790 have 128-bit wide GPRs, where the upper 64 bits + * are only used by the specific quadword (128-bit) LQ/SQ load/store + * instructions and certain multimedia instructions (MMIs). These MMIs + * configure the 128-bit data path as two 64-bit, four 32-bit, eight 16-bit + * or sixteen 8-bit paths. + * + * Reference: + * + * The Toshiba TX System RISC TX79 Core Architecture manual, + * https://wiki.qemu.org/File:C790.pdf + */ + bool decode_ext_tx79(DisasContext *ctx, uint32_t insn) { if (TARGET_LONG_BITS =3D=3D 64 && decode_tx79(ctx, insn)) { @@ -22,6 +38,30 @@ bool decode_ext_tx79(DisasContext *ctx, uint32_t insn) return false; } =20 +/* + * Three-Operand Multiply and Multiply-Add (4 instructions) + * -------------------------------------------------------- + * MADD [rd,] rs, rt Multiply/Add + * MADDU [rd,] rs, rt Multiply/Add Unsigned + * MULT [rd,] rs, rt Multiply (3-operand) + * MULTU [rd,] rs, rt Multiply Unsigned (3-operand) + */ + +/* + * Multiply Instructions for Pipeline 1 (10 instructions) + * ------------------------------------------------------ + * MULT1 [rd,] rs, rt Multiply Pipeline 1 + * MULTU1 [rd,] rs, rt Multiply Unsigned Pipeline 1 + * DIV1 rs, rt Divide Pipeline 1 + * DIVU1 rs, rt Divide Unsigned Pipeline 1 + * MADD1 [rd,] rs, rt Multiply-Add Pipeline 1 + * MADDU1 [rd,] rs, rt Multiply-Add Unsigned Pipeline 1 + * MFHI1 rd Move From HI1 Register + * MFLO1 rd Move From LO1 Register + * MTHI1 rs Move To HI1 Register + * MTLO1 rs Move To LO1 Register + */ + static bool trans_MFHI1(DisasContext *ctx, arg_rtype *a) { gen_store_gpr(cpu_HI[1], a->rd); @@ -50,6 +90,154 @@ static bool trans_MTLO1(DisasContext *ctx, arg_rtype *a) return true; } =20 +/* + * Arithmetic (19 instructions) + * ---------------------------- + * PADDB rd, rs, rt Parallel Add Byte + * PSUBB rd, rs, rt Parallel Subtract Byte + * PADDH rd, rs, rt Parallel Add Halfword + * PSUBH rd, rs, rt Parallel Subtract Halfword + * PADDW rd, rs, rt Parallel Add Word + * PSUBW rd, rs, rt Parallel Subtract Word + * PADSBH rd, rs, rt Parallel Add/Subtract Halfword + * PADDSB rd, rs, rt Parallel Add with Signed Saturation Byte + * PSUBSB rd, rs, rt Parallel Subtract with Signed Saturation Byte + * PADDSH rd, rs, rt Parallel Add with Signed Saturation Halfword + * PSUBSH rd, rs, rt Parallel Subtract with Signed Saturation Half= word + * PADDSW rd, rs, rt Parallel Add with Signed Saturation Word + * PSUBSW rd, rs, rt Parallel Subtract with Signed Saturation Word + * PADDUB rd, rs, rt Parallel Add with Unsigned saturation Byte + * PSUBUB rd, rs, rt Parallel Subtract with Unsigned saturation By= te + * PADDUH rd, rs, rt Parallel Add with Unsigned saturation Halfword + * PSUBUH rd, rs, rt Parallel Subtract with Unsigned saturation Ha= lfword + * PADDUW rd, rs, rt Parallel Add with Unsigned saturation Word + * PSUBUW rd, rs, rt Parallel Subtract with Unsigned saturation Wo= rd + */ + +/* + * Min/Max (4 instructions) + * ------------------------ + * PMAXH rd, rs, rt Parallel Maximum Halfword + * PMINH rd, rs, rt Parallel Minimum Halfword + * PMAXW rd, rs, rt Parallel Maximum Word + * PMINW rd, rs, rt Parallel Minimum Word + */ + +/* + * Absolute (2 instructions) + * ------------------------- + * PABSH rd, rt Parallel Absolute Halfword + * PABSW rd, rt Parallel Absolute Word + */ + +/* + * Logical (4 instructions) + * ------------------------ + * PAND rd, rs, rt Parallel AND + * POR rd, rs, rt Parallel OR + * PXOR rd, rs, rt Parallel XOR + * PNOR rd, rs, rt Parallel NOR + */ + +/* + * Shift (9 instructions) + * ---------------------- + * PSLLH rd, rt, sa Parallel Shift Left Logical Halfword + * PSRLH rd, rt, sa Parallel Shift Right Logical Halfword + * PSRAH rd, rt, sa Parallel Shift Right Arithmetic Halfword + * PSLLW rd, rt, sa Parallel Shift Left Logical Word + * PSRLW rd, rt, sa Parallel Shift Right Logical Word + * PSRAW rd, rt, sa Parallel Shift Right Arithmetic Word + * PSLLVW rd, rt, rs Parallel Shift Left Logical Variable Word + * PSRLVW rd, rt, rs Parallel Shift Right Logical Variable Word + * PSRAVW rd, rt, rs Parallel Shift Right Arithmetic Variable Word + */ + +/* + * Compare (6 instructions) + * ------------------------ + * PCGTB rd, rs, rt Parallel Compare for Greater Than Byte + * PCEQB rd, rs, rt Parallel Compare for Equal Byte + * PCGTH rd, rs, rt Parallel Compare for Greater Than Halfword + * PCEQH rd, rs, rt Parallel Compare for Equal Halfword + * PCGTW rd, rs, rt Parallel Compare for Greater Than Word + * PCEQW rd, rs, rt Parallel Compare for Equal Word + */ + +/* + * LZC (1 instruction) + * ------------------- + * PLZCW rd, rs Parallel Leading Zero or One Count Word + */ + +/* + * Quadword Load and Store (2 instructions) + * ---------------------------------------- + * LQ rt, offset(base) Load Quadword + * SQ rt, offset(base) Store Quadword + */ + +/* + * Multiply and Divide (19 instructions) + * ------------------------------------- + * PMULTW rd, rs, rt Parallel Multiply Word + * PMULTUW rd, rs, rt Parallel Multiply Unsigned Word + * PDIVW rs, rt Parallel Divide Word + * PDIVUW rs, rt Parallel Divide Unsigned Word + * PMADDW rd, rs, rt Parallel Multiply-Add Word + * PMADDUW rd, rs, rt Parallel Multiply-Add Unsigned Word + * PMSUBW rd, rs, rt Parallel Multiply-Subtract Word + * PMULTH rd, rs, rt Parallel Multiply Halfword + * PMADDH rd, rs, rt Parallel Multiply-Add Halfword + * PMSUBH rd, rs, rt Parallel Multiply-Subtract Halfword + * PHMADH rd, rs, rt Parallel Horizontal Multiply-Add Halfword + * PHMSBH rd, rs, rt Parallel Horizontal Multiply-Subtract Halfword + * PDIVBW rs, rt Parallel Divide Broadcast Word + * PMFHI rd Parallel Move From HI Register + * PMFLO rd Parallel Move From LO Register + * PMTHI rs Parallel Move To HI Register + * PMTLO rs Parallel Move To LO Register + * PMFHL rd Parallel Move From HI/LO Register + * PMTHL rs Parallel Move To HI/LO Register + */ + +/* + * Pack/Extend (11 instructions) + * ----------------------------- + * PPAC5 rd, rt Parallel Pack to 5 bits + * PPACB rd, rs, rt Parallel Pack to Byte + * PPACH rd, rs, rt Parallel Pack to Halfword + * PPACW rd, rs, rt Parallel Pack to Word + * PEXT5 rd, rt Parallel Extend Upper from 5 bits + * PEXTUB rd, rs, rt Parallel Extend Upper from Byte + * PEXTLB rd, rs, rt Parallel Extend Lower from Byte + * PEXTUH rd, rs, rt Parallel Extend Upper from Halfword + * PEXTLH rd, rs, rt Parallel Extend Lower from Halfword + * PEXTUW rd, rs, rt Parallel Extend Upper from Word + * PEXTLW rd, rs, rt Parallel Extend Lower from Word + */ + +/* + * Others (16 instructions) + * ------------------------ + * PCPYH rd, rt Parallel Copy Halfword + * PCPYLD rd, rs, rt Parallel Copy Lower Doubleword + * PCPYUD rd, rs, rt Parallel Copy Upper Doubleword + * PREVH rd, rt Parallel Reverse Halfword + * PINTH rd, rs, rt Parallel Interleave Halfword + * PINTEH rd, rs, rt Parallel Interleave Even Halfword + * PEXEH rd, rt Parallel Exchange Even Halfword + * PEXCH rd, rt Parallel Exchange Center Halfword + * PEXEW rd, rt Parallel Exchange Even Word + * PEXCW rd, rt Parallel Exchange Center Word + * QFSRV rd, rs, rt Quadword Funnel Shift Right Variable + * MFSA rd Move from Shift Amount Register + * MTSA rs Move to Shift Amount Register + * MTSAB rs, immediate Move Byte Count to Shift Amount Register + * MTSAH rs, immediate Move Halfword Count to Shift Amount Register + * PROT3W rd, rt Parallel Rotate 3 Words + */ + /* Parallel Copy Halfword */ static bool trans_PCPYH(DisasContext *s, arg_rtype *a) { --=20 2.26.2