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[88.21.201.17]) by smtp.gmail.com with ESMTPSA id y18sm7934661wrq.61.2021.03.12.08.24.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 Mar 2021 08:24:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3h2ByVuiQYLkvSCliAgbNV57VpJyk3eWoocPDwDsdg8=; b=cTsjpcxf7ptX2TY3ebaXZxKb99PjUv6IfrZbzgJxwqZKompZSgIopeojudCirGNu5U 28O/GmmCBdvqrwpkNTWDvif6XUA9P4aTtEIdN0Vc/5HX2bSnFRRp7vGXCLVfdZ/zXF6P VCBuMUyyqWDX4nM2Oo0NyWDDbqUL6C3ibD3ujdCuLqke3oj/q3e8J/5FlrJACtKJRdXb vrjgY2LkkJoued2fMXrSqMx+Y+VNp1hGkOzqSjRdoGBnfwLWpLjhgO0/X1q+OfStD9eT T/b1hEjSSrjCH37aWqv8STaFwCw0NwLpVqzlbIOL5vs3PeJxau2Eclj5O7wvFNibzbzC JP0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=3h2ByVuiQYLkvSCliAgbNV57VpJyk3eWoocPDwDsdg8=; b=t4imARpv0u8TigPL6UNAnZC0PI9DHa86OeAbDZ64mn4MDuN9/ibyUbs2VOqWPEioo8 kGZ5fKWpMlHdEWt/v8XBdEhOrC3V5vHZYBmo4AjGdwp2uVaYPtUwYM9NiKLKlqBAMyvJ N1zIZHleNyJNfPSIS5ua/rVJZp+df8ma+oVb5RBEh6OKwOJAV25u+u9tusJ1Y6Egx2CT s4adh/33xlN81iQK7b/lkadOS7VJOma6KsfJc9FZJbDYiJmzNtL6yonWMpcT91wqeqrj 8f9GCf612y9t5nDmf/+YUJuvCjzjmgf+fWNmesEwfz8l4t5aZZZ7VvICZ1oDy5fXliTL GM1g== X-Gm-Message-State: AOAM530yhl0VJCGTJpZafwttBpnBgCtcpeh5/QQ5C2PCj5ajJMc9WcJ8 ttMoZSZyIwpMG73gEGPc9iA= X-Google-Smtp-Source: ABdhPJw87WxNPpl+bu7+9qZlkT/hBDs7x5sMqSIHxQAjazH2omtJjdKygBVFNfjdcXcEytnSlbUh9Q== X-Received: by 2002:adf:a418:: with SMTP id d24mr14716942wra.187.1615566297291; Fri, 12 Mar 2021 08:24:57 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , "Maciej W . Rozycki" , Aleksandar Rikalo , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Fredrik Noring , Richard Henderson Subject: [PATCH v3 4/5] target/mips: Reintroduce the R5900 CPU Date: Fri, 12 Mar 2021 17:24:33 +0100 Message-Id: <20210312162434.1869129-5-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210312162434.1869129-1-f4bug@amsat.org> References: <20210312162434.1869129-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Now that we have the minimum prerequisites to support the R5900 CPU, we can reintroduce it. While we are reverting commit 823f2897bdd ("Disable R5900 support"), we effectively cherry-pick commit ed4f49ba9bb ("target/mips: Define the R5900 CPU"). This reverts commit 823f2897bdd78185f3ba33292a25105ba8bad1b5. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20210214175912.732946-31-f4bug@amsat.org> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/cpu-defs.c.inc | 59 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc index e03b2a998cd..1a73b5409f0 100644 --- a/target/mips/cpu-defs.c.inc +++ b/target/mips/cpu-defs.c.inc @@ -411,6 +411,65 @@ const mips_def_t mips_defs[] =3D .insn_flags =3D CPU_MIPS32R5, .mmu_type =3D MMU_TYPE_R4000, }, + { + /* + * The Toshiba TX System RISC TX79 Core Architecture manual + * + * https://wiki.qemu.org/File:C790.pdf + * + * describes the C790 processor that is a follow-up to the R5900. + * There are a few notable differences in that the R5900 FPU + * + * - is not IEEE 754-1985 compliant, + * - does not implement double format, and + * - its machine code is nonstandard. + */ + .name =3D "R5900", + .CP0_PRid =3D 0x00002E00, + /* No L2 cache, icache size 32k, dcache size 32k, uncached coheren= cy. */ + .CP0_Config0 =3D (0x3 << 9) | (0x3 << 6) | (0x2 << CP0C0_K0), + .CP0_Status_rw_bitmask =3D 0xF4C79C1F, +#ifdef CONFIG_USER_ONLY + /* + * R5900 hardware traps to the Linux kernel for IEEE 754-1985 and = LL/SC + * emulation. For user only, QEMU is the kernel, so we emulate the= traps + * by simply emulating the instructions directly. + * + * Note: Config1 is only used internally, the R5900 has only Confi= g0. + */ + .CP0_Config1 =3D (1 << CP0C1_FP) | (47 << CP0C1_MMU), + .CP0_LLAddr_rw_bitmask =3D 0xFFFFFFFF, + .CP0_LLAddr_shift =3D 4, + .CP1_fcr0 =3D (0x38 << FCR0_PRID) | (0x0 << FCR0_REV), + .CP1_fcr31 =3D 0, + .CP1_fcr31_rw_bitmask =3D 0x0183FFFF, +#else + /* + * The R5900 COP1 FPU implements single-precision floating-point + * operations but is not entirely IEEE 754-1985 compatible. In + * particular, + * + * - NaN (not a number) and +/- infinities are not supported; + * - exception mechanisms are not fully supported; + * - denormalized numbers are not supported; + * - rounding towards nearest and +/- infinities are not supported; + * - computed results usually differs in the least significant bit; + * - saturations can differ more than the least significant bit. + * + * Since only rounding towards zero is supported, the two least + * significant bits of FCR31 are hardwired to 01. + * + * FPU emulation is disabled here until it is implemented. + * + * Note: Config1 is only used internally, the R5900 has only Confi= g0. + */ + .CP0_Config1 =3D (47 << CP0C1_MMU), +#endif /* !CONFIG_USER_ONLY */ + .SEGBITS =3D 32, + .PABITS =3D 32, + .insn_flags =3D CPU_MIPS3 | INSN_R5900 | ASE_MMI, + .mmu_type =3D MMU_TYPE_R4000, + }, { /* A generic CPU supporting MIPS32 Release 6 ISA. FIXME: Support IEEE 754-2008 FP. --=20 2.26.2