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[88.21.201.17]) by smtp.gmail.com with ESMTPSA id a5sm8254544wrs.35.2021.03.12.08.24.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 Mar 2021 08:24:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cj7xaGDPrgy2UUgO8dM6PRrVcsRJS/AQHkPM7IdHo58=; b=Oy+8h9Urgsi8flv6zMXCr8t3k4HIqX9EM+KD3MldAL45NjN8bfWVD9CAn3HRPLNS96 FXcjO1+I1xir0DYHbvrXv5y0XBekACXWuWlNmaNyCoNsJ3dGFnV66bh02M67hDBjlNYL Bwxgd4e+dWOTMKgeJArLIVy3SzLPAsSOEm2DX3QwauEpNZN4AmJ61+71KRag/pXw5i6u P8cR+XkeeifaNHu6z7DpLw4fjgC20gQBIOrQ5FhgnHHWS11C6YfspXjF83GAyMQf84ix ETq/SmYKyay6bXIaj4uWQ3KlvOC3XKCXOKLIL+a65aR4SpciMqJPUWOzE9zOk/YH0yXZ ytUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=cj7xaGDPrgy2UUgO8dM6PRrVcsRJS/AQHkPM7IdHo58=; b=lhwbyMMZVnw01N578rc0LqcE9Vcxs6qM8JsZw9Gx2Aui+ju9FJeTYpld6V8GGYCPXw Uhfbg7j4NsbIBWwU+h6SrcR5MwrDDoiX+iwvFGKtCdcoPuijq1jSiNIfV0WdbqWECnFt cz2iNObM9QjoBdHmgT9CtusOEFQTmjm6Gzs1pSIgEYopFn9FD9VT1hVlF241/DFazN9n uMflkm2aGhe8ZZJQuReig4UY1sUdeHzXDiwgNKYth7TbWAUWwSjEnYj/k57ktPjrsXXj SGmQ5oEEx6hJSeGeLV1dVJ0MVKiQxCqHjSiJB83sZHGjHvApQJ7fqZQ4Hak1Eg3QIjbd MFfA== X-Gm-Message-State: AOAM531Oo3qfhIQaEPH6AjcAuwsOiTaFxy0h6ENu2pvFZqZagMid2mdt 8HyuGLrl9zZif8QkmhxHQeE= X-Google-Smtp-Source: ABdhPJwXptNh9KrFE+vicYo0lLqav6YOgn1veqRUNAkRTGtFTzaEzhcgj9xnuyOsnzUcpOfWXwxENg== X-Received: by 2002:adf:e68e:: with SMTP id r14mr14602282wrm.273.1615566282091; Fri, 12 Mar 2021 08:24:42 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , "Maciej W . Rozycki" , Aleksandar Rikalo , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Fredrik Noring , Richard Henderson Subject: [PATCH v3 1/5] target/mips/tx79: Introduce LQ opcode (Load Quadword) Date: Fri, 12 Mar 2021 17:24:30 +0100 Message-Id: <20210312162434.1869129-2-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210312162434.1869129-1-f4bug@amsat.org> References: <20210312162434.1869129-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Introduce the LQ opcode (Load Quadword) and remove unreachable code. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20210214175912.732946-26-f4bug@amsat.org> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/tx79.decode | 8 ++++++++ target/mips/translate.c | 16 ++-------------- target/mips/tx79_translate.c | 35 +++++++++++++++++++++++++++++++++++ 3 files changed, 45 insertions(+), 14 deletions(-) diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode index 0f748b53a64..f1f17470a00 100644 --- a/target/mips/tx79.decode +++ b/target/mips/tx79.decode @@ -13,6 +13,8 @@ =20 &rtype rs rt rd sa =20 +&itype base rt offset + ########################################################################### # Named instruction formats. These are generally used to # reduce the amount of duplication between instruction patterns. @@ -22,6 +24,8 @@ @rs ...... rs:5 ..... .......... ...... &rtype rt=3D0 rd= =3D0 sa=3D0 @rd ...... .......... rd:5 ..... ...... &rtype rs=3D0 rt= =3D0 sa=3D0 =20 +@ldst ...... base:5 rt:5 offset:16 &itype + ########################################################################### =20 MFHI1 011100 0000000000 ..... 00000 010000 @rd @@ -37,3 +41,7 @@ PCPYLD 011100 ..... ..... ..... 01110 001001 @= rs_rt_rd =20 PCPYUD 011100 ..... ..... ..... 01110 101001 @rs_rt_rd PCPYH 011100 00000 ..... ..... 11011 101001 @rt_rd + +# SPECIAL + +LQ 011110 ..... ..... ................ @ldst diff --git a/target/mips/translate.c b/target/mips/translate.c index c518bf3963b..c822083f031 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1167,7 +1167,6 @@ enum { =20 enum { MMI_OPC_CLASS_MMI =3D 0x1C << 26, /* Same as OPC_SPECIAL2 */ - MMI_OPC_LQ =3D 0x1E << 26, /* Same as OPC_MSA */ MMI_OPC_SQ =3D 0x1F << 26, /* Same as OPC_SPECIAL3 */ }; =20 @@ -24429,11 +24428,6 @@ static void decode_mmi(CPUMIPSState *env, DisasCon= text *ctx) } } =20 -static void gen_mmi_lq(CPUMIPSState *env, DisasContext *ctx) -{ - gen_reserved_instruction(ctx); /* TODO: MMI_OPC_LQ */ -} - static void gen_mmi_sq(DisasContext *ctx, int base, int rt, int offset) { gen_reserved_instruction(ctx); /* TODO: MMI_OPC_SQ */ @@ -25332,14 +25326,8 @@ static bool decode_opc_legacy(CPUMIPSState *env, D= isasContext *ctx) gen_compute_branch(ctx, op, 4, rs, rt, offset, 4); } break; - case OPC_MDMX: /* MMI_OPC_LQ */ - if (ctx->insn_flags & INSN_R5900) { -#if defined(TARGET_MIPS64) - gen_mmi_lq(env, ctx); -#endif - } else { - /* MDMX: Not implemented. */ - } + case OPC_MDMX: + /* MDMX: Not implemented. */ break; case OPC_PCREL: check_insn(ctx, ISA_MIPS_R6); diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c index ad83774b977..b5a9eb3de76 100644 --- a/target/mips/tx79_translate.c +++ b/target/mips/tx79_translate.c @@ -177,6 +177,41 @@ static bool trans_MTLO1(DisasContext *ctx, arg_rtype *= a) * SQ rt, offset(base) Store Quadword */ =20 +static bool trans_LQ(DisasContext *ctx, arg_itype *a) +{ + TCGv_i64 t0; + TCGv addr; + + if (a->rt =3D=3D 0) { + /* nop */ + return true; + } + + t0 =3D tcg_temp_new_i64(); + addr =3D tcg_temp_new(); + + gen_base_offset_addr(ctx, addr, a->base, a->offset); + /* + * Clear least-significant four bits of the effective + * address, effectively creating an aligned address. + */ + tcg_gen_andi_tl(addr, addr, ~0xf); + + /* Lower half */ + tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, MO_TEQ); + gen_store_gpr(t0, a->rt); + + /* Upper half */ + tcg_gen_addi_i64(addr, addr, 8); + tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, MO_TEQ); + gen_store_gpr_hi(t0, a->rt); + + tcg_temp_free(t0); + tcg_temp_free(addr); + + return true; +} + /* * Multiply and Divide (19 instructions) * ------------------------------------- --=20 2.26.2 From nobody Sat May 18 21:16:05 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.44 as permitted sender) client-ip=209.85.221.44; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f44.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.44 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1615566288; cv=none; d=zohomail.com; s=zohoarc; b=YL0xAVqiyVQa2mOS03qpPjt7hKnSdv0l0Z8lJmRuyY01bDTxh9wc2ZMqnO39SnM4xkO0czsnLbJKMHeVeU/dgs+PRZbbtcOybpWE1lD79Js86rdxJUvzwWsCOM0sFOadsbBEw43hKJE4htCRJ+cdS1mwixxIYnbG9XkHM1mlDCw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615566288; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=MFJpIurynqRyhm6WKyjjaiH7G1UzD6b8NLnAxQpA8KU=; b=eKOJHYNkufR1lOCzXBtyBwMELejZufI84sjCudVxcajNYrmOOrV+R9CS0guS3lOxfskxgF9E0Y/aKFqGqXAKBorQ9MqmcP6QK0YN6SjPrsG1Fwj7AbSCN0oSySsg3WXtmxOUyesZvmBKyJnY0noII58OzhRHoX3fynrkHe7G5E4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.44 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f44.google.com (mail-wr1-f44.google.com [209.85.221.44]) by mx.zohomail.com with SMTPS id 1615566288879163.40124852618476; Fri, 12 Mar 2021 08:24:48 -0800 (PST) Received: by mail-wr1-f44.google.com with SMTP id v15so5137054wrx.4 for ; Fri, 12 Mar 2021 08:24:48 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (17.red-88-21-201.staticip.rima-tde.net. [88.21.201.17]) by smtp.gmail.com with ESMTPSA id h20sm2647242wmm.19.2021.03.12.08.24.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 Mar 2021 08:24:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MFJpIurynqRyhm6WKyjjaiH7G1UzD6b8NLnAxQpA8KU=; b=vFbABkIwCdoK19IPc/6UZIPdJakyJst5vRSLQCfdlDjSyX0Sw+efqZK+TlSkDNHO5r ZXFx8UxoAixlU7gVsOrt/R+mcvFxn2gZPQ8NZkqkK62ZuA37sfcDf1T5b61B7K/HSmr+ +5tGgW1LLesfl5c6ESVrlyCUskNjGIZzom/YDaDEnNZIhqmbV/ckicXn5Zv4xkTZZqBe Cqtrr52eT45Qp4tyYMf7mUb3RHEpZy6q/cPsahBcQ/zB3wyrxaASj313ps9WqN/xYGNt tKe4efJoITMzBVi+2/50BiJKLfq7shwLT6eMM5tgLnVBBiXgbSbwP5wts59xipcUU+FJ 8Afg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=MFJpIurynqRyhm6WKyjjaiH7G1UzD6b8NLnAxQpA8KU=; b=gnVL+yHhumVuGW/kh5E0d10V900Wp6LZKPiUc0lqfAAAUxG+tVReccgd9Um3yxLguE OqM7Cu0ncPBD8M2A7gTy0h3JF+oOpxEJ/1Gqb/mH0WqabIyMlb2nSNCAZf7ANiEtI+31 3mb6N5WvOyuLdo6SrD041lFEPS4vAd2uXnF3uw6mhjgPnTS7sJl/lD50iG3b8eTBi7wU 1AKOF8VYlJKasT1qDwxtJToi6D0WLW1+3rhRJ3awGoXJhzQRe0nXbpfA7l8fhnzc6DvE QBM/JWOcOx3JW/e34Xlzku16D419ZRVWj7tkXVvu2ui3vfcRq1g5VmC0EPxy1XJzDIrs jvmg== X-Gm-Message-State: AOAM530mvvezrOa8uXVxmUWFjqP0QEjfPN5etYNW40GNgMxIQxxw/KtH Xu6TzFzOhIk5ISwX1qK6nAg= X-Google-Smtp-Source: ABdhPJxJlwsre6e/xO37BMerFwaJ76nFWEMAvLNhrq5mWYEVqaVCpN4rH27bTHOoS4BLjiFxvdkdew== X-Received: by 2002:a5d:49ca:: with SMTP id t10mr6723713wrs.76.1615566287171; Fri, 12 Mar 2021 08:24:47 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , "Maciej W . Rozycki" , Aleksandar Rikalo , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Fredrik Noring , Richard Henderson Subject: [PATCH v3 2/5] target/mips/tx79: Introduce SQ opcode (Store Quadword) Date: Fri, 12 Mar 2021 17:24:31 +0100 Message-Id: <20210312162434.1869129-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210312162434.1869129-1-f4bug@amsat.org> References: <20210312162434.1869129-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Introduce the SQ opcode (Store Quadword). Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20210214175912.732946-27-f4bug@amsat.org> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/tx79.decode | 1 + target/mips/tx79_translate.c | 27 +++++++++++++++++++++++++++ 2 files changed, 28 insertions(+) diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode index f1f17470a00..0756b13149e 100644 --- a/target/mips/tx79.decode +++ b/target/mips/tx79.decode @@ -45,3 +45,4 @@ PCPYH 011100 00000 ..... ..... 11011 101001 @= rt_rd # SPECIAL =20 LQ 011110 ..... ..... ................ @ldst +SQ 011111 ..... ..... ................ @ldst diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c index b5a9eb3de76..d840dfdb9cc 100644 --- a/target/mips/tx79_translate.c +++ b/target/mips/tx79_translate.c @@ -212,6 +212,33 @@ static bool trans_LQ(DisasContext *ctx, arg_itype *a) return true; } =20 +static bool trans_SQ(DisasContext *ctx, arg_itype *a) +{ + TCGv_i64 t0 =3D tcg_temp_new_i64(); + TCGv addr =3D tcg_temp_new(); + + gen_base_offset_addr(ctx, addr, a->base, a->offset); + /* + * Clear least-significant four bits of the effective + * address, effectively creating an aligned address. + */ + tcg_gen_andi_tl(addr, addr, ~0xf); + + /* Lower half */ + gen_load_gpr(t0, a->rt); + tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, MO_TEQ); + + /* Upper half */ + tcg_gen_addi_i64(addr, addr, 8); + gen_load_gpr_hi(t0, a->rt); + tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, MO_TEQ); + + tcg_temp_free(addr); + tcg_temp_free(t0); + + return true; +} + /* * Multiply and Divide (19 instructions) * ------------------------------------- --=20 2.26.2 From nobody Sat May 18 21:16:05 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.54 as permitted sender) client-ip=209.85.221.54; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f54.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.54 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1615566294; cv=none; d=zohomail.com; s=zohoarc; b=jTxVjJ6uHSXaNOd/PIauzGo2khV8amQFeneK4bJVdoExbX9kjyZ6daMbCF9m5u8oDcgmaqa37I6LhY/+fjMSroCDWFQdY9l/QHXGerECufDqxHVpOGvvAC1ifmtuKuLeZldaYiqX9+LN54dzPM73NL/bW0gmtrkdx8dsT0cRV6s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615566294; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=2gPDu/Ty5jqHRFQM/IZw1IHTYbKSYtKRCoaMu1hNtJg=; b=URp9x6uZhwBwxGwbivh7/1djomeOhfuTOFyrtVKn+XLId5qVAWSZxr7M7xXMG5rYKzWD0rbzPbysRTOsjuE8Ok8hL/xTSNM0kzLhQHbQS/3XgcxU0UseYrUu0DoSVYFH57g1bmXc0ZM8k3ssdhuRfXPYRE2lUUCQnqwxC1CssxA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.54 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f54.google.com (mail-wr1-f54.google.com [209.85.221.54]) by mx.zohomail.com with SMTPS id 1615566294098836.2248086265175; Fri, 12 Mar 2021 08:24:54 -0800 (PST) Received: by mail-wr1-f54.google.com with SMTP id v11so2098128wro.7 for ; Fri, 12 Mar 2021 08:24:53 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (17.red-88-21-201.staticip.rima-tde.net. [88.21.201.17]) by smtp.gmail.com with ESMTPSA id 36sm8940686wrh.94.2021.03.12.08.24.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 Mar 2021 08:24:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2gPDu/Ty5jqHRFQM/IZw1IHTYbKSYtKRCoaMu1hNtJg=; b=opaP+sKv3o+CTb/+1nZPe8WzTv0FMlPn9NoD4ukcUmfMee5p0WFmRA57rGzjmraDus +B8/hH1WAF4KwfkTAdj1vPqPOvd0Hz/qITa4VK+3fRnzGEII/SAkTbn65H0DKdC9SDFN SteFG4Tz3dT1kwKpulKVzyXaLha8Naf9eh52zh6P/kqR3X9xoHDMGht+AH/nXfRru5cs sfUHWfwOVCkJ3IoFN7ixPTjj1u4h7gZXx3vZG2zLdRzjUevxi1dO4pCNNLTLhqtfIoWu zwtrJFGu8hI6PhsJn/puRmht3Bh3K8WD47eYBiO8pICND7gz1o8BhU9fbrIBQ5EkiWrs 4XsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=2gPDu/Ty5jqHRFQM/IZw1IHTYbKSYtKRCoaMu1hNtJg=; b=cv19yQdGFpM28wYuTEshW16/Sn+CxgYaHcLDyubqjzZ7jmJqzBitzfzg8EYTWtYLQn zCQNKaw8OBGLfBAZUzJ1ZaKPmdtGT852ehEVQG0mhWpGkItEyTd37BbTwOFqwo7InJIu RNhP3bkHzUC3ytbTL69Zzx1p5aAtLuXQTMCoCVwqD+tiwou8pIZiQ3ZIANkfeaf4tCEd HMqAX24z9C5RADzRwdxfswJJItkcIVKSrUOKdAajOZkariaTS7qgBdMtmeWWYIFBC2Gs UcCa+TL1b9b9VWnIp+lB+iuWbFeWD4X861kItq9BG2Bf88h3VKsr7Q+8P0doZgRGj2XC NnJg== X-Gm-Message-State: AOAM530sDUMOd/bgHC9pROs5Y27a8If/Ro21sOQ/AhYKs2w/ImRSOw2/ RfrY5w9sa8ZUNTXZ8O4eToM= X-Google-Smtp-Source: ABdhPJytn7GnramAHLTdAS8CTpDSfs/HEECkrvhnWvw0oHWxuAORSRC2DZSkC/+wftr96QQZSQmx3w== X-Received: by 2002:adf:de91:: with SMTP id w17mr15255416wrl.268.1615566292240; Fri, 12 Mar 2021 08:24:52 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , "Maciej W . Rozycki" , Aleksandar Rikalo , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Fredrik Noring , Richard Henderson Subject: [PATCH v3 3/5] target/mips/tx79: Move RDHWR usermode kludge to trans_SQ() Date: Fri, 12 Mar 2021 17:24:32 +0100 Message-Id: <20210312162434.1869129-4-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210312162434.1869129-1-f4bug@amsat.org> References: <20210312162434.1869129-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Now than SQ is properly implemented, we can move the RDHWR kludge required to have usermode working with recent glibc. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- v2: { RDHWR_user } (rth) Fredrik, I'm not understanding fully your discussion with Maciej: https://www.mail-archive.com/qemu-devel@nongnu.org/msg783053.html So any help welcome to get your patch merged into mainstream. --- target/mips/tx79.decode | 5 +++- target/mips/translate.c | 56 ------------------------------------ target/mips/tx79_translate.c | 31 ++++++++++++++++++++ 3 files changed, 35 insertions(+), 57 deletions(-) diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode index 0756b13149e..25ddaa92bbd 100644 --- a/target/mips/tx79.decode +++ b/target/mips/tx79.decode @@ -45,4 +45,7 @@ PCPYH 011100 00000 ..... ..... 11011 101001 @= rt_rd # SPECIAL =20 LQ 011110 ..... ..... ................ @ldst -SQ 011111 ..... ..... ................ @ldst +{ + RDHWR_user 011111 00000 ..... ..... 00000 111011 @rt_rd + SQ 011111 ..... ..... ................ @ldst +} diff --git a/target/mips/translate.c b/target/mips/translate.c index c822083f031..671c67f5fc7 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1167,7 +1167,6 @@ enum { =20 enum { MMI_OPC_CLASS_MMI =3D 0x1C << 26, /* Same as OPC_SPECIAL2 */ - MMI_OPC_SQ =3D 0x1F << 26, /* Same as OPC_SPECIAL3 */ }; =20 /* @@ -24428,53 +24427,6 @@ static void decode_mmi(CPUMIPSState *env, DisasCon= text *ctx) } } =20 -static void gen_mmi_sq(DisasContext *ctx, int base, int rt, int offset) -{ - gen_reserved_instruction(ctx); /* TODO: MMI_OPC_SQ */ -} - -/* - * The TX79-specific instruction Store Quadword - * - * +--------+-------+-------+------------------------+ - * | 011111 | base | rt | offset | SQ - * +--------+-------+-------+------------------------+ - * 6 5 5 16 - * - * has the same opcode as the Read Hardware Register instruction - * - * +--------+-------+-------+-------+-------+--------+ - * | 011111 | 00000 | rt | rd | 00000 | 111011 | RDHWR - * +--------+-------+-------+-------+-------+--------+ - * 6 5 5 5 5 6 - * - * that is required, trapped and emulated by the Linux kernel. However, all - * RDHWR encodings yield address error exceptions on the TX79 since the SQ - * offset is odd. Therefore all valid SQ instructions can execute normally. - * In user mode, QEMU must verify the upper and lower 11 bits to distingui= sh - * between SQ and RDHWR, as the Linux kernel does. - */ -static void decode_mmi_sq(CPUMIPSState *env, DisasContext *ctx) -{ - int base =3D extract32(ctx->opcode, 21, 5); - int rt =3D extract32(ctx->opcode, 16, 5); - int offset =3D extract32(ctx->opcode, 0, 16); - -#ifdef CONFIG_USER_ONLY - uint32_t op1 =3D MASK_SPECIAL3(ctx->opcode); - uint32_t op2 =3D extract32(ctx->opcode, 6, 5); - - if (base =3D=3D 0 && op2 =3D=3D 0 && op1 =3D=3D OPC_RDHWR) { - int rd =3D extract32(ctx->opcode, 11, 5); - - gen_rdhwr(ctx, rt, rd, 0); - return; - } -#endif - - gen_mmi_sq(ctx, base, rt, offset); -} - #endif =20 static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx) @@ -24664,15 +24616,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, D= isasContext *ctx) decode_opc_special2_legacy(env, ctx); break; case OPC_SPECIAL3: -#if defined(TARGET_MIPS64) - if (ctx->insn_flags & INSN_R5900) { - decode_mmi_sq(env, ctx); /* MMI_OPC_SQ */ - } else { - decode_opc_special3(env, ctx); - } -#else decode_opc_special3(env, ctx); -#endif break; case OPC_REGIMM: op1 =3D MASK_REGIMM(ctx->opcode); diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c index d840dfdb9cc..3b1ef05e95b 100644 --- a/target/mips/tx79_translate.c +++ b/target/mips/tx79_translate.c @@ -239,6 +239,37 @@ static bool trans_SQ(DisasContext *ctx, arg_itype *a) return true; } =20 +/* + * The TX79-specific instruction Store Quadword + * + * +--------+-------+-------+------------------------+ + * | 011111 | base | rt | offset | SQ + * +--------+-------+-------+------------------------+ + * 6 5 5 16 + * + * has the same opcode as the Read Hardware Register instruction + * + * +--------+-------+-------+-------+-------+--------+ + * | 011111 | 00000 | rt | rd | 00000 | 111011 | RDHWR + * +--------+-------+-------+-------+-------+--------+ + * 6 5 5 5 5 6 + * + * that is required, trapped and emulated by the Linux kernel. However, all + * RDHWR encodings yield address error exceptions on the TX79 since the SQ + * offset is odd. Therefore all valid SQ instructions can execute normally. + * In user mode, QEMU must verify the upper and lower 11 bits to distingui= sh + * between SQ and RDHWR, as the Linux kernel does. + */ +static bool trans_RDHWR_user(DisasContext *ctx, arg_rtype *a) +{ +#if defined(CONFIG_USER_ONLY) + gen_rdhwr(ctx, a->rt, a->rd, 0); + return true; +#else + return false; +#endif +} + /* * Multiply and Divide (19 instructions) * ------------------------------------- --=20 2.26.2 From nobody Sat May 18 21:16:05 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) client-ip=209.85.221.53; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f53.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1615566299; cv=none; d=zohomail.com; s=zohoarc; b=k9mVb6ptaHjt3uNx370EOc8ipWQkdlaHc1Yq0mZiJkeY+HEZqfUCn9zbjJcOnoAWQmBHtPsScc9h+PcYKsiVuGxeR064VgG8QbNEz2SkvnPwyVqunOzDOizvMd9iIxAQpaiq4GwDJYzAvE+0merDaLFBXlHGPiqIcW4X9TdMFZQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615566299; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=3h2ByVuiQYLkvSCliAgbNV57VpJyk3eWoocPDwDsdg8=; b=hs6zXquK0yAX7md+DnqrXyeUj5EsYcFvI9+idPwPhCIuf0ahAhigHaimH5lgXraOqII7cTu10/OBSkm3S1d4Kq12c8v34TSz+LqPKDpicwNGsQLH0qg8O1hlUB1enpM0GAFDnkym4ysJYMg7sdDTNDlXx7fQeNl4GlyD8zxckEg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f53.google.com (mail-wr1-f53.google.com [209.85.221.53]) by mx.zohomail.com with SMTPS id 1615566299083772.8042733761082; Fri, 12 Mar 2021 08:24:59 -0800 (PST) Received: by mail-wr1-f53.google.com with SMTP id b9so2104761wrt.8 for ; Fri, 12 Mar 2021 08:24:58 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (17.red-88-21-201.staticip.rima-tde.net. [88.21.201.17]) by smtp.gmail.com with ESMTPSA id y18sm7934661wrq.61.2021.03.12.08.24.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 Mar 2021 08:24:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3h2ByVuiQYLkvSCliAgbNV57VpJyk3eWoocPDwDsdg8=; b=cTsjpcxf7ptX2TY3ebaXZxKb99PjUv6IfrZbzgJxwqZKompZSgIopeojudCirGNu5U 28O/GmmCBdvqrwpkNTWDvif6XUA9P4aTtEIdN0Vc/5HX2bSnFRRp7vGXCLVfdZ/zXF6P VCBuMUyyqWDX4nM2Oo0NyWDDbqUL6C3ibD3ujdCuLqke3oj/q3e8J/5FlrJACtKJRdXb vrjgY2LkkJoued2fMXrSqMx+Y+VNp1hGkOzqSjRdoGBnfwLWpLjhgO0/X1q+OfStD9eT T/b1hEjSSrjCH37aWqv8STaFwCw0NwLpVqzlbIOL5vs3PeJxau2Eclj5O7wvFNibzbzC JP0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=3h2ByVuiQYLkvSCliAgbNV57VpJyk3eWoocPDwDsdg8=; b=t4imARpv0u8TigPL6UNAnZC0PI9DHa86OeAbDZ64mn4MDuN9/ibyUbs2VOqWPEioo8 kGZ5fKWpMlHdEWt/v8XBdEhOrC3V5vHZYBmo4AjGdwp2uVaYPtUwYM9NiKLKlqBAMyvJ N1zIZHleNyJNfPSIS5ua/rVJZp+df8ma+oVb5RBEh6OKwOJAV25u+u9tusJ1Y6Egx2CT s4adh/33xlN81iQK7b/lkadOS7VJOma6KsfJc9FZJbDYiJmzNtL6yonWMpcT91wqeqrj 8f9GCf612y9t5nDmf/+YUJuvCjzjmgf+fWNmesEwfz8l4t5aZZZ7VvICZ1oDy5fXliTL GM1g== X-Gm-Message-State: AOAM530yhl0VJCGTJpZafwttBpnBgCtcpeh5/QQ5C2PCj5ajJMc9WcJ8 ttMoZSZyIwpMG73gEGPc9iA= X-Google-Smtp-Source: ABdhPJw87WxNPpl+bu7+9qZlkT/hBDs7x5sMqSIHxQAjazH2omtJjdKygBVFNfjdcXcEytnSlbUh9Q== X-Received: by 2002:adf:a418:: with SMTP id d24mr14716942wra.187.1615566297291; Fri, 12 Mar 2021 08:24:57 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , "Maciej W . Rozycki" , Aleksandar Rikalo , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Fredrik Noring , Richard Henderson Subject: [PATCH v3 4/5] target/mips: Reintroduce the R5900 CPU Date: Fri, 12 Mar 2021 17:24:33 +0100 Message-Id: <20210312162434.1869129-5-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210312162434.1869129-1-f4bug@amsat.org> References: <20210312162434.1869129-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Now that we have the minimum prerequisites to support the R5900 CPU, we can reintroduce it. While we are reverting commit 823f2897bdd ("Disable R5900 support"), we effectively cherry-pick commit ed4f49ba9bb ("target/mips: Define the R5900 CPU"). This reverts commit 823f2897bdd78185f3ba33292a25105ba8bad1b5. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20210214175912.732946-31-f4bug@amsat.org> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/cpu-defs.c.inc | 59 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc index e03b2a998cd..1a73b5409f0 100644 --- a/target/mips/cpu-defs.c.inc +++ b/target/mips/cpu-defs.c.inc @@ -411,6 +411,65 @@ const mips_def_t mips_defs[] =3D .insn_flags =3D CPU_MIPS32R5, .mmu_type =3D MMU_TYPE_R4000, }, + { + /* + * The Toshiba TX System RISC TX79 Core Architecture manual + * + * https://wiki.qemu.org/File:C790.pdf + * + * describes the C790 processor that is a follow-up to the R5900. + * There are a few notable differences in that the R5900 FPU + * + * - is not IEEE 754-1985 compliant, + * - does not implement double format, and + * - its machine code is nonstandard. + */ + .name =3D "R5900", + .CP0_PRid =3D 0x00002E00, + /* No L2 cache, icache size 32k, dcache size 32k, uncached coheren= cy. */ + .CP0_Config0 =3D (0x3 << 9) | (0x3 << 6) | (0x2 << CP0C0_K0), + .CP0_Status_rw_bitmask =3D 0xF4C79C1F, +#ifdef CONFIG_USER_ONLY + /* + * R5900 hardware traps to the Linux kernel for IEEE 754-1985 and = LL/SC + * emulation. For user only, QEMU is the kernel, so we emulate the= traps + * by simply emulating the instructions directly. + * + * Note: Config1 is only used internally, the R5900 has only Confi= g0. + */ + .CP0_Config1 =3D (1 << CP0C1_FP) | (47 << CP0C1_MMU), + .CP0_LLAddr_rw_bitmask =3D 0xFFFFFFFF, + .CP0_LLAddr_shift =3D 4, + .CP1_fcr0 =3D (0x38 << FCR0_PRID) | (0x0 << FCR0_REV), + .CP1_fcr31 =3D 0, + .CP1_fcr31_rw_bitmask =3D 0x0183FFFF, +#else + /* + * The R5900 COP1 FPU implements single-precision floating-point + * operations but is not entirely IEEE 754-1985 compatible. In + * particular, + * + * - NaN (not a number) and +/- infinities are not supported; + * - exception mechanisms are not fully supported; + * - denormalized numbers are not supported; + * - rounding towards nearest and +/- infinities are not supported; + * - computed results usually differs in the least significant bit; + * - saturations can differ more than the least significant bit. + * + * Since only rounding towards zero is supported, the two least + * significant bits of FCR31 are hardwired to 01. + * + * FPU emulation is disabled here until it is implemented. + * + * Note: Config1 is only used internally, the R5900 has only Confi= g0. + */ + .CP0_Config1 =3D (47 << CP0C1_MMU), +#endif /* !CONFIG_USER_ONLY */ + .SEGBITS =3D 32, + .PABITS =3D 32, + .insn_flags =3D CPU_MIPS3 | INSN_R5900 | ASE_MMI, + .mmu_type =3D MMU_TYPE_R4000, + }, { /* A generic CPU supporting MIPS32 Release 6 ISA. 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Rozycki" , Aleksandar Rikalo , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Fredrik Noring , Richard Henderson Subject: [PATCH v3 5/5] tests/tcg/mips: Test user mode DMULT for the R5900 Date: Fri, 12 Mar 2021 17:24:34 +0100 Message-Id: <20210312162434.1869129-6-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210312162434.1869129-1-f4bug@amsat.org> References: <20210312162434.1869129-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) From: Fredrik Noring The R5900 reports itself as MIPS III but does not implement DMULT. Verify that DMULT is emulated properly in user mode by multiplying two 64-bit numbers to produce a 128-bit number. Signed-off-by: Fredrik Noring Message-Id: [PMD: Moved to tests/tcg/mips/] Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- tests/tcg/mips/test-r5900-dmult.c | 40 +++++++++++++++++++++++++++++++ tests/tcg/mips/Makefile.target | 11 ++++++--- 2 files changed, 48 insertions(+), 3 deletions(-) create mode 100644 tests/tcg/mips/test-r5900-dmult.c diff --git a/tests/tcg/mips/test-r5900-dmult.c b/tests/tcg/mips/test-r5900-= dmult.c new file mode 100644 index 00000000000..2827ab5358f --- /dev/null +++ b/tests/tcg/mips/test-r5900-dmult.c @@ -0,0 +1,40 @@ +/* + * Test DMULT. + */ + +#include +#include +#include + +struct hi_lo { int64_t hi; uint64_t lo; }; + +static struct hi_lo dmult(int64_t rs, int64_t rt) +{ + int64_t hi; + uint64_t lo; + + /* + * The R5900 reports itself as MIPS III but does not implement DMULT. + * Verify that DMULT is emulated properly in user mode. + */ + __asm__ __volatile__ ( + " .set mips3\n" + " dmult %2, %3\n" + " mfhi %0\n" + " mflo %1\n" + : "=3Dr" (hi), "=3Dr" (lo) + : "r" (rs), "r" (rt)); + + return (struct hi_lo) { .hi =3D hi, .lo =3D lo }; +} + +int main() +{ + /* Verify that multiplying two 64-bit numbers yields a 128-bit number.= */ + struct hi_lo r =3D dmult(2760727302517, 5665449960167); + + assert(r.hi =3D=3D 847887); + assert(r.lo =3D=3D 7893651516417804947); + + return 0; +} diff --git a/tests/tcg/mips/Makefile.target b/tests/tcg/mips/Makefile.target index 1a994d5525e..59e9d6fb76a 100644 --- a/tests/tcg/mips/Makefile.target +++ b/tests/tcg/mips/Makefile.target @@ -11,9 +11,14 @@ VPATH +=3D $(MIPS_SRC) # hello-mips is 32 bit only ifeq ($(findstring 64,$(TARGET_NAME)),) MIPS_TESTS=3Dhello-mips - -TESTS +=3D $(MIPS_TESTS) - hello-mips: CFLAGS+=3D-mno-abicalls -fno-PIC -mabi=3D32 hello-mips: LDFLAGS+=3D-nostdlib endif + +# r5900 is only 64 bit little-endian +ifneq ($(findstring 64el,$(TARGET_NAME)),) +MIPS_TESTS +=3D test-r5900-dmult +test-r5900-dmult: CFLAGS +=3D -mabi=3Dn32 -march=3Dr5900 +endif + +TESTS +=3D $(MIPS_TESTS) --=20 2.26.2