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bh=zFgBNfN+EXZP+WSaoe1F1U579Ovmtt8f8ednlmO7Lns=; b=MoVF2pVww2nFOltJEW+B3tRwtuNCFtdjiBiteYYBGRWauXPkfymbKSZY6tetEajB+F h1lHaPVkZYrosGsuuQI0TRjiVTvhKSfJe+f1VK9SYVq5eCC6gYUjcLE48TIxampD5ueY KPUzq8CP9wF8QLlZa/Cw0UoFkDfQEiP+B3IIvfsbKrdgT6cjlr2dprpQJs1Td/6VJQJj OIXU0+QV3+9guKKgZP2JXfX4QTSZVrjPMcqjhcpPg+EzAlDmODXrURi2SlBAsxQGIkfN M933GBVVHqD6iSwPHRqh/Yc2hHWD6jTAKWDGykKszxCHGBASRO5TGXowKZKuJnTZg1i9 rMsA== X-Gm-Message-State: AOAM532Lymyk0Dh1mi6Vn9kftx3XbAAkaVLrEd8aQFIrv48gLaTLL3RE fy4EkPB3IcviD+URZ9C5cOY= X-Google-Smtp-Source: ABdhPJzJtD6uRGtSvvj7f5mjjFw9qO3q/GQgTCRoSe7Fnp3JHnjRQOqewCIU0+QPNS1+W3r4itaNNA== X-Received: by 2002:a17:902:9a45:b029:e6:1444:5287 with SMTP id x5-20020a1709029a45b02900e614445287mr10667599plv.54.1615506468670; Thu, 11 Mar 2021 15:47:48 -0800 (PST) From: Joel Stanley To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Thomas Huth , Laurent Vivier Subject: [PATCH v2 2/3] aspeed: Integrate HACE Date: Fri, 12 Mar 2021 10:17:25 +1030 Message-Id: <20210311234726.437676-3-joel@jms.id.au> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210311234726.437676-1-joel@jms.id.au> References: <20210311234726.437676-1-joel@jms.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=joel.stan@gmail.com; helo=mail-pj1-x102a.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jeffery , Paolo Bonzini , qemu-arm@nongnu.org, qemu-devel@nongnu.org, Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Add the hash and crypto engine model to the aspeed socs. Reviewed-by: Andrew Jeffery Signed-off-by: Joel Stanley --- docs/system/arm/aspeed.rst | 2 +- include/hw/arm/aspeed_soc.h | 3 +++ hw/arm/aspeed_ast2600.c | 14 ++++++++++++++ hw/arm/aspeed_soc.c | 15 +++++++++++++++ 4 files changed, 33 insertions(+), 1 deletion(-) diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst index 690bada7842b..ec30cad88a58 100644 --- a/docs/system/arm/aspeed.rst +++ b/docs/system/arm/aspeed.rst @@ -48,6 +48,7 @@ Supported devices * UART * Ethernet controllers * Front LEDs (PCA9552 on I2C bus) + * Hash/Crypto Engine (HACE) - SHA support only, no scatter-gather =20 =20 Missing devices @@ -59,7 +60,6 @@ Missing devices * LPC Bus Controller * Slave GPIO Controller * Super I/O Controller - * Hash/Crypto Engine * PCI-Express 1 Controller * Graphic Display Controller * PECI Controller diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 11cfe6e3585b..a8c9a22e5882 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -21,6 +21,7 @@ #include "hw/rtc/aspeed_rtc.h" #include "hw/i2c/aspeed_i2c.h" #include "hw/ssi/aspeed_smc.h" +#include "hw/misc/aspeed_hace.h" #include "hw/watchdog/wdt_aspeed.h" #include "hw/net/ftgmac100.h" #include "target/arm/cpu.h" @@ -49,6 +50,7 @@ struct AspeedSoCState { AspeedTimerCtrlState timerctrl; AspeedI2CState i2c; AspeedSCUState scu; + AspeedHACEState hace; AspeedXDMAState xdma; AspeedSMCState fmc; AspeedSMCState spi[ASPEED_SPIS_NUM]; @@ -130,6 +132,7 @@ enum { ASPEED_DEV_SDRAM, ASPEED_DEV_XDMA, ASPEED_DEV_EMMC, + ASPEED_DEV_HACE, }; =20 #endif /* ASPEED_SOC_H */ diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index bf31ca351feb..7aba3effd7bc 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -42,6 +42,7 @@ static const hwaddr aspeed_soc_ast2600_memmap[] =3D { [ASPEED_DEV_ETH2] =3D 0x1E680000, [ASPEED_DEV_ETH4] =3D 0x1E690000, [ASPEED_DEV_VIC] =3D 0x1E6C0000, + [ASPEED_DEV_HACE] =3D 0x1E6D0000, [ASPEED_DEV_SDMC] =3D 0x1E6E0000, [ASPEED_DEV_SCU] =3D 0x1E6E2000, [ASPEED_DEV_XDMA] =3D 0x1E6E7000, @@ -102,6 +103,7 @@ static const int aspeed_soc_ast2600_irqmap[] =3D { [ASPEED_DEV_I2C] =3D 110, /* 110 -> 125 */ [ASPEED_DEV_ETH1] =3D 2, [ASPEED_DEV_ETH2] =3D 3, + [ASPEED_DEV_HACE] =3D 4, [ASPEED_DEV_ETH3] =3D 32, [ASPEED_DEV_ETH4] =3D 33, =20 @@ -211,6 +213,8 @@ static void aspeed_soc_ast2600_init(Object *obj) =20 object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0= ], TYPE_SYSBUS_SDHCI); + + object_initialize_child(obj, "hace", &s->hace, TYPE_ASPEED_HACE); } =20 /* @@ -469,6 +473,16 @@ static void aspeed_soc_ast2600_realize(DeviceState *de= v, Error **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->emmc), 0, sc->memmap[ASPEED_DEV_EMM= C]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, aspeed_soc_get_irq(s, ASPEED_DEV_EMMC)); + + /* HACE */ + object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr), + &error_abort); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->hace), 0, sc->memmap[ASPEED_DEV_HAC= E]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, + aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); } =20 static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index 7eefd54ac07a..ce9b8f8c5d6f 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -34,6 +34,7 @@ static const hwaddr aspeed_soc_ast2400_memmap[] =3D { [ASPEED_DEV_VIC] =3D 0x1E6C0000, [ASPEED_DEV_SDMC] =3D 0x1E6E0000, [ASPEED_DEV_SCU] =3D 0x1E6E2000, + [ASPEED_DEV_HACE] =3D 0x1E6E3000, [ASPEED_DEV_XDMA] =3D 0x1E6E7000, [ASPEED_DEV_VIDEO] =3D 0x1E700000, [ASPEED_DEV_ADC] =3D 0x1E6E9000, @@ -65,6 +66,7 @@ static const hwaddr aspeed_soc_ast2500_memmap[] =3D { [ASPEED_DEV_VIC] =3D 0x1E6C0000, [ASPEED_DEV_SDMC] =3D 0x1E6E0000, [ASPEED_DEV_SCU] =3D 0x1E6E2000, + [ASPEED_DEV_HACE] =3D 0x1E6E3000, [ASPEED_DEV_XDMA] =3D 0x1E6E7000, [ASPEED_DEV_ADC] =3D 0x1E6E9000, [ASPEED_DEV_VIDEO] =3D 0x1E700000, @@ -118,6 +120,7 @@ static const int aspeed_soc_ast2400_irqmap[] =3D { [ASPEED_DEV_ETH2] =3D 3, [ASPEED_DEV_XDMA] =3D 6, [ASPEED_DEV_SDHCI] =3D 26, + [ASPEED_DEV_HACE] =3D 4, }; =20 #define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap @@ -211,6 +214,8 @@ static void aspeed_soc_init(Object *obj) object_initialize_child(obj, "sdhci[*]", &s->sdhci.slots[i], TYPE_SYSBUS_SDHCI); } + + object_initialize_child(obj, "hace", &s->hace, TYPE_ASPEED_HACE); } =20 static void aspeed_soc_realize(DeviceState *dev, Error **errp) @@ -393,6 +398,16 @@ static void aspeed_soc_realize(DeviceState *dev, Error= **errp) sc->memmap[ASPEED_DEV_SDHCI]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); + + /* HACE */ + object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr), + &error_abort); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->hace), 0, sc->memmap[ASPEED_DEV_HAC= E]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, + aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); } static Property aspeed_soc_properties[] =3D { DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION, --=20 2.30.1