From nobody Sat May 18 21:15:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1615497210; cv=none; d=zohomail.com; s=zohoarc; b=ZKvBd03v7zh7+nArBclvQ4SUJuZsS9eIFq0IES/dXJGY9Mky8PFK4vS6br9yZ2u/VbKv01BaqwYflN5eyNQSnW4DGQuBCioc78RXgNoXqLpWL4AmgxApVt7NF2VGypKKMtmjAz5Ck32JIPVq2JnEXV/gHqbYtyjjN85e8jDmeyE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615497210; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=vkltsa6ZSjbcstfoblKkNPNsJl33zFe7s81r6Z0MiW8=; b=IAsEumE65CjebFWdYDFGRhRPhRXAZjtYu4Laz6QDkb5N2nVhxNVMWY0T6nN58KEVeWiO+nXws7y8xEXeW0kvwHbL/5tnGuqn6zsaABy3XVJ1s4STXcypLqs6mChegHq1B8gFvnjzj5wk+ObtQu3oiLWInczI3MH7VRFAa8I7wD4= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1615497210194739.4038470496275; Thu, 11 Mar 2021 13:13:30 -0800 (PST) Received: from localhost ([::1]:42040 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lKSca-0002FL-WF for importer@patchew.org; Thu, 11 Mar 2021 16:13:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45562) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lKSYy-0006bb-49 for qemu-devel@nongnu.org; Thu, 11 Mar 2021 16:09:44 -0500 Received: from mout.kundenserver.de ([212.227.17.10]:51903) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lKSYv-0004xX-Nn for qemu-devel@nongnu.org; Thu, 11 Mar 2021 16:09:43 -0500 Received: from localhost.localdomain ([82.142.6.26]) by mrelayeu.kundenserver.de (mreue109 [212.227.15.183]) with ESMTPSA (Nemesis) id 1McY0J-1lshO3336b-00czBV; Thu, 11 Mar 2021 22:09:38 +0100 From: Laurent Vivier To: qemu-devel@nongnu.org Subject: [PULL 1/9] target/m68k: implement rtr instruction Date: Thu, 11 Mar 2021 22:09:26 +0100 Message-Id: <20210311210934.1935587-2-laurent@vivier.eu> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210311210934.1935587-1-laurent@vivier.eu> References: <20210311210934.1935587-1-laurent@vivier.eu> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K1:dLwuW91EHnI+SPKPMwSFv2b8hryoWJFSd8qaDOclf4lQA/cuaoB 6nCCiJ9Us5/RBKUofkLJbgfXkQaWACwokZ17H9fzBjMYDxjPIpyaRWZ7VsiB2BmKaRWnhnD bN7+0YyAsjR38+XTZBuKj9yQGBICltw8s9f9DHmauZ3iaE8dBJ6JL74LjIM3HkwYTrOYT1a iwtTWh+rugvyUBKvZsgdg== X-UI-Out-Filterresults: notjunk:1;V03:K0:r2kmfd/yGKE=:DE2Mz97Q3gMwKe0+MbgLh+ /gQO2EPP8wDwi+5QpAZu5172N+M5DPx7OSGGNTq6WxqZIkm+U/4pNHbFeNCgBv9gYXB0tX2kG 5I2cF/43PXTNCssAC0k54wYKChAXdn5T9ouOqKOtKqHaM96ApBFx1pggRRHOCOaI1/T0UZzKa sSaGdGGRzI8RpdkqZ5g0wH1QCVvNKQPXMlCOewDvu5uvYuCQyOTgQFNfzpSJWoGrQkPhBtryU Vb1TqaGOexc2OZnXxW8n4/7YeoDp3b+fkjMozTMS03i29fZTP25YiIaL7vFeL4LAcuIRGd1qw ogz47orK/SMfrs/5DD38ddhcPHkWNJrLHE0sgREdkG2ELBcBHkM+B1NICxNqB2YdCGF7JxnuL XGTgsr/HHnQZROCE1a4aXj4EXFarMZgCClu2GC6LiG6r5l4R+3rUSfZI9D2aECF8rNszwqS5f p496MaYqCw== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=212.227.17.10; envelope-from=laurent@vivier.eu; helo=mout.kundenserver.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Mark Cave-Ayland , Laurent Vivier Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" This is needed to boot MacOS ROM. Pull the condition code and the program counter from the stack. Operation: (SP) -> CCR SP + 2 -> SP (SP) -> PC SP + 4 -> SP This operation is not privileged. Reported-by: Mark Cave-Ayland Tested-by: Mark Cave-Ayland Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson Message-Id: <20210307212552.523552-1-laurent@vivier.eu> --- target/m68k/translate.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index ac936ebe8f14..200018ae6a63 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -2969,6 +2969,25 @@ DISAS_INSN(rtd) gen_jmp(s, tmp); } =20 +DISAS_INSN(rtr) +{ + TCGv tmp; + TCGv ccr; + TCGv sp; + + sp =3D tcg_temp_new(); + ccr =3D gen_load(s, OS_WORD, QREG_SP, 0, IS_USER(s)); + tcg_gen_addi_i32(sp, QREG_SP, 2); + tmp =3D gen_load(s, OS_LONG, sp, 0, IS_USER(s)); + tcg_gen_addi_i32(QREG_SP, sp, 4); + tcg_temp_free(sp); + + gen_set_sr(s, ccr, true); + tcg_temp_free(ccr); + + gen_jmp(s, tmp); +} + DISAS_INSN(rts) { TCGv tmp; @@ -6015,6 +6034,7 @@ void register_m68k_insns (CPUM68KState *env) BASE(nop, 4e71, ffff); INSN(rtd, 4e74, ffff, RTD); BASE(rts, 4e75, ffff); + INSN(rtr, 4e77, ffff, M68000); BASE(jump, 4e80, ffc0); BASE(jump, 4ec0, ffc0); INSN(addsubq, 5000, f080, M68000); --=20 2.29.2 From nobody Sat May 18 21:15:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1615497064; cv=none; d=zohomail.com; s=zohoarc; b=kKPWbe8MJxkyAv1UOewjhv3CCLUztLIZqrddwF3QkwcX8avQ6sZ10s6dK07jwOptDZ5I3LMzDTGV0PS5kY4CijqvzvgyR2Y/ozajK+MwEk3UX2mMYeD5y1kGN84+UlucnOu+5/bSJo6HZAIvBswkambr5CtxliwNSeEHy3bN6GY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615497064; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ACsF1i8AKwGxOE3tYLU5bYNqGeVpywHusbFN2CtvFk0=; b=ijY6IxTWI/IVrQ+0jUZDI0C2gUh623NiFNm56KFIfA8FNRxpZOg0PcsU3WgL7ObwPrVW7Txo2sVKODtDRZ7NHb4JKLwNTTvrYy/9nMvQH0L+VCjFA+gOPZMwHUagOeWKXrS4EXvIjRESLeMCEkkH3lLc1K8JJ8TF4b69R9NFZGw= ARC-Authentication-Results: i=1; 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Thu, 11 Mar 2021 22:09:39 +0100 From: Laurent Vivier To: qemu-devel@nongnu.org Subject: [PULL 2/9] target/m68k: don't set SSW ATC bit for physical bus errors Date: Thu, 11 Mar 2021 22:09:27 +0100 Message-Id: <20210311210934.1935587-3-laurent@vivier.eu> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210311210934.1935587-1-laurent@vivier.eu> References: <20210311210934.1935587-1-laurent@vivier.eu> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K1:wxrnRbg+7k54Zn4OHJr2pWGbUtLEPu6hHngR9kx8JqC8s29tYaZ tqqBuim90p24/wl1PIMUwsjj+OEuQiA/ht1n8cx5w+7D3JzTtnti9fQ6MjWhomjqde4V2pU iIxTLla9JtpjnrJ+xxYkIFscyTsyKIuy87ft41rGjcrNN3/NoP4ZOGAMQwUog8/ZQ26KEBe EfNkus1sSnf65CX/oa2Uw== X-UI-Out-Filterresults: notjunk:1;V03:K0:HnR1wfMOBDE=:wUYMr93OImOHinbPAmphUI WkFkZQSoMPiwM/56WWgm0sFTwD6e8p65MrqlWu3cYFR3q90JJA9lAHlKqfjE0doqZ1FBb1cEk GzvOSmniZmTW5PT7JRrkbD9S/fph2XQv8iUFhoXZYTu3AWMeKn1IwMG5wQfYvyJcy6fDSWiK3 Imca5jQdN3vtx6gVuQBdrfWsUgJJxt/U7n9edwFrg8lzvkamu14zkd656lswJhuadj91JSkk3 ihbYoZ8t/wXqZ6hKYVNIW5peWABfQgkmmVuh8TEQxW0p3ZZu+o32i6xBqmVoYHLer2MitIQwI cp6iHFgWzL5XutiXZsV/WIyr0UkeyI8cYUjrJnmMV6iPUIfaRWuGmx3wBEDXWFsgAN4EupnjS IR2YG+hJsYLZaWrNzTH2x7oFqYFjPeQ15pAea9oonOTPPGHrnTp2OUag3ZLjPEko+OR6qC+qM Zl51YR68hA== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=212.227.17.10; envelope-from=laurent@vivier.eu; helo=mout.kundenserver.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland , Laurent Vivier Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Mark Cave-Ayland If a NuBus slot doesn't contain a card, the Quadra hardware generates a phy= sical bus error if the CPU attempts to access the slot address space. Both Linux = and MacOS use a separate bus error handler during NuBus accesses in order to de= tect and recover when addressing empty slots. According to the MC68040 users manual the ATC bit of the SSW is used to distinguish between ATC faults and physical bus errors. MacOS specifically = checks the stack frame generated by a NuBus error and panics if the SSW ATC bit is= set. Update m68k_cpu_transaction_failed() so that the SSW ATC bit is not set if = the memory API returns MEMTX_DECODE_ERROR which will be used to indicate that an access to an empty NuBus slot occurred. Signed-off-by: Mark Cave-Ayland Reviewed-by: Laurent Vivier Message-Id: <20210308121155.2476-2-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier --- target/m68k/op_helper.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 730cdf774445..5f981e5bf628 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -468,7 +468,17 @@ void m68k_cpu_transaction_failed(CPUState *cs, hwaddr = physaddr, vaddr addr, =20 if (m68k_feature(env, M68K_FEATURE_M68040)) { env->mmu.mmusr =3D 0; - env->mmu.ssw |=3D M68K_ATC_040; + + /* + * According to the MC68040 users manual the ATC bit of the SSW is + * used to distinguish between ATC faults and physical bus errors. + * In the case of a bus error e.g. during nubus read from an empty + * slot this bit should not be set + */ + if (response !=3D MEMTX_DECODE_ERROR) { + env->mmu.ssw |=3D M68K_ATC_040; + } + /* FIXME: manage MMU table access error */ env->mmu.ssw &=3D ~M68K_TM_040; if (env->sr & SR_S) { /* SUPERVISOR */ --=20 2.29.2 From nobody Sat May 18 21:15:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1615497210; cv=none; d=zohomail.com; s=zohoarc; b=YAzl9IvvBU71T66fqc3QhFHLcQWJcXzQ38GWVxZ1IJnQjGVSzf2PB/gY17+k/Di5+LV/YKNVa3Wl3ka7KEaf9VJJq2Le+cynUOK6nXmmYKHvdTmSJetW3VpqC1PHHNiKEsyrirb6+2y9RLabOsEZmOQgAPmpPPoTik4xier6wZc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615497210; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=SBQpdbpgoU/6L1ret0H3Hez37+f28XKx1VHiCOn6ZKo=; b=fhrhzN7x9L3TEDgqcmBxtfk/KngtfxMceqfXt+k4T4O/2cW8PDmYltI9/BpAXsCqL72wLaNEyP5NkGPrQp6rwjWNbn6WulBRFyEA2UBSZJe/55PZL+lwAwU4gXEslKcszUV/AJ7hnBerHOy3Av9qc203wgC7clWOwpblSQRAXBY= ARC-Authentication-Results: i=1; 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Thu, 11 Mar 2021 22:09:39 +0100 From: Laurent Vivier To: qemu-devel@nongnu.org Subject: [PULL 3/9] target/m68k: reformat m68k_features enum Date: Thu, 11 Mar 2021 22:09:28 +0100 Message-Id: <20210311210934.1935587-4-laurent@vivier.eu> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210311210934.1935587-1-laurent@vivier.eu> References: <20210311210934.1935587-1-laurent@vivier.eu> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K1:sKmoVwHrc2rugZUczC7p1JGt/bStYchDJ8ABrsELnYydaCsCnju 1al+MuKjbcNYwG9pHwHc8slHJJqJF3hMmcL4V5zqGdlXss345CnfhglRFO2sXW/BSPpwjMt yttqeawepxNOQ9+MeAudKTSHVWcuaOEVXDqRIGGYHeQ7oLmzQTGMw7LKtOuqs/MeJxWwYkI mUI7za93RIJS+I+Nj3DDA== X-UI-Out-Filterresults: notjunk:1;V03:K0:6IMlN5zMgQw=:cR7eEYKnGUOkcqUAsUuYAs NW5TnrEsRrTjzhWxxc9fo6Gy+qnImpzlgW/p3TlUTq28EPMYrBiBwoFfPH9gi3hvhWMGowR1e DriDJZImcQXsUZ+pwbEAMA51heIuRKwEWzYOm+o1+tQxZQV5vePPldGlYPyKC/Hdi2AIeEWWh DJGLpX0hZ4ptvQWvYky9UzMx8x+kIAex9F1q6iUqsNaD+Zd1s/ExTJWKIDWbZnclwaxmy7xag KWxaZ0KBi+Ia+ombEiybEIsoSC2BkP8hy2uLfpzXUmd7sfxHAh805IE95zFLkVdahRK8ZwE+P Nx2VPiHYABUO6MpCfE1UL0l4YsUqeHRww1LCi5N/dUrCB5/N+SmreMrUzmmABwnpbCsJSmEWd 4TONphindNSJv503X8c7BY8dHQUMwGst98pQaZMZQcFKP1eYN2YYlRYA9TWu/VfWXO4yworT7 0pDwskFn3w== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=212.227.17.13; envelope-from=laurent@vivier.eu; helo=mout.kundenserver.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Mark Cave-Ayland , Laurent Vivier Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Mark Cave-Ayland Move the feature comment from after the feature name to the preceding line = to allow for longer feature names and descriptions without hitting the 80 character line limit. Signed-off-by: Mark Cave-Ayland Reviewed-by: Laurent Vivier Reviewed-by: Richard Henderson Message-Id: <20210308121155.2476-3-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier --- target/m68k/cpu.h | 66 +++++++++++++++++++++++++++++++---------------- 1 file changed, 44 insertions(+), 22 deletions(-) diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 7c3feeaf8a64..ce558e9b03e7 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -475,36 +475,58 @@ void do_m68k_semihosting(CPUM68KState *env, int nr); */ =20 enum m68k_features { - M68K_FEATURE_M68000, /* Base m68k instruction set */ + /* Base m68k instruction set */ + M68K_FEATURE_M68000, M68K_FEATURE_M68010, M68K_FEATURE_M68020, M68K_FEATURE_M68030, M68K_FEATURE_M68040, M68K_FEATURE_M68060, - M68K_FEATURE_CF_ISA_A, /* Base Coldfire set Rev A. */ - M68K_FEATURE_CF_ISA_B, /* (ISA B or C). */ - M68K_FEATURE_CF_ISA_APLUSC, /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C).= */ - M68K_FEATURE_BRAL, /* BRA with Long branch. (680[2346]0, ISA A+ or B).= */ + /* Base Coldfire set Rev A. */ + M68K_FEATURE_CF_ISA_A, + /* (ISA B or C). */ + M68K_FEATURE_CF_ISA_B, + /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C). */ + M68K_FEATURE_CF_ISA_APLUSC, + /* BRA with Long branch. (680[2346]0, ISA A+ or B). */ + M68K_FEATURE_BRAL, M68K_FEATURE_CF_FPU, M68K_FEATURE_CF_MAC, M68K_FEATURE_CF_EMAC, - M68K_FEATURE_CF_EMAC_B, /* Revision B EMAC (dual accumulate). */ - M68K_FEATURE_USP, /* User Stack Pointer. (680[012346]0, ISA A+, B or C= ).*/ - M68K_FEATURE_MSP, /* Master Stack Pointer. (680[234]0) */ - M68K_FEATURE_EXT_FULL, /* 68020+ full extension word. */ - M68K_FEATURE_WORD_INDEX, /* word sized address index registers. */ - M68K_FEATURE_SCALED_INDEX, /* scaled address index registers. */ - M68K_FEATURE_LONG_MULDIV, /* 32 bit mul/div. (680[2346]0, and CPU32) */ - M68K_FEATURE_QUAD_MULDIV, /* 64 bit mul/div. (680[2346]0, and CPU32) */ - M68K_FEATURE_BCCL, /* Bcc with Long branches. (680[2346]0, and CPU32)= */ - M68K_FEATURE_BITFIELD, /* BFxxx Bit field insns. (680[2346]0) */ - M68K_FEATURE_FPU, /* fpu insn. (680[46]0) */ - M68K_FEATURE_CAS, /* CAS/CAS2[WL] insns. (680[2346]0) */ - M68K_FEATURE_BKPT, /* BKPT insn. (680[12346]0, and CPU32) */ - M68K_FEATURE_RTD, /* RTD insn. (680[12346]0, and CPU32) */ - M68K_FEATURE_CHK2, /* CHK2 insn. (680[2346]0, and CPU32) */ - M68K_FEATURE_MOVEP, /* MOVEP insn. (680[01234]0, and CPU32) */ - M68K_FEATURE_MOVEC, /* MOVEC insn. (from 68010) */ + /* Revision B EMAC (dual accumulate). */ + M68K_FEATURE_CF_EMAC_B, + /* User Stack Pointer. (680[012346]0, ISA A+, B or C). */ + M68K_FEATURE_USP, + /* Master Stack Pointer. (680[234]0) */ + M68K_FEATURE_MSP, + /* 68020+ full extension word. */ + M68K_FEATURE_EXT_FULL, + /* word sized address index registers. */ + M68K_FEATURE_WORD_INDEX, + /* scaled address index registers. */ + M68K_FEATURE_SCALED_INDEX, + /* 32 bit mul/div. (680[2346]0, and CPU32) */ + M68K_FEATURE_LONG_MULDIV, + /* 64 bit mul/div. (680[2346]0, and CPU32) */ + M68K_FEATURE_QUAD_MULDIV, + /* Bcc with Long branches. (680[2346]0, and CPU32) */ + M68K_FEATURE_BCCL, + /* BFxxx Bit field insns. (680[2346]0) */ + M68K_FEATURE_BITFIELD, + /* fpu insn. (680[46]0) */ + M68K_FEATURE_FPU, + /* CAS/CAS2[WL] insns. (680[2346]0) */ + M68K_FEATURE_CAS, + /* BKPT insn. (680[12346]0, and CPU32) */ + M68K_FEATURE_BKPT, + /* RTD insn. (680[12346]0, and CPU32) */ + M68K_FEATURE_RTD, + /* CHK2 insn. (680[2346]0, and CPU32) */ + M68K_FEATURE_CHK2, + /* MOVEP insn. (680[01234]0, and CPU32) */ + M68K_FEATURE_MOVEP, + /* MOVEC insn. (from 68010) */ + M68K_FEATURE_MOVEC, }; =20 static inline int m68k_feature(CPUM68KState *env, int feature) --=20 2.29.2 From nobody Sat May 18 21:15:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1615497310; cv=none; d=zohomail.com; s=zohoarc; b=HByPp37w61RxzpyyOf3ohT+0ea/qpqneEmNEQRXkibDEfr1SWE6WH8N/M32VQzR64ERGtR9mA5DAnl7J2VMsez84BQD2kZSOMU01ZbsmMHbjHnTV5oWQSRvbpkpD0iShtcW86xA9O/+Nxv3VTMXCx3ZFJNx7Wu0LhOmINyaQwAU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615497310; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=TbnTFshjIFgj5YmVr3kLMDoMDYUOqpq5IgXXL+oaJu4=; b=k9oaPvNfrfi8eKP0MXOqnYiJkHmfZPEaLSfrEMM4Jhapt1RShVgj9UeNjQYNuuUOBwZzn6COUGHm61mblkg87BSmezi5NAfeggeg7J1aJsEeQ/0mtZQifUn7ZEaoQI3Gab4dSlqYPH0fox/kOkIa0gVb4txmV7I82FjPmxIt0cE= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1615497310785894.555813648894; Thu, 11 Mar 2021 13:15:10 -0800 (PST) Received: from localhost ([::1]:47692 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lKSeD-000562-Qc for importer@patchew.org; Thu, 11 Mar 2021 16:15:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45566) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lKSYy-0006bv-V5 for qemu-devel@nongnu.org; Thu, 11 Mar 2021 16:09:45 -0500 Received: from mout.kundenserver.de ([212.227.17.13]:54131) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lKSYw-0004xr-Cx for qemu-devel@nongnu.org; Thu, 11 Mar 2021 16:09:44 -0500 Received: from localhost.localdomain ([82.142.6.26]) by mrelayeu.kundenserver.de (mreue109 [212.227.15.183]) with ESMTPSA (Nemesis) id 1N4i3d-1lldrf1GNT-011hsV; Thu, 11 Mar 2021 22:09:40 +0100 From: Laurent Vivier To: qemu-devel@nongnu.org Subject: [PULL 4/9] target/m68k: add M68K_FEATURE_UNALIGNED_DATA feature Date: Thu, 11 Mar 2021 22:09:29 +0100 Message-Id: <20210311210934.1935587-5-laurent@vivier.eu> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210311210934.1935587-1-laurent@vivier.eu> References: <20210311210934.1935587-1-laurent@vivier.eu> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K1:ZmKagHLy5yAoXzTTIYZc4qWkGeOV/lHRoHAr9M+imcANBCizrWq i0v1mWkBMYV+ZNAEJHjs9ap4YI/H/j4dZJy4Fe4u4X4FL+mcE9HSq2pfiH8gRYiILtZkHh6 Givkl0cKsuokfFoiHE6gFSvlYFyiBYpilchvMovm1olnQXFG7OgbT2L9BBlhtZNg0qh5wWL A71zfHSeVRonGldLYTbsQ== X-UI-Out-Filterresults: notjunk:1;V03:K0:GyYSxtjEftc=:1dz21aK63cnJb0KSJmHfFz P2cEQcgUJFMEuoea8b6znWatSphDn4bYlJa60yiZc7w9VYSl1cICd/ErbqTrgVwE3o8eUCpU2 /C1j8BM+SD3yOgItsVNm0ME3DE/Bf0g6rthUVdXZljS2xz7i/obIp1W76yAYHHn3Q52ka26Gj OmmY0UeXQqhVDC3y+GoPheS+P5j33/tYelilPGf9AAQi0w1Wc4VhDf4DeB6vR8+R9VsggRcTw EBExETEktQ4sivoSw5CpbBTFtiONTroDhtdy2JbbsjSKv67EvnN34uuQgTXSsR5R7sIO2hu1t xUmgrifUCu/kUjjt9oB6A2KENhUNqqh9U86rLSLjO6BjV3QrW/1u8vtXNktgCR5gJwcLQg8fG SB1TVg7qeY+okXGOYolM/e2blIYBZlKLUljSAJ+JPMn0+Esd0g3+X879uf41zh7E3oKNRlPqI GOKLLoaZJQ== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=212.227.17.13; envelope-from=laurent@vivier.eu; helo=mout.kundenserver.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Mark Cave-Ayland , Laurent Vivier Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Mark Cave-Ayland According to the M68040UM Appendix D the requirement for data accesses to be word aligned is only for the 68000, 68008 and 68010 CPUs. Later CPUs from t= he 68020 onwards will allow unaligned data accesses but at the cost of being l= ess efficient. Add a new M68K_FEATURE_UNALIGNED_DATA feature to specify that data accesses= are not required to be word aligned, and don't perform the alignment on the sta= ck pointer when taking an exception if this feature is not selected. This is required because the MacOS DAFB driver attempts to call an A-trap with a byte-aligned stack pointer during initialisation and without this the stack pointer is off by one when the A-trap returns. Signed-off-by: Mark Cave-Ayland Reviewed-by: Laurent Vivier Reviewed-by: Richard Henderson Message-Id: <20210308121155.2476-4-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier --- target/m68k/cpu.h | 2 ++ target/m68k/cpu.c | 1 + target/m68k/op_helper.c | 5 ++++- 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index ce558e9b03e7..402c86c8769e 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -527,6 +527,8 @@ enum m68k_features { M68K_FEATURE_MOVEP, /* MOVEC insn. (from 68010) */ M68K_FEATURE_MOVEC, + /* Unaligned data accesses (680[2346]0) */ + M68K_FEATURE_UNALIGNED_DATA, }; =20 static inline int m68k_feature(CPUM68KState *env, int feature) diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 37d2ed9dc79c..a14874b4da28 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -161,6 +161,7 @@ static void m68020_cpu_initfn(Object *obj) m68k_set_feature(env, M68K_FEATURE_CAS); m68k_set_feature(env, M68K_FEATURE_CHK2); m68k_set_feature(env, M68K_FEATURE_MSP); + m68k_set_feature(env, M68K_FEATURE_UNALIGNED_DATA); } =20 /* diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 5f981e5bf628..46ff81acc9f5 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -348,7 +348,10 @@ static void m68k_interrupt_all(CPUM68KState *env, int = is_hw) cpu_m68k_set_sr(env, sr); sp =3D env->aregs[7]; =20 - sp &=3D ~1; + if (!m68k_feature(env, M68K_FEATURE_UNALIGNED_DATA)) { + sp &=3D ~1; + } + if (cs->exception_index =3D=3D EXCP_ACCESS) { if (env->mmu.fault) { cpu_abort(cs, "DOUBLE MMU FAULT\n"); --=20 2.29.2 From nobody Sat May 18 21:15:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1615497711; cv=none; d=zohomail.com; s=zohoarc; b=WKTVaK0cyd0eAiE6LVUovbitNQBiswadIN6O6N/HshhUB9L1qTX6IHd0vdnADjeSisTIXjkUph60YKd6zq+UnAVsWTC+b+HknzwycyJ7eDclL2WqyrcFhfy496CuyIS5sgIKm1u+eqf8ULf2bxm/ggycpUiXeT+maLbM5EM1VL8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615497711; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Xt7/abnTmNRYQdf7pgXpX7GhpEvjNrGmTz+dr2Qn/Ic=; b=cx/w98dDbDPK/9SD47g6zRNMIiBfEbjQ+XIJvS+WHvbqli08OHOyX6jhKME/kKtRUP3vu1zr4thnMaS+Dct3MwJgGss6O3njQb9baKOo153b7TE92eG4XLGhdkd6j+bANRVLgZAoIhrwLdbKBGEFEPeHa1Af+I6uaA0Nr0oDStg= ARC-Authentication-Results: i=1; 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Thu, 11 Mar 2021 22:09:41 +0100 From: Laurent Vivier To: qemu-devel@nongnu.org Subject: [PULL 5/9] char: add goldfish-tty Date: Thu, 11 Mar 2021 22:09:30 +0100 Message-Id: <20210311210934.1935587-6-laurent@vivier.eu> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210311210934.1935587-1-laurent@vivier.eu> References: <20210311210934.1935587-1-laurent@vivier.eu> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K1:EJD8nxh1KbmWqONChKKWIcFEoDiwfAjWpK3/M7vw9zD9Uej74+A YCigd1G5GNen8XqbLkook2IX9xaX1nWRz45DsJ6/2Ulfh4aShaRsDunUT2AoJjyifvl0Sqe yVjV+YufrqpqVqcOAv/AZM/BQRpa8ZIRGyKam55CYVVQG6IqCWVy4bEizgvYG47m2Ao3C90 CGVasqMeiSrOYY1EjiyTA== X-UI-Out-Filterresults: notjunk:1;V03:K0:PW8LGMEBpZI=:BlcTO6/W5HmtIctiZcLnR/ qcjezoWb3ebbQpmI4E36yQVfUTUSP02M06PsxnkDI+O/xN8ayJ1nNeQkTUcRDxkMIGyS0g0M5 p/pBYJtI+7xIloHHiS4dMpsluJiRJPKhkuhisII3YNfWqgPFYJc1KmTWdrukM6c8sr7H74cCB DfZmBUA6kXQ5iOmhReaqyDxexa2aFWls7zI+qfyV8dDjZ0ZwZcTnPYqPPPIgx7YPlGDoOFobk dpIxkZs4+tTEhP79kf3AJAugJXzn+xzOIEkz9XTfZJRwJFORfLTR789UuqbWKYnTPWyMiLn1t 7vfTsIKzmYvTkiIr8LvEM5lHMKRwU+xOgkDA+WwwAljZpQRWKxYPGQmPuk9IJXbab6TS1UmP2 ct4P5Y8ELrG/yVoS2uSnCa8KhRiLfrJhft51Jrod17G5ORn/z+0yFM7caK/8Pn8VA/ctYgtqg ysl8bL/quQ== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=217.72.192.74; envelope-from=laurent@vivier.eu; helo=mout.kundenserver.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Implement the goldfish tty device as defined in https://android.googlesource.com/platform/external/qemu/+/master/docs/GOLDF= ISH-VIRTUAL-HARDWARE.TXT and based on the kernel driver code: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/dri= vers/tty/goldfish.c Signed-off-by: Laurent Vivier Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20210309195941.763896-2-laurent@vivier.eu> Signed-off-by: Laurent Vivier --- include/hw/char/goldfish_tty.h | 35 ++++ hw/char/goldfish_tty.c | 283 +++++++++++++++++++++++++++++++++ hw/char/Kconfig | 3 + hw/char/meson.build | 2 + hw/char/trace-events | 10 ++ 5 files changed, 333 insertions(+) create mode 100644 include/hw/char/goldfish_tty.h create mode 100644 hw/char/goldfish_tty.c diff --git a/include/hw/char/goldfish_tty.h b/include/hw/char/goldfish_tty.h new file mode 100644 index 000000000000..b9dd67362a68 --- /dev/null +++ b/include/hw/char/goldfish_tty.h @@ -0,0 +1,35 @@ +/* + * SPDX-License-Identifer: GPL-2.0-or-later + * + * Goldfish TTY + * + * (c) 2020 Laurent Vivier + * + */ + +#ifndef HW_CHAR_GOLDFISH_TTY_H +#define HW_CHAR_GOLDFISH_TTY_H + +#include "qemu/fifo8.h" +#include "chardev/char-fe.h" + +#define TYPE_GOLDFISH_TTY "goldfish_tty" +OBJECT_DECLARE_SIMPLE_TYPE(GoldfishTTYState, GOLDFISH_TTY) + +#define GOLFISH_TTY_BUFFER_SIZE 128 + +struct GoldfishTTYState { + SysBusDevice parent_obj; + + MemoryRegion iomem; + qemu_irq irq; + CharBackend chr; + + uint32_t data_len; + uint64_t data_ptr; + bool int_enabled; + + Fifo8 rx_fifo; +}; + +#endif diff --git a/hw/char/goldfish_tty.c b/hw/char/goldfish_tty.c new file mode 100644 index 000000000000..9f705f8653cc --- /dev/null +++ b/hw/char/goldfish_tty.c @@ -0,0 +1,283 @@ +/* + * SPDX-License-Identifer: GPL-2.0-or-later + * + * Goldfish TTY + * + * (c) 2020 Laurent Vivier + * + */ + +#include "qemu/osdep.h" +#include "hw/irq.h" +#include "hw/qdev-properties-system.h" +#include "hw/sysbus.h" +#include "migration/vmstate.h" +#include "chardev/char-fe.h" +#include "qemu/log.h" +#include "trace.h" +#include "exec/address-spaces.h" +#include "hw/char/goldfish_tty.h" + +/* registers */ + +enum { + REG_PUT_CHAR =3D 0x00, + REG_BYTES_READY =3D 0x04, + REG_CMD =3D 0x08, + REG_DATA_PTR =3D 0x10, + REG_DATA_LEN =3D 0x14, + REG_DATA_PTR_HIGH =3D 0x18, + REG_VERSION =3D 0x20, +}; + +/* commands */ + +enum { + CMD_INT_DISABLE =3D 0x00, + CMD_INT_ENABLE =3D 0x01, + CMD_WRITE_BUFFER =3D 0x02, + CMD_READ_BUFFER =3D 0x03, +}; + +static uint64_t goldfish_tty_read(void *opaque, hwaddr addr, + unsigned size) +{ + GoldfishTTYState *s =3D opaque; + uint64_t value =3D 0; + + switch (addr) { + case REG_BYTES_READY: + value =3D fifo8_num_used(&s->rx_fifo); + break; + case REG_VERSION: + value =3D 0; + break; + default: + qemu_log_mask(LOG_UNIMP, + "%s: unimplemented register read 0x%02"HWADDR_PRIx"\= n", + __func__, addr); + break; + } + + trace_goldfish_tty_read(s, addr, size, value); + + return value; +} + +static void goldfish_tty_cmd(GoldfishTTYState *s, uint32_t cmd) +{ + uint32_t to_copy; + uint8_t *buf; + uint8_t data_out[GOLFISH_TTY_BUFFER_SIZE]; + int len; + uint64_t ptr; + + switch (cmd) { + case CMD_INT_DISABLE: + if (s->int_enabled) { + if (!fifo8_is_empty(&s->rx_fifo)) { + qemu_set_irq(s->irq, 0); + } + s->int_enabled =3D false; + } + break; + case CMD_INT_ENABLE: + if (!s->int_enabled) { + if (!fifo8_is_empty(&s->rx_fifo)) { + qemu_set_irq(s->irq, 1); + } + s->int_enabled =3D true; + } + break; + case CMD_WRITE_BUFFER: + len =3D s->data_len; + ptr =3D s->data_ptr; + while (len) { + to_copy =3D MIN(GOLFISH_TTY_BUFFER_SIZE, len); + + address_space_rw(&address_space_memory, ptr, + MEMTXATTRS_UNSPECIFIED, data_out, to_copy, 0); + qemu_chr_fe_write_all(&s->chr, data_out, to_copy); + + len -=3D to_copy; + ptr +=3D to_copy; + } + break; + case CMD_READ_BUFFER: + len =3D s->data_len; + ptr =3D s->data_ptr; + while (len && !fifo8_is_empty(&s->rx_fifo)) { + buf =3D (uint8_t *)fifo8_pop_buf(&s->rx_fifo, len, &to_copy); + address_space_rw(&address_space_memory, ptr, + MEMTXATTRS_UNSPECIFIED, buf, to_copy, 1); + + len -=3D to_copy; + ptr +=3D to_copy; + } + if (s->int_enabled && fifo8_is_empty(&s->rx_fifo)) { + qemu_set_irq(s->irq, 0); + } + break; + } +} + +static void goldfish_tty_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size) +{ + GoldfishTTYState *s =3D opaque; + unsigned char c; + + trace_goldfish_tty_write(s, addr, size, value); + + switch (addr) { + case REG_PUT_CHAR: + c =3D value; + qemu_chr_fe_write_all(&s->chr, &c, sizeof(c)); + break; + case REG_CMD: + goldfish_tty_cmd(s, value); + break; + case REG_DATA_PTR: + s->data_ptr =3D value; + break; + case REG_DATA_PTR_HIGH: + s->data_ptr =3D deposit64(s->data_ptr, 32, 32, value); + break; + case REG_DATA_LEN: + s->data_len =3D value; + break; + default: + qemu_log_mask(LOG_UNIMP, + "%s: unimplemented register write 0x%02"HWADDR_PRIx"= \n", + __func__, addr); + break; + } +} + +static const MemoryRegionOps goldfish_tty_ops =3D { + .read =3D goldfish_tty_read, + .write =3D goldfish_tty_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid.max_access_size =3D 4, + .impl.max_access_size =3D 4, + .impl.min_access_size =3D 4, +}; + +static int goldfish_tty_can_receive(void *opaque) +{ + GoldfishTTYState *s =3D opaque; + int available =3D fifo8_num_free(&s->rx_fifo); + + trace_goldfish_tty_can_receive(s, available); + + return available; +} + +static void goldfish_tty_receive(void *opaque, const uint8_t *buffer, int = size) +{ + GoldfishTTYState *s =3D opaque; + + trace_goldfish_tty_receive(s, size); + + g_assert(size <=3D fifo8_num_free(&s->rx_fifo)); + + fifo8_push_all(&s->rx_fifo, buffer, size); + + if (s->int_enabled && !fifo8_is_empty(&s->rx_fifo)) { + qemu_set_irq(s->irq, 1); + } +} + +static void goldfish_tty_reset(DeviceState *dev) +{ + GoldfishTTYState *s =3D GOLDFISH_TTY(dev); + + trace_goldfish_tty_reset(s); + + fifo8_reset(&s->rx_fifo); + s->int_enabled =3D false; + s->data_ptr =3D 0; + s->data_len =3D 0; +} + +static void goldfish_tty_realize(DeviceState *dev, Error **errp) +{ + GoldfishTTYState *s =3D GOLDFISH_TTY(dev); + + trace_goldfish_tty_realize(s); + + fifo8_create(&s->rx_fifo, GOLFISH_TTY_BUFFER_SIZE); + memory_region_init_io(&s->iomem, OBJECT(s), &goldfish_tty_ops, s, + "goldfish_tty", 0x24); + + if (qemu_chr_fe_backend_connected(&s->chr)) { + qemu_chr_fe_set_handlers(&s->chr, goldfish_tty_can_receive, + goldfish_tty_receive, NULL, NULL, + s, NULL, true); + } +} + +static void goldfish_tty_unrealize(DeviceState *dev) +{ + GoldfishTTYState *s =3D GOLDFISH_TTY(dev); + + trace_goldfish_tty_unrealize(s); + + fifo8_destroy(&s->rx_fifo); +} + +static const VMStateDescription vmstate_goldfish_tty =3D { + .name =3D "goldfish_tty", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32(data_len, GoldfishTTYState), + VMSTATE_UINT64(data_ptr, GoldfishTTYState), + VMSTATE_BOOL(int_enabled, GoldfishTTYState), + VMSTATE_FIFO8(rx_fifo, GoldfishTTYState), + VMSTATE_END_OF_LIST() + } +}; + +static Property goldfish_tty_properties[] =3D { + DEFINE_PROP_CHR("chardev", GoldfishTTYState, chr), + DEFINE_PROP_END_OF_LIST(), +}; + +static void goldfish_tty_instance_init(Object *obj) +{ + SysBusDevice *dev =3D SYS_BUS_DEVICE(obj); + GoldfishTTYState *s =3D GOLDFISH_TTY(obj); + + trace_goldfish_tty_instance_init(s); + + sysbus_init_mmio(dev, &s->iomem); + sysbus_init_irq(dev, &s->irq); +} + +static void goldfish_tty_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + device_class_set_props(dc, goldfish_tty_properties); + dc->reset =3D goldfish_tty_reset; + dc->realize =3D goldfish_tty_realize; + dc->unrealize =3D goldfish_tty_unrealize; + dc->vmsd =3D &vmstate_goldfish_tty; + set_bit(DEVICE_CATEGORY_INPUT, dc->categories); +} + +static const TypeInfo goldfish_tty_info =3D { + .name =3D TYPE_GOLDFISH_TTY, + .parent =3D TYPE_SYS_BUS_DEVICE, + .class_init =3D goldfish_tty_class_init, + .instance_init =3D goldfish_tty_instance_init, + .instance_size =3D sizeof(GoldfishTTYState), +}; + +static void goldfish_tty_register_types(void) +{ + type_register_static(&goldfish_tty_info); +} + +type_init(goldfish_tty_register_types) diff --git a/hw/char/Kconfig b/hw/char/Kconfig index f6f4fffd1b7c..4cf36ac637ba 100644 --- a/hw/char/Kconfig +++ b/hw/char/Kconfig @@ -64,3 +64,6 @@ config MCHP_PFSOC_MMUART =20 config SIFIVE_UART bool + +config GOLDFISH_TTY + bool diff --git a/hw/char/meson.build b/hw/char/meson.build index afe9a0af88c1..6f5c3e5b5bfa 100644 --- a/hw/char/meson.build +++ b/hw/char/meson.build @@ -39,3 +39,5 @@ specific_ss.add(when: 'CONFIG_HTIF', if_true: files('risc= v_htif.c')) specific_ss.add(when: 'CONFIG_TERMINAL3270', if_true: files('terminal3270.= c')) specific_ss.add(when: 'CONFIG_VIRTIO', if_true: files('virtio-serial-bus.c= ')) specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_vty.c')) + +specific_ss.add(when: 'CONFIG_GOLDFISH_TTY', if_true: files('goldfish_tty.= c')) diff --git a/hw/char/trace-events b/hw/char/trace-events index 81026f661277..76d52938ead3 100644 --- a/hw/char/trace-events +++ b/hw/char/trace-events @@ -20,6 +20,16 @@ virtio_console_flush_buf(unsigned int port, size_t len, = ssize_t ret) "port %u, i virtio_console_chr_read(unsigned int port, int size) "port %u, size %d" virtio_console_chr_event(unsigned int port, int event) "port %u, event %d" =20 +# goldfish_tty.c +goldfish_tty_read(void *dev, unsigned int addr, unsigned int size, uint64_= t value) "tty: %p reg: 0x%02x size: %d value: 0x%"PRIx64 +goldfish_tty_write(void *dev, unsigned int addr, unsigned int size, uint64= _t value) "tty: %p reg: 0x%02x size: %d value: 0x%"PRIx64 +goldfish_tty_can_receive(void *dev, unsigned int available) "tty: %p avail= able: %u" +goldfish_tty_receive(void *dev, unsigned int size) "tty: %p size: %u" +goldfish_tty_reset(void *dev) "tty: %p" +goldfish_tty_realize(void *dev) "tty: %p" +goldfish_tty_unrealize(void *dev) "tty: %p" +goldfish_tty_instance_init(void *dev) "tty: %p" + # grlib_apbuart.c grlib_apbuart_event(int event) "event:%d" grlib_apbuart_writel_unknown(uint64_t addr, uint32_t value) "addr 0x%"PRIx= 64" value 0x%x" --=20 2.29.2 From nobody Sat May 18 21:15:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 11 Mar 2021 13:11:14 -0800 (PST) Received: from localhost ([::1]:36408 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lKSaP-0008HG-4Y for importer@patchew.org; Thu, 11 Mar 2021 16:11:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45624) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lKSZ7-0006pr-Px for qemu-devel@nongnu.org; Thu, 11 Mar 2021 16:09:53 -0500 Received: from mout.kundenserver.de ([212.227.17.10]:52513) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lKSZ5-00053D-Hv for qemu-devel@nongnu.org; Thu, 11 Mar 2021 16:09:53 -0500 Received: from localhost.localdomain ([82.142.6.26]) by mrelayeu.kundenserver.de (mreue109 [212.227.15.183]) with ESMTPSA (Nemesis) id 1MIMXC-1lYo2T2QFw-00EQwm; Thu, 11 Mar 2021 22:09:41 +0100 From: Laurent Vivier To: qemu-devel@nongnu.org Subject: [PULL 6/9] intc: add goldfish-pic Date: Thu, 11 Mar 2021 22:09:31 +0100 Message-Id: <20210311210934.1935587-7-laurent@vivier.eu> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210311210934.1935587-1-laurent@vivier.eu> References: <20210311210934.1935587-1-laurent@vivier.eu> MIME-Version: 1.0 Content-Type: text/plain; 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helo=lists.gnu.org; Received-SPF: none client-ip=212.227.17.10; envelope-from=laurent@vivier.eu; helo=mout.kundenserver.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Implement the goldfish pic device as defined in https://android.googlesource.com/platform/external/qemu/+/master/docs/GOLDF= ISH-VIRTUAL-HARDWARE.TXT Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20210309195941.763896-3-laurent@vivier.eu> Signed-off-by: Laurent Vivier --- include/hw/intc/goldfish_pic.h | 33 +++++ hw/intc/goldfish_pic.c | 219 +++++++++++++++++++++++++++++++++ hw/intc/Kconfig | 3 + hw/intc/meson.build | 1 + hw/intc/trace-events | 8 ++ 5 files changed, 264 insertions(+) create mode 100644 include/hw/intc/goldfish_pic.h create mode 100644 hw/intc/goldfish_pic.c diff --git a/include/hw/intc/goldfish_pic.h b/include/hw/intc/goldfish_pic.h new file mode 100644 index 000000000000..ad13ab37fc3e --- /dev/null +++ b/include/hw/intc/goldfish_pic.h @@ -0,0 +1,33 @@ +/* + * SPDX-License-Identifer: GPL-2.0-or-later + * + * Goldfish PIC + * + * (c) 2020 Laurent Vivier + * + */ + +#ifndef HW_INTC_GOLDFISH_PIC_H +#define HW_INTC_GOLDFISH_PIC_H + +#define TYPE_GOLDFISH_PIC "goldfish_pic" +OBJECT_DECLARE_SIMPLE_TYPE(GoldfishPICState, GOLDFISH_PIC) + +#define GOLDFISH_PIC_IRQ_NB 32 + +struct GoldfishPICState { + SysBusDevice parent_obj; + + MemoryRegion iomem; + qemu_irq irq; + + uint32_t pending; + uint32_t enabled; + + /* statistics */ + uint64_t stats_irq_count[32]; + /* for tracing */ + uint8_t idx; +}; + +#endif diff --git a/hw/intc/goldfish_pic.c b/hw/intc/goldfish_pic.c new file mode 100644 index 000000000000..e3b43a69f163 --- /dev/null +++ b/hw/intc/goldfish_pic.c @@ -0,0 +1,219 @@ +/* + * SPDX-License-Identifer: GPL-2.0-or-later + * + * Goldfish PIC + * + * (c) 2020 Laurent Vivier + * + */ + +#include "qemu/osdep.h" +#include "hw/irq.h" +#include "hw/qdev-properties.h" +#include "hw/sysbus.h" +#include "migration/vmstate.h" +#include "monitor/monitor.h" +#include "qemu/log.h" +#include "trace.h" +#include "hw/intc/intc.h" +#include "hw/intc/goldfish_pic.h" + +/* registers */ + +enum { + REG_STATUS =3D 0x00, + REG_IRQ_PENDING =3D 0x04, + REG_IRQ_DISABLE_ALL =3D 0x08, + REG_DISABLE =3D 0x0c, + REG_ENABLE =3D 0x10, +}; + +static bool goldfish_pic_get_statistics(InterruptStatsProvider *obj, + uint64_t **irq_counts, + unsigned int *nb_irqs) +{ + GoldfishPICState *s =3D GOLDFISH_PIC(obj); + + *irq_counts =3D s->stats_irq_count; + *nb_irqs =3D ARRAY_SIZE(s->stats_irq_count); + return true; +} + +static void goldfish_pic_print_info(InterruptStatsProvider *obj, Monitor *= mon) +{ + GoldfishPICState *s =3D GOLDFISH_PIC(obj); + monitor_printf(mon, "goldfish-pic.%d: pending=3D0x%08x enabled=3D0x%08= x\n", + s->idx, s->pending, s->enabled); +} + +static void goldfish_pic_update(GoldfishPICState *s) +{ + if (s->pending & s->enabled) { + qemu_irq_raise(s->irq); + } else { + qemu_irq_lower(s->irq); + } +} + +static void goldfish_irq_request(void *opaque, int irq, int level) +{ + GoldfishPICState *s =3D opaque; + + trace_goldfish_irq_request(s, s->idx, irq, level); + + if (level) { + s->pending |=3D 1 << irq; + s->stats_irq_count[irq]++; + } else { + s->pending &=3D ~(1 << irq); + } + goldfish_pic_update(s); +} + +static uint64_t goldfish_pic_read(void *opaque, hwaddr addr, + unsigned size) +{ + GoldfishPICState *s =3D opaque; + uint64_t value =3D 0; + + switch (addr) { + case REG_STATUS: + /* The number of pending interrupts (0 to 32) */ + value =3D ctpop32(s->pending & s->enabled); + break; + case REG_IRQ_PENDING: + /* The pending interrupt mask */ + value =3D s->pending & s->enabled; + break; + default: + qemu_log_mask(LOG_UNIMP, + "%s: unimplemented register read 0x%02"HWADDR_PRIx"\= n", + __func__, addr); + break; + } + + trace_goldfish_pic_read(s, s->idx, addr, size, value); + + return value; +} + +static void goldfish_pic_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size) +{ + GoldfishPICState *s =3D opaque; + + trace_goldfish_pic_write(s, s->idx, addr, size, value); + + switch (addr) { + case REG_IRQ_DISABLE_ALL: + s->enabled =3D 0; + s->pending =3D 0; + break; + case REG_DISABLE: + s->enabled &=3D ~value; + break; + case REG_ENABLE: + s->enabled |=3D value; + break; + default: + qemu_log_mask(LOG_UNIMP, + "%s: unimplemented register write 0x%02"HWADDR_PRIx"= \n", + __func__, addr); + break; + } + goldfish_pic_update(s); +} + +static const MemoryRegionOps goldfish_pic_ops =3D { + .read =3D goldfish_pic_read, + .write =3D goldfish_pic_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid.max_access_size =3D 4, + .impl.min_access_size =3D 4, + .impl.max_access_size =3D 4, +}; + +static void goldfish_pic_reset(DeviceState *dev) +{ + GoldfishPICState *s =3D GOLDFISH_PIC(dev); + int i; + + trace_goldfish_pic_reset(s, s->idx); + s->pending =3D 0; + s->enabled =3D 0; + + for (i =3D 0; i < ARRAY_SIZE(s->stats_irq_count); i++) { + s->stats_irq_count[i] =3D 0; + } +} + +static void goldfish_pic_realize(DeviceState *dev, Error **errp) +{ + GoldfishPICState *s =3D GOLDFISH_PIC(dev); + + trace_goldfish_pic_realize(s, s->idx); + + memory_region_init_io(&s->iomem, OBJECT(s), &goldfish_pic_ops, s, + "goldfish_pic", 0x24); +} + +static const VMStateDescription vmstate_goldfish_pic =3D { + .name =3D "goldfish_pic", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32(pending, GoldfishPICState), + VMSTATE_UINT32(enabled, GoldfishPICState), + VMSTATE_END_OF_LIST() + } +}; + +static void goldfish_pic_instance_init(Object *obj) +{ + SysBusDevice *dev =3D SYS_BUS_DEVICE(obj); + GoldfishPICState *s =3D GOLDFISH_PIC(obj); + + trace_goldfish_pic_instance_init(s); + + sysbus_init_mmio(dev, &s->iomem); + sysbus_init_irq(dev, &s->irq); + + qdev_init_gpio_in(DEVICE(obj), goldfish_irq_request, GOLDFISH_PIC_IRQ_= NB); +} + +static Property goldfish_pic_properties[] =3D { + DEFINE_PROP_UINT8("index", GoldfishPICState, idx, 0), + DEFINE_PROP_END_OF_LIST(), +}; + +static void goldfish_pic_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + InterruptStatsProviderClass *ic =3D INTERRUPT_STATS_PROVIDER_CLASS(oc); + + dc->reset =3D goldfish_pic_reset; + dc->realize =3D goldfish_pic_realize; + dc->vmsd =3D &vmstate_goldfish_pic; + ic->get_statistics =3D goldfish_pic_get_statistics; + ic->print_info =3D goldfish_pic_print_info; + device_class_set_props(dc, goldfish_pic_properties); +} + +static const TypeInfo goldfish_pic_info =3D { + .name =3D TYPE_GOLDFISH_PIC, + .parent =3D TYPE_SYS_BUS_DEVICE, + .class_init =3D goldfish_pic_class_init, + .instance_init =3D goldfish_pic_instance_init, + .instance_size =3D sizeof(GoldfishPICState), + .interfaces =3D (InterfaceInfo[]) { + { TYPE_INTERRUPT_STATS_PROVIDER }, + { } + }, +}; + +static void goldfish_pic_register_types(void) +{ + type_register_static(&goldfish_pic_info); +} + +type_init(goldfish_pic_register_types) diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig index 66bf0b90b47a..186cb5daa0ff 100644 --- a/hw/intc/Kconfig +++ b/hw/intc/Kconfig @@ -67,3 +67,6 @@ config SIFIVE_CLINT =20 config SIFIVE_PLIC bool + +config GOLDFISH_PIC + bool diff --git a/hw/intc/meson.build b/hw/intc/meson.build index b3d9345a0d2e..ad22fdc5deb9 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -57,3 +57,4 @@ specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('x= ics_spapr.c', 'spapr_xi specific_ss.add(when: 'CONFIG_XIVE', if_true: files('xive.c')) specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_XIVE'], if_true: files('spapr_xive_kvm.c')) +specific_ss.add(when: 'CONFIG_GOLDFISH_PIC', if_true: files('goldfish_pic.= c')) diff --git a/hw/intc/trace-events b/hw/intc/trace-events index 45ddaf48df8e..c9ab17234b44 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -239,3 +239,11 @@ xive_end_source_read(uint8_t end_blk, uint32_t end_idx= , uint64_t addr) "END 0x%x =20 # pnv_xive.c pnv_xive_ic_hw_trigger(uint64_t addr, uint64_t val) "@0x%"PRIx64" val=3D0x= %"PRIx64 + +# goldfish_pic.c +goldfish_irq_request(void *dev, int idx, int irq, int level) "pic: %p gold= fish-irq.%d irq: %d level: %d" +goldfish_pic_read(void *dev, int idx, unsigned int addr, unsigned int size= , uint64_t value) "pic: %p goldfish-irq.%d reg: 0x%02x size: %d value: 0x%"= PRIx64 +goldfish_pic_write(void *dev, int idx, unsigned int addr, unsigned int siz= e, uint64_t value) "pic: %p goldfish-irq.%d reg: 0x%02x size: %d value: 0x%= "PRIx64 +goldfish_pic_reset(void *dev, int idx) "pic: %p goldfish-irq.%d" +goldfish_pic_realize(void *dev, int idx) "pic: %p goldfish-irq.%d" +goldfish_pic_instance_init(void *dev) "pic: %p goldfish-irq" --=20 2.29.2 From nobody Sat May 18 21:15:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 11 Mar 2021 13:18:34 -0800 (PST) Received: from localhost ([::1]:53072 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lKShV-0008TG-7t for importer@patchew.org; Thu, 11 Mar 2021 16:18:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45596) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lKSZ3-0006jK-SY for qemu-devel@nongnu.org; Thu, 11 Mar 2021 16:09:49 -0500 Received: from mout.kundenserver.de ([217.72.192.73]:47737) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lKSZ1-00050r-P9 for qemu-devel@nongnu.org; Thu, 11 Mar 2021 16:09:49 -0500 Received: from localhost.localdomain ([82.142.6.26]) by mrelayeu.kundenserver.de (mreue109 [212.227.15.183]) with ESMTPSA (Nemesis) id 1M2fDl-1lJ5Nx0tg7-004CKd; Thu, 11 Mar 2021 22:09:42 +0100 From: Laurent Vivier To: qemu-devel@nongnu.org Subject: [PULL 7/9] m68k: add an interrupt controller Date: Thu, 11 Mar 2021 22:09:32 +0100 Message-Id: <20210311210934.1935587-8-laurent@vivier.eu> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210311210934.1935587-1-laurent@vivier.eu> References: <20210311210934.1935587-1-laurent@vivier.eu> MIME-Version: 1.0 Content-Type: text/plain; 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helo=lists.gnu.org; Received-SPF: none client-ip=217.72.192.73; envelope-from=laurent@vivier.eu; helo=mout.kundenserver.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" A (generic) copy of the GLUE device we already have for q800 to use with the m68k-virt machine. The q800 one would disappear in the future as q800 uses actually the djMEMC controller. Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20210309195941.763896-4-laurent@vivier.eu> Signed-off-by: Laurent Vivier --- include/hw/intc/m68k_irqc.h | 41 +++++++++++++ hw/intc/m68k_irqc.c | 119 ++++++++++++++++++++++++++++++++++++ hw/intc/Kconfig | 3 + hw/intc/meson.build | 1 + 4 files changed, 164 insertions(+) create mode 100644 include/hw/intc/m68k_irqc.h create mode 100644 hw/intc/m68k_irqc.c diff --git a/include/hw/intc/m68k_irqc.h b/include/hw/intc/m68k_irqc.h new file mode 100644 index 000000000000..dbcfcfc2e000 --- /dev/null +++ b/include/hw/intc/m68k_irqc.h @@ -0,0 +1,41 @@ +/* + * SPDX-License-Identifer: GPL-2.0-or-later + * + * QEMU Motorola 680x0 IRQ Controller + * + * (c) 2020 Laurent Vivier + * + */ + +#ifndef M68K_IRQC_H +#define M68K_IRQC_H + +#include "hw/sysbus.h" + +#define TYPE_M68K_IRQC "m68k-irq-controller" +#define M68K_IRQC(obj) OBJECT_CHECK(M68KIRQCState, (obj), \ + TYPE_M68K_IRQC) + +#define M68K_IRQC_AUTOVECTOR_BASE 25 + +enum { + M68K_IRQC_LEVEL_1 =3D 0, + M68K_IRQC_LEVEL_2, + M68K_IRQC_LEVEL_3, + M68K_IRQC_LEVEL_4, + M68K_IRQC_LEVEL_5, + M68K_IRQC_LEVEL_6, + M68K_IRQC_LEVEL_7, +}; +#define M68K_IRQC_LEVEL_NUM (M68K_IRQC_LEVEL_7 - M68K_IRQC_LEVEL_1 + 1) + +typedef struct M68KIRQCState { + SysBusDevice parent_obj; + + uint8_t ipr; + + /* statistics */ + uint64_t stats_irq_count[M68K_IRQC_LEVEL_NUM]; +} M68KIRQCState; + +#endif diff --git a/hw/intc/m68k_irqc.c b/hw/intc/m68k_irqc.c new file mode 100644 index 000000000000..2133d2a698ab --- /dev/null +++ b/hw/intc/m68k_irqc.c @@ -0,0 +1,119 @@ +/* + * SPDX-License-Identifer: GPL-2.0-or-later + * + * QEMU Motorola 680x0 IRQ Controller + * + * (c) 2020 Laurent Vivier + * + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "migration/vmstate.h" +#include "monitor/monitor.h" +#include "hw/nmi.h" +#include "hw/intc/intc.h" +#include "hw/intc/m68k_irqc.h" + + +static bool m68k_irqc_get_statistics(InterruptStatsProvider *obj, + uint64_t **irq_counts, unsigned int *= nb_irqs) +{ + M68KIRQCState *s =3D M68K_IRQC(obj); + + *irq_counts =3D s->stats_irq_count; + *nb_irqs =3D ARRAY_SIZE(s->stats_irq_count); + return true; +} + +static void m68k_irqc_print_info(InterruptStatsProvider *obj, Monitor *mon) +{ + M68KIRQCState *s =3D M68K_IRQC(obj); + monitor_printf(mon, "m68k-irqc: ipr=3D0x%x\n", s->ipr); +} + +static void m68k_set_irq(void *opaque, int irq, int level) +{ + M68KIRQCState *s =3D opaque; + M68kCPU *cpu =3D M68K_CPU(first_cpu); + int i; + + if (level) { + s->ipr |=3D 1 << irq; + s->stats_irq_count[irq]++; + } else { + s->ipr &=3D ~(1 << irq); + } + + for (i =3D M68K_IRQC_LEVEL_7; i >=3D M68K_IRQC_LEVEL_1; i--) { + if ((s->ipr >> i) & 1) { + m68k_set_irq_level(cpu, i + 1, i + M68K_IRQC_AUTOVECTOR_BASE); + return; + } + } + m68k_set_irq_level(cpu, 0, 0); +} + +static void m68k_irqc_reset(DeviceState *d) +{ + M68KIRQCState *s =3D M68K_IRQC(d); + int i; + + s->ipr =3D 0; + for (i =3D 0; i < ARRAY_SIZE(s->stats_irq_count); i++) { + s->stats_irq_count[i] =3D 0; + } +} + +static void m68k_irqc_instance_init(Object *obj) +{ + qdev_init_gpio_in(DEVICE(obj), m68k_set_irq, M68K_IRQC_LEVEL_NUM); +} + +static void m68k_nmi(NMIState *n, int cpu_index, Error **errp) +{ + m68k_set_irq(n, M68K_IRQC_LEVEL_7, 1); +} + +static const VMStateDescription vmstate_m68k_irqc =3D { + .name =3D "m68k-irqc", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT8(ipr, M68KIRQCState), + VMSTATE_END_OF_LIST() + } +}; + +static void m68k_irqc_class_init(ObjectClass *oc, void *data) + { + DeviceClass *dc =3D DEVICE_CLASS(oc); + NMIClass *nc =3D NMI_CLASS(oc); + InterruptStatsProviderClass *ic =3D INTERRUPT_STATS_PROVIDER_CLASS(oc); + + nc->nmi_monitor_handler =3D m68k_nmi; + dc->reset =3D m68k_irqc_reset; + dc->vmsd =3D &vmstate_m68k_irqc; + ic->get_statistics =3D m68k_irqc_get_statistics; + ic->print_info =3D m68k_irqc_print_info; +} + +static const TypeInfo m68k_irqc_type_info =3D { + .name =3D TYPE_M68K_IRQC, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(M68KIRQCState), + .instance_init =3D m68k_irqc_instance_init, + .class_init =3D m68k_irqc_class_init, + .interfaces =3D (InterfaceInfo[]) { + { TYPE_NMI }, + { TYPE_INTERRUPT_STATS_PROVIDER }, + { } + }, +}; + +static void q800_irq_register_types(void) +{ + type_register_static(&m68k_irqc_type_info); +} + +type_init(q800_irq_register_types); diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig index 186cb5daa0ff..f4694088a483 100644 --- a/hw/intc/Kconfig +++ b/hw/intc/Kconfig @@ -70,3 +70,6 @@ config SIFIVE_PLIC =20 config GOLDFISH_PIC bool + +config M68K_IRQC + bool diff --git a/hw/intc/meson.build b/hw/intc/meson.build index ad22fdc5deb9..4ab911e71bb9 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -58,3 +58,4 @@ specific_ss.add(when: 'CONFIG_XIVE', if_true: files('xive= .c')) specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_XIVE'], if_true: files('spapr_xive_kvm.c')) specific_ss.add(when: 'CONFIG_GOLDFISH_PIC', if_true: files('goldfish_pic.= c')) +specific_ss.add(when: 'CONFIG_M68K_IRQC', if_true: files('m68k_irqc.c')) --=20 2.29.2 From nobody Sat May 18 21:15:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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Thu, 11 Mar 2021 13:13:41 -0800 (PST) Received: from localhost ([::1]:42974 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lKScm-0002e0-12 for importer@patchew.org; Thu, 11 Mar 2021 16:13:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45656) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lKSZ9-0006rn-Rq for qemu-devel@nongnu.org; Thu, 11 Mar 2021 16:09:55 -0500 Received: from mout.kundenserver.de ([212.227.17.13]:41619) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lKSZ6-00053s-92 for qemu-devel@nongnu.org; Thu, 11 Mar 2021 16:09:55 -0500 Received: from localhost.localdomain ([82.142.6.26]) by mrelayeu.kundenserver.de (mreue109 [212.227.15.183]) with ESMTPSA (Nemesis) id 1MqrsF-1m72rX3QUT-00mwPx; Thu, 11 Mar 2021 22:09:43 +0100 From: Laurent Vivier To: qemu-devel@nongnu.org Subject: [PULL 8/9] m68k: add a system controller Date: Thu, 11 Mar 2021 22:09:33 +0100 Message-Id: <20210311210934.1935587-9-laurent@vivier.eu> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210311210934.1935587-1-laurent@vivier.eu> References: <20210311210934.1935587-1-laurent@vivier.eu> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K1:QSIRdpNJ6FO19xn6LfAizCbwrBdV+N3TBINhEf0qNSpX8SV/v5C lDZWjEdSI/WJM5I/9+SuzZvYcC3WSEGMT8uxD7ehiQhe4KKl3rUqA8910fZltuJQpHxjKcL IL9csZutWz4XSbpp3mYmAPS1EXgc74uJK+IGA+qGeoK03TySCY9rYE14+PRpSXyWA4cVcmD EprOKe5KgtfQ49cbgb/nQ== X-UI-Out-Filterresults: notjunk:1;V03:K0:lMLNVK7C9GQ=:CGSK0ruNeTs4YbM96bZZf5 sKv92FpSiDpMwv0zkYbAL92+o/NT5N8rEgz1R00tTPuP+ERwGb9XrozdIQikuialXthxIFDlI ZEUXUNasGawplPNXDTzH5jUtxo0NYlVPll6LQrKtmiWxlyRJnDKU/nQluLUgeynEuXlKYzHuG X2TNmkh0azDlr2YhWJwjiFshmMzrgO44C59qbq5Biuhs2PyxPe1d0PlkdC5DFHmnB5RDnL5qx /dZnNInaBICDjEHFqVV5AYpgnTVTm1zNCVeykvD8XPbUIR0IKzvQaJ7WmBq4GpU9ukyUORTrK nepRDU5m9L2iN9zgLleODtpVTNt4/WbcAfTutwsEj2KHqILYdyRuBlOCnuiyqAF8WINDJCNwm Sy2VuW2U9gAfy0AAGrbgxLQn3K4Z6Dlc7n6io18K59hHmkWFjbOwLxMkpBFcX Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=212.227.17.13; envelope-from=laurent@vivier.eu; helo=mout.kundenserver.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Add a system controller for the m68k-virt machine. This controller allows the kernel to power off or reset the machine. Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20210309195941.763896-5-laurent@vivier.eu> Signed-off-by: Laurent Vivier --- docs/specs/virt-ctlr.txt | 26 +++++++ include/hw/misc/virt_ctrl.h | 22 ++++++ hw/misc/virt_ctrl.c | 151 ++++++++++++++++++++++++++++++++++++ hw/misc/Kconfig | 3 + hw/misc/meson.build | 3 + hw/misc/trace-events | 7 ++ 6 files changed, 212 insertions(+) create mode 100644 docs/specs/virt-ctlr.txt create mode 100644 include/hw/misc/virt_ctrl.h create mode 100644 hw/misc/virt_ctrl.c diff --git a/docs/specs/virt-ctlr.txt b/docs/specs/virt-ctlr.txt new file mode 100644 index 000000000000..24d38084f7fd --- /dev/null +++ b/docs/specs/virt-ctlr.txt @@ -0,0 +1,26 @@ +Virtual System Controller +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D + +This device is a simple interface defined for the pure virtual machine wit= h no +hardware reference implementation to allow the guest kernel to send command +to the host hypervisor. + +The specification can evolve, the current state is defined as below. + +This is a MMIO mapped device using 256 bytes. + +Two 32bit registers are defined: + +1- the features register (read-only, address 0x00) + + This register allows the device to report features supported by the + controller. + The only feature supported for the moment is power control (0x01). + +2- the command register (write-only, address 0x04) + + This register allows the kernel to send the commands to the hypervisor. + The implemented commands are part of the power control feature and + are reset (1), halt (2) and panic (3). + A basic command, no-op (0), is always present and can be used to test t= he + register access. This command has no effect. diff --git a/include/hw/misc/virt_ctrl.h b/include/hw/misc/virt_ctrl.h new file mode 100644 index 000000000000..edfadc469505 --- /dev/null +++ b/include/hw/misc/virt_ctrl.h @@ -0,0 +1,22 @@ +/* + * SPDX-License-Identifer: GPL-2.0-or-later + * + * Virt system Controller + */ + +#ifndef VIRT_CTRL_H +#define VIRT_CTRL_H + +#define TYPE_VIRT_CTRL "virt-ctrl" +OBJECT_DECLARE_SIMPLE_TYPE(VirtCtrlState, VIRT_CTRL) + +struct VirtCtrlState { + SysBusDevice parent_obj; + + MemoryRegion iomem; + qemu_irq irq; + + uint32_t irq_enabled; +}; + +#endif diff --git a/hw/misc/virt_ctrl.c b/hw/misc/virt_ctrl.c new file mode 100644 index 000000000000..2ea01bd7a1f0 --- /dev/null +++ b/hw/misc/virt_ctrl.c @@ -0,0 +1,151 @@ +/* + * SPDX-License-Identifer: GPL-2.0-or-later + * + * Virt system Controller + */ + +#include "qemu/osdep.h" +#include "hw/irq.h" +#include "hw/qdev-properties.h" +#include "hw/sysbus.h" +#include "migration/vmstate.h" +#include "qemu/log.h" +#include "trace.h" +#include "sysemu/runstate.h" +#include "hw/misc/virt_ctrl.h" + +enum { + REG_FEATURES =3D 0x00, + REG_CMD =3D 0x04, +}; + +#define FEAT_POWER_CTRL 0x00000001 + +enum { + CMD_NOOP, + CMD_RESET, + CMD_HALT, + CMD_PANIC, +}; + +static uint64_t virt_ctrl_read(void *opaque, hwaddr addr, unsigned size) +{ + VirtCtrlState *s =3D opaque; + uint64_t value =3D 0; + + switch (addr) { + case REG_FEATURES: + value =3D FEAT_POWER_CTRL; + break; + default: + qemu_log_mask(LOG_UNIMP, + "%s: unimplemented register read 0x%02"HWADDR_PRIx"\= n", + __func__, addr); + break; + } + + trace_virt_ctrl_write(s, addr, size, value); + + return value; +} + +static void virt_ctrl_write(void *opaque, hwaddr addr, uint64_t value, + unsigned size) +{ + VirtCtrlState *s =3D opaque; + + trace_virt_ctrl_write(s, addr, size, value); + + switch (addr) { + case REG_CMD: + switch (value) { + case CMD_NOOP: + break; + case CMD_RESET: + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); + break; + case CMD_HALT: + qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); + break; + case CMD_PANIC: + qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_PANIC); + break; + } + break; + default: + qemu_log_mask(LOG_UNIMP, + "%s: unimplemented register write 0x%02"HWADDR_PRIx"= \n", + __func__, addr); + break; + } +} + +static const MemoryRegionOps virt_ctrl_ops =3D { + .read =3D virt_ctrl_read, + .write =3D virt_ctrl_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid.max_access_size =3D 4, + .impl.max_access_size =3D 4, +}; + +static void virt_ctrl_reset(DeviceState *dev) +{ + VirtCtrlState *s =3D VIRT_CTRL(dev); + + trace_virt_ctrl_reset(s); +} + +static void virt_ctrl_realize(DeviceState *dev, Error **errp) +{ + VirtCtrlState *s =3D VIRT_CTRL(dev); + + trace_virt_ctrl_instance_init(s); + + memory_region_init_io(&s->iomem, OBJECT(s), &virt_ctrl_ops, s, + "virt-ctrl", 0x100); +} + +static const VMStateDescription vmstate_virt_ctrl =3D { + .name =3D "virt-ctrl", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32(irq_enabled, VirtCtrlState), + VMSTATE_END_OF_LIST() + } +}; + +static void virt_ctrl_instance_init(Object *obj) +{ + SysBusDevice *dev =3D SYS_BUS_DEVICE(obj); + VirtCtrlState *s =3D VIRT_CTRL(obj); + + trace_virt_ctrl_instance_init(s); + + sysbus_init_mmio(dev, &s->iomem); + sysbus_init_irq(dev, &s->irq); +} + +static void virt_ctrl_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + dc->reset =3D virt_ctrl_reset; + dc->realize =3D virt_ctrl_realize; + dc->vmsd =3D &vmstate_virt_ctrl; +} + +static const TypeInfo virt_ctrl_info =3D { + .name =3D TYPE_VIRT_CTRL, + .parent =3D TYPE_SYS_BUS_DEVICE, + .class_init =3D virt_ctrl_class_init, + .instance_init =3D virt_ctrl_instance_init, + .instance_size =3D sizeof(VirtCtrlState), +}; + +static void virt_ctrl_register_types(void) +{ + type_register_static(&virt_ctrl_info); +} + +type_init(virt_ctrl_register_types) diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig index 5426b9b1a1ad..c71ed2582046 100644 --- a/hw/misc/Kconfig +++ b/hw/misc/Kconfig @@ -183,4 +183,7 @@ config SIFIVE_U_OTP config SIFIVE_U_PRCI bool =20 +config VIRT_CTRL + bool + source macio/Kconfig diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 00356cf12ec7..f44d068e2dbd 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -24,6 +24,9 @@ softmmu_ss.add(when: 'CONFIG_ARM11SCU', if_true: files('a= rm11scu.c')) # Mac devices softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c')) =20 +# virt devices +softmmu_ss.add(when: 'CONFIG_VIRT_CTRL', if_true: files('virt_ctrl.c')) + # RISC-V devices softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_DMC', if_true: files('mchp_pfsoc_d= mc.c')) softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_IOSCB', if_true: files('mchp_pfsoc= _ioscb.c')) diff --git a/hw/misc/trace-events b/hw/misc/trace-events index 4b15db8ca488..e77d63f4e9b4 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -247,3 +247,10 @@ pca955x_gpio_change(const char *description, unsigned = id, unsigned prev_state, u bcm2835_cprman_read(uint64_t offset, uint64_t value) "offset:0x%" PRIx64 "= value:0x%" PRIx64 bcm2835_cprman_write(uint64_t offset, uint64_t value) "offset:0x%" PRIx64 = " value:0x%" PRIx64 bcm2835_cprman_write_invalid_magic(uint64_t offset, uint64_t value) "offse= t:0x%" PRIx64 " value:0x%" PRIx64 + +# virt_ctrl.c +virt_ctrl_read(void *dev, unsigned int addr, unsigned int size, uint64_t v= alue) "ctrl: %p reg: 0x%02x size: %d value: 0x%"PRIx64 +virt_ctrl_write(void *dev, unsigned int addr, unsigned int size, uint64_t = value) "ctrl: %p reg: 0x%02x size: %d value: 0x%"PRIx64 +virt_ctrl_reset(void *dev) "ctrl: %p" +virt_ctrl_realize(void *dev) "ctrl: %p" +virt_ctrl_instance_init(void *dev) "ctrl: %p" --=20 2.29.2 From nobody Sat May 18 21:15:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 11 Mar 2021 13:23:41 -0800 (PST) Received: from localhost ([::1]:35318 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lKSmS-0005tG-E4 for importer@patchew.org; Thu, 11 Mar 2021 16:23:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45658) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lKSZB-0006tJ-Ot for qemu-devel@nongnu.org; Thu, 11 Mar 2021 16:09:59 -0500 Received: from mout.kundenserver.de ([217.72.192.74]:58713) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lKSZ6-00053w-L8 for qemu-devel@nongnu.org; Thu, 11 Mar 2021 16:09:57 -0500 Received: from localhost.localdomain ([82.142.6.26]) by mrelayeu.kundenserver.de (mreue109 [212.227.15.183]) with ESMTPSA (Nemesis) id 1MIxBc-1l0Bcj1odO-00KLda; Thu, 11 Mar 2021 22:09:43 +0100 From: Laurent Vivier To: qemu-devel@nongnu.org Subject: [PULL 9/9] m68k: add Virtual M68k Machine Date: Thu, 11 Mar 2021 22:09:34 +0100 Message-Id: <20210311210934.1935587-10-laurent@vivier.eu> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210311210934.1935587-1-laurent@vivier.eu> References: <20210311210934.1935587-1-laurent@vivier.eu> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K1:E6BilKKcTi5+/9SlmpqPVwc5aqsvieR+dLlne1HvvgLvWF9AUw1 PrM3oGVPYVNqs56o/bEJJnd/sHAi264hEMAkE0lIJw6yDeLWd7T1Ni0FXq3GnsR1bjCs5u5 xU3C4QtfUr9mU8MqPksCSaKw1RsxFvXySfidRrbngK6HH0GKgxIv+5xWDSUDW9TAKgAPfuX ycFEjuTObM/zlLtcd82vw== X-UI-Out-Filterresults: notjunk:1;V03:K0:b3ZBN+ILLKY=:OjirhMZvJMxIjDUphBpEXO tJ1t5SJ+OIvTTU0CUy97VGZSG0CSstjl21Z2+Q8qEZ+JcWszdXXzjbSPNJPvbeGz7OYPh38cT La9sHLkXCsLuQXK7ZcmoVcCHig3WXq25bacEvIhu2799sN5R8JPSK4gXI/rh1PTZcFjygNeuh 7E/Pbmr4UaPn0K+K+fZ7EM9R++QtmMR1FNFoOiizJYK+0E3s6dDX+1Yf72beSQ6mQi0Va4mbA FZr8LfrfhmS+J1gBGsSMHJWDfEgnp5GsNxh4u3A/XftK4KCVHTfPa5vgMb+H+fsbZOcIEyfBT /I/h83b4sG8dmN3oegvhLaaNdt56xYY8rlhEthLoeatvIUnK9OqGSjU+yhewL3f3e3pldQhMy zxCi8VYeHf7nUS4VyuXUv+tHDnOonC9sgK3djdzA+TLlbaGZu/lSxnWWBlava Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=217.72.192.74; envelope-from=laurent@vivier.eu; helo=mout.kundenserver.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" The machine is based on Goldfish interfaces defined by Google for Android simulator. It uses Goldfish-rtc (timer and RTC), Goldfish-pic (PIC) and Goldfish-tty (for serial port and early tty). The machine is created with 128 virtio-mmio bus, and they can be used to use serial console, GPU, disk, NIC, HID, ... Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20210309195941.763896-6-laurent@vivier.eu> Signed-off-by: Laurent Vivier --- default-configs/devices/m68k-softmmu.mak | 1 + .../standard-headers/asm-m68k/bootinfo-virt.h | 18 + hw/m68k/virt.c | 313 ++++++++++++++++++ MAINTAINERS | 13 + hw/m68k/Kconfig | 9 + hw/m68k/meson.build | 1 + 6 files changed, 355 insertions(+) create mode 100644 include/standard-headers/asm-m68k/bootinfo-virt.h create mode 100644 hw/m68k/virt.c diff --git a/default-configs/devices/m68k-softmmu.mak b/default-configs/dev= ices/m68k-softmmu.mak index 6629fd2aa330..7f8619e42786 100644 --- a/default-configs/devices/m68k-softmmu.mak +++ b/default-configs/devices/m68k-softmmu.mak @@ -8,3 +8,4 @@ CONFIG_AN5206=3Dy CONFIG_MCF5208=3Dy CONFIG_NEXTCUBE=3Dy CONFIG_Q800=3Dy +CONFIG_M68K_VIRT=3Dy diff --git a/include/standard-headers/asm-m68k/bootinfo-virt.h b/include/st= andard-headers/asm-m68k/bootinfo-virt.h new file mode 100644 index 000000000000..81be1e092497 --- /dev/null +++ b/include/standard-headers/asm-m68k/bootinfo-virt.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +/* +** asm/bootinfo-virt.h -- Virtual-m68k-specific boot information definitio= ns +*/ + +#ifndef _UAPI_ASM_M68K_BOOTINFO_VIRT_H +#define _UAPI_ASM_M68K_BOOTINFO_VIRT_H + +#define BI_VIRT_QEMU_VERSION 0x8000 +#define BI_VIRT_GF_PIC_BASE 0x8001 +#define BI_VIRT_GF_RTC_BASE 0x8002 +#define BI_VIRT_GF_TTY_BASE 0x8003 +#define BI_VIRT_VIRTIO_BASE 0x8004 +#define BI_VIRT_CTRL_BASE 0x8005 + +#define VIRT_BOOTI_VERSION MK_BI_VERSION(2, 0) + +#endif /* _UAPI_ASM_M68K_BOOTINFO_MAC_H */ diff --git a/hw/m68k/virt.c b/hw/m68k/virt.c new file mode 100644 index 000000000000..e9a5d4c69b97 --- /dev/null +++ b/hw/m68k/virt.c @@ -0,0 +1,313 @@ +/* + * SPDX-License-Identifer: GPL-2.0-or-later + * + * QEMU Vitual M68K Machine + * + * (c) 2020 Laurent Vivier + * + */ + +#include "qemu/osdep.h" +#include "qemu/units.h" +#include "qemu-common.h" +#include "sysemu/sysemu.h" +#include "cpu.h" +#include "hw/hw.h" +#include "hw/boards.h" +#include "hw/irq.h" +#include "hw/qdev-properties.h" +#include "elf.h" +#include "hw/loader.h" +#include "ui/console.h" +#include "exec/address-spaces.h" +#include "hw/sysbus.h" +#include "standard-headers/asm-m68k/bootinfo.h" +#include "standard-headers/asm-m68k/bootinfo-virt.h" +#include "bootinfo.h" +#include "net/net.h" +#include "qapi/error.h" +#include "sysemu/qtest.h" +#include "sysemu/runstate.h" +#include "sysemu/reset.h" + +#include "hw/intc/m68k_irqc.h" +#include "hw/misc/virt_ctrl.h" +#include "hw/char/goldfish_tty.h" +#include "hw/rtc/goldfish_rtc.h" +#include "hw/intc/goldfish_pic.h" +#include "hw/virtio/virtio-mmio.h" +#include "hw/virtio/virtio-blk.h" + +/* + * 6 goldfish-pic for CPU IRQ #1 to IRQ #6 + * CPU IRQ #1 -> PIC #1 + * IRQ #1 to IRQ #31 -> unused + * IRQ #32 -> goldfish-tty + * CPU IRQ #2 -> PIC #2 + * IRQ #1 to IRQ #32 -> virtio-mmio from 1 to 32 + * CPU IRQ #3 -> PIC #3 + * IRQ #1 to IRQ #32 -> virtio-mmio from 33 to 64 + * CPU IRQ #4 -> PIC #4 + * IRQ #1 to IRQ #32 -> virtio-mmio from 65 to 96 + * CPU IRQ #5 -> PIC #5 + * IRQ #1 to IRQ #32 -> virtio-mmio from 97 to 128 + * CPU IRQ #6 -> PIC #6 + * IRQ #1 -> goldfish-rtc + * IRQ #2 to IRQ #32 -> unused + * CPU IRQ #7 -> NMI + */ + +#define PIC_IRQ_BASE(num) (8 + (num - 1) * 32) +#define PIC_IRQ(num, irq) (PIC_IRQ_BASE(num) + irq - 1) +#define PIC_GPIO(pic_irq) (qdev_get_gpio_in(pic_dev[(pic_irq - 8) / 32= ], \ + (pic_irq - 8) % 32)) + +#define VIRT_GF_PIC_MMIO_BASE 0xff000000 /* MMIO: 0xff000000 - 0xff005= fff */ +#define VIRT_GF_PIC_IRQ_BASE 1 /* IRQ: #1 -> #6 */ +#define VIRT_GF_PIC_NB 6 + +/* 2 goldfish-rtc (and timer) */ +#define VIRT_GF_RTC_MMIO_BASE 0xff006000 /* MMIO: 0xff006000 - 0xff007= fff */ +#define VIRT_GF_RTC_IRQ_BASE PIC_IRQ(6, 1) /* PIC: #6, IRQ: #1 */ +#define VIRT_GF_RTC_NB 2 + +/* 1 goldfish-tty */ +#define VIRT_GF_TTY_MMIO_BASE 0xff008000 /* MMIO: 0xff008000 - 0xff008= fff */ +#define VIRT_GF_TTY_IRQ_BASE PIC_IRQ(1, 32) /* PIC: #1, IRQ: #32 */ + +/* 1 virt-ctrl */ +#define VIRT_CTRL_MMIO_BASE 0xff009000 /* MMIO: 0xff009000 - 0xff009fff= */ +#define VIRT_CTRL_IRQ_BASE PIC_IRQ(1, 1) /* PIC: #1, IRQ: #1 */ + +/* + * virtio-mmio size is 0x200 bytes + * we use 4 goldfish-pic to attach them, + * we can attach 32 virtio devices / goldfish-pic + * -> we can manage 32 * 4 =3D 128 virtio devices + */ +#define VIRT_VIRTIO_MMIO_BASE 0xff010000 /* MMIO: 0xff010000 - 0xff01f= fff */ +#define VIRT_VIRTIO_IRQ_BASE PIC_IRQ(2, 1) /* PIC: 2, 3, 4, 5, IRQ: ALL = */ + +static void main_cpu_reset(void *opaque) +{ + M68kCPU *cpu =3D opaque; + CPUState *cs =3D CPU(cpu); + + cpu_reset(cs); + cpu->env.aregs[7] =3D ldl_phys(cs->as, 0); + cpu->env.pc =3D ldl_phys(cs->as, 4); +} + +static void virt_init(MachineState *machine) +{ + M68kCPU *cpu =3D NULL; + int32_t kernel_size; + uint64_t elf_entry; + ram_addr_t initrd_base; + int32_t initrd_size; + ram_addr_t ram_size =3D machine->ram_size; + const char *kernel_filename =3D machine->kernel_filename; + const char *initrd_filename =3D machine->initrd_filename; + const char *kernel_cmdline =3D machine->kernel_cmdline; + hwaddr parameters_base; + DeviceState *dev; + DeviceState *irqc_dev; + DeviceState *pic_dev[VIRT_GF_PIC_NB]; + SysBusDevice *sysbus; + hwaddr io_base; + int i; + + if (ram_size > 3399672 * KiB) { + /* + * The physical memory can be up to 4 GiB - 16 MiB, but linux + * kernel crashes after this limit (~ 3.2 GiB) + */ + error_report("Too much memory for this machine: %" PRId64 " KiB, " + "maximum 3399672 KiB", ram_size / KiB); + exit(1); + } + + /* init CPUs */ + cpu =3D M68K_CPU(cpu_create(machine->cpu_type)); + qemu_register_reset(main_cpu_reset, cpu); + + /* RAM */ + memory_region_add_subregion(get_system_memory(), 0, machine->ram); + + /* IRQ Controller */ + + irqc_dev =3D qdev_new(TYPE_M68K_IRQC); + sysbus_realize_and_unref(SYS_BUS_DEVICE(irqc_dev), &error_fatal); + + /* + * 6 goldfish-pic + * + * map: 0xff000000 - 0xff006fff =3D 28 KiB + * IRQ: #1 (lower priority) -> #6 (higher priority) + * + */ + io_base =3D VIRT_GF_PIC_MMIO_BASE; + for (i =3D 0; i < VIRT_GF_PIC_NB; i++) { + pic_dev[i] =3D qdev_new(TYPE_GOLDFISH_PIC); + sysbus =3D SYS_BUS_DEVICE(pic_dev[i]); + qdev_prop_set_uint8(pic_dev[i], "index", i); + sysbus_realize_and_unref(sysbus, &error_fatal); + + sysbus_mmio_map(sysbus, 0, io_base); + sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(irqc_dev, i)); + + io_base +=3D 0x1000; + } + + /* goldfish-rtc */ + io_base =3D VIRT_GF_RTC_MMIO_BASE; + for (i =3D 0; i < VIRT_GF_RTC_NB; i++) { + dev =3D qdev_new(TYPE_GOLDFISH_RTC); + sysbus =3D SYS_BUS_DEVICE(dev); + sysbus_realize_and_unref(sysbus, &error_fatal); + sysbus_mmio_map(sysbus, 0, io_base); + sysbus_connect_irq(sysbus, 0, PIC_GPIO(VIRT_GF_RTC_IRQ_BASE + i)); + + io_base +=3D 0x1000; + } + + /* goldfish-tty */ + dev =3D qdev_new(TYPE_GOLDFISH_TTY); + sysbus =3D SYS_BUS_DEVICE(dev); + qdev_prop_set_chr(dev, "chardev", serial_hd(0)); + sysbus_realize_and_unref(sysbus, &error_fatal); + sysbus_mmio_map(sysbus, 0, VIRT_GF_TTY_MMIO_BASE); + sysbus_connect_irq(sysbus, 0, PIC_GPIO(VIRT_GF_TTY_IRQ_BASE)); + + /* virt controller */ + dev =3D qdev_new(TYPE_VIRT_CTRL); + sysbus =3D SYS_BUS_DEVICE(dev); + sysbus_realize_and_unref(sysbus, &error_fatal); + sysbus_mmio_map(sysbus, 0, VIRT_CTRL_MMIO_BASE); + sysbus_connect_irq(sysbus, 0, PIC_GPIO(VIRT_CTRL_IRQ_BASE)); + + /* virtio-mmio */ + io_base =3D VIRT_VIRTIO_MMIO_BASE; + for (i =3D 0; i < 128; i++) { + dev =3D qdev_new(TYPE_VIRTIO_MMIO); + qdev_prop_set_bit(dev, "force-legacy", false); + sysbus =3D SYS_BUS_DEVICE(dev); + sysbus_realize_and_unref(sysbus, &error_fatal); + sysbus_connect_irq(sysbus, 0, PIC_GPIO(VIRT_VIRTIO_IRQ_BASE + i)); + sysbus_mmio_map(sysbus, 0, io_base); + io_base +=3D 0x200; + } + + if (kernel_filename) { + CPUState *cs =3D CPU(cpu); + uint64_t high; + + kernel_size =3D load_elf(kernel_filename, NULL, NULL, NULL, + &elf_entry, NULL, &high, NULL, 1, + EM_68K, 0, 0); + if (kernel_size < 0) { + error_report("could not load kernel '%s'", kernel_filename); + exit(1); + } + stl_phys(cs->as, 4, elf_entry); /* reset initial PC */ + parameters_base =3D (high + 1) & ~1; + + BOOTINFO1(cs->as, parameters_base, BI_MACHTYPE, MACH_VIRT); + BOOTINFO1(cs->as, parameters_base, BI_FPUTYPE, FPU_68040); + BOOTINFO1(cs->as, parameters_base, BI_MMUTYPE, MMU_68040); + BOOTINFO1(cs->as, parameters_base, BI_CPUTYPE, CPU_68040); + BOOTINFO2(cs->as, parameters_base, BI_MEMCHUNK, 0, ram_size); + + BOOTINFO1(cs->as, parameters_base, BI_VIRT_QEMU_VERSION, + ((QEMU_VERSION_MAJOR << 24) | (QEMU_VERSION_MINOR << 16)= | + (QEMU_VERSION_MICRO << 8))); + BOOTINFO2(cs->as, parameters_base, BI_VIRT_GF_PIC_BASE, + VIRT_GF_PIC_MMIO_BASE, VIRT_GF_PIC_IRQ_BASE); + BOOTINFO2(cs->as, parameters_base, BI_VIRT_GF_RTC_BASE, + VIRT_GF_RTC_MMIO_BASE, VIRT_GF_RTC_IRQ_BASE); + BOOTINFO2(cs->as, parameters_base, BI_VIRT_GF_TTY_BASE, + VIRT_GF_TTY_MMIO_BASE, VIRT_GF_TTY_IRQ_BASE); + BOOTINFO2(cs->as, parameters_base, BI_VIRT_CTRL_BASE, + VIRT_CTRL_MMIO_BASE, VIRT_CTRL_IRQ_BASE); + BOOTINFO2(cs->as, parameters_base, BI_VIRT_VIRTIO_BASE, + VIRT_VIRTIO_MMIO_BASE, VIRT_VIRTIO_IRQ_BASE); + + if (kernel_cmdline) { + BOOTINFOSTR(cs->as, parameters_base, BI_COMMAND_LINE, + kernel_cmdline); + } + + /* load initrd */ + if (initrd_filename) { + initrd_size =3D get_image_size(initrd_filename); + if (initrd_size < 0) { + error_report("could not load initial ram disk '%s'", + initrd_filename); + exit(1); + } + + initrd_base =3D (ram_size - initrd_size) & TARGET_PAGE_MASK; + load_image_targphys(initrd_filename, initrd_base, + ram_size - initrd_base); + BOOTINFO2(cs->as, parameters_base, BI_RAMDISK, initrd_base, + initrd_size); + } else { + initrd_base =3D 0; + initrd_size =3D 0; + } + BOOTINFO0(cs->as, parameters_base, BI_LAST); + } +} + +static void virt_machine_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + mc->desc =3D "QEMU M68K Virtual Machine"; + mc->init =3D virt_init; + mc->default_cpu_type =3D M68K_CPU_TYPE_NAME("m68040"); + mc->max_cpus =3D 1; + mc->no_floppy =3D 1; + mc->no_parallel =3D 1; + mc->default_ram_id =3D "m68k_virt.ram"; +} + +static const TypeInfo virt_machine_info =3D { + .name =3D MACHINE_TYPE_NAME("virt"), + .parent =3D TYPE_MACHINE, + .abstract =3D true, + .class_init =3D virt_machine_class_init, +}; + +static void virt_machine_register_types(void) +{ + type_register_static(&virt_machine_info); +} + +type_init(virt_machine_register_types) + +#define DEFINE_VIRT_MACHINE(major, minor, latest) \ + static void virt_##major##_##minor##_class_init(ObjectClass *oc, \ + void *data) \ + { \ + MachineClass *mc =3D MACHINE_CLASS(oc); \ + virt_machine_##major##_##minor##_options(mc); \ + mc->desc =3D "QEMU " # major "." # minor " M68K Virtual Machine"; \ + if (latest) { \ + mc->alias =3D "virt"; \ + } \ + } \ + static const TypeInfo machvirt_##major##_##minor##_info =3D { \ + .name =3D MACHINE_TYPE_NAME("virt-" # major "." # minor), \ + .parent =3D MACHINE_TYPE_NAME("virt"), \ + .class_init =3D virt_##major##_##minor##_class_init, \ + }; \ + static void machvirt_machine_##major##_##minor##_init(void) \ + { \ + type_register_static(&machvirt_##major##_##minor##_info); \ + } \ + type_init(machvirt_machine_##major##_##minor##_init); + +static void virt_machine_6_0_options(MachineClass *mc) +{ +} +DEFINE_VIRT_MACHINE(6, 0, true) diff --git a/MAINTAINERS b/MAINTAINERS index 7da465dcdbc8..dab193e86feb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1130,6 +1130,19 @@ F: include/hw/nubus/* F: include/hw/display/macfb.h F: include/hw/block/swim.h =20 +virt +M: Laurent Vivier +S: Maintained +F: hw/m68k/virt.c +F: hw/char/goldfish_tty.c +F: hw/intc/goldfish_pic.c +F: hw/intc/m68k_irqc.c +F: hw/misc/virt_ctrl.c +F: include/hw/char/goldfish_tty.h +F: include/hw/intc/goldfish_pic.h +F: include/hw/intc/m68k_irqc.h +F: include/hw/misc/virt_ctrl.h + MicroBlaze Machines ------------------- petalogix_s3adsp1800 diff --git a/hw/m68k/Kconfig b/hw/m68k/Kconfig index 60d7bcfb8f2b..f839f8a03064 100644 --- a/hw/m68k/Kconfig +++ b/hw/m68k/Kconfig @@ -23,3 +23,12 @@ config Q800 select ESP select DP8393X select OR_IRQ + +config M68K_VIRT + bool + select M68K_IRQC + select VIRT_CTRL + select GOLDFISH_PIC + select GOLDFISH_TTY + select GOLDFISH_RTC + select VIRTIO_MMIO diff --git a/hw/m68k/meson.build b/hw/m68k/meson.build index ca0044c652d3..31248641d301 100644 --- a/hw/m68k/meson.build +++ b/hw/m68k/meson.build @@ -3,5 +3,6 @@ m68k_ss.add(when: 'CONFIG_AN5206', if_true: files('an5206.c= ', 'mcf5206.c')) m68k_ss.add(when: 'CONFIG_MCF5208', if_true: files('mcf5208.c', 'mcf_intc.= c')) m68k_ss.add(when: 'CONFIG_NEXTCUBE', if_true: files('next-kbd.c', 'next-cu= be.c')) m68k_ss.add(when: 'CONFIG_Q800', if_true: files('q800.c')) +m68k_ss.add(when: 'CONFIG_M68K_VIRT', if_true: files('virt.c')) =20 hw_arch +=3D {'m68k': m68k_ss} --=20 2.29.2