From nobody Sun May 19 15:05:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1615480538; cv=none; d=zohomail.com; s=zohoarc; b=TRYofT+AnFzeTg72+PklCux3kOd+pH9CqpBPk3IQ//tqAHwvu0casWHA8cTbFbfqMZWkYgRPHA1E7QnJcw1lCnndJt1+XYlyueUijSpSf47A0NOjVS5taThzmroVY3hmQ34EvRsi2JVBZr0H3wbBADMUch6TdWjxh7BB2QjDtmM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615480538; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=wGhxJpk6W78D0zSq9SUWVN6rl2oAc3LYQTuXbHOxXgc=; b=cmoAKzi9eaTRGY0X52MUXtxmr8IeVQXDcYKf1uYaaYqITcXOkR6XicybLb9krxAdQkLcmnjtMlBBvRznZeb66DNas7tkyqzYvpR/0Q0GDCqNwK3E0Vnw8V5VpQJ+//ejiiVCI1Om5LEo2/cRjx066LBwZ+pDjdMTukrIAU3sM+A= ARC-Authentication-Results: i=1; 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Thu, 11 Mar 2021 11:18:06 -0500 Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-454-53ceA3tVOUKINEvZd4GouQ-1; Thu, 11 Mar 2021 11:17:56 -0500 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 6CB8A83DD23; Thu, 11 Mar 2021 16:17:55 +0000 (UTC) Received: from t480s.redhat.com (ovpn-115-26.ams2.redhat.com [10.36.115.26]) by smtp.corp.redhat.com (Postfix) with ESMTP id 9CFEB1001B2C; Thu, 11 Mar 2021 16:17:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1615479478; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=wGhxJpk6W78D0zSq9SUWVN6rl2oAc3LYQTuXbHOxXgc=; b=BhEacPOm1LgE0DjCCMhhUZGCwsqGnO+yIdm+7Q5FIUBLtBbtnsaM8vbriNHDRObjJOcUzE 2+Zuk1tkylVYYYc/j74SVp8hkVJ2PwRY+QROa5aSkpMx/jHRg/duCMUh884Zr0+dUQY9w7 Cv9U9NSoLBbOXwZEVnUxh2NjEKmB1r8= X-MC-Unique: 53ceA3tVOUKINEvZd4GouQ-1 From: David Hildenbrand To: qemu-devel@nongnu.org Subject: [PATCH v5 1/2] target/s390x: Implement the MVPG condition-code-option bit Date: Thu, 11 Mar 2021 17:17:46 +0100 Message-Id: <20210311161747.129834-2-david@redhat.com> In-Reply-To: <20210311161747.129834-1-david@redhat.com> References: <20210311161747.129834-1-david@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=david@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=63.128.21.124; envelope-from=david@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.25, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-s390x@nongnu.org, Cornelia Huck , Richard Henderson , Thomas Huth , David Hildenbrand Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Richard Henderson If the CCO bit is set, MVPG should not generate an exception but report page translation faults via a CC code. Create a new helper, access_prepare_nf, which can use probe_access_flags in non-faulting mode, and then handle watchpoints. Signed-off-by: Richard Henderson [thuth: Added logic to still inject protection exceptions] Signed-off-by: Thomas Huth [david: Look at env->tlb_fill_exc to determine if there was an exception] Signed-off-by: David Hildenbrand --- target/s390x/cpu.h | 5 ++ target/s390x/excp_helper.c | 3 + target/s390x/mem_helper.c | 124 ++++++++++++++++++++++++++++++------- 3 files changed, 110 insertions(+), 22 deletions(-) diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 60d434d5ed..468b4430f3 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -114,6 +114,11 @@ struct CPUS390XState { =20 uint64_t diag318_info; =20 +#if !defined(CONFIG_USER_ONLY) + uint64_t tlb_fill_tec; /* translation exception code during tlb_fill= */ + int tlb_fill_exc; /* exception number seen during tlb_fill */ +#endif + /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; =20 diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c index ce16af394b..c48cd6b46f 100644 --- a/target/s390x/excp_helper.c +++ b/target/s390x/excp_helper.c @@ -164,6 +164,9 @@ bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int= size, tec =3D 0; /* unused */ } =20 + env->tlb_fill_exc =3D excp; + env->tlb_fill_tec =3D tec; + if (!excp) { qemu_log_mask(CPU_LOG_MMU, "%s: set tlb %" PRIx64 " -> %" PRIx64 " (%x)\n", diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c index 25cfede806..ebb55884c9 100644 --- a/target/s390x/mem_helper.c +++ b/target/s390x/mem_helper.c @@ -130,28 +130,93 @@ typedef struct S390Access { int mmu_idx; } S390Access; =20 -static S390Access access_prepare(CPUS390XState *env, vaddr vaddr, int size, - MMUAccessType access_type, int mmu_idx, - uintptr_t ra) +/* + * With nofault=3D1, return the PGM_ exception that would have been inject= ed + * into the guest; return 0 if no exception was detected. + * + * For !CONFIG_USER_ONLY, the TEC is stored stored to env->tlb_fill_tec. + * For CONFIG_USER_ONLY, the faulting address is stored to env->__excp_add= r. + */ +static int access_prepare_nf(S390Access *access, CPUS390XState *env, + bool nofault, vaddr vaddr1, int size, + MMUAccessType access_type, + int mmu_idx, uintptr_t ra) { - S390Access access =3D { - .vaddr1 =3D vaddr, - .size1 =3D MIN(size, -(vaddr | TARGET_PAGE_MASK)), - .mmu_idx =3D mmu_idx, - }; + void *haddr1, *haddr2 =3D NULL; + int size1, size2; + vaddr vaddr2 =3D 0; + int flags; + + assert(size > 0 && size <=3D 4096); =20 - g_assert(size > 0 && size <=3D 4096); - access.haddr1 =3D probe_access(env, access.vaddr1, access.size1, acces= s_type, - mmu_idx, ra); + size1 =3D MIN(size, -(vaddr1 | TARGET_PAGE_MASK)), + size2 =3D size - size1; =20 - if (unlikely(access.size1 !=3D size)) { +#if !defined(CONFIG_USER_ONLY) + /* + * For !CONFIG_USER_ONLY, we cannot rely on TLB_INVALID_MASK or haddr= =3D=3DNULL + * to detect if there was an exception during tlb_fill(). + */ + env->tlb_fill_exc =3D 0; +#endif + flags =3D probe_access_flags(env, vaddr1, access_type, mmu_idx, + nofault, &haddr1, ra); +#if !defined(CONFIG_USER_ONLY) + if (env->tlb_fill_exc) { + return env->tlb_fill_exc; + } +#else + if (!haddr1) { + env->__excp_addr =3D vaddr1; + return PGM_ADDRESSING; + } +#endif + if (unlikely(size2)) { /* The access crosses page boundaries. */ - access.vaddr2 =3D wrap_address(env, vaddr + access.size1); - access.size2 =3D size - access.size1; - access.haddr2 =3D probe_access(env, access.vaddr2, access.size2, - access_type, mmu_idx, ra); + vaddr2 =3D wrap_address(env, vaddr1 + size1); + flags |=3D probe_access_flags(env, vaddr2, access_type, mmu_idx, + nofault, &haddr2, ra); +#if !defined(CONFIG_USER_ONLY) + if (env->tlb_fill_exc) { + return env->tlb_fill_exc; + } +#else + if (!haddr2) { + env->__excp_addr =3D vaddr2; + return PGM_ADDRESSING; + } +#endif } - return access; + + if (unlikely(flags & TLB_WATCHPOINT)) { + /* S390 does not presently use transaction attributes. */ + cpu_check_watchpoint(env_cpu(env), vaddr1, size, + MEMTXATTRS_UNSPECIFIED, + (access_type =3D=3D MMU_DATA_STORE + ? BP_MEM_WRITE : BP_MEM_READ), ra); + } + + *access =3D (S390Access) { + .vaddr1 =3D vaddr1, + .vaddr2 =3D vaddr2, + .haddr1 =3D haddr1, + .haddr2 =3D haddr2, + .size1 =3D size1, + .size2 =3D size2, + .mmu_idx =3D mmu_idx + }; + return 0; +} + +static S390Access access_prepare(CPUS390XState *env, vaddr vaddr, int size, + MMUAccessType access_type, int mmu_idx, + uintptr_t ra) +{ + S390Access ret; + int exc =3D access_prepare_nf(&ret, env, false, vaddr, size, + access_type, mmu_idx, ra); + assert(!exc); + return ret; } =20 /* Helper to handle memset on a single page. */ @@ -845,8 +910,10 @@ uint32_t HELPER(mvpg)(CPUS390XState *env, uint64_t r0,= uint64_t r1, uint64_t r2) const int mmu_idx =3D cpu_mmu_index(env, false); const bool f =3D extract64(r0, 11, 1); const bool s =3D extract64(r0, 10, 1); + const bool cco =3D extract64(r0, 8, 1); uintptr_t ra =3D GETPC(); S390Access srca, desta; + int exc; =20 if ((f && s) || extract64(r0, 12, 4)) { tcg_s390_program_interrupt(env, PGM_SPECIFICATION, GETPC()); @@ -858,13 +925,26 @@ uint32_t HELPER(mvpg)(CPUS390XState *env, uint64_t r0= , uint64_t r1, uint64_t r2) /* * TODO: * - Access key handling - * - CC-option with surpression of page-translation exceptions * - Store r1/r2 register identifiers at real location 162 */ - srca =3D access_prepare(env, r2, TARGET_PAGE_SIZE, MMU_DATA_LOAD, mmu_= idx, - ra); - desta =3D access_prepare(env, r1, TARGET_PAGE_SIZE, MMU_DATA_STORE, mm= u_idx, - ra); + exc =3D access_prepare_nf(&srca, env, cco, r2, TARGET_PAGE_SIZE, + MMU_DATA_LOAD, mmu_idx, ra); + if (exc) { + return 2; + } + exc =3D access_prepare_nf(&desta, env, cco, r1, TARGET_PAGE_SIZE, + MMU_DATA_STORE, mmu_idx, ra); + if (exc) { +#if !defined(CONFIG_USER_ONLY) + if (exc =3D=3D PGM_PROTECTION) { + stq_phys(env_cpu(env)->as, + env->psa + offsetof(LowCore, trans_exc_code), + env->tlb_fill_tec); + tcg_s390_program_interrupt(env, PGM_PROTECTION, ra); + } +#endif + return 1; + } access_memmove(env, &desta, &srca, ra); return 0; /* data moved */ } --=20 2.29.2 From nobody Sun May 19 15:05:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 11 Mar 2021 11:18:04 -0500 Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-585-SXUoTS-oN5m5nzFxAyVkhw-1; Thu, 11 Mar 2021 11:17:58 -0500 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 356E219200C0; Thu, 11 Mar 2021 16:17:57 +0000 (UTC) Received: from t480s.redhat.com (ovpn-115-26.ams2.redhat.com [10.36.115.26]) by smtp.corp.redhat.com (Postfix) with ESMTP id BF9841000358; Thu, 11 Mar 2021 16:17:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1615479480; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Zs2nUFsInhPIJEY+eitd68h57soEVovZP0V1TfxprsE=; b=cPPPdq4cjsIgekntRi09267D+GP1n/6hTaB9o/0LnjslSXxN+2TqF4cjCldNvIadLxn+U1 z8E6WsxbzCFiIc50gqfAbKzaRvvMyPP7zsAGiy4HW9qfgmGW88+o4r3nwRfYsOopUnKorb l0eTsWrvmYAnK6HZBqAy6L0/z9hwox0= X-MC-Unique: SXUoTS-oN5m5nzFxAyVkhw-1 From: David Hildenbrand To: qemu-devel@nongnu.org Subject: [PATCH v5 2/2] target/s390x: Store r1/r2 for page-translation exceptions during MVPG Date: Thu, 11 Mar 2021 17:17:47 +0100 Message-Id: <20210311161747.129834-3-david@redhat.com> In-Reply-To: <20210311161747.129834-1-david@redhat.com> References: <20210311161747.129834-1-david@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=david@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.205.24.124; envelope-from=david@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.25, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-s390x@nongnu.org, Cornelia Huck , Richard Henderson , Thomas Huth , David Hildenbrand Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The PoP states: When EDAT-1 does not apply, and a program interruption due to a page-translation exception is recognized by the MOVE PAGE instruction, the contents of the R1 field of the instruction are stored in bit positions 0-3 of location 162, and the contents of the R2 field are stored in bit positions 4-7. If [...] an ASCE-type, region-first-translation, region-second-translation, region-third-translation, or segment-translation exception was recognized, the contents of location 162 are unpredictable. So we have to write r1/r2 into the lowcore on page-translation exceptions. Simply handle all exceptions inside our mvpg helper now. Signed-off-by: David Hildenbrand --- target/s390x/helper.h | 2 +- target/s390x/insn-data.def | 2 +- target/s390x/mem_helper.c | 44 ++++++++++++++++++++++---------------- target/s390x/translate.c | 7 +++++- 4 files changed, 34 insertions(+), 21 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index 55bd1551e6..d4e4f3388f 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -18,7 +18,7 @@ DEF_HELPER_3(srstu, void, env, i32, i32) DEF_HELPER_4(clst, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(mvn, TCG_CALL_NO_WG, void, env, i32, i64, i64) DEF_HELPER_FLAGS_4(mvo, TCG_CALL_NO_WG, void, env, i32, i64, i64) -DEF_HELPER_FLAGS_4(mvpg, TCG_CALL_NO_WG, i32, env, i64, i64, i64) +DEF_HELPER_FLAGS_4(mvpg, TCG_CALL_NO_WG, i32, env, i64, i32, i32) DEF_HELPER_FLAGS_4(mvz, TCG_CALL_NO_WG, void, env, i32, i64, i64) DEF_HELPER_3(mvst, i32, env, i32, i32) DEF_HELPER_4(ex, void, env, i32, i64, i64) diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def index e5b6efabf3..0bb1886a2e 100644 --- a/target/s390x/insn-data.def +++ b/target/s390x/insn-data.def @@ -641,7 +641,7 @@ /* MOVE NUMERICS */ C(0xd100, MVN, SS_a, Z, la1, a2, 0, 0, mvn, 0) /* MOVE PAGE */ - C(0xb254, MVPG, RRE, Z, r1_o, r2_o, 0, 0, mvpg, 0) + C(0xb254, MVPG, RRE, Z, 0, 0, 0, 0, mvpg, 0) /* MOVE STRING */ C(0xb255, MVST, RRE, Z, 0, 0, 0, 0, mvst, 0) /* MOVE WITH OPTIONAL SPECIFICATION */ diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c index ebb55884c9..432c1a4954 100644 --- a/target/s390x/mem_helper.c +++ b/target/s390x/mem_helper.c @@ -905,8 +905,10 @@ uint64_t HELPER(clst)(CPUS390XState *env, uint64_t c, = uint64_t s1, uint64_t s2) } =20 /* move page */ -uint32_t HELPER(mvpg)(CPUS390XState *env, uint64_t r0, uint64_t r1, uint64= _t r2) +uint32_t HELPER(mvpg)(CPUS390XState *env, uint64_t r0, uint32_t r1, uint32= _t r2) { + const uint64_t src =3D get_address(env, r2) & TARGET_PAGE_MASK; + const uint64_t dst =3D get_address(env, r1) & TARGET_PAGE_MASK; const int mmu_idx =3D cpu_mmu_index(env, false); const bool f =3D extract64(r0, 11, 1); const bool s =3D extract64(r0, 10, 1); @@ -919,34 +921,40 @@ uint32_t HELPER(mvpg)(CPUS390XState *env, uint64_t r0= , uint64_t r1, uint64_t r2) tcg_s390_program_interrupt(env, PGM_SPECIFICATION, GETPC()); } =20 - r1 =3D wrap_address(env, r1 & TARGET_PAGE_MASK); - r2 =3D wrap_address(env, r2 & TARGET_PAGE_MASK); - /* - * TODO: - * - Access key handling - * - Store r1/r2 register identifiers at real location 162 + * We always manually handle exceptions such that we can properly store + * r1/r2 to the lowcore on page-translation exceptions. + * + * TODO: Access key handling */ - exc =3D access_prepare_nf(&srca, env, cco, r2, TARGET_PAGE_SIZE, + exc =3D access_prepare_nf(&srca, env, true, src, TARGET_PAGE_SIZE, MMU_DATA_LOAD, mmu_idx, ra); if (exc) { - return 2; + if (cco) { + return 2; + } + goto inject_exc; } - exc =3D access_prepare_nf(&desta, env, cco, r1, TARGET_PAGE_SIZE, + exc =3D access_prepare_nf(&desta, env, true, dst, TARGET_PAGE_SIZE, MMU_DATA_STORE, mmu_idx, ra); if (exc) { -#if !defined(CONFIG_USER_ONLY) - if (exc =3D=3D PGM_PROTECTION) { - stq_phys(env_cpu(env)->as, - env->psa + offsetof(LowCore, trans_exc_code), - env->tlb_fill_tec); - tcg_s390_program_interrupt(env, PGM_PROTECTION, ra); + if (cco && exc !=3D PGM_PROTECTION) { + return 1; } -#endif - return 1; + goto inject_exc; } access_memmove(env, &desta, &srca, ra); return 0; /* data moved */ +inject_exc: +#if !defined(CONFIG_USER_ONLY) + stq_phys(env_cpu(env)->as, env->psa + offsetof(LowCore, trans_exc_code= ), + env->tlb_fill_tec); + if (exc =3D=3D PGM_PAGE_TRANS) { + stb_phys(env_cpu(env)->as, env->psa + offsetof(LowCore, op_access_= id), + r1 << 4 | r2); + } +#endif + tcg_s390_program_interrupt(env, exc, ra); } =20 /* string copy */ diff --git a/target/s390x/translate.c b/target/s390x/translate.c index 61dd0341e4..4f953ddfba 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -3513,7 +3513,12 @@ static DisasJumpType op_mvo(DisasContext *s, DisasOp= s *o) =20 static DisasJumpType op_mvpg(DisasContext *s, DisasOps *o) { - gen_helper_mvpg(cc_op, cpu_env, regs[0], o->in1, o->in2); + TCGv_i32 t1 =3D tcg_const_i32(get_field(s, r1)); + TCGv_i32 t2 =3D tcg_const_i32(get_field(s, r2)); + + gen_helper_mvpg(cc_op, cpu_env, regs[0], t1, t2); + tcg_temp_free_i32(t1); + tcg_temp_free_i32(t2); set_cc_static(s); return DISAS_NEXT; } --=20 2.29.2