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charset="utf-8" From: Heecheol Yang Add some of these features for AVR GPIO: - GPIO I/O : PORTx registers - Data Direction : DDRx registers - DDRx toggling : PINx registers Following things are not supported yet: - MCUR registers Signed-off-by: Heecheol Yang Signed-off-by: G S Niteesh Babu Message-id: DM6PR16MB2473D96C4D975DE569A330F2E60C0@DM6PR16MB2473.namprd16.p= rod.outlook.com Reviewed-by: Michael Rolnik --- hw/avr/Kconfig | 1 + hw/avr/atmega.c | 7 +- hw/avr/atmega.h | 2 + hw/gpio/Kconfig | 3 + hw/gpio/avr_gpio.c | 140 +++++++++++++++++++++++++++++++++++++ hw/gpio/meson.build | 1 + include/hw/gpio/avr_gpio.h | 53 ++++++++++++++ 7 files changed, 205 insertions(+), 2 deletions(-) create mode 100644 hw/gpio/avr_gpio.c create mode 100644 include/hw/gpio/avr_gpio.h diff --git a/hw/avr/Kconfig b/hw/avr/Kconfig index d31298c3cc..16a57ced11 100644 --- a/hw/avr/Kconfig +++ b/hw/avr/Kconfig @@ -3,6 +3,7 @@ config AVR_ATMEGA_MCU select AVR_TIMER16 select AVR_USART select AVR_POWER + select AVR_GPIO =20 config ARDUINO select AVR_ATMEGA_MCU diff --git a/hw/avr/atmega.c b/hw/avr/atmega.c index 44c6afebbb..ad942028fd 100644 --- a/hw/avr/atmega.c +++ b/hw/avr/atmega.c @@ -283,8 +283,11 @@ static void atmega_realize(DeviceState *dev, Error **e= rrp) continue; } devname =3D g_strdup_printf("atmega-gpio-%c", 'a' + (char)i); - create_unimplemented_device(devname, - OFFSET_DATA + mc->dev[idx].addr, 3); + object_initialize_child(OBJECT(dev), devname, &s->gpio[i], + TYPE_AVR_GPIO); + sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), &error_abort); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, + OFFSET_DATA + mc->dev[idx].addr); g_free(devname); } =20 diff --git a/hw/avr/atmega.h b/hw/avr/atmega.h index a99ee15c7e..e2289d5744 100644 --- a/hw/avr/atmega.h +++ b/hw/avr/atmega.h @@ -13,6 +13,7 @@ =20 #include "hw/char/avr_usart.h" #include "hw/timer/avr_timer16.h" +#include "hw/gpio/avr_gpio.h" #include "hw/misc/avr_power.h" #include "target/avr/cpu.h" #include "qom/object.h" @@ -44,6 +45,7 @@ struct AtmegaMcuState { DeviceState *io; AVRMaskState pwr[POWER_MAX]; AVRUsartState usart[USART_MAX]; + AVRGPIOState gpio[GPIO_MAX]; AVRTimer16State timer[TIMER_MAX]; uint64_t xtal_freq_hz; }; diff --git a/hw/gpio/Kconfig b/hw/gpio/Kconfig index f0e7405f6e..fde7019b2b 100644 --- a/hw/gpio/Kconfig +++ b/hw/gpio/Kconfig @@ -13,3 +13,6 @@ config GPIO_PWR =20 config SIFIVE_GPIO bool + +config AVR_GPIO + bool diff --git a/hw/gpio/avr_gpio.c b/hw/gpio/avr_gpio.c new file mode 100644 index 0000000000..8fc192dbcb --- /dev/null +++ b/hw/gpio/avr_gpio.c @@ -0,0 +1,140 @@ +/* + * AVR processors GPIO registers emulation. + * + * Copyright (C) 2020 Heecheol Yang + * Copyright (C) 2021 Niteesh Babu G S + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 or + * (at your option) version 3 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/sysbus.h" +#include "hw/irq.h" +#include "hw/gpio/avr_gpio.h" +#include "hw/qdev-properties.h" + +static void avr_gpio_reset(DeviceState *dev) +{ + AVRGPIOState *gpio =3D AVR_GPIO(dev); + gpio->reg.pin =3D 0u; + gpio->reg.ddr =3D 0u; + gpio->reg.port =3D 0u; +} + +static void avr_gpio_write_port(AVRGPIOState *s, uint64_t value) +{ + uint8_t pin; + uint8_t org_val =3D value; + uint8_t cur_port_val =3D s->reg.port; + uint8_t cur_ddr_val =3D s->reg.ddr; + + for (pin =3D 0u; pin < 8u ; pin++) { + uint8_t cur_port_pin_val =3D cur_port_val & 0x01u; + uint8_t cur_ddr_pin_val =3D cur_ddr_val & 0x01u; + uint8_t new_port_pin_val =3D value & 0x01u; + + if (cur_ddr_pin_val && (cur_port_pin_val !=3D new_port_pin_val)) { + qemu_set_irq(s->out[pin], new_port_pin_val); + } + cur_port_val >>=3D 1u; + cur_ddr_val >>=3D 1u; + value >>=3D 1u; + } + s->reg.port =3D org_val & s->reg.ddr; +} +static uint64_t avr_gpio_read(void *opaque, hwaddr offset, unsigned int si= ze) +{ + AVRGPIOState *s =3D (AVRGPIOState *)opaque; + switch (offset) { + case GPIO_PIN: + return s->reg.pin; + case GPIO_DDR: + return s->reg.ddr; + case GPIO_PORT: + return s->reg.port; + default: + g_assert_not_reached(); + break; + } + return 0; +} + +static void avr_gpio_write(void *opaque, hwaddr offset, uint64_t value, + unsigned int size) +{ + AVRGPIOState *s =3D (AVRGPIOState *)opaque; + value =3D value & 0xFF; + + trace_avr_gpio_write(offset, value); + switch (offset) { + case GPIO_PIN: + s->reg.pin =3D value; + s->reg.port ^=3D s->reg.pin; + break; + case GPIO_DDR: + s->reg.ddr =3D value; + break; + case GPIO_PORT: + avr_gpio_write_port(s, value); + break; + default: + g_assert_not_reached(); + break; + } +} + +static const MemoryRegionOps avr_gpio_ops =3D { + .read =3D avr_gpio_read, + .write =3D avr_gpio_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, +}; + +static void avr_gpio_init(Object *obj) +{ + AVRGPIOState *s =3D AVR_GPIO(obj); + qdev_init_gpio_out(DEVICE(obj), s->out, ARRAY_SIZE(s->out)); + memory_region_init_io(&s->mmio, obj, &avr_gpio_ops, s, TYPE_AVR_GPIO, = 3); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); +} +static void avr_gpio_realize(DeviceState *dev, Error **errp) +{ + /* Do nothing currently */ +} + + +static void avr_gpio_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->reset =3D avr_gpio_reset; + dc->realize =3D avr_gpio_realize; +} + +static const TypeInfo avr_gpio_info =3D { + .name =3D TYPE_AVR_GPIO, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(AVRGPIOState), + .instance_init =3D avr_gpio_init, + .class_init =3D avr_gpio_class_init, +}; + +static void avr_gpio_register_types(void) +{ + type_register_static(&avr_gpio_info); +} + +type_init(avr_gpio_register_types) diff --git a/hw/gpio/meson.build b/hw/gpio/meson.build index 79568f00ce..366aca52ca 100644 --- a/hw/gpio/meson.build +++ b/hw/gpio/meson.build @@ -13,3 +13,4 @@ softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_= gpio.c')) softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_gpio.c')) softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_gpio.c')) softmmu_ss.add(when: 'CONFIG_SIFIVE_GPIO', if_true: files('sifive_gpio.c')) +softmmu_ss.add(when: 'CONFIG_AVR_GPIO', if_true: files('avr_gpio.c')) diff --git a/include/hw/gpio/avr_gpio.h b/include/hw/gpio/avr_gpio.h new file mode 100644 index 0000000000..498a7275f0 --- /dev/null +++ b/include/hw/gpio/avr_gpio.h @@ -0,0 +1,53 @@ +/* + * AVR processors GPIO registers definition. + * + * Copyright (C) 2020 Heecheol Yang + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 or + * (at your option) version 3 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef AVR_GPIO_H +#define AVR_GPIO_H + +#include "hw/sysbus.h" +#include "qom/object.h" + +/* Offsets of registers. */ +#define GPIO_PIN 0x00 +#define GPIO_DDR 0x01 +#define GPIO_PORT 0x02 + +#define TYPE_AVR_GPIO "avr-gpio" +OBJECT_DECLARE_SIMPLE_TYPE(AVRGPIOState, AVR_GPIO) +#define AVR_GPIO_COUNT 8 + +struct AVRGPIOState { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + MemoryRegion mmio; + + struct { + uint8_t pin; + uint8_t ddr; + uint8_t port; + } reg; + + /* PORTx data changed IRQs */ + qemu_irq out[8u]; + +}; + +#endif /* AVR_GPIO_H */ --=20 2.17.1 From nobody Sun May 19 13:54:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Thu, 11 Mar 2021 05:56:31 -0800 (PST) From: G S Niteesh Babu To: qemu-devel@nongnu.org Subject: [PATCH 2/3] hw/gpio/avr_gpio.c: add tracing for read and writes Date: Thu, 11 Mar 2021 19:25:38 +0530 Message-Id: <20210311135539.10206-3-niteesh.gs@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210311135539.10206-1-niteesh.gs@gmail.com> References: <20210311135539.10206-1-niteesh.gs@gmail.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=niteesh.gs@gmail.com; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: S.E.Harris@kent.ac.uk, mrolnik@gmail.com, f4bug@amsat.org, G S Niteesh Babu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Added tracing for gpio read, write, and update output irq. 1) trace_avr_gpio_update_ouput_irq 2) trace_avr_gpio_read 3) trace_avr_gpio_write Signed-off-by: G S Niteesh Babu Reviewed-by: Michael Rolnik --- hw/gpio/avr_gpio.c | 16 ++++++++++++---- hw/gpio/trace-events | 6 ++++++ 2 files changed, 18 insertions(+), 4 deletions(-) diff --git a/hw/gpio/avr_gpio.c b/hw/gpio/avr_gpio.c index 8fc192dbcb..8498a99dd2 100644 --- a/hw/gpio/avr_gpio.c +++ b/hw/gpio/avr_gpio.c @@ -26,6 +26,7 @@ #include "hw/irq.h" #include "hw/gpio/avr_gpio.h" #include "hw/qdev-properties.h" +#include "trace.h" =20 static void avr_gpio_reset(DeviceState *dev) { @@ -49,6 +50,7 @@ static void avr_gpio_write_port(AVRGPIOState *s, uint64_t= value) =20 if (cur_ddr_pin_val && (cur_port_pin_val !=3D new_port_pin_val)) { qemu_set_irq(s->out[pin], new_port_pin_val); + trace_avr_gpio_update_output_irq(pin, new_port_pin_val); } cur_port_val >>=3D 1u; cur_ddr_val >>=3D 1u; @@ -58,19 +60,25 @@ static void avr_gpio_write_port(AVRGPIOState *s, uint64= _t value) } static uint64_t avr_gpio_read(void *opaque, hwaddr offset, unsigned int si= ze) { + uint8_t val =3D 0; AVRGPIOState *s =3D (AVRGPIOState *)opaque; switch (offset) { case GPIO_PIN: - return s->reg.pin; + val =3D s->reg.pin; + break; case GPIO_DDR: - return s->reg.ddr; + val =3D s->reg.ddr; + break; case GPIO_PORT: - return s->reg.port; + val =3D s->reg.port; + break; default: g_assert_not_reached(); break; } - return 0; + + trace_avr_gpio_read(offset, val); + return val; } =20 static void avr_gpio_write(void *opaque, hwaddr offset, uint64_t value, diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events index 46ab9323bd..a054def07c 100644 --- a/hw/gpio/trace-events +++ b/hw/gpio/trace-events @@ -18,3 +18,9 @@ sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%= " PRIx64 " value 0x%" P sifive_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " v= alue 0x%" PRIx64 sifive_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PR= Ii64 sifive_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64= " value %" PRIi64 + +# avr_gpio.c +avr_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%= " PRIx64 +avr_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " valu= e 0x%" PRIx64 +avr_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64 +avr_gpio_update_output_irq(int64_t line, int64_t value) "pin %" PRIi64 " v= alue %" PRIi64 --=20 2.17.1 From nobody Sun May 19 13:54:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 11 Mar 2021 05:56:34 -0800 (PST) From: G S Niteesh Babu To: qemu-devel@nongnu.org Subject: [PATCH 3/3] avr/arduino: Add D13 LED Date: Thu, 11 Mar 2021 19:25:39 +0530 Message-Id: <20210311135539.10206-4-niteesh.gs@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210311135539.10206-1-niteesh.gs@gmail.com> References: <20210311135539.10206-1-niteesh.gs@gmail.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=niteesh.gs@gmail.com; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: S.E.Harris@kent.ac.uk, mrolnik@gmail.com, f4bug@amsat.org, G S Niteesh Babu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: G S Niteesh Babu Reviewed-by: Michael Rolnik --- hw/avr/Kconfig | 1 + hw/avr/arduino.c | 15 +++++++++++++++ 2 files changed, 16 insertions(+) diff --git a/hw/avr/Kconfig b/hw/avr/Kconfig index 16a57ced11..e0d4fc5537 100644 --- a/hw/avr/Kconfig +++ b/hw/avr/Kconfig @@ -8,3 +8,4 @@ config AVR_ATMEGA_MCU config ARDUINO select AVR_ATMEGA_MCU select UNIMP + select LED diff --git a/hw/avr/arduino.c b/hw/avr/arduino.c index 3c8388490d..5cdba3201c 100644 --- a/hw/avr/arduino.c +++ b/hw/avr/arduino.c @@ -13,6 +13,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "hw/boards.h" +#include "hw/misc/led.h" #include "atmega.h" #include "boot.h" #include "qom/object.h" @@ -22,6 +23,8 @@ struct ArduinoMachineState { MachineState parent_obj; /*< public >*/ AtmegaMcuState mcu; + + LEDState *onboard_led; }; typedef struct ArduinoMachineState ArduinoMachineState; =20 @@ -49,6 +52,18 @@ static void arduino_machine_init(MachineState *machine) amc->xtal_hz, &error_abort); sysbus_realize(SYS_BUS_DEVICE(&ams->mcu), &error_abort); =20 + ams->onboard_led =3D led_create_simple(OBJECT(ams), + GPIO_POLARITY_ACTIVE_HIGH, + LED_COLOR_BLUE, + "D13 LED"); + + /* TODO: Add macro or function to map pins to ports */ + /* The onboard led is connected to PIN 13 in all boards currently supp= orted + * in QEMU. And PIN 13 is mapped to PORT B BIT 5. + */ + qdev_connect_gpio_out(DEVICE(&ams->mcu.gpio[1]), 5, + qdev_get_gpio_in(DEVICE(ams->onboard_led), 0)); + if (machine->firmware) { if (!avr_load_firmware(&ams->mcu.cpu, machine, &ams->mcu.flash, machine->firmware)) { --=20 2.17.1