From nobody Sun May 19 14:40:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1615456161; cv=none; d=zohomail.com; s=zohoarc; b=IBBvT8icss9e9fUNXyB9R3G2/Y8woLSZARQn2OTHSQ7iXLZj396walMQCs99MJ0RhVj+YRFKDq6ktiukfpRllZ9zeXchfC+ATtFGRC7M+fLiaNdDB3wjbj5hvSVXTBGe4YkwZx8cGjbTCKLJ0X+A7eTS089EYtfyvg83ZA+WcCs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615456161; h=Content-Transfer-Encoding:Cc:Date:From:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:To; bh=/EydoaOV/PPHn1Nr4DCDo+4VZr9LWyMzCvyNgPvjSys=; b=IPcuGAKAT5WnTKzFx8yMGup1l6STW7yMJkA/7TZjCd1Tvz+QXnpPtCD6A9ZF2lq8sJ62QvfH9+K/3OQh5UfrWA2w6l6k2U7wD9imbgt32LWaTJYVKQcZLwXYQmP9gnWYTmAiPjsgzfv8ZrlpVbL6ywMgNMVbDGCiG/DYEffJ4fY= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1615456161623677.1696094125879; Thu, 11 Mar 2021 01:49:21 -0800 (PST) Received: from localhost ([::1]:51266 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lKHwW-0003oR-4Q for importer@patchew.org; Thu, 11 Mar 2021 04:49:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59756) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lKHvJ-0002qd-SY; Thu, 11 Mar 2021 04:48:05 -0500 Received: from serv1.kernkonzept.com ([2a01:4f8:1c1c:b490::2]:56843 helo=mx.kernkonzept.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lKHvH-0001jq-Kp; Thu, 11 Mar 2021 04:48:05 -0500 Received: from [86.56.46.35] (helo=broc.lan) by mx.kernkonzept.com with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) id 1lKHv8-0005Te-7L; Thu, 11 Mar 2021 10:47:54 +0100 From: Georg Kotheimer To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH] target/riscv: Fix read and write accesses to vsip and vsie Date: Thu, 11 Mar 2021 10:47:38 +0100 Message-Id: <20210311094738.1376795-1-georg.kotheimer@kernkonzept.com> X-Mailer: git-send-email 2.30.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=2a01:4f8:1c1c:b490::2; envelope-from=georg.kotheimer@kernkonzept.com; helo=mx.kernkonzept.com X-Spam_score_int: -11 X-Spam_score: -1.2 X-Spam_bar: - X-Spam_report: (-1.2 / 5.0 requ) BAYES_00=-1.9, KHOP_HELO_FCRDNS=0.02, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Georg Kotheimer Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The previous implementation was broken in many ways: - Used mideleg instead of hideleg to mask accesses - Used MIP_VSSIP instead of VS_MODE_INTERRUPTS to mask writes to vsie - Did not shift between S bits and VS bits (VSEIP <-> SEIP, ...) Signed-off-by: Georg Kotheimer Reviewed-by: Alistair Francis --- target/riscv/csr.c | 68 +++++++++++++++++++++++----------------------- 1 file changed, 34 insertions(+), 34 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index fd2e6363f3..4a5b362ec1 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -748,30 +748,42 @@ static int write_sstatus(CPURISCVState *env, int csrn= o, target_ulong val) return write_mstatus(env, CSR_MSTATUS, newval); } =20 +static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val) +{ + /* Shift the VS bits to their S bit location in vsie */ + *val =3D (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1; + return 0; +} + static int read_sie(CPURISCVState *env, int csrno, target_ulong *val) { if (riscv_cpu_virt_enabled(env)) { - /* Tell the guest the VS bits, shifted to the S bit locations */ - *val =3D (env->mie & env->mideleg & VS_MODE_INTERRUPTS) >> 1; + read_vsie(env, CSR_VSIE, val); } else { *val =3D env->mie & env->mideleg; } return 0; } =20 -static int write_sie(CPURISCVState *env, int csrno, target_ulong val) +static int write_vsie(CPURISCVState *env, int csrno, target_ulong val) { - target_ulong newval; + /* Shift the S bits to their VS bit location in mie */ + target_ulong newval =3D (env->mie & ~VS_MODE_INTERRUPTS) | + ((val << 1) & env->hideleg & VS_MODE_INTERRUPTS); + return write_mie(env, CSR_MIE, newval); +} =20 +static int write_sie(CPURISCVState *env, int csrno, target_ulong val) +{ if (riscv_cpu_virt_enabled(env)) { - /* Shift the guests S bits to VS */ - newval =3D (env->mie & ~VS_MODE_INTERRUPTS) | - ((val << 1) & VS_MODE_INTERRUPTS); + write_vsie(env, CSR_VSIE, val); } else { - newval =3D (env->mie & ~S_MODE_INTERRUPTS) | (val & S_MODE_INTERRU= PTS); + target_ulong newval =3D (env->mie & ~S_MODE_INTERRUPTS) | + (val & S_MODE_INTERRUPTS); + write_mie(env, CSR_MIE, newval); } =20 - return write_mie(env, CSR_MIE, newval); + return 0; } =20 static int read_stvec(CPURISCVState *env, int csrno, target_ulong *val) @@ -852,17 +864,25 @@ static int write_sbadaddr(CPURISCVState *env, int csr= no, target_ulong val) return 0; } =20 +static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value, + target_ulong new_value, target_ulong write_mask) +{ + /* Shift the S bits to their VS bit location in mip */ + int ret =3D rmw_mip(env, 0, ret_value, new_value << 1, + (write_mask << 1) & vsip_writable_mask & env->hidele= g); + *ret_value &=3D VS_MODE_INTERRUPTS; + /* Shift the VS bits to their S bit location in vsip */ + *ret_value >>=3D 1; + return ret; +} + static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value, target_ulong new_value, target_ulong write_mask) { int ret; =20 if (riscv_cpu_virt_enabled(env)) { - /* Shift the new values to line up with the VS bits */ - ret =3D rmw_mip(env, CSR_MSTATUS, ret_value, new_value << 1, - (write_mask & sip_writable_mask) << 1 & env->mideleg= ); - ret &=3D vsip_writable_mask; - ret >>=3D 1; + ret =3D rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask); } else { ret =3D rmw_mip(env, CSR_MSTATUS, ret_value, new_value, write_mask & env->mideleg & sip_writable_mask); @@ -1121,26 +1141,6 @@ static int write_vsstatus(CPURISCVState *env, int cs= rno, target_ulong val) return 0; } =20 -static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value, - target_ulong new_value, target_ulong write_mask) -{ - int ret =3D rmw_mip(env, 0, ret_value, new_value, - write_mask & env->mideleg & vsip_writable_mask); - return ret; -} - -static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val) -{ - *val =3D env->mie & env->mideleg & VS_MODE_INTERRUPTS; - return 0; -} - -static int write_vsie(CPURISCVState *env, int csrno, target_ulong val) -{ - target_ulong newval =3D (env->mie & ~env->mideleg) | (val & env->midel= eg & MIP_VSSIP); - return write_mie(env, CSR_MIE, newval); -} - static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val) { *val =3D env->vstvec; --=20 2.30.1