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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=66.111.4.25; envelope-from=its@irrelevant.dk; helo=out1-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Kevin Wolf , qemu-block@nongnu.org, Klaus Jensen , Gollu Appalanaidu , Max Reitz , Klaus Jensen , Stefan Hajnoczi , Keith Busch Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Gollu Appalanaidu Add the 'oncs' nvme device parameter to allow optional features to be enabled/disabled explicitly. Since most of these are optional commands, make the CSE log pages dynamic to account for the value of ONCS. Signed-off-by: Gollu Appalanaidu Signed-off-by: Klaus Jensen --- hw/block/nvme.h | 7 ++++ hw/block/nvme.c | 101 ++++++++++++++++++++++++++++++++---------------- 2 files changed, 74 insertions(+), 34 deletions(-) diff --git a/hw/block/nvme.h b/hw/block/nvme.h index 4955d649c7d4..65c80cfaef62 100644 --- a/hw/block/nvme.h +++ b/hw/block/nvme.h @@ -9,6 +9,7 @@ =20 #define NVME_DEFAULT_ZONE_SIZE (128 * MiB) #define NVME_DEFAULT_MAX_ZA_SIZE (128 * KiB) +#define NVME_MAX_COMMANDS 0x100 =20 /* * Subsystem namespace list for allocated namespaces should be larger than @@ -28,6 +29,7 @@ typedef struct NvmeParams { bool use_intel_id; uint8_t zasl; bool legacy_cmb; + uint16_t oncs; } NvmeParams; =20 typedef struct NvmeAsyncEvent { @@ -210,6 +212,11 @@ typedef struct NvmeCtrl { NvmeCQueue admin_cq; NvmeIdCtrl id_ctrl; NvmeFeatureVal features; + + struct { + uint32_t nvm[NVME_MAX_COMMANDS]; + uint32_t zoned[NVME_MAX_COMMANDS]; + } iocs; } NvmeCtrl; =20 static inline NvmeNamespace *nvme_ns(NvmeCtrl *n, uint32_t nsid) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index d439e44db839..fbb578a6e669 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -84,6 +84,11 @@ * the minimum memory page size (CAP.MPSMIN). The default value is 0 (i.= e. * defaulting to the value of `mdts`). * + * - `oncs` + * This field indicates the optional NVM commands and features supported + * by the controller. To add support for the optional feature, needs to + * set the corresponding support indicated bit. + * * nvme namespace device parameters * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ * - `subsys` @@ -185,7 +190,7 @@ static const uint32_t nvme_feature_cap[NVME_FID_MAX] = =3D { [NVME_TIMESTAMP] =3D NVME_FEAT_CAP_CHANGE, }; =20 -static const uint32_t nvme_cse_acs[256] =3D { +static const uint32_t nvme_cse_acs[NVME_MAX_COMMANDS] =3D { [NVME_ADM_CMD_DELETE_SQ] =3D NVME_CMD_EFF_CSUPP, [NVME_ADM_CMD_CREATE_SQ] =3D NVME_CMD_EFF_CSUPP, [NVME_ADM_CMD_GET_LOG_PAGE] =3D NVME_CMD_EFF_CSUPP, @@ -199,30 +204,7 @@ static const uint32_t nvme_cse_acs[256] =3D { [NVME_ADM_CMD_NS_ATTACHMENT] =3D NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_= NIC, }; =20 -static const uint32_t nvme_cse_iocs_none[256]; - -static const uint32_t nvme_cse_iocs_nvm[256] =3D { - [NVME_CMD_FLUSH] =3D NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_= LBCC, - [NVME_CMD_WRITE_ZEROES] =3D NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_= LBCC, - [NVME_CMD_WRITE] =3D NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_= LBCC, - [NVME_CMD_READ] =3D NVME_CMD_EFF_CSUPP, - [NVME_CMD_DSM] =3D NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_= LBCC, - [NVME_CMD_COPY] =3D NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_= LBCC, - [NVME_CMD_COMPARE] =3D NVME_CMD_EFF_CSUPP, -}; - -static const uint32_t nvme_cse_iocs_zoned[256] =3D { - [NVME_CMD_FLUSH] =3D NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_= LBCC, - [NVME_CMD_WRITE_ZEROES] =3D NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_= LBCC, - [NVME_CMD_WRITE] =3D NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_= LBCC, - [NVME_CMD_READ] =3D NVME_CMD_EFF_CSUPP, - [NVME_CMD_DSM] =3D NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_= LBCC, - [NVME_CMD_COPY] =3D NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_= LBCC, - [NVME_CMD_COMPARE] =3D NVME_CMD_EFF_CSUPP, - [NVME_CMD_ZONE_APPEND] =3D NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_= LBCC, - [NVME_CMD_ZONE_MGMT_SEND] =3D NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_= LBCC, - [NVME_CMD_ZONE_MGMT_RECV] =3D NVME_CMD_EFF_CSUPP, -}; +static const uint32_t nvme_cse_iocs_none[NVME_MAX_COMMANDS]; =20 static void nvme_process_sq(void *opaque); =20 @@ -3071,17 +3053,17 @@ static uint16_t nvme_cmd_effects(NvmeCtrl *n, uint8= _t csi, uint32_t buf_len, =20 switch (NVME_CC_CSS(n->bar.cc)) { case NVME_CC_CSS_NVM: - src_iocs =3D nvme_cse_iocs_nvm; + src_iocs =3D n->iocs.nvm; /* fall through */ case NVME_CC_CSS_ADMIN_ONLY: break; case NVME_CC_CSS_CSI: switch (csi) { case NVME_CSI_NVM: - src_iocs =3D nvme_cse_iocs_nvm; + src_iocs =3D n->iocs.nvm; break; case NVME_CSI_ZONED: - src_iocs =3D nvme_cse_iocs_zoned; + src_iocs =3D n->iocs.zoned; break; } } @@ -3684,6 +3666,10 @@ static uint16_t nvme_get_feature(NvmeCtrl *n, NvmeRe= quest *req) return NVME_INVALID_FIELD | NVME_DNR; } =20 + if (!(le16_to_cpu(n->id_ctrl.oncs) & NVME_ONCS_FEATURES) && sel) { + return NVME_INVALID_FIELD | NVME_DNR; + } + if (nvme_feature_cap[fid] & NVME_FEAT_CAP_NS) { if (!nvme_nsid_valid(n, nsid) || nsid =3D=3D NVME_NSID_BROADCAST) { /* @@ -3766,6 +3752,9 @@ static uint16_t nvme_get_feature(NvmeCtrl *n, NvmeReq= uest *req) result =3D n->features.async_config; goto out; case NVME_TIMESTAMP: + if (!(le16_to_cpu(n->id_ctrl.oncs) & NVME_ONCS_TIMESTAMP)) { + return NVME_INVALID_FIELD | NVME_DNR; + } return nvme_get_feature_timestamp(n, req); default: break; @@ -3843,6 +3832,10 @@ static uint16_t nvme_set_feature(NvmeCtrl *n, NvmeRe= quest *req) =20 trace_pci_nvme_setfeat(nvme_cid(req), nsid, fid, save, dw11); =20 + if (save && !(le16_to_cpu(n->id_ctrl.oncs) & NVME_ONCS_FEATURES)) { + return NVME_INVALID_FIELD | NVME_DNR; + } + if (save && !(nvme_feature_cap[fid] & NVME_FEAT_CAP_SAVE)) { return NVME_FID_NOT_SAVEABLE | NVME_DNR; } @@ -3959,6 +3952,9 @@ static uint16_t nvme_set_feature(NvmeCtrl *n, NvmeReq= uest *req) n->features.async_config =3D dw11; break; case NVME_TIMESTAMP: + if (!(le16_to_cpu(n->id_ctrl.oncs) & NVME_ONCS_TIMESTAMP)) { + return NVME_INVALID_FIELD | NVME_DNR; + } return nvme_set_feature_timestamp(n, req); case NVME_COMMAND_SET_PROFILE: if (dw11 & 0x1ff) { @@ -4201,14 +4197,14 @@ static void __nvme_select_ns_iocs(NvmeCtrl *n, Nvme= Namespace *ns) switch (ns->csi) { case NVME_CSI_NVM: if (NVME_CC_CSS(n->bar.cc) !=3D NVME_CC_CSS_ADMIN_ONLY) { - ns->iocs =3D nvme_cse_iocs_nvm; + ns->iocs =3D n->iocs.nvm; } break; case NVME_CSI_ZONED: if (NVME_CC_CSS(n->bar.cc) =3D=3D NVME_CC_CSS_CSI) { - ns->iocs =3D nvme_cse_iocs_zoned; + ns->iocs =3D n->iocs.zoned; } else if (NVME_CC_CSS(n->bar.cc) =3D=3D NVME_CC_CSS_NVM) { - ns->iocs =3D nvme_cse_iocs_nvm; + ns->iocs =3D n->iocs.nvm; } break; } @@ -4838,6 +4834,40 @@ static void nvme_check_constraints(NvmeCtrl *n, Erro= r **errp) } } =20 +static void nvme_init_cse_iocs(NvmeCtrl *n) +{ + uint16_t oncs =3D n->params.oncs; + + n->iocs.nvm[NVME_CMD_FLUSH] =3D NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC; + n->iocs.nvm[NVME_CMD_WRITE] =3D NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC; + n->iocs.nvm[NVME_CMD_READ] =3D NVME_CMD_EFF_CSUPP; + + if (oncs & NVME_ONCS_WRITE_ZEROES) { + n->iocs.nvm[NVME_CMD_WRITE_ZEROES] =3D NVME_CMD_EFF_CSUPP | + NVME_CMD_EFF_LBCC; + } + + if (oncs & NVME_ONCS_COMPARE) { + n->iocs.nvm[NVME_CMD_COMPARE] =3D NVME_CMD_EFF_CSUPP; + } + + if (oncs & NVME_ONCS_DSM) { + n->iocs.nvm[NVME_CMD_DSM] =3D NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LB= CC; + } + + if (oncs & NVME_ONCS_COPY) { + n->iocs.nvm[NVME_CMD_COPY] =3D NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_L= BCC; + } + + memcpy(n->iocs.zoned, n->iocs.nvm, sizeof(n->iocs.nvm)); + + n->iocs.zoned[NVME_CMD_ZONE_APPEND] =3D NVME_CMD_EFF_CSUPP | + NVME_CMD_EFF_LBCC; + n->iocs.zoned[NVME_CMD_ZONE_MGMT_SEND] =3D NVME_CMD_EFF_CSUPP | + NVME_CMD_EFF_LBCC; + n->iocs.zoned[NVME_CMD_ZONE_MGMT_RECV] =3D NVME_CMD_EFF_CSUPP; +} + static void nvme_init_state(NvmeCtrl *n) { n->num_namespaces =3D NVME_MAX_NAMESPACES; @@ -4850,6 +4880,8 @@ static void nvme_init_state(NvmeCtrl *n) n->features.temp_thresh_hi =3D NVME_TEMPERATURE_WARNING; n->starttime_ms =3D qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL); n->aer_reqs =3D g_new0(NvmeRequest *, n->params.aerl + 1); + + nvme_init_cse_iocs(n); } =20 static int nvme_attach_namespace(NvmeCtrl *n, NvmeNamespace *ns, Error **e= rrp) @@ -5091,9 +5123,7 @@ static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *pc= i_dev) id->sqes =3D (0x6 << 4) | 0x6; id->cqes =3D (0x4 << 4) | 0x4; id->nn =3D cpu_to_le32(n->num_namespaces); - id->oncs =3D cpu_to_le16(NVME_ONCS_WRITE_ZEROES | NVME_ONCS_TIMESTAMP | - NVME_ONCS_FEATURES | NVME_ONCS_DSM | - NVME_ONCS_COMPARE | NVME_ONCS_COPY); + id->oncs =3D cpu_to_le16(n->params.oncs); =20 /* * NOTE: If this device ever supports a command set that does NOT use = 0x0 @@ -5239,6 +5269,9 @@ static Property nvme_props[] =3D { DEFINE_PROP_BOOL("use-intel-id", NvmeCtrl, params.use_intel_id, false), DEFINE_PROP_BOOL("legacy-cmb", NvmeCtrl, params.legacy_cmb, false), DEFINE_PROP_UINT8("zoned.zasl", NvmeCtrl, params.zasl, 0), + DEFINE_PROP_UINT16("oncs", NvmeCtrl, params.oncs, NVME_ONCS_WRITE_ZERO= ES | + NVME_ONCS_TIMESTAMP | NVME_ONCS_DSM | + NVME_ONCS_COMPARE | NVME_ONCS_FEATURES | NVME_ONCS_= COPY), DEFINE_PROP_END_OF_LIST(), }; =20 --=20 2.30.1