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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id v23sm2516474ots.63.2021.03.09.08.20.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Mar 2021 08:20:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hYJXwe4FbJfgTdVPMN7My2daIn3Bg5z6ffUixEKobJI=; b=H3usu8MFzXk95EuTUYgzbCBYkuTSnaT2kJRw72Y3R+tuSgAz56SxHuGNH7gdhC2A5X 20V3EyL2kLhB+8d6dHZjLP5ErtnVhQNws2df7nyTdpBn35sIuq6oHzv4ZgngRnSfWWYT 0vQiYV/mLk+MuGF/kc92nIWO3gV9/mu/5T5xmqp8iHJ62HIhIRukH+rkzfp2C3Ls3vbC H8y3gDXIMA+zt9iKmT1fl60kydLpCVeXYyuXzb8t4xHfQNcgLheC4UhdbcgI/UTgjnwA /EQqoipyJ0FoXdYRbdNczgGpZ+wE63xSijN99T4cNMZdeKgQOIU+tIIEABYiw1pbYWFA ilzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hYJXwe4FbJfgTdVPMN7My2daIn3Bg5z6ffUixEKobJI=; b=Vk0eCW7MqyOehGNW2ShCcWYICnet52AHZEfz83fFdxRsRHstYIY/w3qhuAxxDYuShS bJb4T0mUhB9454sSRMq621YtjDOml2icw/eYDIWuJdBhixPA7wpzeRb6UT4B8Z43dv4N Up8obOLLryOc4+rm/SbApQflaR52tej6zaOSF4kLFECZqKBme9wTDMCovvXi4DyPQ98P I5qYUm+CTBTdJXdcacBBJw39WmBMBbUYmmxM7F+W8lAJoeaaY4m43oj9tArzlSKqvoEK Y8BO6lFtySZNzDPuq1A0/33QlreHNKAqcvJPz+VGOBLqrsiMluImz+z827zmddl+Fyki C1jQ== X-Gm-Message-State: AOAM531D9DAHR21kMfi1YKY7k60li+2SUqB2VKNHpQNTD/2zDn7c2cFX untohp5X7J/7YwbhuUpbkpN94SLjKISB7clZ X-Google-Smtp-Source: ABdhPJwW6zIlJTjDzJCzNIyM/j0OVjqEKAwt2tyyNg07fSL7Qkjt4rVOmFwynm1WssghTr7WKG5VxA== X-Received: by 2002:aca:de82:: with SMTP id v124mr3481050oig.125.1615306844573; Tue, 09 Mar 2021 08:20:44 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 01/78] target/arm: Add ID_AA64ZFR0 fields and isar_feature_aa64_sve2 Date: Tue, 9 Mar 2021 08:19:24 -0800 Message-Id: <20210309162041.23124-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210309162041.23124-1-richard.henderson@linaro.org> References: <20210309162041.23124-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22e; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Will be used for SVE2 isa subset enablement. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- v2: Do not read zfr0 from kvm unless sve is available. --- target/arm/cpu.h | 16 ++++++++++++++++ target/arm/helper.c | 3 +-- target/arm/kvm64.c | 11 +++++++++++ 3 files changed, 28 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 193a49ec7f..ee92ea876e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -942,6 +942,7 @@ struct ARMCPU { uint64_t id_aa64mmfr2; uint64_t id_aa64dfr0; uint64_t id_aa64dfr1; + uint64_t id_aa64zfr0; } isar; uint64_t midr; uint32_t revidr; @@ -2029,6 +2030,16 @@ FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4) FIELD(ID_AA64DFR0, TRACEFILT, 40, 4) FIELD(ID_AA64DFR0, MTPMU, 48, 4) =20 +FIELD(ID_AA64ZFR0, SVEVER, 0, 4) +FIELD(ID_AA64ZFR0, AES, 4, 4) +FIELD(ID_AA64ZFR0, BITPERM, 16, 4) +FIELD(ID_AA64ZFR0, BFLOAT16, 20, 4) +FIELD(ID_AA64ZFR0, SHA3, 32, 4) +FIELD(ID_AA64ZFR0, SM4, 40, 4) +FIELD(ID_AA64ZFR0, I8MM, 44, 4) +FIELD(ID_AA64ZFR0, F32MM, 52, 4) +FIELD(ID_AA64ZFR0, F64MM, 56, 4) + FIELD(ID_DFR0, COPDBG, 0, 4) FIELD(ID_DFR0, COPSDBG, 4, 4) FIELD(ID_DFR0, MMAPDBG, 8, 4) @@ -4182,6 +4193,11 @@ static inline bool isar_feature_aa64_ssbs(const ARMI= SARegisters *id) return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) !=3D 0; } =20 +static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) !=3D 0; +} + /* * Feature tests for "does this exist in either 32-bit or 64-bit?" */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 904b0927cd..48c00de6ca 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7561,8 +7561,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 4, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - /* At present, only SVEver =3D=3D 0 is defined anyway. */ - .resetvalue =3D 0 }, + .resetvalue =3D cpu->isar.id_aa64zfr0 }, { .name =3D "ID_AA64PFR5_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 5, .access =3D PL1_R, .type =3D ARM_CP_CONST, diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index dff85f6db9..e8729b53fd 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -567,6 +567,17 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures = *ahcf) err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr2, ARM64_SYS_REG(3, 0, 0, 7, 2)); =20 + /* + * Before v5.1, KVM did not support SVE and did not expose + * ID_AA64ZFR0_EL1 even as RAZ. After v5.1, KVM still does + * not expose the register to "user" requests like this + * unless the host supports SVE. + */ + if (isar_feature_aa64_sve(&ahcf->isar)) { + err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, + ARM64_SYS_REG(3, 0, 0, 4, 4)); + } + /* * Note that if AArch32 support is not present in the host, * the AArch32 sysregs are present to be read, but will --=20 2.25.1