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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id s9sm3182962edd.16.2021.03.09.06.58.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Mar 2021 06:58:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3h2ByVuiQYLkvSCliAgbNV57VpJyk3eWoocPDwDsdg8=; b=WMgFyNRI8F55jyD5CEONfpd5j2lKSzvGxrBtoOOeSsD4pdbHnwf0P6TCVo5KTsUCfI Atj7pm9MXY2FFk0XP8onKVt7isdUjE4/KirtBH65TslU2wUhv9yYTWkniTK9WZcBDdqY iKK0afIJOq4f0TtVlL4W4r/kFwSNbZCm95Vfmmut0itIDcoX8zaczBaxy4+ENDocXZDY JpDdxo3DBIryERgv3KE10wZPPUoFs8VrHnO4MC1qkAPxKBSYn2FzO+AYVmqtoUzrOb5l nwJ97UGhSMExOTZN6L1oHG27v6s96q8JXJ17NE2kIUuZhjE+st17Fb89zB95mpFl+FO0 iWtw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=3h2ByVuiQYLkvSCliAgbNV57VpJyk3eWoocPDwDsdg8=; b=kwhypLsNBgEsizyW2CsEd1vDvYDnHFjH0sQk9pglKDvSSAysca6r8CRZAwSMY+zWld 5FackeW9bOEUPoWxu9ANpMgVUDsotZ0yOAokBl84yfOVx63wRDgEJuKBKGXNchnnlfuv I1nYvmgtoMDNeyUpVkaY91JelEQzke2Sbn1I8cqnRGjn0k3ESVBS/EqXzbZUpIJE1zos umxm3nS7nWPZeMM4TAMujZVH812LC/4MTpdmZg2THuP945wldHOfWtJbj8wTwA2M3OED Itm7Rk9L6umXm5nUAiJMHrFo2ERREWoC9kkCJViO2gVzTCpyqV7Nl+Lx+H80sx7vbdMd rcsQ== X-Gm-Message-State: AOAM531brK1I2Tk86Ku1KBA2IW5k6CnFRWYUqBHAHxkunKqF4sdnAKXL xY4fQVtxZ+L52LlmppB6rTk= X-Google-Smtp-Source: ABdhPJxRAoG07U3axtmUjYethmyf7yWtTSVEMr2VIG0GMeTEq+3awAlntFDuLQlk600XueskmvzRJA== X-Received: by 2002:aa7:df84:: with SMTP id b4mr4516787edy.240.1615301927879; Tue, 09 Mar 2021 06:58:47 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Aleksandar Rikalo , Jiaxun Yang , Aurelien Jarno , Fredrik Noring , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v2 22/22] target/mips: Reintroduce the R5900 CPU Date: Tue, 9 Mar 2021 15:56:53 +0100 Message-Id: <20210309145653.743937-23-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210309145653.743937-1-f4bug@amsat.org> References: <20210309145653.743937-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Now that we have the minimum prerequisites to support the R5900 CPU, we can reintroduce it. While we are reverting commit 823f2897bdd ("Disable R5900 support"), we effectively cherry-pick commit ed4f49ba9bb ("target/mips: Define the R5900 CPU"). This reverts commit 823f2897bdd78185f3ba33292a25105ba8bad1b5. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20210214175912.732946-31-f4bug@amsat.org> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/cpu-defs.c.inc | 59 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc index e03b2a998cd..1a73b5409f0 100644 --- a/target/mips/cpu-defs.c.inc +++ b/target/mips/cpu-defs.c.inc @@ -411,6 +411,65 @@ const mips_def_t mips_defs[] =3D .insn_flags =3D CPU_MIPS32R5, .mmu_type =3D MMU_TYPE_R4000, }, + { + /* + * The Toshiba TX System RISC TX79 Core Architecture manual + * + * https://wiki.qemu.org/File:C790.pdf + * + * describes the C790 processor that is a follow-up to the R5900. + * There are a few notable differences in that the R5900 FPU + * + * - is not IEEE 754-1985 compliant, + * - does not implement double format, and + * - its machine code is nonstandard. + */ + .name =3D "R5900", + .CP0_PRid =3D 0x00002E00, + /* No L2 cache, icache size 32k, dcache size 32k, uncached coheren= cy. */ + .CP0_Config0 =3D (0x3 << 9) | (0x3 << 6) | (0x2 << CP0C0_K0), + .CP0_Status_rw_bitmask =3D 0xF4C79C1F, +#ifdef CONFIG_USER_ONLY + /* + * R5900 hardware traps to the Linux kernel for IEEE 754-1985 and = LL/SC + * emulation. For user only, QEMU is the kernel, so we emulate the= traps + * by simply emulating the instructions directly. + * + * Note: Config1 is only used internally, the R5900 has only Confi= g0. + */ + .CP0_Config1 =3D (1 << CP0C1_FP) | (47 << CP0C1_MMU), + .CP0_LLAddr_rw_bitmask =3D 0xFFFFFFFF, + .CP0_LLAddr_shift =3D 4, + .CP1_fcr0 =3D (0x38 << FCR0_PRID) | (0x0 << FCR0_REV), + .CP1_fcr31 =3D 0, + .CP1_fcr31_rw_bitmask =3D 0x0183FFFF, +#else + /* + * The R5900 COP1 FPU implements single-precision floating-point + * operations but is not entirely IEEE 754-1985 compatible. In + * particular, + * + * - NaN (not a number) and +/- infinities are not supported; + * - exception mechanisms are not fully supported; + * - denormalized numbers are not supported; + * - rounding towards nearest and +/- infinities are not supported; + * - computed results usually differs in the least significant bit; + * - saturations can differ more than the least significant bit. + * + * Since only rounding towards zero is supported, the two least + * significant bits of FCR31 are hardwired to 01. + * + * FPU emulation is disabled here until it is implemented. + * + * Note: Config1 is only used internally, the R5900 has only Confi= g0. + */ + .CP0_Config1 =3D (47 << CP0C1_MMU), +#endif /* !CONFIG_USER_ONLY */ + .SEGBITS =3D 32, + .PABITS =3D 32, + .insn_flags =3D CPU_MIPS3 | INSN_R5900 | ASE_MMI, + .mmu_type =3D MMU_TYPE_R4000, + }, { /* A generic CPU supporting MIPS32 Release 6 ISA. FIXME: Support IEEE 754-2008 FP. --=20 2.26.2