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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id s13sm9551481edr.86.2021.03.09.06.58.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Mar 2021 06:58:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=y78UYhzpjwwqyIkKdZskzp+sDvMwTfmnMMTxyxcUqTQ=; b=nmv7vBPk25/FIE3RQwb38P+mL2oTue9Z/aRq236XaEdpff0zBEIb6b40lB7KZ2E2E1 CGEZm02xS0Ys4hh17VibVANImElOHitohM5QyHSWQB434UXMsk5Bo5+DASazXm8TjX2/ y2+qUedMdybuoa2lnc5yTKMg4mF83vABav1w0YzCxFBbxOJm0cfmsMFAxjkBw6HPuWDI 2cwpAIAUSteYk3228bcAdBN4dLKvLn1XoMZbGXfwqCt8MhtJ8o5by6I2/sDZsMPjJlUk 6f8h3MJ3HN06A2sT5rsJLvFD6LEV8yN2MRIKywLISm7cPQRYHnOZ4O36ZHMb6cFL9t9l CWSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=y78UYhzpjwwqyIkKdZskzp+sDvMwTfmnMMTxyxcUqTQ=; b=tTJLfwcbGP0K5lTGX/oSRa72QcRvC4ZAJWbRrn5KdL36jnSotG4ah+KwF/0NcMGBuw +pt8xgFSKgTHbCfb5E6xVT1LvBg8zPXetzTnkSopicYRRJ54hSfo/JL7Ckb2LnYknHGy E1LQ5JKeKQVG1YuiqbcoXzFMoSAxXqH30gtGQEA8uTOlKeSHsNlG1uiC/57e7cBaMqsf wWZPeY6FrGtH6cXtIC5yaUBJgftAzj4i2/t9G5NIoL57tDOKBmmSfZDmjRuGAlFRqMFd vkegT1s8AfSHcONv1vMRDYEd5w9FmM8q/vDEQKSoaBzB7vOg1neNBWUzpIpVjsUXd0wd 8BQA== X-Gm-Message-State: AOAM533mYtYmNXR9CseyiXV0BMsDsgcExL48qCiYSzYyxPq84rod7bV4 v1aTuam5d90yOXprtwQATJQ= X-Google-Smtp-Source: ABdhPJxFU24/zE7Oa6xcLXJkxjK1TuIXdvwz96wPl0C9lHXBjRfDcqP5+3ohxRFKm9aRuv68e5EL4A== X-Received: by 2002:aa7:d4d2:: with SMTP id t18mr4572526edr.342.1615301922732; Tue, 09 Mar 2021 06:58:42 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Aleksandar Rikalo , Jiaxun Yang , Aurelien Jarno , Fredrik Noring , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v2 21/22] target/mips/tx79: Move RDHWR usermode kludge to trans_SQ() Date: Tue, 9 Mar 2021 15:56:52 +0100 Message-Id: <20210309145653.743937-22-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210309145653.743937-1-f4bug@amsat.org> References: <20210309145653.743937-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Now than SQ is properly implemented, we can move the RDHWR kludge required to have usermode working with recent glibc. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- v2: { RDHWR_user } (rth) --- target/mips/tx79.decode | 5 +++- target/mips/translate.c | 56 ------------------------------------ target/mips/tx79_translate.c | 31 ++++++++++++++++++++ 3 files changed, 35 insertions(+), 57 deletions(-) diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode index f1cb7ebfa3c..4e8acb7ab9a 100644 --- a/target/mips/tx79.decode +++ b/target/mips/tx79.decode @@ -73,4 +73,7 @@ PCPYH 011100 00000 ..... ..... 11011 101001 @= rt_rd # SPECIAL =20 LQ 011110 ..... ..... ................ @ldst -SQ 011111 ..... ..... ................ @ldst +{ + RDHWR_user 011111 00000 ..... ..... 00000 111011 @rt_rd + SQ 011111 ..... ..... ................ @ldst +} diff --git a/target/mips/translate.c b/target/mips/translate.c index 0d20a0e3b84..b01022a6ad7 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1167,7 +1167,6 @@ enum { =20 enum { MMI_OPC_CLASS_MMI =3D 0x1C << 26, /* Same as OPC_SPECIAL2 */ - MMI_OPC_SQ =3D 0x1F << 26, /* Same as OPC_SPECIAL3 */ }; =20 /* @@ -24428,53 +24427,6 @@ static void decode_mmi(CPUMIPSState *env, DisasCon= text *ctx) } } =20 -static void gen_mmi_sq(DisasContext *ctx, int base, int rt, int offset) -{ - gen_reserved_instruction(ctx); /* TODO: MMI_OPC_SQ */ -} - -/* - * The TX79-specific instruction Store Quadword - * - * +--------+-------+-------+------------------------+ - * | 011111 | base | rt | offset | SQ - * +--------+-------+-------+------------------------+ - * 6 5 5 16 - * - * has the same opcode as the Read Hardware Register instruction - * - * +--------+-------+-------+-------+-------+--------+ - * | 011111 | 00000 | rt | rd | 00000 | 111011 | RDHWR - * +--------+-------+-------+-------+-------+--------+ - * 6 5 5 5 5 6 - * - * that is required, trapped and emulated by the Linux kernel. However, all - * RDHWR encodings yield address error exceptions on the TX79 since the SQ - * offset is odd. Therefore all valid SQ instructions can execute normally. - * In user mode, QEMU must verify the upper and lower 11 bits to distingui= sh - * between SQ and RDHWR, as the Linux kernel does. - */ -static void decode_mmi_sq(CPUMIPSState *env, DisasContext *ctx) -{ - int base =3D extract32(ctx->opcode, 21, 5); - int rt =3D extract32(ctx->opcode, 16, 5); - int offset =3D extract32(ctx->opcode, 0, 16); - -#ifdef CONFIG_USER_ONLY - uint32_t op1 =3D MASK_SPECIAL3(ctx->opcode); - uint32_t op2 =3D extract32(ctx->opcode, 6, 5); - - if (base =3D=3D 0 && op2 =3D=3D 0 && op1 =3D=3D OPC_RDHWR) { - int rd =3D extract32(ctx->opcode, 11, 5); - - gen_rdhwr(ctx, rt, rd, 0); - return; - } -#endif - - gen_mmi_sq(ctx, base, rt, offset); -} - #endif =20 static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx) @@ -24664,15 +24616,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, D= isasContext *ctx) decode_opc_special2_legacy(env, ctx); break; case OPC_SPECIAL3: -#if defined(TARGET_MIPS64) - if (ctx->insn_flags & INSN_R5900) { - decode_mmi_sq(env, ctx); /* MMI_OPC_SQ */ - } else { - decode_opc_special3(env, ctx); - } -#else decode_opc_special3(env, ctx); -#endif break; case OPC_REGIMM: op1 =3D MASK_REGIMM(ctx->opcode); diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c index e32c6218852..5e69783420a 100644 --- a/target/mips/tx79_translate.c +++ b/target/mips/tx79_translate.c @@ -396,6 +396,37 @@ static bool trans_SQ(DisasContext *ctx, arg_itype *a) return true; } =20 +/* + * The TX79-specific instruction Store Quadword + * + * +--------+-------+-------+------------------------+ + * | 011111 | base | rt | offset | SQ + * +--------+-------+-------+------------------------+ + * 6 5 5 16 + * + * has the same opcode as the Read Hardware Register instruction + * + * +--------+-------+-------+-------+-------+--------+ + * | 011111 | 00000 | rt | rd | 00000 | 111011 | RDHWR + * +--------+-------+-------+-------+-------+--------+ + * 6 5 5 5 5 6 + * + * that is required, trapped and emulated by the Linux kernel. However, all + * RDHWR encodings yield address error exceptions on the TX79 since the SQ + * offset is odd. Therefore all valid SQ instructions can execute normally. + * In user mode, QEMU must verify the upper and lower 11 bits to distingui= sh + * between SQ and RDHWR, as the Linux kernel does. + */ +static bool trans_RDHWR_user(DisasContext *ctx, arg_rtype *a) +{ +#if defined(CONFIG_USER_ONLY) + gen_rdhwr(ctx, a->rt, a->rd, 0); + return true; +#else + return false; +#endif +} + /* * Multiply and Divide (19 instructions) * ------------------------------------- --=20 2.26.2