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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id fi11sm8334289ejb.73.2021.03.09.06.26.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Mar 2021 06:26:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kTzOWUKGqF7Ld/iGKjPTw96gS52bnIzue7kcTaEyF0A=; b=P1E0nl4ApF344B/DEimob+BwmXQW9S6iciz3emiux8uHmIECrr+jOfxXv324ArZ/l3 5BuuX6hvFHbT9qJWtQSEbwze4CfsdP+z+PJKqQjfN0i5n6VU110tmesCMonhmBwmTajq BZeIcMu/tl5rYLi0ZcszMQ7boFmRCgTcVw4cDDnnSWUhRkMS3CdFz0/7FNcLbnisJ6rQ jl3qZDAT7XdS2PZTd0jKEJ5BlLmwTR/CCY3d7Ejzyr2l2Cc86utx0tG8mABGNwHC8Y0D P7lCO/B5OIXd1kP97nH3nr+U/huyr0a8f1mJDxoFavbC2yD9McRM4FZSuPDVaVAV4fvw RKUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=kTzOWUKGqF7Ld/iGKjPTw96gS52bnIzue7kcTaEyF0A=; b=mkAZjmobtkkQR5M//YzgcFxEhOFSHMTZ090qPKdjAFEFZCSWS6VeT8kqpo0sarEXlF TjIeauVyjiL/dB4/dHnTOu5cCsA9xMc8FARCjDz7UIBGdb4Hb8VJL4lItqRXRtOUy/us s+UzE3jN+IAudXk1mD05NDYemj1d6ayTYDfdKBRnkhkdYX44GbZtFcCAdlL6JzKVYqMI RzDsjCOVxD8Mduheckds/6fjRuW77e2UXUkFws0uw4IHlHRYgdsQsUTFcpvrtOCiKkwE yDFD97FVfutR2m6YJUph9kFZkqTEEtM/NWSI4x6dQ2gA3noZkqP9wn2x1JhZ4shJczdO LP6w== X-Gm-Message-State: AOAM531YIZSC7E/snsX2CCge1rc0EhiBHNOqOHaIH1nvFBxqjUliCanB Ps6c6ALiPCObI8I4BeemcTd8I9bIXIk= X-Google-Smtp-Source: ABdhPJw1XqhAvLADOuBl1+YA1ITDwzXbDHzpgnzAGtL0saGD7JJTelhu2DDZ9z6mM6SVcOgEnV8Sew== X-Received: by 2002:a17:906:3849:: with SMTP id w9mr20939996ejc.7.1615300013215; Tue, 09 Mar 2021 06:26:53 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno , Jiaxun Yang , BALATON Zoltan Subject: [PATCH RESEND 4/6] hw/mips/gt64xxx: Rename trace events related to interrupt registers Date: Tue, 9 Mar 2021 15:26:28 +0100 Message-Id: <20210309142630.728014-5-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210309142630.728014-1-f4bug@amsat.org> References: <20210309142630.728014-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) We want to trace all register accesses. First rename the current gt64120_read / gt64120_write events with '_intreg' suffix, as they are restricted to interrupt registers. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: BALATON Zoltan --- hw/mips/gt64xxx_pci.c | 16 ++++++++-------- hw/mips/trace-events | 4 ++-- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index 8ff31380d74..9a12d00d1e1 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -642,19 +642,19 @@ static void gt64120_writel(void *opaque, hwaddr addr, /* not really implemented */ s->regs[saddr] =3D ~(~(s->regs[saddr]) | ~(val & 0xfffffffe)); s->regs[saddr] |=3D !!(s->regs[saddr] & 0xfffffffe); - trace_gt64120_write("INTRCAUSE", size, val); + trace_gt64120_write_intreg("INTRCAUSE", size, val); break; case GT_INTRMASK: s->regs[saddr] =3D val & 0x3c3ffffe; - trace_gt64120_write("INTRMASK", size, val); + trace_gt64120_write_intreg("INTRMASK", size, val); break; case GT_PCI0_ICMASK: s->regs[saddr] =3D val & 0x03fffffe; - trace_gt64120_write("ICMASK", size, val); + trace_gt64120_write_intreg("ICMASK", size, val); break; case GT_PCI0_SERR0MASK: s->regs[saddr] =3D val & 0x0000003f; - trace_gt64120_write("SERR0MASK", size, val); + trace_gt64120_write_intreg("SERR0MASK", size, val); break; =20 /* Reserved when only PCI_0 is configured. */ @@ -929,19 +929,19 @@ static uint64_t gt64120_readl(void *opaque, /* Interrupts */ case GT_INTRCAUSE: val =3D s->regs[saddr]; - trace_gt64120_read("INTRCAUSE", size, val); + trace_gt64120_read_intreg("INTRCAUSE", size, val); break; case GT_INTRMASK: val =3D s->regs[saddr]; - trace_gt64120_read("INTRMASK", size, val); + trace_gt64120_read_intreg("INTRMASK", size, val); break; case GT_PCI0_ICMASK: val =3D s->regs[saddr]; - trace_gt64120_read("ICMASK", size, val); + trace_gt64120_read_intreg("ICMASK", size, val); break; case GT_PCI0_SERR0MASK: val =3D s->regs[saddr]; - trace_gt64120_read("SERR0MASK", size, val); + trace_gt64120_read_intreg("SERR0MASK", size, val); break; =20 /* Reserved when only PCI_0 is configured. */ diff --git a/hw/mips/trace-events b/hw/mips/trace-events index 915139d9811..b7e934c3933 100644 --- a/hw/mips/trace-events +++ b/hw/mips/trace-events @@ -1,4 +1,4 @@ # gt64xxx_pci.c -gt64120_read(const char *regname, unsigned size, uint64_t value) "gt64120 = read %s size:%u value:0x%08" PRIx64 -gt64120_write(const char *regname, unsigned size, uint64_t value) "gt64120= write %s size:%u value:0x%08" PRIx64 +gt64120_read_intreg(const char *regname, unsigned size, uint64_t value) "g= t64120 read %s size:%u value:0x%08" PRIx64 +gt64120_write_intreg(const char *regname, unsigned size, uint64_t value) "= gt64120 write %s size:%u value:0x%08" PRIx64 gt64120_isd_remap(uint64_t from_length, uint64_t from_addr, uint64_t to_le= ngth, uint64_t to_addr) "ISD: 0x%08" PRIx64 "@0x%08" PRIx64 " -> 0x%08" PRI= x64 "@0x%08" PRIx64 --=20 2.26.2