From nobody Wed Nov 19 10:02:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1615300966; cv=none; d=zohomail.com; s=zohoarc; b=RuiGmAU9w3/oabks3gXUuGrIhiC1rGJsqsyUYbpKI1i9hEwd+bQyKP1cX/nzlSKffcUaqCrVAbrGlrOaIyw5LzT37ioXpwRWEP/sMg8sCkDB7MYwmzp0q0/LUyMWFbEcPZcDzg9+V0rd/VUQXIhg1EVERDS1URMtM7NWQEe1BFE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615300966; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=n9OHRPiIgNNSQjRqZcJ3Q/FYJblN7to23uT95DZq1cQ=; b=c/D8XmRXYzy9WIIuNsLjzbI2qR6qO+09gCRyUS1Nii+rlOJNp6W8cmu28lOQnc+dISKwp9gaXFD0PwHZNs9bIaUaj7GVoBRx9AlMNaw/8PC7sTqSyxA1dAq44OR7a5xgVDbVwnhOMGCO1Cfuiy7HQ6J35Edy7qNGTmNdWkYjzFc= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1615300966351655.2726893882444; Tue, 9 Mar 2021 06:42:46 -0800 (PST) Received: from localhost ([::1]:52532 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lJdZN-0004Jk-9a for importer@patchew.org; Tue, 09 Mar 2021 09:42:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41780) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lJdJG-0003MN-AP for qemu-devel@nongnu.org; Tue, 09 Mar 2021 09:26:06 -0500 Received: from mx2.suse.de ([195.135.220.15]:45186) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lJdJE-0005bT-6v for qemu-devel@nongnu.org; Tue, 09 Mar 2021 09:26:05 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id B8FFEAE6E; Tue, 9 Mar 2021 14:25:52 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [RFC v5 12/36] target/arm: only perform TCG cpu and machine inits if TCG enabled Date: Tue, 9 Mar 2021 15:25:20 +0100 Message-Id: <20210309142544.5020-13-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210309142544.5020-1-cfontana@suse.de> References: <20210309142544.5020-1-cfontana@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Roman Bolshakov , Claudio Fontana , Eduardo Habkost , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" of note, cpreg lists were previously initialized by TCG first, and then thrown away and replaced with the data coming from KVM. Now we just initialize once, either for TCG or for KVM. Signed-off-by: Claudio Fontana --- target/arm/cpu.c | 32 ++++++++++++++++++-------------- target/arm/kvm.c | 18 +++++++++--------- target/arm/machine.c | 20 +++++++++++++------- 3 files changed, 40 insertions(+), 30 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 7a21944d43..88e866cc8f 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -436,9 +436,11 @@ static void arm_cpu_reset(DeviceState *dev) } #endif =20 - hw_breakpoint_update_all(cpu); - hw_watchpoint_update_all(cpu); - arm_rebuild_hflags(env); + if (tcg_enabled()) { + hw_breakpoint_update_all(cpu); + hw_watchpoint_update_all(cpu); + arm_rebuild_hflags(env); + } } =20 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, @@ -1319,6 +1321,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) } } =20 +#ifdef CONFIG_TCG { uint64_t scale; =20 @@ -1344,7 +1347,8 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) cpu->gt_timer[GTIMER_HYPVIRT] =3D timer_new(QEMU_CLOCK_VIRTUAL, sc= ale, arm_gt_hvtimer_cb, cpu); } -#endif +#endif /* CONFIG_TCG */ +#endif /* !CONFIG_USER_ONLY */ =20 cpu_exec_realizefn(cs, &local_err); if (local_err !=3D NULL) { @@ -1645,17 +1649,16 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) unset_feature(env, ARM_FEATURE_PMU); } if (arm_feature(env, ARM_FEATURE_PMU)) { - pmu_init(cpu); - - if (!kvm_enabled()) { + if (tcg_enabled()) { + pmu_init(cpu); arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); - } =20 #ifndef CONFIG_USER_ONLY - cpu->pmu_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_= cb, - cpu); + cpu->pmu_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_ti= mer_cb, + cpu); #endif + } } else { cpu->isar.id_aa64dfr0 =3D FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0); @@ -1738,10 +1741,11 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) set_feature(env, ARM_FEATURE_VBAR); } =20 - register_cp_regs_for_features(cpu); - arm_cpu_register_gdb_regs_for_features(cpu); - - init_cpreg_list(cpu); + if (tcg_enabled()) { + register_cp_regs_for_features(cpu); + arm_cpu_register_gdb_regs_for_features(cpu); + init_cpreg_list(cpu); + } =20 #ifndef CONFIG_USER_ONLY MachineState *ms =3D MACHINE(qdev_get_machine()); diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 00e124c812..e04aa7281a 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -429,9 +429,11 @@ static uint64_t *kvm_arm_get_cpreg_ptr(ARMCPU *cpu, ui= nt64_t regidx) return &cpu->cpreg_values[res - cpu->cpreg_indexes]; } =20 -/* Initialize the ARMCPU cpreg list according to the kernel's - * definition of what CPU registers it knows about (and throw away - * the previous TCG-created cpreg list). +/* + * Initialize the ARMCPU cpreg list according to the kernel's + * definition of what CPU registers it knows about. + * + * The parallel for TCG is init_cpreg_list() in tcg/ */ int kvm_arm_init_cpreg_list(ARMCPU *cpu) { @@ -473,12 +475,10 @@ int kvm_arm_init_cpreg_list(ARMCPU *cpu) arraylen++; } =20 - cpu->cpreg_indexes =3D g_renew(uint64_t, cpu->cpreg_indexes, arraylen); - cpu->cpreg_values =3D g_renew(uint64_t, cpu->cpreg_values, arraylen); - cpu->cpreg_vmstate_indexes =3D g_renew(uint64_t, cpu->cpreg_vmstate_in= dexes, - arraylen); - cpu->cpreg_vmstate_values =3D g_renew(uint64_t, cpu->cpreg_vmstate_val= ues, - arraylen); + cpu->cpreg_indexes =3D g_new(uint64_t, arraylen); + cpu->cpreg_values =3D g_new(uint64_t, arraylen); + cpu->cpreg_vmstate_indexes =3D g_new(uint64_t, arraylen); + cpu->cpreg_vmstate_values =3D g_new(uint64_t, arraylen); cpu->cpreg_array_len =3D arraylen; cpu->cpreg_vmstate_array_len =3D arraylen; =20 diff --git a/target/arm/machine.c b/target/arm/machine.c index e568662cca..2982e8d7f4 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -2,6 +2,7 @@ #include "cpu.h" #include "qemu/error-report.h" #include "sysemu/kvm.h" +#include "sysemu/tcg.h" #include "kvm_arm.h" #include "internals.h" #include "migration/cpu.h" @@ -635,7 +636,7 @@ static int cpu_pre_save(void *opaque) { ARMCPU *cpu =3D opaque; =20 - if (!kvm_enabled()) { + if (tcg_enabled()) { pmu_op_start(&cpu->env); } =20 @@ -670,7 +671,7 @@ static int cpu_post_save(void *opaque) { ARMCPU *cpu =3D opaque; =20 - if (!kvm_enabled()) { + if (tcg_enabled()) { pmu_op_finish(&cpu->env); } =20 @@ -689,7 +690,7 @@ static int cpu_pre_load(void *opaque) */ env->irq_line_state =3D UINT32_MAX; =20 - if (!kvm_enabled()) { + if (tcg_enabled()) { pmu_op_start(&cpu->env); } =20 @@ -759,13 +760,13 @@ static int cpu_post_load(void *opaque, int version_id) } } =20 - hw_breakpoint_update_all(cpu); - hw_watchpoint_update_all(cpu); + if (tcg_enabled()) { + hw_breakpoint_update_all(cpu); + hw_watchpoint_update_all(cpu); =20 - if (!kvm_enabled()) { pmu_op_finish(&cpu->env); + arm_rebuild_hflags(&cpu->env); } - arm_rebuild_hflags(&cpu->env); =20 return 0; } @@ -815,8 +816,13 @@ const VMStateDescription vmstate_arm_cpu =3D { VMSTATE_UINT32(env.exception.syndrome, ARMCPU), VMSTATE_UINT32(env.exception.fsr, ARMCPU), VMSTATE_UINT64(env.exception.vaddress, ARMCPU), +#ifdef CONFIG_TCG VMSTATE_TIMER_PTR(gt_timer[GTIMER_PHYS], ARMCPU), VMSTATE_TIMER_PTR(gt_timer[GTIMER_VIRT], ARMCPU), +#else + VMSTATE_UNUSED(sizeof(QEMUTimer *)), + VMSTATE_UNUSED(sizeof(QEMUTimer *)), +#endif /* CONFIG_TCG */ { .name =3D "power_state", .version_id =3D 0, --=20 2.26.2