From nobody Fri Dec 19 06:18:32 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1615296069; cv=none; d=zohomail.com; s=zohoarc; b=UuiAkJkdsSJKNWofCGDbDid0Pe2rwEDFIWl7T5x/GIp97n3ozmJIaU4+yRcibZcbHxF/vEZDUMS5NhdstRKfsKxcm+S8RfqMap3uSt4KZSu0OTNoR2tmV1AW7b8Ed9sCBuAyvI67QR4GR+2vJuoMxjc0CuuK15bygfv3Laf3bBQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615296069; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=fna6enZXAYFfcesA62niTMHmMfq8+njy85nCkvdbQ8Q=; b=iN69nSwDjl1EsOUsZEZtw/Id0QsDX8xOs+JdrwMqGn3aa3NYR0yi4oK/k3+U7eB/faem2T5S2UfOBekDSYwMqKFUFRsC5jHUX4nKtgt+E18t8ytJNQUpag4ionG/jPIZ1DlF6MnmmaDQMqS/QV5Kxn2Rv9Mpi5E4HuBC+gsq8ck= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1615296069371338.367850140311; Tue, 9 Mar 2021 05:21:09 -0800 (PST) Received: from localhost ([::1]:48638 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lJcIO-0003sk-92 for importer@patchew.org; Tue, 09 Mar 2021 08:21:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43906) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lJcEW-00025v-QS; Tue, 09 Mar 2021 08:17:09 -0500 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:37838) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lJcER-0007AZ-Qj; Tue, 09 Mar 2021 08:17:08 -0500 Received: from pps.filterd (m0127361.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 129D3WFe117548; Tue, 9 Mar 2021 08:16:48 -0500 Received: from ppma04fra.de.ibm.com (6a.4a.5195.ip4.static.sl-reverse.com [149.81.74.106]) by mx0a-001b2d01.pphosted.com with ESMTP id 375wcm9ca6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 09 Mar 2021 08:16:47 -0500 Received: from pps.filterd (ppma04fra.de.ibm.com [127.0.0.1]) by ppma04fra.de.ibm.com (8.16.0.43/8.16.0.43) with SMTP id 129DBeCl023362; Tue, 9 Mar 2021 13:16:46 GMT Received: from b06cxnps4075.portsmouth.uk.ibm.com (d06relay12.portsmouth.uk.ibm.com [9.149.109.197]) by ppma04fra.de.ibm.com with ESMTP id 3768v0r0w9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 09 Mar 2021 13:16:46 +0000 Received: from d06av24.portsmouth.uk.ibm.com (d06av24.portsmouth.uk.ibm.com [9.149.105.60]) by b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 129DGhSW55247346 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 9 Mar 2021 13:16:43 GMT Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C842642047; Tue, 9 Mar 2021 13:16:43 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8C94D42045; Tue, 9 Mar 2021 13:16:43 +0000 (GMT) Received: from smtp.tlslab.ibm.com (unknown [9.101.4.1]) by d06av24.portsmouth.uk.ibm.com (Postfix) with SMTP; Tue, 9 Mar 2021 13:16:43 +0000 (GMT) Received: from yukon.ibmuc.com (unknown [9.171.48.251]) by smtp.tlslab.ibm.com (Postfix) with ESMTP id E9B8C220270; Tue, 9 Mar 2021 14:16:42 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: Peter Maydell Subject: [PULL 1/7] arm/ast2600: Fix SMP booting with -kernel Date: Tue, 9 Mar 2021 14:16:35 +0100 Message-Id: <20210309131641.2709380-2-clg@kaod.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210309131641.2709380-1-clg@kaod.org> References: <20210309131641.2709380-1-clg@kaod.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761 definitions=2021-03-09_11:2021-03-08, 2021-03-09 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 impostorscore=0 spamscore=0 suspectscore=0 phishscore=0 adultscore=0 bulkscore=0 mlxscore=0 clxscore=1034 priorityscore=1501 mlxlogscore=856 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2103090064 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=148.163.158.5; envelope-from=clg@kaod.org; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-arm@nongnu.org, qemu-devel@nongnu.org, Joel Stanley Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Joel Stanley The ast2600 machines do not have PSCI firmware, so this property should have never been set. Removing this node fixes SMP booting Linux kernels that have PSCI enabled, as Linux fails to find PSCI in the device tree and falls back to the soc-specific method for enabling secondary CPUs. The comment is out of date as Qemu has supported -kernel booting since 9bb6d14081ce ("aspeed: Add boot stub for smp booting"), in v5.1. Fixes: f25c0ae1079d ("aspeed/soc: Add AST2600 support") Signed-off-by: Joel Stanley Reviewed-by: C=C3=A9dric Le Goater Tested-by: C=C3=A9dric Le Goater Message-Id: <20210303010505.635621-1-joel@jms.id.au> Signed-off-by: C=C3=A9dric Le Goater --- hw/arm/aspeed_ast2600.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index bf31ca351feb..49b00763864c 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -241,8 +241,6 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev= , Error **errp) =20 /* CPU */ for (i =3D 0; i < sc->num_cpus; i++) { - object_property_set_int(OBJECT(&s->cpu[i]), "psci-conduit", - QEMU_PSCI_CONDUIT_SMC, &error_abort); if (sc->num_cpus > 1) { object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar", ASPEED_A7MPCORE_ADDR, &error_abort); @@ -253,11 +251,6 @@ static void aspeed_soc_ast2600_realize(DeviceState *de= v, Error **errp) object_property_set_int(OBJECT(&s->cpu[i]), "cntfrq", 1125000000, &error_abort); =20 - /* - * TODO: the secondary CPUs are started and a boot helper - * is needed when using -kernel - */ - if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) { return; } --=20 2.26.2 From nobody Fri Dec 19 06:18:32 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1615296783; cv=none; d=zohomail.com; s=zohoarc; b=MP2r6OrNxytg+QCytNoczO/V1dLEj9agpOW8J2EqDWHQ1RsMuHoZqIrnENsGsgFeVdVbLZjEbSQg2DG496a4Ny5yxNbYGWnM024fPCf75kDNkYiOnif9Yi2MwuAbmA737ZXvpemIo7ocLWvZ6hD+MJXFQyN6GsBdj5pDHcXJBpY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615296783; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=a/EomKl5QhAdgZW+JQ/w4ti663V7vNUdTgU9TqBqEVw=; b=ZyDpaZ2eW74KrTxkrupw+TKc4Wvk3dS8yi9aR2kI08gpSJvMQ3pvkEk7f6iW4tnB3A73c/v8vyhM2YcSEkey2GnrSVJxiSEGpTEvCEeJty/nhorBxjUn2dlqOnEP146+FlZlQbN++OBTElUdRV5jSgbMI+q324jabAZfLYhIMHw= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1615296783393669.6731412785447; Tue, 9 Mar 2021 05:33:03 -0800 (PST) Received: from localhost ([::1]:51100 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lJcTu-0000OU-7g for importer@patchew.org; Tue, 09 Mar 2021 08:33:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43884) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lJcEV-00025n-Nj; Tue, 09 Mar 2021 08:17:09 -0500 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:60196) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lJcEQ-000762-DH; Tue, 09 Mar 2021 08:17:07 -0500 Received: from pps.filterd (m0098393.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 129D3lJE087316; Tue, 9 Mar 2021 08:16:49 -0500 Received: from ppma03fra.de.ibm.com (6b.4a.5195.ip4.static.sl-reverse.com [149.81.74.107]) by mx0a-001b2d01.pphosted.com with ESMTP id 375wet2v5v-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 09 Mar 2021 08:16:49 -0500 Received: from pps.filterd (ppma03fra.de.ibm.com [127.0.0.1]) by ppma03fra.de.ibm.com (8.16.0.43/8.16.0.43) with SMTP id 129D7v8i029541; Tue, 9 Mar 2021 13:16:47 GMT Received: from b06cxnps4076.portsmouth.uk.ibm.com (d06relay13.portsmouth.uk.ibm.com [9.149.109.198]) by ppma03fra.de.ibm.com with ESMTP id 3768mpr130-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 09 Mar 2021 13:16:46 +0000 Received: from b06wcsmtp001.portsmouth.uk.ibm.com (b06wcsmtp001.portsmouth.uk.ibm.com [9.149.105.160]) by b06cxnps4076.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 129DGiEH33096066 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 9 Mar 2021 13:16:44 GMT Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 55688A4054; Tue, 9 Mar 2021 13:16:44 +0000 (GMT) Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 195B0A405B; Tue, 9 Mar 2021 13:16:44 +0000 (GMT) Received: from smtp.tlslab.ibm.com (unknown [9.101.4.1]) by b06wcsmtp001.portsmouth.uk.ibm.com (Postfix) with SMTP; Tue, 9 Mar 2021 13:16:44 +0000 (GMT) Received: from yukon.ibmuc.com (unknown [9.171.48.251]) by smtp.tlslab.ibm.com (Postfix) with ESMTP id 76D9922025C; Tue, 9 Mar 2021 14:16:43 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: Peter Maydell Subject: [PULL 2/7] hw/arm/aspeed: Fix location of firmware images in documentation Date: Tue, 9 Mar 2021 14:16:36 +0100 Message-Id: <20210309131641.2709380-3-clg@kaod.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210309131641.2709380-1-clg@kaod.org> References: <20210309131641.2709380-1-clg@kaod.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761 definitions=2021-03-09_11:2021-03-08, 2021-03-09 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 mlxscore=0 spamscore=0 bulkscore=0 impostorscore=0 clxscore=1034 lowpriorityscore=0 malwarescore=0 adultscore=0 priorityscore=1501 mlxlogscore=999 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2103090064 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=148.163.156.1; envelope-from=clg@kaod.org; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: 1 X-Spam_score: 0.1 X-Spam_bar: / X-Spam_report: (0.1 / 5.0 requ) BAYES_00=-1.9, PDS_OTHER_BAD_TLD=1.999, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, Joel Stanley , qemu-devel@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Firmware images can be found on the OpenBMC jenkins site and on the OpenBMC GitHub release page. Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: Joel Stanley Message-Id: <20210303072743.1551329-1-clg@kaod.org> Signed-off-by: C=C3=A9dric Le Goater --- docs/system/arm/aspeed.rst | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst index 690bada7842b..8972aa3f7bbe 100644 --- a/docs/system/arm/aspeed.rst +++ b/docs/system/arm/aspeed.rst @@ -72,18 +72,22 @@ Missing devices Boot options ------------ =20 -The Aspeed machines can be started using the -kernel option to load a -Linux kernel or from a firmware image which can be downloaded from the -OpenPOWER jenkins : +The Aspeed machines can be started using the ``-kernel`` option to +load a Linux kernel or from a firmware. Images can be downloaded from +the OpenBMC jenkins : =20 - https://openpower.xyz/ + https://jenkins.openbmc.org/job/ci-openbmc/lastSuccessfulBuild/distro= =3Dubuntu,label=3Ddocker-builder + +or directly from the OpenBMC GitHub release repository : + + https://github.com/openbmc/openbmc/releases =20 The image should be attached as an MTD drive. Run : =20 .. code-block:: bash =20 $ qemu-system-arm -M romulus-bmc -nic user \ - -drive file=3Dflash-romulus,format=3Draw,if=3Dmtd -nographic + -drive file=3Dobmc-phosphor-image-romulus.static.mtd,format=3Draw,if=3Dmt= d -nographic =20 Options specific to Aspeed machines are : =20 --=20 2.26.2 From nobody Fri Dec 19 06:18:32 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1615296283; cv=none; d=zohomail.com; s=zohoarc; b=Fy44d/exYqRiY5AWVCXV/4Scl358LbgpI8ArXCH4YfibUKeVCOmAL/ys9GiRL8KmCXE12NP4u9EDIw0b07V7LspRwLjp2/i/FSAkCCWspB3E+9AjV8IGw2k4W9373riQMHdYZzRSbs95h4oYaFR/4mylNOtLwlTcIWWRd+Z61CE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615296283; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=AbWDEZnJjRwLmJ+zWeNL+JW6mXQc0yuliSDIlXIG6jI=; b=enXUIHvPKbftWa2E3qQ0rxapbXXTQMh8mO7Jiuph92v0dkmJPzIlbyggwch/0068+INRJ9WlIruCOX3wGDAI20LImWW2B5LBcmF2jDPQDlc/NIDozUuCHzu7pZklwjVNWrGsgDLfpHN8D0LSbXWAvUivyopP1HoR8iiVNhW4PR0= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 161529628367266.94578246622189; Tue, 9 Mar 2021 05:24:43 -0800 (PST) Received: from localhost ([::1]:57208 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lJcLq-0007no-Fw for importer@patchew.org; Tue, 09 Mar 2021 08:24:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43886) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lJcEV-00025o-Oa; Tue, 09 Mar 2021 08:17:09 -0500 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:36122) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lJcER-00079s-Gh; Tue, 09 Mar 2021 08:17:07 -0500 Received: from pps.filterd (m0187473.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 129D3qog087193; Tue, 9 Mar 2021 08:16:49 -0500 Received: from ppma03ams.nl.ibm.com (62.31.33a9.ip4.static.sl-reverse.com [169.51.49.98]) by mx0a-001b2d01.pphosted.com with ESMTP id 375wfksmqu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 09 Mar 2021 08:16:49 -0500 Received: from pps.filterd (ppma03ams.nl.ibm.com [127.0.0.1]) by ppma03ams.nl.ibm.com (8.16.0.43/8.16.0.43) with SMTP id 129D8oQq007518; Tue, 9 Mar 2021 13:16:47 GMT Received: from b06avi18626390.portsmouth.uk.ibm.com (b06avi18626390.portsmouth.uk.ibm.com [9.149.26.192]) by ppma03ams.nl.ibm.com with ESMTP id 3768t4g1q3-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 09 Mar 2021 13:16:47 +0000 Received: from d06av23.portsmouth.uk.ibm.com (d06av23.portsmouth.uk.ibm.com [9.149.105.59]) by b06avi18626390.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 129DGTbT24904152 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 9 Mar 2021 13:16:29 GMT Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D97E1A4055; Tue, 9 Mar 2021 13:16:44 +0000 (GMT) Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9DCCEA404D; Tue, 9 Mar 2021 13:16:44 +0000 (GMT) Received: from smtp.tlslab.ibm.com (unknown [9.101.4.1]) by d06av23.portsmouth.uk.ibm.com (Postfix) with SMTP; Tue, 9 Mar 2021 13:16:44 +0000 (GMT) Received: from yukon.ibmuc.com (unknown [9.171.48.251]) by smtp.tlslab.ibm.com (Postfix) with ESMTP id 060DE220270; Tue, 9 Mar 2021 14:16:43 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: Peter Maydell Subject: [PULL 3/7] hw/arm: ast2600: Force a multiple of 32 of IRQs for the GIC Date: Tue, 9 Mar 2021 14:16:37 +0100 Message-Id: <20210309131641.2709380-4-clg@kaod.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210309131641.2709380-1-clg@kaod.org> References: <20210309131641.2709380-1-clg@kaod.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761 definitions=2021-03-09_11:2021-03-08, 2021-03-09 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 clxscore=1034 mlxscore=0 mlxlogscore=573 spamscore=0 suspectscore=0 lowpriorityscore=0 phishscore=0 adultscore=0 bulkscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2103090064 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=148.163.156.1; envelope-from=clg@kaod.org; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jeffery , qemu-arm@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Andrew Jeffery This appears to be a requirement of the GIC model. The AST2600 allocates 197 GIC IRQs, which we will adjust shortly. Signed-off-by: Andrew Jeffery Reviewed-by: C=C3=A9dric Le Goater Message-Id: <20210302014317.915120-2-andrew@aj.id.au> Signed-off-by: C=C3=A9dric Le Goater --- hw/arm/aspeed_ast2600.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index 49b00763864c..3d9e78fcc6b7 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -65,7 +65,7 @@ static const hwaddr aspeed_soc_ast2600_memmap[] =3D { =20 #define ASPEED_A7MPCORE_ADDR 0x40460000 =20 -#define ASPEED_SOC_AST2600_MAX_IRQ 128 +#define AST2600_MAX_IRQ 128 =20 /* Shared Peripheral Interrupt values below are offset by -32 from datashe= et */ static const int aspeed_soc_ast2600_irqmap[] =3D { @@ -260,7 +260,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev= , Error **errp) object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", sc->num_cpus, &error_abort); object_property_set_int(OBJECT(&s->a7mpcore), "num-irq", - ASPEED_SOC_AST2600_MAX_IRQ + GIC_INTERNAL, + ROUND_UP(AST2600_MAX_IRQ + GIC_INTERNAL, 32), &error_abort); =20 sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort); --=20 2.26.2 From nobody Fri Dec 19 06:18:32 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1615296499; cv=none; d=zohomail.com; s=zohoarc; b=CPZAeZ1BLgujyb2zh9s1CP9YyEml6YgYOxb49MWh5IHYoR9gKVVAda/He9ZovXi6v5ATXohl0HDbxysoUWgIBEc5wYvSN7SBCyecgcMN7w6k/Dm7Evl/KEoz/W3EuCRFYdwrSeHCHw7RY7l28CKSoUNBmfOFwCLCDoIP0iUd7Gw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615296499; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=fHCxmJtQHvkTgTp2iyXU04T5luc0fbSW5c1V58D6FRM=; b=U1R7IWRDtjPM8vQXhgwroSZL7jEjw/rZYo93NSMmYXAAEKGf7YR0xyU+Rx6nS5RyTVn3ePQ1Qy1Fvk/Jwoggb4w9R3ywDj1Psk9XWs6q11L+eXzbRGMqY8FXHFXe3eSAm34X0OMtMlBfdoh/9iDMe8ueo1GEOKwptnE0oMmZewI= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1615296499969370.8212249286112; Tue, 9 Mar 2021 05:28:19 -0800 (PST) Received: from localhost ([::1]:36762 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lJcPK-0002oe-Sp for importer@patchew.org; Tue, 09 Mar 2021 08:28:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44030) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lJcEe-00027x-IG; Tue, 09 Mar 2021 08:17:17 -0500 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:63436) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lJcEZ-0007DB-6L; Tue, 09 Mar 2021 08:17:15 -0500 Received: from pps.filterd (m0098409.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 129D2nbR098669; Tue, 9 Mar 2021 08:16:50 -0500 Received: from ppma02fra.de.ibm.com (47.49.7a9f.ip4.static.sl-reverse.com [159.122.73.71]) by mx0a-001b2d01.pphosted.com with ESMTP id 37640j2dra-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 09 Mar 2021 08:16:50 -0500 Received: from pps.filterd (ppma02fra.de.ibm.com [127.0.0.1]) by ppma02fra.de.ibm.com (8.16.0.43/8.16.0.43) with SMTP id 129DBJUG029946; Tue, 9 Mar 2021 13:16:48 GMT Received: from b06cxnps3075.portsmouth.uk.ibm.com (d06relay10.portsmouth.uk.ibm.com [9.149.109.195]) by ppma02fra.de.ibm.com with ESMTP id 3768mv81a1-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 09 Mar 2021 13:16:48 +0000 Received: from d06av25.portsmouth.uk.ibm.com (d06av25.portsmouth.uk.ibm.com [9.149.105.61]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 129DGjxE39321936 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 9 Mar 2021 13:16:45 GMT Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 84D6011C04A; Tue, 9 Mar 2021 13:16:45 +0000 (GMT) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 42A9E11C04C; Tue, 9 Mar 2021 13:16:45 +0000 (GMT) Received: from smtp.tlslab.ibm.com (unknown [9.101.4.1]) by d06av25.portsmouth.uk.ibm.com (Postfix) with SMTP; Tue, 9 Mar 2021 13:16:45 +0000 (GMT) Received: from yukon.ibmuc.com (unknown [9.171.48.251]) by smtp.tlslab.ibm.com (Postfix) with ESMTP id 8BBB722025C; Tue, 9 Mar 2021 14:16:44 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: Peter Maydell Subject: [PULL 4/7] hw/arm: ast2600: Set AST2600_MAX_IRQ to value from datasheet Date: Tue, 9 Mar 2021 14:16:38 +0100 Message-Id: <20210309131641.2709380-5-clg@kaod.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210309131641.2709380-1-clg@kaod.org> References: <20210309131641.2709380-1-clg@kaod.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761 definitions=2021-03-09_11:2021-03-08, 2021-03-09 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 mlxlogscore=391 clxscore=1034 spamscore=0 impostorscore=0 mlxscore=0 suspectscore=0 phishscore=0 lowpriorityscore=0 bulkscore=0 priorityscore=1501 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2103090064 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=148.163.156.1; envelope-from=clg@kaod.org; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jeffery , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-arm@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Andrew Jeffery The datasheet says we have 197 IRQs allocated, and we need more than 128 to describe IRQs from LPC devices. Raise the value now to allow modelling of the LPC devices. Signed-off-by: Andrew Jeffery Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: C=C3=A9dric Le Goater Message-Id: <20210302014317.915120-3-andrew@aj.id.au> Signed-off-by: C=C3=A9dric Le Goater --- hw/arm/aspeed_ast2600.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index 3d9e78fcc6b7..1dc56ce4781c 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -65,7 +65,7 @@ static const hwaddr aspeed_soc_ast2600_memmap[] =3D { =20 #define ASPEED_A7MPCORE_ADDR 0x40460000 =20 -#define AST2600_MAX_IRQ 128 +#define AST2600_MAX_IRQ 197 =20 /* Shared Peripheral Interrupt values below are offset by -32 from datashe= et */ static const int aspeed_soc_ast2600_irqmap[] =3D { --=20 2.26.2 From nobody Fri Dec 19 06:18:32 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1615296623; cv=none; d=zohomail.com; s=zohoarc; b=M5riO1NWE7c6tKqqjRrHrmAR6x70sqski+CBUAzUuNl58Ac5x4/pop23UyPn9gi8cXUfOGX2Zylfjyp4oW/14jHe96ca29gFcmEbDw8Z1WfZZfRGkqZ8WYhOmqPYjIEslYvGFQVW0mQjvIm5sM0RS+Tl20sUVdb1v8T4i/zWpBw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615296623; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=9z4p8bMRH3z4zweIHhWpq5SrpEvw5xtcjhGxb/Uoulk=; b=IT3nKnExRSi7s/5iGc8dtGn4T2uJuhNx8zDR3+osQAWAdbPjF2Xs+Kn7jzj1NhVQY0WRJXONmcVZ1zUituH1o91gRRRIgUZSnptDXKYgM9n+m1YMfzpUVqNw2stnx2zW9iVcxIj99dTTEOQMvcPJuBTrIwp+bIp2mNSVrLpAaiw= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 161529662332138.23109654095515; Tue, 9 Mar 2021 05:30:23 -0800 (PST) Received: from localhost ([::1]:43830 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lJcRK-0005hw-6X for importer@patchew.org; Tue, 09 Mar 2021 08:30:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44028) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lJcEe-00027w-Gm; Tue, 09 Mar 2021 08:17:17 -0500 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:53896) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lJcEZ-0007D9-5v; Tue, 09 Mar 2021 08:17:15 -0500 Received: from pps.filterd (m0098409.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 129D2p6B098851; Tue, 9 Mar 2021 08:16:51 -0500 Received: from ppma02fra.de.ibm.com (47.49.7a9f.ip4.static.sl-reverse.com [159.122.73.71]) by mx0a-001b2d01.pphosted.com with ESMTP id 37640j2drf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 09 Mar 2021 08:16:50 -0500 Received: from pps.filterd (ppma02fra.de.ibm.com [127.0.0.1]) by ppma02fra.de.ibm.com (8.16.0.43/8.16.0.43) with SMTP id 129D9WRJ026686; Tue, 9 Mar 2021 13:16:48 GMT Received: from b06avi18626390.portsmouth.uk.ibm.com (b06avi18626390.portsmouth.uk.ibm.com [9.149.26.192]) by ppma02fra.de.ibm.com with ESMTP id 3768mv81a2-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 09 Mar 2021 13:16:48 +0000 Received: from d06av24.portsmouth.uk.ibm.com (mk.ibm.com [9.149.105.60]) by b06avi18626390.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 129DGUF424904158 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 9 Mar 2021 13:16:31 GMT Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 2A89642042; Tue, 9 Mar 2021 13:16:46 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id DA7D342041; Tue, 9 Mar 2021 13:16:45 +0000 (GMT) Received: from smtp.tlslab.ibm.com (unknown [9.101.4.1]) by d06av24.portsmouth.uk.ibm.com (Postfix) with SMTP; Tue, 9 Mar 2021 13:16:45 +0000 (GMT) Received: from yukon.ibmuc.com (unknown [9.171.48.251]) by smtp.tlslab.ibm.com (Postfix) with ESMTP id 2FD13220270; Tue, 9 Mar 2021 14:16:45 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: Peter Maydell Subject: [PULL 5/7] hw/arm: ast2600: Correct the iBT interrupt ID Date: Tue, 9 Mar 2021 14:16:39 +0100 Message-Id: <20210309131641.2709380-6-clg@kaod.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210309131641.2709380-1-clg@kaod.org> References: <20210309131641.2709380-1-clg@kaod.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761 definitions=2021-03-09_11:2021-03-08, 2021-03-09 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 mlxlogscore=556 clxscore=1034 spamscore=0 impostorscore=0 mlxscore=0 suspectscore=0 phishscore=0 lowpriorityscore=0 bulkscore=0 priorityscore=1501 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2103090064 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=148.163.156.1; envelope-from=clg@kaod.org; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jeffery , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-arm@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Andrew Jeffery The AST2600 allocates distinct GIC IRQs for the LPC subdevices such as the iBT device. Previously on the AST2400 and AST2500 the LPC subdevices shared a single LPC IRQ. Signed-off-by: Andrew Jeffery Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: C=C3=A9dric Le Goater Message-Id: <20210302014317.915120-4-andrew@aj.id.au> Signed-off-by: C=C3=A9dric Le Goater --- hw/arm/aspeed_ast2600.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index 1dc56ce4781c..7635d4bae9d0 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -98,7 +98,7 @@ static const int aspeed_soc_ast2600_irqmap[] =3D { [ASPEED_DEV_WDT] =3D 24, [ASPEED_DEV_PWM] =3D 44, [ASPEED_DEV_LPC] =3D 35, - [ASPEED_DEV_IBT] =3D 35, /* LPC */ + [ASPEED_DEV_IBT] =3D 143, [ASPEED_DEV_I2C] =3D 110, /* 110 -> 125 */ [ASPEED_DEV_ETH1] =3D 2, [ASPEED_DEV_ETH2] =3D 3, --=20 2.26.2 From nobody Fri Dec 19 06:18:32 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1615296941; cv=none; d=zohomail.com; s=zohoarc; b=WZ42G8YC7uBSq8DuyOFX9Eiajive+IkOH2eT0geTr4qfvkFf/eEbwPl/ptX+hMyHbm6xNLCjMeyN7fo7+rK2w/EmnxTcx3lZk8YyF0EzdGrvZ/iSyD/NzwGrtaY0p3Q2mIgd4YJX7I23UA88/qNVS6Fn3G81wHziC5WZLfNmTco= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615296941; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=kne5uuuvJYOPtz4fCob6LpxZ0OEztlNZgb4arzlu5Qc=; b=CCJDDA6UVs0/JiUTd5CgUazdjfDNGGqr06iF90nD5dMk9MMIhg0Zzwcp2+JA4g1/FBel7E9w+lArb0bzMaNJAu9r4LCXEHofFD04r5FuEkRxMTV67FPyUSUNexKG7uCSMjZ2thAhrQblgYyC3RcD2COako0+F9RiL4e2MDcPA8g= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1615296941223942.0203011880687; Tue, 9 Mar 2021 05:35:41 -0800 (PST) Received: from localhost ([::1]:59398 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lJcWS-0003tL-0K for importer@patchew.org; Tue, 09 Mar 2021 08:35:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43942) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lJcEY-00026T-RW; Tue, 09 Mar 2021 08:17:11 -0500 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:25006) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lJcEU-0007Ak-MB; Tue, 09 Mar 2021 08:17:10 -0500 Received: from pps.filterd (m0098410.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 129D5XVZ057968; Tue, 9 Mar 2021 08:16:51 -0500 Received: from ppma04ams.nl.ibm.com (63.31.33a9.ip4.static.sl-reverse.com [169.51.49.99]) by mx0a-001b2d01.pphosted.com with ESMTP id 3762wr47bs-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 09 Mar 2021 08:16:51 -0500 Received: from pps.filterd (ppma04ams.nl.ibm.com [127.0.0.1]) by ppma04ams.nl.ibm.com (8.16.0.43/8.16.0.43) with SMTP id 129D7w3o023796; Tue, 9 Mar 2021 13:16:49 GMT Received: from b06avi18626390.portsmouth.uk.ibm.com (b06avi18626390.portsmouth.uk.ibm.com [9.149.26.192]) by ppma04ams.nl.ibm.com with ESMTP id 3768n1g2fs-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 09 Mar 2021 13:16:48 +0000 Received: from d06av24.portsmouth.uk.ibm.com (d06av24.portsmouth.uk.ibm.com [9.149.105.60]) by b06avi18626390.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 129DGVq236831574 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 9 Mar 2021 13:16:31 GMT Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A656842041; Tue, 9 Mar 2021 13:16:46 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 66F994203F; Tue, 9 Mar 2021 13:16:46 +0000 (GMT) Received: from smtp.tlslab.ibm.com (unknown [9.101.4.1]) by d06av24.portsmouth.uk.ibm.com (Postfix) with SMTP; Tue, 9 Mar 2021 13:16:46 +0000 (GMT) Received: from yukon.ibmuc.com (unknown [9.171.48.251]) by smtp.tlslab.ibm.com (Postfix) with ESMTP id C847F22025C; Tue, 9 Mar 2021 14:16:45 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: Peter Maydell Subject: [PULL 6/7] hw/misc: Add a basic Aspeed LPC controller model Date: Tue, 9 Mar 2021 14:16:40 +0100 Message-Id: <20210309131641.2709380-7-clg@kaod.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210309131641.2709380-1-clg@kaod.org> References: <20210309131641.2709380-1-clg@kaod.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761 definitions=2021-03-09_11:2021-03-08, 2021-03-09 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 impostorscore=0 bulkscore=0 adultscore=0 spamscore=0 malwarescore=0 priorityscore=1501 suspectscore=0 phishscore=0 clxscore=1034 mlxlogscore=889 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2103090064 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=148.163.156.1; envelope-from=clg@kaod.org; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jeffery , qemu-arm@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" This is a very minimal framework to access registers which are used to configure the AHB memory mapping of the flash chips on the LPC HC Firmware address space. Signed-off-by: C=C3=A9dric Le Goater Signed-off-by: Andrew Jeffery Message-Id: <20210302014317.915120-5-andrew@aj.id.au> Signed-off-by: C=C3=A9dric Le Goater --- docs/system/arm/aspeed.rst | 2 +- include/hw/arm/aspeed_soc.h | 2 + include/hw/misc/aspeed_lpc.h | 32 +++++++++ hw/arm/aspeed_ast2600.c | 10 +++ hw/arm/aspeed_soc.c | 10 +++ hw/misc/aspeed_lpc.c | 131 +++++++++++++++++++++++++++++++++++ hw/misc/meson.build | 7 +- 7 files changed, 192 insertions(+), 2 deletions(-) create mode 100644 include/hw/misc/aspeed_lpc.h create mode 100644 hw/misc/aspeed_lpc.c diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst index 8972aa3f7bbe..d1fb8f25b39c 100644 --- a/docs/system/arm/aspeed.rst +++ b/docs/system/arm/aspeed.rst @@ -48,6 +48,7 @@ Supported devices * UART * Ethernet controllers * Front LEDs (PCA9552 on I2C bus) + * LPC Peripheral Controller (a subset of subdevices are supported) =20 =20 Missing devices @@ -56,7 +57,6 @@ Missing devices * Coprocessor support * ADC (out of tree implementation) * PWM and Fan Controller - * LPC Bus Controller * Slave GPIO Controller * Super I/O Controller * Hash/Crypto Engine diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 11cfe6e3585b..42c64bd28ba2 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -28,6 +28,7 @@ #include "hw/sd/aspeed_sdhci.h" #include "hw/usb/hcd-ehci.h" #include "qom/object.h" +#include "hw/misc/aspeed_lpc.h" =20 #define ASPEED_SPIS_NUM 2 #define ASPEED_EHCIS_NUM 2 @@ -61,6 +62,7 @@ struct AspeedSoCState { AspeedGPIOState gpio_1_8v; AspeedSDHCIState sdhci; AspeedSDHCIState emmc; + AspeedLPCState lpc; }; =20 #define TYPE_ASPEED_SOC "aspeed-soc" diff --git a/include/hw/misc/aspeed_lpc.h b/include/hw/misc/aspeed_lpc.h new file mode 100644 index 000000000000..0fbb7f68bed2 --- /dev/null +++ b/include/hw/misc/aspeed_lpc.h @@ -0,0 +1,32 @@ +/* + * ASPEED LPC Controller + * + * Copyright (C) 2017-2018 IBM Corp. + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + */ + +#ifndef ASPEED_LPC_H +#define ASPEED_LPC_H + +#include "hw/sysbus.h" + +#define TYPE_ASPEED_LPC "aspeed.lpc" +#define ASPEED_LPC(obj) OBJECT_CHECK(AspeedLPCState, (obj), TYPE_ASPEED_LP= C) + +#define ASPEED_LPC_NR_REGS (0x260 >> 2) + +typedef struct AspeedLPCState { + /* */ + SysBusDevice parent; + + /*< public >*/ + MemoryRegion iomem; + qemu_irq irq; + + uint32_t regs[ASPEED_LPC_NR_REGS]; + uint32_t hicr7; +} AspeedLPCState; + +#endif /* _ASPEED_LPC_H_ */ diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index 7635d4bae9d0..78a8d6e62f52 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -211,6 +211,8 @@ static void aspeed_soc_ast2600_init(Object *obj) =20 object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0= ], TYPE_SYSBUS_SDHCI); + + object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC); } =20 /* @@ -462,6 +464,14 @@ static void aspeed_soc_ast2600_realize(DeviceState *de= v, Error **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->emmc), 0, sc->memmap[ASPEED_DEV_EMM= C]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, aspeed_soc_get_irq(s, ASPEED_DEV_EMMC)); + + /* LPC */ + if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) { + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]= ); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, + aspeed_soc_get_irq(s, ASPEED_DEV_LPC)); } =20 static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index 7eefd54ac07a..4f098da437ac 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -211,6 +211,8 @@ static void aspeed_soc_init(Object *obj) object_initialize_child(obj, "sdhci[*]", &s->sdhci.slots[i], TYPE_SYSBUS_SDHCI); } + + object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC); } =20 static void aspeed_soc_realize(DeviceState *dev, Error **errp) @@ -393,6 +395,14 @@ static void aspeed_soc_realize(DeviceState *dev, Error= **errp) sc->memmap[ASPEED_DEV_SDHCI]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); + + /* LPC */ + if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) { + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]= ); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, + aspeed_soc_get_irq(s, ASPEED_DEV_LPC)); } static Property aspeed_soc_properties[] =3D { DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION, diff --git a/hw/misc/aspeed_lpc.c b/hw/misc/aspeed_lpc.c new file mode 100644 index 000000000000..e668e985ff04 --- /dev/null +++ b/hw/misc/aspeed_lpc.c @@ -0,0 +1,131 @@ +/* + * ASPEED LPC Controller + * + * Copyright (C) 2017-2018 IBM Corp. + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/error-report.h" +#include "hw/misc/aspeed_lpc.h" +#include "qapi/error.h" +#include "hw/qdev-properties.h" +#include "migration/vmstate.h" + +#define TO_REG(offset) ((offset) >> 2) + +#define HICR0 TO_REG(0x00) +#define HICR1 TO_REG(0x04) +#define HICR2 TO_REG(0x08) +#define HICR3 TO_REG(0x0C) +#define HICR4 TO_REG(0x10) +#define HICR5 TO_REG(0x80) +#define HICR6 TO_REG(0x84) +#define HICR7 TO_REG(0x88) +#define HICR8 TO_REG(0x8C) + +static uint64_t aspeed_lpc_read(void *opaque, hwaddr offset, unsigned size) +{ + AspeedLPCState *s =3D ASPEED_LPC(opaque); + int reg =3D TO_REG(offset); + + if (reg >=3D ARRAY_SIZE(s->regs)) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "= \n", + __func__, offset); + return 0; + } + + return s->regs[reg]; +} + +static void aspeed_lpc_write(void *opaque, hwaddr offset, uint64_t data, + unsigned int size) +{ + AspeedLPCState *s =3D ASPEED_LPC(opaque); + int reg =3D TO_REG(offset); + + if (reg >=3D ARRAY_SIZE(s->regs)) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx = "\n", + __func__, offset); + return; + } + + s->regs[reg] =3D data; +} + +static const MemoryRegionOps aspeed_lpc_ops =3D { + .read =3D aspeed_lpc_read, + .write =3D aspeed_lpc_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 4, + }, +}; + +static void aspeed_lpc_reset(DeviceState *dev) +{ + struct AspeedLPCState *s =3D ASPEED_LPC(dev); + + memset(s->regs, 0, sizeof(s->regs)); + + s->regs[HICR7] =3D s->hicr7; +} + +static void aspeed_lpc_realize(DeviceState *dev, Error **errp) +{ + AspeedLPCState *s =3D ASPEED_LPC(dev); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + + sysbus_init_irq(sbd, &s->irq); + + memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_lpc_ops, s, + TYPE_ASPEED_LPC, 0x1000); + + sysbus_init_mmio(sbd, &s->iomem); +} + +static const VMStateDescription vmstate_aspeed_lpc =3D { + .name =3D TYPE_ASPEED_LPC, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, AspeedLPCState, ASPEED_LPC_NR_REGS), + VMSTATE_END_OF_LIST(), + } +}; + +static Property aspeed_lpc_properties[] =3D { + DEFINE_PROP_UINT32("hicr7", AspeedLPCState, hicr7, 0), + DEFINE_PROP_END_OF_LIST(), +}; + +static void aspeed_lpc_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D aspeed_lpc_realize; + dc->reset =3D aspeed_lpc_reset; + dc->desc =3D "Aspeed LPC Controller", + dc->vmsd =3D &vmstate_aspeed_lpc; + device_class_set_props(dc, aspeed_lpc_properties); +} + +static const TypeInfo aspeed_lpc_info =3D { + .name =3D TYPE_ASPEED_LPC, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(AspeedLPCState), + .class_init =3D aspeed_lpc_class_init, +}; + +static void aspeed_lpc_register_types(void) +{ + type_register_static(&aspeed_lpc_info); +} + +type_init(aspeed_lpc_register_types); diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 629283957fcc..e3263383cd59 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -102,7 +102,12 @@ softmmu_ss.add(when: 'CONFIG_ARMSSE_MHU', if_true: fil= es('armsse-mhu.c')) softmmu_ss.add(when: 'CONFIG_PVPANIC_ISA', if_true: files('pvpanic-isa.c')) softmmu_ss.add(when: 'CONFIG_PVPANIC_PCI', if_true: files('pvpanic-pci.c')) softmmu_ss.add(when: 'CONFIG_AUX', if_true: files('auxbus.c')) -softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_scu.c', '= aspeed_sdmc.c', 'aspeed_xdma.c')) +softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( + 'aspeed_lpc.c', + 'aspeed_scu.c', + 'aspeed_sdmc.c', + 'aspeed_xdma.c')) + softmmu_ss.add(when: 'CONFIG_MSF2', if_true: files('msf2-sysreg.c')) softmmu_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_rng.c')) =20 --=20 2.26.2 From nobody Fri Dec 19 06:18:32 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1615296204; cv=none; d=zohomail.com; s=zohoarc; b=JYLMxW5TIWKRUN4VXbSYGqKwGgpDsggpvxNPQZs5QQ3jwV0BNMhoKzKSyc9V9CRKWk7OE7XJEUVODkCKpO+oOBW/02kz8Y1QIzxdAojivbDCZYK69RTvZU0HpAfOZ1Gm/bhZ0cSJQyeKScTU8OcIFy52koHS8uTQwrDlfK4BwDg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615296204; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=B8NSvHU3m8K2tZVB2yzgXNW3x2nyN8IxK4OVbsBf+rg=; b=fn9x3yXBmJxPTHNN/92pYcoHT8uF7CDZbSgpEzLdkQ4qXVQe4CrsMcU+9zXTziVrLNt0PQUYKPTxf+t7UlmLRK37ZCZ7tED4zF70VFEqyg0yrqlW0/YUD6e0ZfjOb5v9J5LsSqYET1ZuSRarS1pdS9qJoyZHx6iRFwrwWqufUnM= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1615296204305418.5641043749787; Tue, 9 Mar 2021 05:23:24 -0800 (PST) Received: from localhost ([::1]:55192 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lJcKZ-000701-6I for importer@patchew.org; Tue, 09 Mar 2021 08:23:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43940) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lJcEY-00026S-QI; Tue, 09 Mar 2021 08:17:11 -0500 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:59984) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lJcEU-00077O-Mo; Tue, 09 Mar 2021 08:17:09 -0500 Received: from pps.filterd (m0127361.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 129D3VDJ117542; Tue, 9 Mar 2021 08:16:52 -0500 Received: from ppma02fra.de.ibm.com (47.49.7a9f.ip4.static.sl-reverse.com [159.122.73.71]) by mx0a-001b2d01.pphosted.com with ESMTP id 375wcm9cbn-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 09 Mar 2021 08:16:52 -0500 Received: from pps.filterd (ppma02fra.de.ibm.com [127.0.0.1]) by ppma02fra.de.ibm.com (8.16.0.43/8.16.0.43) with SMTP id 129D9krj026985; Tue, 9 Mar 2021 13:16:49 GMT Received: from b06cxnps4075.portsmouth.uk.ibm.com (d06relay12.portsmouth.uk.ibm.com [9.149.109.197]) by ppma02fra.de.ibm.com with ESMTP id 3768mv81a3-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 09 Mar 2021 13:16:49 +0000 Received: from d06av25.portsmouth.uk.ibm.com (d06av25.portsmouth.uk.ibm.com [9.149.105.61]) by b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 129DGlE864880962 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 9 Mar 2021 13:16:47 GMT Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 4E92E11C05B; Tue, 9 Mar 2021 13:16:47 +0000 (GMT) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id F3ED711C04C; Tue, 9 Mar 2021 13:16:46 +0000 (GMT) Received: from smtp.tlslab.ibm.com (unknown [9.101.4.1]) by d06av25.portsmouth.uk.ibm.com (Postfix) with SMTP; Tue, 9 Mar 2021 13:16:46 +0000 (GMT) Received: from yukon.ibmuc.com (unknown [9.171.48.251]) by smtp.tlslab.ibm.com (Postfix) with ESMTP id 53599220270; Tue, 9 Mar 2021 14:16:46 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: Peter Maydell Subject: [PULL 7/7] hw/misc: Model KCS devices in the Aspeed LPC controller Date: Tue, 9 Mar 2021 14:16:41 +0100 Message-Id: <20210309131641.2709380-8-clg@kaod.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210309131641.2709380-1-clg@kaod.org> References: <20210309131641.2709380-1-clg@kaod.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761 definitions=2021-03-09_11:2021-03-08, 2021-03-09 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 impostorscore=0 spamscore=0 suspectscore=0 phishscore=0 adultscore=0 bulkscore=0 mlxscore=0 clxscore=1034 priorityscore=1501 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2103090064 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=148.163.158.5; envelope-from=clg@kaod.org; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jeffery , qemu-arm@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Andrew Jeffery Keyboard-Controller-Style devices for IPMI purposes are exposed via LPC IO cycles from the BMC to the host. Expose support on the BMC side by implementing the usual MMIO behaviours, and expose the ability to inspect the KCS registers in "host" style by accessing QOM properties associated with each register. The model caters to the IRQ style of both the AST2600 and the earlier SoCs (AST2400 and AST2500). The AST2600 allocates an IRQ for each LPC sub-device, while there is a single IRQ shared across all subdevices on the AST2400 and AST2500. Signed-off-by: Andrew Jeffery Reviewed-by: C=C3=A9dric Le Goater Message-Id: <20210302014317.915120-6-andrew@aj.id.au> Signed-off-by: C=C3=A9dric Le Goater --- include/hw/arm/aspeed_soc.h | 1 + include/hw/misc/aspeed_lpc.h | 17 +- hw/arm/aspeed_ast2600.c | 28 ++- hw/arm/aspeed_soc.c | 24 ++- hw/misc/aspeed_lpc.c | 359 ++++++++++++++++++++++++++++++++++- 5 files changed, 424 insertions(+), 5 deletions(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 42c64bd28ba2..9359d6da336d 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -132,6 +132,7 @@ enum { ASPEED_DEV_SDRAM, ASPEED_DEV_XDMA, ASPEED_DEV_EMMC, + ASPEED_DEV_KCS, }; =20 #endif /* ASPEED_SOC_H */ diff --git a/include/hw/misc/aspeed_lpc.h b/include/hw/misc/aspeed_lpc.h index 0fbb7f68bed2..df418cfcd36c 100644 --- a/include/hw/misc/aspeed_lpc.h +++ b/include/hw/misc/aspeed_lpc.h @@ -12,10 +12,22 @@ =20 #include "hw/sysbus.h" =20 +#include + #define TYPE_ASPEED_LPC "aspeed.lpc" #define ASPEED_LPC(obj) OBJECT_CHECK(AspeedLPCState, (obj), TYPE_ASPEED_LP= C) =20 -#define ASPEED_LPC_NR_REGS (0x260 >> 2) +#define ASPEED_LPC_NR_REGS (0x260 >> 2) + +enum aspeed_lpc_subdevice { + aspeed_lpc_kcs_1 =3D 0, + aspeed_lpc_kcs_2, + aspeed_lpc_kcs_3, + aspeed_lpc_kcs_4, + aspeed_lpc_ibt, +}; + +#define ASPEED_LPC_NR_SUBDEVS 5 =20 typedef struct AspeedLPCState { /* */ @@ -25,6 +37,9 @@ typedef struct AspeedLPCState { MemoryRegion iomem; qemu_irq irq; =20 + qemu_irq subdevice_irqs[ASPEED_LPC_NR_SUBDEVS]; + uint32_t subdevice_irqs_pending; + uint32_t regs[ASPEED_LPC_NR_REGS]; uint32_t hicr7; } AspeedLPCState; diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index 78a8d6e62f52..bc87e754a3cc 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -104,7 +104,7 @@ static const int aspeed_soc_ast2600_irqmap[] =3D { [ASPEED_DEV_ETH2] =3D 3, [ASPEED_DEV_ETH3] =3D 32, [ASPEED_DEV_ETH4] =3D 33, - + [ASPEED_DEV_KCS] =3D 138, /* 138 -> 142 */ }; =20 static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl) @@ -470,8 +470,34 @@ static void aspeed_soc_ast2600_realize(DeviceState *de= v, Error **errp) return; } sysbus_mmio_map(SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]= ); + + /* Connect the LPC IRQ to the GIC. It is otherwise unused. */ sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, aspeed_soc_get_irq(s, ASPEED_DEV_LPC)); + + /* + * On the AST2600 LPC subdevice IRQs are connected straight to the GIC. + * + * LPC subdevice IRQ sources are offset from 1 because the LPC model c= aters + * to the AST2400 and AST2500. SoCs before the AST2600 have one LPC IRQ + * shared across the subdevices, and the shared IRQ output to the VIC = is at + * offset 0. + */ + sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1, + qdev_get_gpio_in(DEVICE(&s->a7mpcore), + sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kc= s_1)); + + sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2, + qdev_get_gpio_in(DEVICE(&s->a7mpcore), + sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kc= s_2)); + + sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3, + qdev_get_gpio_in(DEVICE(&s->a7mpcore), + sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kc= s_3)); + + sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4, + qdev_get_gpio_in(DEVICE(&s->a7mpcore), + sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kc= s_4)); } =20 static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index 4f098da437ac..057d053c8478 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -112,7 +112,6 @@ static const int aspeed_soc_ast2400_irqmap[] =3D { [ASPEED_DEV_WDT] =3D 27, [ASPEED_DEV_PWM] =3D 28, [ASPEED_DEV_LPC] =3D 8, - [ASPEED_DEV_IBT] =3D 8, /* LPC */ [ASPEED_DEV_I2C] =3D 12, [ASPEED_DEV_ETH1] =3D 2, [ASPEED_DEV_ETH2] =3D 3, @@ -401,8 +400,31 @@ static void aspeed_soc_realize(DeviceState *dev, Error= **errp) return; } sysbus_mmio_map(SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]= ); + + /* Connect the LPC IRQ to the VIC */ sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, aspeed_soc_get_irq(s, ASPEED_DEV_LPC)); + + /* + * On the AST2400 and AST2500 the one LPC IRQ is shared between all of= the + * subdevices. Connect the LPC subdevice IRQs to the LPC controller IR= Q (by + * contrast, on the AST2600, the subdevice IRQs are connected straight= to + * the GIC). + * + * LPC subdevice IRQ sources are offset from 1 because the shared IRQ = output + * to the VIC is at offset 0. + */ + sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1, + qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_1)= ); + + sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2, + qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_2)= ); + + sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3, + qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_3)= ); + + sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4, + qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_4)= ); } static Property aspeed_soc_properties[] =3D { DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION, diff --git a/hw/misc/aspeed_lpc.c b/hw/misc/aspeed_lpc.c index e668e985ff04..2dddb27c35d0 100644 --- a/hw/misc/aspeed_lpc.c +++ b/hw/misc/aspeed_lpc.c @@ -12,20 +12,301 @@ #include "qemu/error-report.h" #include "hw/misc/aspeed_lpc.h" #include "qapi/error.h" +#include "qapi/visitor.h" +#include "hw/irq.h" #include "hw/qdev-properties.h" #include "migration/vmstate.h" =20 #define TO_REG(offset) ((offset) >> 2) =20 #define HICR0 TO_REG(0x00) +#define HICR0_LPC3E BIT(7) +#define HICR0_LPC2E BIT(6) +#define HICR0_LPC1E BIT(5) #define HICR1 TO_REG(0x04) #define HICR2 TO_REG(0x08) +#define HICR2_IBFIE3 BIT(3) +#define HICR2_IBFIE2 BIT(2) +#define HICR2_IBFIE1 BIT(1) #define HICR3 TO_REG(0x0C) #define HICR4 TO_REG(0x10) +#define HICR4_KCSENBL BIT(2) +#define IDR1 TO_REG(0x24) +#define IDR2 TO_REG(0x28) +#define IDR3 TO_REG(0x2C) +#define ODR1 TO_REG(0x30) +#define ODR2 TO_REG(0x34) +#define ODR3 TO_REG(0x38) +#define STR1 TO_REG(0x3C) +#define STR_OBF BIT(0) +#define STR_IBF BIT(1) +#define STR_CMD_DATA BIT(3) +#define STR2 TO_REG(0x40) +#define STR3 TO_REG(0x44) #define HICR5 TO_REG(0x80) #define HICR6 TO_REG(0x84) #define HICR7 TO_REG(0x88) #define HICR8 TO_REG(0x8C) +#define HICRB TO_REG(0x100) +#define HICRB_IBFIE4 BIT(1) +#define HICRB_LPC4E BIT(0) +#define IDR4 TO_REG(0x114) +#define ODR4 TO_REG(0x118) +#define STR4 TO_REG(0x11C) + +enum aspeed_kcs_channel_id { + kcs_channel_1 =3D 0, + kcs_channel_2, + kcs_channel_3, + kcs_channel_4, +}; + +static const enum aspeed_lpc_subdevice aspeed_kcs_subdevice_map[] =3D { + [kcs_channel_1] =3D aspeed_lpc_kcs_1, + [kcs_channel_2] =3D aspeed_lpc_kcs_2, + [kcs_channel_3] =3D aspeed_lpc_kcs_3, + [kcs_channel_4] =3D aspeed_lpc_kcs_4, +}; + +struct aspeed_kcs_channel { + enum aspeed_kcs_channel_id id; + + int idr; + int odr; + int str; +}; + +static const struct aspeed_kcs_channel aspeed_kcs_channel_map[] =3D { + [kcs_channel_1] =3D { + .id =3D kcs_channel_1, + .idr =3D IDR1, + .odr =3D ODR1, + .str =3D STR1 + }, + + [kcs_channel_2] =3D { + .id =3D kcs_channel_2, + .idr =3D IDR2, + .odr =3D ODR2, + .str =3D STR2 + }, + + [kcs_channel_3] =3D { + .id =3D kcs_channel_3, + .idr =3D IDR3, + .odr =3D ODR3, + .str =3D STR3 + }, + + [kcs_channel_4] =3D { + .id =3D kcs_channel_4, + .idr =3D IDR4, + .odr =3D ODR4, + .str =3D STR4 + }, +}; + +struct aspeed_kcs_register_data { + const char *name; + int reg; + const struct aspeed_kcs_channel *chan; +}; + +static const struct aspeed_kcs_register_data aspeed_kcs_registers[] =3D { + { + .name =3D "idr1", + .reg =3D IDR1, + .chan =3D &aspeed_kcs_channel_map[kcs_channel_1], + }, + { + .name =3D "odr1", + .reg =3D ODR1, + .chan =3D &aspeed_kcs_channel_map[kcs_channel_1], + }, + { + .name =3D "str1", + .reg =3D STR1, + .chan =3D &aspeed_kcs_channel_map[kcs_channel_1], + }, + { + .name =3D "idr2", + .reg =3D IDR2, + .chan =3D &aspeed_kcs_channel_map[kcs_channel_2], + }, + { + .name =3D "odr2", + .reg =3D ODR2, + .chan =3D &aspeed_kcs_channel_map[kcs_channel_2], + }, + { + .name =3D "str2", + .reg =3D STR2, + .chan =3D &aspeed_kcs_channel_map[kcs_channel_2], + }, + { + .name =3D "idr3", + .reg =3D IDR3, + .chan =3D &aspeed_kcs_channel_map[kcs_channel_3], + }, + { + .name =3D "odr3", + .reg =3D ODR3, + .chan =3D &aspeed_kcs_channel_map[kcs_channel_3], + }, + { + .name =3D "str3", + .reg =3D STR3, + .chan =3D &aspeed_kcs_channel_map[kcs_channel_3], + }, + { + .name =3D "idr4", + .reg =3D IDR4, + .chan =3D &aspeed_kcs_channel_map[kcs_channel_4], + }, + { + .name =3D "odr4", + .reg =3D ODR4, + .chan =3D &aspeed_kcs_channel_map[kcs_channel_4], + }, + { + .name =3D "str4", + .reg =3D STR4, + .chan =3D &aspeed_kcs_channel_map[kcs_channel_4], + }, + { }, +}; + +static const struct aspeed_kcs_register_data * +aspeed_kcs_get_register_data_by_name(const char *name) +{ + const struct aspeed_kcs_register_data *pos =3D aspeed_kcs_registers; + + while (pos->name) { + if (!strcmp(pos->name, name)) { + return pos; + } + pos++; + } + + return NULL; +} + +static const struct aspeed_kcs_channel * +aspeed_kcs_get_channel_by_register(int reg) +{ + const struct aspeed_kcs_register_data *pos =3D aspeed_kcs_registers; + + while (pos->name) { + if (pos->reg =3D=3D reg) { + return pos->chan; + } + pos++; + } + + return NULL; +} + +static void aspeed_kcs_get_register_property(Object *obj, + Visitor *v, + const char *name, + void *opaque, + Error **errp) +{ + const struct aspeed_kcs_register_data *data; + AspeedLPCState *s =3D ASPEED_LPC(obj); + uint32_t val; + + data =3D aspeed_kcs_get_register_data_by_name(name); + if (!data) { + return; + } + + if (!strncmp("odr", name, 3)) { + s->regs[data->chan->str] &=3D ~STR_OBF; + } + + val =3D s->regs[data->reg]; + + visit_type_uint32(v, name, &val, errp); +} + +static bool aspeed_kcs_channel_enabled(AspeedLPCState *s, + const struct aspeed_kcs_channel *ch= annel) +{ + switch (channel->id) { + case kcs_channel_1: return s->regs[HICR0] & HICR0_LPC1E; + case kcs_channel_2: return s->regs[HICR0] & HICR0_LPC2E; + case kcs_channel_3: + return (s->regs[HICR0] & HICR0_LPC3E) && + (s->regs[HICR4] & HICR4_KCSENBL); + case kcs_channel_4: return s->regs[HICRB] & HICRB_LPC4E; + default: return false; + } +} + +static bool +aspeed_kcs_channel_ibf_irq_enabled(AspeedLPCState *s, + const struct aspeed_kcs_channel *channe= l) +{ + if (!aspeed_kcs_channel_enabled(s, channel)) { + return false; + } + + switch (channel->id) { + case kcs_channel_1: return s->regs[HICR2] & HICR2_IBFIE1; + case kcs_channel_2: return s->regs[HICR2] & HICR2_IBFIE2; + case kcs_channel_3: return s->regs[HICR2] & HICR2_IBFIE3; + case kcs_channel_4: return s->regs[HICRB] & HICRB_IBFIE4; + default: return false; + } +} + +static void aspeed_kcs_set_register_property(Object *obj, + Visitor *v, + const char *name, + void *opaque, + Error **errp) +{ + const struct aspeed_kcs_register_data *data; + AspeedLPCState *s =3D ASPEED_LPC(obj); + uint32_t val; + + data =3D aspeed_kcs_get_register_data_by_name(name); + if (!data) { + return; + } + + if (!visit_type_uint32(v, name, &val, errp)) { + return; + } + + if (strncmp("str", name, 3)) { + s->regs[data->reg] =3D val; + } + + if (!strncmp("idr", name, 3)) { + s->regs[data->chan->str] |=3D STR_IBF; + if (aspeed_kcs_channel_ibf_irq_enabled(s, data->chan)) { + enum aspeed_lpc_subdevice subdev; + + subdev =3D aspeed_kcs_subdevice_map[data->chan->id]; + qemu_irq_raise(s->subdevice_irqs[subdev]); + } + } +} + +static void aspeed_lpc_set_irq(void *opaque, int irq, int level) +{ + AspeedLPCState *s =3D (AspeedLPCState *)opaque; + + if (level) { + s->subdevice_irqs_pending |=3D BIT(irq); + } else { + s->subdevice_irqs_pending &=3D ~BIT(irq); + } + + qemu_set_irq(s->irq, !!s->subdevice_irqs_pending); +} =20 static uint64_t aspeed_lpc_read(void *opaque, hwaddr offset, unsigned size) { @@ -39,6 +320,29 @@ static uint64_t aspeed_lpc_read(void *opaque, hwaddr of= fset, unsigned size) return 0; } =20 + switch (reg) { + case IDR1: + case IDR2: + case IDR3: + case IDR4: + { + const struct aspeed_kcs_channel *channel; + + channel =3D aspeed_kcs_get_channel_by_register(reg); + if (s->regs[channel->str] & STR_IBF) { + enum aspeed_lpc_subdevice subdev; + + subdev =3D aspeed_kcs_subdevice_map[channel->id]; + qemu_irq_lower(s->subdevice_irqs[subdev]); + } + + s->regs[channel->str] &=3D ~STR_IBF; + break; + } + default: + break; + } + return s->regs[reg]; } =20 @@ -55,6 +359,18 @@ static void aspeed_lpc_write(void *opaque, hwaddr offse= t, uint64_t data, return; } =20 + + switch (reg) { + case ODR1: + case ODR2: + case ODR3: + case ODR4: + s->regs[aspeed_kcs_get_channel_by_register(reg)->str] |=3D STR_OBF; + break; + default: + break; + } + s->regs[reg] =3D data; } =20 @@ -72,6 +388,8 @@ static void aspeed_lpc_reset(DeviceState *dev) { struct AspeedLPCState *s =3D ASPEED_LPC(dev); =20 + s->subdevice_irqs_pending =3D 0; + memset(s->regs, 0, sizeof(s->regs)); =20 s->regs[HICR7] =3D s->hicr7; @@ -83,19 +401,55 @@ static void aspeed_lpc_realize(DeviceState *dev, Error= **errp) SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); =20 sysbus_init_irq(sbd, &s->irq); + sysbus_init_irq(sbd, &s->subdevice_irqs[aspeed_lpc_kcs_1]); + sysbus_init_irq(sbd, &s->subdevice_irqs[aspeed_lpc_kcs_2]); + sysbus_init_irq(sbd, &s->subdevice_irqs[aspeed_lpc_kcs_3]); + sysbus_init_irq(sbd, &s->subdevice_irqs[aspeed_lpc_kcs_4]); + sysbus_init_irq(sbd, &s->subdevice_irqs[aspeed_lpc_ibt]); =20 memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_lpc_ops, s, TYPE_ASPEED_LPC, 0x1000); =20 sysbus_init_mmio(sbd, &s->iomem); + + qdev_init_gpio_in(dev, aspeed_lpc_set_irq, ASPEED_LPC_NR_SUBDEVS); +} + +static void aspeed_lpc_init(Object *obj) +{ + object_property_add(obj, "idr1", "uint32", aspeed_kcs_get_register_pro= perty, + aspeed_kcs_set_register_property, NULL, NULL); + object_property_add(obj, "odr1", "uint32", aspeed_kcs_get_register_pro= perty, + aspeed_kcs_set_register_property, NULL, NULL); + object_property_add(obj, "str1", "uint32", aspeed_kcs_get_register_pro= perty, + aspeed_kcs_set_register_property, NULL, NULL); + object_property_add(obj, "idr2", "uint32", aspeed_kcs_get_register_pro= perty, + aspeed_kcs_set_register_property, NULL, NULL); + object_property_add(obj, "odr2", "uint32", aspeed_kcs_get_register_pro= perty, + aspeed_kcs_set_register_property, NULL, NULL); + object_property_add(obj, "str2", "uint32", aspeed_kcs_get_register_pro= perty, + aspeed_kcs_set_register_property, NULL, NULL); + object_property_add(obj, "idr3", "uint32", aspeed_kcs_get_register_pro= perty, + aspeed_kcs_set_register_property, NULL, NULL); + object_property_add(obj, "odr3", "uint32", aspeed_kcs_get_register_pro= perty, + aspeed_kcs_set_register_property, NULL, NULL); + object_property_add(obj, "str3", "uint32", aspeed_kcs_get_register_pro= perty, + aspeed_kcs_set_register_property, NULL, NULL); + object_property_add(obj, "idr4", "uint32", aspeed_kcs_get_register_pro= perty, + aspeed_kcs_set_register_property, NULL, NULL); + object_property_add(obj, "odr4", "uint32", aspeed_kcs_get_register_pro= perty, + aspeed_kcs_set_register_property, NULL, NULL); + object_property_add(obj, "str4", "uint32", aspeed_kcs_get_register_pro= perty, + aspeed_kcs_set_register_property, NULL, NULL); } =20 static const VMStateDescription vmstate_aspeed_lpc =3D { .name =3D TYPE_ASPEED_LPC, - .version_id =3D 1, - .minimum_version_id =3D 1, + .version_id =3D 2, + .minimum_version_id =3D 2, .fields =3D (VMStateField[]) { VMSTATE_UINT32_ARRAY(regs, AspeedLPCState, ASPEED_LPC_NR_REGS), + VMSTATE_UINT32(subdevice_irqs_pending, AspeedLPCState), VMSTATE_END_OF_LIST(), } }; @@ -121,6 +475,7 @@ static const TypeInfo aspeed_lpc_info =3D { .parent =3D TYPE_SYS_BUS_DEVICE, .instance_size =3D sizeof(AspeedLPCState), .class_init =3D aspeed_lpc_class_init, + .instance_init =3D aspeed_lpc_init, }; =20 static void aspeed_lpc_register_types(void) --=20 2.26.2